[Clang][RISCV] Guard vector int64, float32, float64 with semantic analysis

[eopXD]

Summary

Depends on D143657

[eopXD]

Bump CI.

[craig.topper]

clang/include/clang/AST/Type.h

7209 ↗

(On Diff #496185)

This function is RVV specific so it's name is misleading. It's also identical to the isRVVFloat32Type function

clang/include/clang/Basic/TargetInfo.h

668 ↗

(On Diff #496185)

Having a different virtual method for each type doesn't scale well. Could we have a single function that take the bitwidth and a bool for int or FP?

It's also very misleading based on the current names to return false for targets like X86 that do support float32 and float64.

Overall it might be cleaner to call S.Context.getTargetInfo().hasFeature( from RISCV-V specific code in Sema instead of trying to define a generic interface.

[eopXD]

clang/include/clang/Basic/TargetInfo.h

668 ↗

(On Diff #496185)

It's also very misleading based on the current names to return false for targets like X86 that do support float32 and float64.

This is the base class of TargetInfo, we may add code under x86 to override it.

[eopXD]

clang/lib/Sema/Sema.cpp

2041–2046

Overall it might be cleaner to call S.Context.getTargetInfo().hasFeature( from RISCV-V specific code in Sema instead of trying to define a generic interface.

If so, we will have something like:

if (Ty->isRVVInt64Type() && !Context.getTargetInfo().hasFeature("zve64x")) {
  Diag(Loc, diag::err_riscv_type_requires_extension, FD) << Ty << "zve64x";
}

I don't have a preference here, if this matches your expectation, I will update the revision this way.

[craig.topper]

clang/lib/Sema/Sema.cpp

2041–2046

I'm ok with what you did the Zvfh patch.

[eopXD]

Update code.

[eopXD]

Update code.

[craig.topper]

LGTM

clang/lib/Sema/Sema.cpp

if (IsRetTy && !TI.hasFPReturn() && (IsDouble || IsFloat)) {
           << false /*show bit size*/ << 0 << Ty << true /*return*/
           << Context.getTargetInfo().getTriple().str()) {
         if (D)
           D->setInvalidDecl();
       }
       if (D)
         targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
     }
 
+    // RISC-V vector builtin types (RISCVVTypes.def)
+    if (Ty->isRVVType(/* Bitwidth */ 64, /* IsFloat */ false) &&
+        !Context.getTargetInfo().hasFeature("zve64x"))
+      Diag(Loc, diag::err_riscv_type_requires_extension, FD) << Ty << "zve64x";
     if (Ty->isRVVType(/* Bitwidth */ 16, /* IsFloat */ true) &&
-        !Context.getTargetInfo().hasFeature("experimental-zvfh")) {
+        !Context.getTargetInfo().hasFeature("experimental-zvfh"))
       Diag(Loc, diag::err_riscv_type_requires_extension, FD)
           << Ty << "zvfh";
-    }
+    if (Ty->isRVVType(/* Bitwidth */ 32, /* IsFloat */ true) &&
+        !Context.getTargetInfo().hasFeature("zve32f"))
+      Diag(Loc, diag::err_riscv_type_requires_extension, FD) << Ty << "zve32f";
+    if (Ty->isRVVType(/* Bitwidth */ 64, /* IsFloat */ true) &&
+        !Context.getTargetInfo().hasFeature("zve64d"))
+      Diag(Loc, diag::err_riscv_type_requires_extension, FD) << Ty << "zve64d";
 
     // Don't allow SVE types in functions without a SVE target.
     if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) {
       llvm::StringMap<bool> CallerFeatureMap;
       Context.getFunctionFeatureMap(CallerFeatureMap, FD);
       if (!Builtin::evaluateRequiredTargetFeatures(
           "sve", CallerFeatureMap))
         Diag(D->getLocation(), diag::err_sve_vector_in_non_sve_target) << Ty;

clang/lib/Sema/SemaRISCVVectorLookup.cpp

public:
   // return true, otherwise return false.
   bool CreateIntrinsicIfFound(LookupResult &LR, IdentifierInfo *II,
                               Preprocessor &PP) override;
 };
 } // namespace
 
 void RISCVIntrinsicManagerImpl::InitIntrinsicList() {
   const TargetInfo &TI = Context.getTargetInfo();
-  bool HasVectorFloat32 = TI.hasFeature("zve32f");
-  bool HasVectorFloat64 = TI.hasFeature("zve64d");
   bool HasRV64 = TI.hasFeature("64bit");
   bool HasFullMultiply = TI.hasFeature("v");
 
   // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
   // in RISCVVEmitter.cpp.
   for (auto &Record : RVVIntrinsicRecords) {
     // Create Intrinsics for each type and LMUL.
     BasicType BaseType = BasicType::Unknown;
for (unsigned int TypeRangeMaskShift = 0;
          ++TypeRangeMaskShift) {
       unsigned int BaseTypeI = 1 << TypeRangeMaskShift;
       BaseType = static_cast<BasicType>(BaseTypeI);
 
       if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI)
         continue;
 
       // Check requirement.
-      if (BaseType == BasicType::Float32 && !HasVectorFloat32)
-        continue;
-
-      if (BaseType == BasicType::Float64 && !HasVectorFloat64)
-        continue;
-
       if (((Record.RequiredExtensions & RVV_REQ_RV64) == RVV_REQ_RV64) &&
           !HasRV64)
         continue;
 
       if ((BaseType == BasicType::Int64) &&
           ((Record.RequiredExtensions & RVV_REQ_FullMultiply) ==
            RVV_REQ_FullMultiply) &&
           !HasFullMultiply)

clang/test/Sema/riscv-vector-float32-check.c

+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +zve32x -target-feature +zfh \
+// RUN:   -disable-O0-optnone -o - -fsyntax-only %s -verify 
+// REQUIRES: riscv-registered-target
+#include <riscv_vector.h>
+
+vfloat32m1_t foo() { /* expected-error {{RISC-V type 'vfloat32m1_t' (aka '__rvv_float32m1_t') requires the 'zve32f' extension}} */
+} /* expected-warning {{non-void function does not return a value}}*/

clang/test/Sema/riscv-vector-float64-check.c

+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +zve64f -target-feature +zfh \
+// RUN:   -disable-O0-optnone -o - -fsyntax-only %s -verify 
+// REQUIRES: riscv-registered-target
+#include <riscv_vector.h>
+
+vfloat64m1_t foo() { /* expected-error {{RISC-V type 'vfloat64m1_t' (aka '__rvv_float64m1_t') requires the 'zve64d' extension}} */
+} /* expected-warning {{non-void function does not return a value}}*/

clang/test/Sema/riscv-vector-int64-check.c

+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +zve32x -target-feature +zfh \
+// RUN:   -disable-O0-optnone -o - -fsyntax-only %s -verify 
+// REQUIRES: riscv-registered-target
+#include <riscv_vector.h>
+
+vint64m1_t foo() { /* expected-error {{RISC-V type 'vint64m1_t' (aka '__rvv_int64m1_t') requires the 'zve64x' extension}} */
+} /* expected-warning {{non-void function does not return a value}}*/

clang/utils/TableGen/RISCVVEmitter.cpp

void RVVEmitter::createHeader(raw_ostream &OS) {
 
   for (int Log2LMUL : Log2LMULs) {
     auto T = TypeCache.computeType(BasicType::Float16, Log2LMUL,
                                    PrototypeDescriptor::Vector);
     if (T)
       printType(*T);
   }
 
-  OS << "#if (__riscv_v_elen_fp >= 32)\n";
   for (int Log2LMUL : Log2LMULs) {
     auto T = TypeCache.computeType(BasicType::Float32, Log2LMUL,
                                    PrototypeDescriptor::Vector);
     if (T)
       printType(*T);
   }
-  OS << "#endif\n";
 
-  OS << "#if (__riscv_v_elen_fp >= 64)\n";
   for (int Log2LMUL : Log2LMULs) {
     auto T = TypeCache.computeType(BasicType::Float64, Log2LMUL,
                                    PrototypeDescriptor::Vector);
     if (T)
       printType(*T);
   }
-  OS << "#endif\n\n";
 
   OS << "#define __riscv_v_intrinsic_overloading 1\n";
 
   OS << "\n#ifdef __cplusplus\n";
   OS << "}\n";
   OS << "#endif // __cplusplus\n";
   OS << "#endif // __RISCV_VECTOR_H\n";
 }