[AArch64]SME2 instructions that use ZTO operand

[CarolineConcatto]

Summary

This patch adds the assembly/disassembly for the following instructions:

ZERO (ZT0): Zero ZT0.
LDR (ZT0): Load ZT0 register.
STR (ZT0): Store ZT0 register.
MOVT (scalar to ZT0): Move 8 bytes from general-purpose register to ZT0.
     (ZT0 to scalar): Move 8 bytes from ZT0 to general-purpose register.

Consecutive:

LUTI2 (single): Lookup table read with 2-bit indexes.
      (two registers): Lookup table read with 2-bit indexes.
      (four registers): Lookup table read with 2-bit indexes.
LUTI4 (single): Lookup table read with 4-bit indexes.
      (two registers): Lookup table read with 4-bit indexes.
      (four registers): Lookup table read with 4-bit indexes.

The reference can be found here:

https://developer.arm.com/documentation/ddi0602/2022-09

This patch also adds a new register class and operand for zt0
and a another index operand uimm3s8

[paulwalker-arm]

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

574–580

Can I suggest using Zt to represent ZT0 within instruction names (e.g. LUTI2_2ZZtZI. This fits with how we handle other multiple letter operands, for example Pm and Pz for predicate registers.

[CarolineConcatto]

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

574–580

We had a discussion about that, the problem is that it may be mistaken with stand-alone Z.
That is the reason we choose to go with T.

[CarolineConcatto]

• Rebase

[CarolineConcatto]

Add Instruction naming conventions note

[paulwalker-arm]

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

574–580

As mentioned we support Pm, Pz as well as P, which has worked fine for years now. My problem with T is what happens if we start having registers t0-t#.

So I cannot say I buy this answer but fair enough, if this is your preference then so be it.

[paulwalker-arm]

llvm/lib/Target/AArch64/AArch64InstrFormats.td

1380

Is this really a memory index? It looks like an offset into the ZT0 vector, so should just be a normal imm/index operand.

1384

I imagine it's not just a simple replacement but as a starting point perhaps use printVectorIndex, given this is how the immediate is used.

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

1300

Just an idea but what about calling the register class ZT, which currently contains the single register ZT0?

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

32

Perhaps add (ZA)?

I think it's worth just committing this comment separately into main given it's already in use by already committed patches.

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

3871–3877

It has been a while since I've had to do this but I suspect you really want you're own ParserMethod/tryParse... method if the existing ones don't already work for you.

4089–4092

My nativity showing here but how does zt0 related to vector lists? and why do you need extra handling for za given this patch relates to zt0?

5653

Match_InvalidLookupTable?

5654

To match similar ZA diagnostics how about invalid lookup table, expected zt0?

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

1218–1226

To me this looks like a sign you're using the wrong print routine.

[CarolineConcatto]

-Address review comments

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

4089–4092

I added because of the test bellow.
But It looks it is not needed.

[paulwalker-arm]

I've only looked at the parsing side of things so far.

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

1272

This should remain as ZT0 because is represents this specific register.

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

4245–4246

I think this is only necessary because you're calling tryParseScalarRegister, which looks to be a bit of a hack if I'm honest.

What about updating matchRegisterNameAlias and then calling that instead? Something like:

if ((RegNum = MatchRegisterName(Name)))
  return Kind == RegKind::LookupTable ? RegNum : 0;

4256

I'm guessing you tried tryParseVectorIndex and it didn't work the way you need?

4265

This assumes the next token is a ], which it might not be so you'll assemble something that is not valid syntax. If tryParseVectorIndex doesn't just work, please look how it handles the closing bracket.

5428

Please remove this.

6096

Please move this to be ordered relative to the other Match_InvalidMemoryIndexed entries.

[paulwalker-arm]

llvm/lib/Target/AArch64/SMEInstrFormats.td

2399

Can this class represent "SME2 zero lookup table"? then change the one use to pass in opc.

2408

Please pass in opc and opc2 so this class better represents the encoding group.

2434

Please pass this in as a 7 bit opc to match the encoding group.

2446

Please pass this in as a 7 bit opc to match the encoding group.

2451

SME2 Lookup Table Expand One Register

2452

Can you pass in opc and opc2 so this class better represents the encoding group?

2471

With the above suggestion you can use the {1, ?, ?...} syntax when passing the opcode into sme2_luti_vector_index.

The following let Inst{17-14} = i is fine as is.

See sve_int_bin_pred_shift_imm_left for what I mean. Your code placement is fine (i.e. there's no need to move anything into multiclass sme2_luti2_vector_index to match the shift example).

2494

Please add a comment containing the name of the encoding group.

Much like my comment on sme2_luti2_vector_index can you pass in opc and opc2 so this class better represents the encoding group.

2539

Same comments as with sme2_luti_vector_vg2_index.

[CarolineConcatto]

• Address review comments

[CarolineConcatto]

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

4245–4246

Oh..I can use matchRegisterNameAlias.
By looking others tryParse<smth> it looked like I should use tryParseScalarRegister.

4245–4246

I created a RegKind::LookupTable. But don't know if that is what you meant.
Is that correct?

4256

CreateVectorIndex I cannot parse
But I can with CreateImm

4265

It has now almost the same code as tryParseVectorIndex.
But for tryParseZTOperand it creates an Imm

Operands.push_back(AArch64Operand::CreateImm(

and for tryParseVectorIndex it creates a vector index:

Operands.push_back(AArch64Operand::CreateVectorIndex(

[paulwalker-arm]

A few minor suggestions but otherwise this looks good to me.

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

2716–2717

Personally I think the following reads better.

return (Kind == RegKind::Scalar) || (Kind == RegKind::LookupTable) ? RegNum : 0;

4245–4246

Yes, the RegKind::LookupTable you've created is what I had in mind. Thanks.

4246–4247

Is this required? now that matchRegisterNameAlias is being used I expect its (RegNum == 0) check to be enough?

4265

I think we should be able to use the existing VectorIndex code with a bit of extra tweaking but for now I good with this.

4267

stray ;

4271

stray ;

5440

Please move this so it sits with the related Match_InvalidMemoryIndexed diagnostics (i.e. just before Match_InvalidMemoryIndexed8UImm5?)

6099

As above, there's an existing group for Match_InvalidMemoryIndexed#UImm# diagnostics.

[CarolineConcatto]

• Address review comments

[CarolineConcatto]

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

4246–4247

I still need the test here, because it could be also a scalar registers.
Because it uses parseRegister, all registers will go through tryParseZTOperand, including the scalars, that use matchRegisterNameAlias. The only difference between the scalar and ZT is the name.

[paulwalker-arm]

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

4246–4247

OK, I see what you mean. In which case I believe this code it just masking a bug in matchRegisterNameAlias and shows you cannot rely on MatchRegisterName for zt0. Instead we likely want something like

if (Name.equals_insensitive("zt0"))
    return Kind == RegKind::LookupTable ? AArch64::ZT0 : 0;

just after the matchMatrixRegName block. I guess you could create matchLookupTableRegName but given there's only one it doesn't seem worth it.

[c-rhodes]

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

73

this new RegKind is causing a warning

/home/culrho01/llvm-project/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:2823:11: warning: enumeration value 'LookupTable' not handled in switch [-Wswitch]
  switch (K) {
          ^

4243–4244

this is causing a warning:

/home/culrho01/llvm-project/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:4347:20: warning: object backing the pointer will be destroyed at the end of the full-expression [-Wdangling-gsl]
  StringRef Name = Tok.getString().lower();
                   ^~~~~~~~~~~~~~~~~~~~~~~

you have to be careful with StringRef::lower it returns an std::string and storing back to StringRef can cause weird behavior. In this case you don't need to lower at all anyway since matchRegisterNameAlias does a case insensitive match.

[c-rhodes]

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

4252

this is the same as StartLoc since no tokens have been lexed between calls, Lex should come before this

4262

this error message needs updating

llvm/lib/Target/AArch64/AArch64InstrFormats.td

 }
 def sme_elm_idx0_15 : Operand<i64>, ImmLeaf<i64, [{
   return ((uint64_t)Imm) <= 15;
 }]> {
   let ParserMatchClass = Imm0_15Operand;
   let PrintMethod = "printMatrixIndex";
 }
 
+// SME2 vector select offset operands
+
+// uimm3s8 predicate
+// True if the immediate is a multiple of 8 in the range [0,56].
+def UImm3s8Operand : UImmScaledMemoryIndexed<3, 8>;
+
+def uimm3s8 : Operand<i64>, ImmLeaf<i64,
+[{ return Imm >= 0 && Imm <= 56 && ((Imm % 8) == 0); }], UImmS8XForm> {
+  let PrintMethod = "printImmScale<8, false>";
+  let ParserMatchClass = UImm3s8Operand;
+}
+
 class UImmScaledMemoryIndexedRange<int Width, int Scale, int OffsetVal> : AsmOperandClass {
   let Name = "UImm" # Width # "s" # Scale # "Range";
   let DiagnosticType = "InvalidMemoryIndexedRange" # Scale # "UImm" # Width;
   let RenderMethod = "addImmScaledRangeOperands<" # Scale # ">";
   let PredicateMethod = "isUImmScaled<" # Width # ", " # Scale # ", " # OffsetVal # ", /*IsRange=*/true>";
   let ParserMethod = "tryParseImmRange";
 }
 

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

 let SubRegIndices = [zasubh0, zasubh1] in {
   def ZAB0 : AArch64Reg<0, "za0.b", [ZAH0, ZAH1]>;
 }
 
 let SubRegIndices = [zasubb] in {
   def ZA : AArch64Reg<0, "za", [ZAB0]>;
 }
 
+def ZT0 : AArch64Reg<0, "zt0">;
+
 // SME Register Classes
 
 let isAllocatable = 0 in {
   // Accumulator array
   def MPR : RegisterClass<"AArch64", [untyped], 2048, (add ZA)> {
     let Size = 2048;
   }
 
let isAllocatable = 0 in {
   def MPR64   : RegisterClass<"AArch64", [untyped],  256, (add (sequence "ZAD%u", 0, 7))> {
     let Size = 256;
   }
   def MPR128  : RegisterClass<"AArch64", [untyped],  128, (add (sequence "ZAQ%u", 0, 15))> {
     let Size = 128;
   }
 }
 
+def ZT0R : RegisterClass<"AArch64", [untyped], 512, (add ZT0)> {
+  let Size = 512;
+  let DiagnosticType = "InvalidZT0";
+}
+
 // SME Register Operands
 // There are three types of SME matrix register operands:
 // * Tiles:
 //
 //   These tiles make up the larger accumulator matrix. The tile representation
 //   has an element type suffix, e.g. za0.b or za15.q and can be any of the
 //   registers:
 //          ZAQ0..ZAQ15

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

 def AArch64_restore_za : SDNode<"AArch64ISD::RESTORE_ZA", SDTypeProfile<0, 3,
                              [SDTCisInt<0>, SDTCisPtrTy<1>]>,
                              [SDNPHasChain, SDNPSideEffect, SDNPVariadic,
                               SDNPOptInGlue]>;
 
 def AArch64ObscureCopy : SDNode<"AArch64ISD::OBSCURE_COPY", SDTypeProfile<1, 1, []>, []>;
 
 //===----------------------------------------------------------------------===//
+// Instruction naming conventions.
+//===----------------------------------------------------------------------===//
+
+// M = SME array register
+// P = Predicate register
+// C = Predicate-as-counter register
+// I = immediate
+// Z = SVE vector register
+// T = ZT0 register
+//
+
+//===----------------------------------------------------------------------===//
 // Add vector elements horizontally or vertically to ZA tile.
 //===----------------------------------------------------------------------===//
 
 def SDT_AArch64RDSVL  : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>]>;
 def AArch64rdsvl : SDNode<"AArch64ISD::RDSVL", SDT_AArch64RDSVL>;
 
 let Predicates = [HasSME] in {
 def RDSVLI_XI  : sve_int_read_vl_a<0b0, 0b11111, "rdsvl", /*streaming_sve=*/0b1>;

 defm BMOPA_TPPZZ : sme2_bmopx_tile_base<"bmopa", 0b000>;
 defm BMOPS_TPPZZ : sme2_bmopx_tile_base<"bmops", 0b001>;
 
 defm SMOPA_TPPZZ : sme2_int_mopx_tile_base<"smopa", 0b100>;
 defm SMOPS_TPPZZ : sme2_int_mopx_tile_base<"smops", 0b101>;
 
 defm UMOPA_TPPZZ : sme2_int_mopx_tile_base<"umopa", 0b110>;
 defm UMOPS_TPPZZ : sme2_int_mopx_tile_base<"umops", 0b111>;
-}
 
+def ZERO_T : sme2_zero_zt<"zero">;
+
+def LDR_TX : sme2_spill_fill_vector<"ldr", 0b0>;
+def STR_TX : sme2_spill_fill_vector<"str", 0b1>;
+
+def MOVT_XTI : sme2_movt_zt_to_scalar<"movt">;
+def MOVT_TIX : sme2_movt_scalar_to_zt<"movt">;
+
+defm LUTI2_ZTZI  : sme2_luti2_vector_index<"luti2">;
+defm LUTI2_2ZTZI : sme2_luti2_vector_vg2_index<"luti2">;
+defm LUTI2_4ZTZI : sme2_luti2_vector_vg4_index<"luti2">;
+
+defm LUTI4_ZTZI  : sme2_luti4_vector_index<"luti4">;
+defm LUTI4_2ZTZI : sme2_luti4_vector_vg2_index<"luti4">;
+defm LUTI4_4ZTZI : sme2_luti4_vector_vg4_index<"luti4">;
+}
 
 let Predicates = [HasSME2, HasSMEI16I64] in {
 defm ADD_VG2_M2ZZ_D  : sme2_dot_mla_add_sub_array_vg24_single<"add", 0b1011010, MatrixOp64, ZZ_d, ZPR4b64>;
 defm ADD_VG4_M4ZZ_D  : sme2_dot_mla_add_sub_array_vg24_single<"add", 0b1111010, MatrixOp64, ZZZZ_d, ZPR4b64>;
 defm ADD_VG2_M2Z2Z_D : sme2_dot_mla_add_sub_array_vg2_multi<"add", 0b111010, MatrixOp64, ZZ_d_mul_r>;
 defm ADD_VG4_M4Z4Z_D : sme2_dot_mla_add_sub_array_vg4_multi<"add", 0b111010, MatrixOp64, ZZZZ_d_mul_r>;
 
 defm SUB_VG2_M2ZZ_D  : sme2_dot_mla_add_sub_array_vg24_single<"sub", 0b1011011, MatrixOp64, ZZ_d, ZPR4b64>;

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

 namespace {
 
 enum class RegKind {
   Scalar,
   NeonVector,
   SVEDataVector,
   SVEPredicateVector,
   Matrix
 };
 
 enum class MatrixKind { Array, Tile, Row, Col };
 
 enum RegConstraintEqualityTy {
   EqualsReg,
   EqualsSuperReg,
   EqualsSubReg
 };
unsigned AArch64AsmParser::matchRegisterNameAlias(StringRef Name,
   if ((RegNum = MatchNeonVectorRegName(Name)))
     return Kind == RegKind::NeonVector ? RegNum : 0;
 
   if ((RegNum = matchMatrixRegName(Name)))
     return Kind == RegKind::Matrix ? RegNum : 0;
 
   // The parsed register must be of RegKind Scalar
   if ((RegNum = MatchRegisterName(Name)))
     return Kind == RegKind::Scalar ? RegNum : 0;
 
   if (!RegNum) {
     // Handle a few common aliases of registers.
     if (auto RegNum = StringSwitch<unsigned>(Name.lower())
                     .Case("fp", AArch64::FP)
                     .Case("lr",  AArch64::LR)
                     .Case("x31", AArch64::XZR)
                     .Case("w31", AArch64::WZR)
                     .Default(0))

 
 /// parseRegister - Parse a register operand.
 bool AArch64AsmParser::parseRegister(OperandVector &Operands) {
   // Try for a Neon vector register.
   if (!tryParseNeonVectorRegister(Operands))
     return false;
 
   // Otherwise try for a scalar register.
-  if (tryParseGPROperand<false>(Operands) == MatchOperand_Success)
+  if (tryParseGPROperand<false>(Operands) == MatchOperand_Success) {
+    const auto &Op = static_cast<AArch64Operand *>(Operands.back().get());
+    if (Op->isReg() && Op->getReg() == AArch64::ZT0 &&
+        getTok().is(AsmToken::LBrac))
+      // There's no comma after indexed ZT0 register, so we can parse the next
+      // operand immediately.
+      return parseOperand(Operands, false, false);
     return false;
+  }
 
   return true;
 }
 
 bool AArch64AsmParser::parseSymbolicImmVal(const MCExpr *&ImmVal) {
   bool HasELFModifier = false;
   AArch64MCExpr::VariantKind RefKind;
 
auto ParseVector = [this](unsigned &Reg, StringRef &Kind, SMLoc Loc,
     auto RegTok = getTok();
     auto ParseRes = tryParseVectorRegister(Reg, Kind, VectorKind);
     if (ParseRes == MatchOperand_Success) {
       if (parseVectorKind(Kind, VectorKind))
         return ParseRes;
       llvm_unreachable("Expected a valid vector kind");
     }
 
+    if (RegTok.is(AsmToken::Identifier) && ParseRes == MatchOperand_NoMatch &&
+        (RegTok.getString().startswith_insensitive("za") ||
+         RegTok.getString().equals_insensitive("zt0")))
+      return MatchOperand_NoMatch;
+
     if (RegTok.isNot(AsmToken::Identifier) ||
         ParseRes == MatchOperand_ParseFail ||
         (ParseRes == MatchOperand_NoMatch && NoMatchIsError &&
          !RegTok.getString().startswith_insensitive("za"))) {
       Error(Loc, "vector register expected");
       return MatchOperand_ParseFail;
     }
 
AArch64AsmParser::tryParseGPR64sp0Operand(OperandVector &Operands) {
   Operands.push_back(AArch64Operand::CreateReg(
       RegNum, RegKind::Scalar, StartLoc, getLoc(), getContext()));
   return MatchOperand_Success;
 }
 
 template <bool ParseShiftExtend, RegConstraintEqualityTy EqTy>
 OperandMatchResultTy
 AArch64AsmParser::tryParseGPROperand(OperandVector &Operands) {
   SMLoc StartLoc = getLoc();
 
   unsigned RegNum;
   OperandMatchResultTy Res = tryParseScalarRegister(RegNum);
   if (Res != MatchOperand_Success)
     return Res;
 
   // No shift/extend is the default.
   if (!ParseShiftExtend || getTok().isNot(AsmToken::Comma)) {
     Operands.push_back(AArch64Operand::CreateReg(
         RegNum, RegKind::Scalar, StartLoc, getLoc(), getContext(), EqTy));
     return MatchOperand_Success;
   }
 
   // Eat the comma
   Lex();
 
   // Match the shift
   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> ExtOpnd;
   Res = tryParseOptionalShiftExtend(ExtOpnd);
   if (Res != MatchOperand_Success)
     return Res;
 
   auto Ext = static_cast<AArch64Operand*>(ExtOpnd.back().get());
   Operands.push_back(AArch64Operand::CreateReg(
       RegNum, RegKind::Scalar, StartLoc, Ext->getEndLoc(), getContext(), EqTy,
       Ext->getShiftExtendType(), Ext->getShiftExtendAmount(),
       Ext->hasShiftExtendAmount()));
 
   return MatchOperand_Success;
 }
 
 bool AArch64AsmParser::parseOptionalMulOperand(OperandVector &Operands) {
   MCAsmParser &Parser = getParser();
 
   // Some SVE instructions have a decoration after the immediate, i.e.
   // "mul vl". We parse them here and add tokens, which must be present in the
bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
   case Match_InvalidImm1_8:
     return Error(Loc, "immediate must be an integer in range [1, 8].");
   case Match_InvalidImm1_16:
     return Error(Loc, "immediate must be an integer in range [1, 16].");
   case Match_InvalidImm1_32:
     return Error(Loc, "immediate must be an integer in range [1, 32].");
   case Match_InvalidImm1_64:
     return Error(Loc, "immediate must be an integer in range [1, 64].");
+    // For SME2
+  case Match_InvalidMemoryIndexed8UImm3:
+    return Error(Loc, "index must be a multiple of 8 in range [0, 56].");
   case Match_InvalidMemoryIndexedRange4UImm1:
   case Match_InvalidMemoryIndexedRange4UImm2:
     return Error(
         Loc,
         "vector select offset must be an immediate range of the form "
         "<immf>:<imml>, "
         "where the first immediate is a multiple of 4 in the range [0, 4] or "
         "[0, 12] "
         "depending on the instruction, and the second immediate is immf + 3.");
   case Match_InvalidMemoryIndexedRange2UImm2:
   case Match_InvalidMemoryIndexedRange2UImm3:
     return Error(
         Loc,
         "vector select offset must be an immediate range of the form "
         "<immf>:<imml>, "
         "where the first immediate is a multiple of 2 in the range [0, 6] or "
         "[0, 14] "
         "depending on the instruction, and the second immediate is immf + 1.");
return Error(Loc, "Invalid vector list, expected list with 2 consecutive "
                       "and with matching element types");
   case Match_InvalidSVEVectorListMul4x8:
   case Match_InvalidSVEVectorListMul4x16:
   case Match_InvalidSVEVectorListMul4x32:
   case Match_InvalidSVEVectorListMul4x64:
     return Error(Loc, "Invalid vector list, expected list with 4 consecutive "
                       "SVE vectors, where the first vector is a multiple of 4 "
                       "and with matching element types");
+  case Match_InvalidZT0:
+    return Error(Loc, "operand must be zt0 register");
   default:
     llvm_unreachable("unexpected error code!");
   }
 }
 
 static const char *getSubtargetFeatureName(uint64_t Val);
 
 bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidImm0_63:
   case Match_InvalidImm0_127:
   case Match_InvalidImm0_255:
   case Match_InvalidImm0_65535:
   case Match_InvalidImm1_8:
   case Match_InvalidImm1_16:
   case Match_InvalidImm1_32:
   case Match_InvalidImm1_64:
+  case Match_InvalidMemoryIndexed8UImm3:
   case Match_InvalidMemoryIndexedRange4UImm1:
   case Match_InvalidMemoryIndexedRange4UImm2:
   case Match_InvalidMemoryIndexedRange2UImm2:
   case Match_InvalidMemoryIndexedRange2UImm3:
   case Match_InvalidSVEAddSubImm8:
   case Match_InvalidSVEAddSubImm16:
   case Match_InvalidSVEAddSubImm32:
   case Match_InvalidSVEAddSubImm64:
   case Match_InvalidSVECpyImm8:
   case Match_InvalidSVECpyImm16:
   case Match_InvalidSVECpyImm32:
bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidMatrixTileVectorV8:
   case Match_InvalidMatrixTileVectorV16:
   case Match_InvalidMatrixTileVectorV32:
   case Match_InvalidMatrixTileVectorV64:
   case Match_InvalidMatrixTileVectorV128:
   case Match_InvalidSVCR:
   case Match_InvalidMatrixIndexGPR32_12_15:
   case Match_InvalidMatrixIndexGPR32_8_11:
+  case Match_InvalidZT0:
   case Match_InvalidSVEVectorListMul2x8:
   case Match_InvalidSVEVectorListMul2x16:
   case Match_InvalidSVEVectorListMul2x32:
   case Match_InvalidSVEVectorListMul2x64:
   case Match_InvalidSVEVectorListMul4x8:
   case Match_InvalidSVEVectorListMul4x16:
   case Match_InvalidSVEVectorListMul4x32:
   case Match_InvalidSVEVectorListMul4x64:

llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

for (unsigned i = 0; i < Desc.getNumOperands(); i++) {
         default:
           break;
         case AArch64::MPRRegClassID:
           MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZA));
           break;
         case AArch64::MPR8RegClassID:
           MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZAB0));
           break;
+        case AArch64::ZT0RRegClassID:
+          MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZT0));
+          break;
         }
       } else if (Desc.OpInfo[i].OperandType ==
                  AArch64::OPERAND_IMPLICIT_IMM_0) {
         MI.insert(MI.begin() + i, MCOperand::createImm(0));
       }
     }
 
     if (MI.getOpcode() == AArch64::LDR_ZA ||

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h

protected:
   void printAMIndexedWB(const MCInst *MI, unsigned OpNum,
                         const MCSubtargetInfo &STI, raw_ostream &O) {
     printAMIndexedWB(MI, OpNum, BitWidth / 8, O);
   }
 
   void printAMNoIndex(const MCInst *MI, unsigned OpNum,
                       const MCSubtargetInfo &STI, raw_ostream &O);
 
-  template <int Scale>
+  template <int Scale, bool PrintHash = true>
   void printImmScale(const MCInst *MI, unsigned OpNum,
                      const MCSubtargetInfo &STI, raw_ostream &O);
 
   template <int Scale, int Offset>
   void printImmRangeScale(const MCInst *MI, unsigned OpNum,
                           const MCSubtargetInfo &STI, raw_ostream &O);
 
   template <bool IsSVEPrefetch = false>

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

 void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
                                         const MCSubtargetInfo &STI,
                                         raw_ostream &O) {
   O << '[';
   printRegName(O, MI->getOperand(OpNum).getReg());
   O << ']';
 }
 
-template<int Scale>
+template <int Scale, bool PrintHash>
 void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
                                        const MCSubtargetInfo &STI,
                                        raw_ostream &O) {
+  if (PrintHash) {
     O << markup("<imm:") << '#'
       << formatImm(Scale * MI->getOperand(OpNum).getImm()) << markup(">");
+  } else
+    O << formatImm(Scale * MI->getOperand(OpNum).getImm());
 }
 
 template <int Scale, int Offset>
 void AArch64InstPrinter::printImmRangeScale(const MCInst *MI, unsigned OpNum,
                                             const MCSubtargetInfo &STI,
                                             raw_ostream &O) {
   unsigned FirstImm = Scale * MI->getOperand(OpNum).getImm();
   O << formatImm(FirstImm);

llvm/lib/Target/AArch64/SMEInstrFormats.td

 
 multiclass sme2_bmopx_tile_base<string mnemonic, bits<3> s>{
   def NAME: sme2_mopx_tile_base<s, ZPR32,  mnemonic>;
 }
 
 multiclass sme2_int_mopx_tile_base<string mnemonic, bits<3> s>{
   def NAME: sme2_mopx_tile_base<s, ZPR16, mnemonic>;
 }
+
+//===----------------------------------------------------------------------===///
+// ZERO instructions.
+class sme2_zero_zt<string mnemonic>
+    : I<(outs ZT0R:$ZT0), (ins ),
+         mnemonic, "\t\\{ $ZT0 \\}",
+         "", []>, Sched<[]> {
+  let Inst{31-0} = 0b11000000010010000000000000000001;
+}
+
+//===----------------------------------------------------------------------===//
+// SME2 lookup table load/store
+class sme2_spill_fill_vector<string mnemonic, bit isStore>
+    : I<!if(isStore, (outs ), (outs ZT0R:$ZTt)),
+        !if(isStore, (ins ZT0R:$ZTt, GPR64sp:$Rn), (ins GPR64sp:$Rn)),
+        mnemonic, "\t$ZTt, [$Rn]",
+        "", []>, Sched<[]> {
+  bits<5> Rn;
+  let Inst{31-22} = 0b1110000100;
+  let Inst{21}    = isStore;
+  let Inst{20-10} = 0b11111100000;
+  let Inst{9-5}   = Rn;
+  let Inst{4-0}   = 0b00000;
+
+  let mayLoad     = !not(isStore);
+  let mayStore    = isStore;
+}
+
+//===----------------------------------------------------------------------===///
+// SME2 move to/from lookup table
+class sme2_movt_zt_to_scalar<string mnemonic>
+    : I<(outs GPR64:$Rt), (ins ZT0R:$ZTt, uimm3s8:$imm3),
+         mnemonic, "\t$Rt, $ZTt[$imm3]",
+         "", []>, Sched<[]> {
+  bits<3> imm3;
+  bits<5> Rt;
+  let Inst{31-15} = 0b11000000010011000;
+  let Inst{14-12} = imm3;
+  let Inst{11-5}  = 0b0011111;
+  let Inst{4-0}   = Rt;
+}
+
+class sme2_movt_scalar_to_zt<string mnemonic>
+    : I<(outs ZT0R:$ZTt), (ins uimm3s8:$imm3, GPR64:$Rt),
+         mnemonic, "\t$ZTt[$imm3], $Rt",
+         "", []>, Sched<[]> {
+  bits<3> imm3;
+  bits<5> Rt;
+  let Inst{31-15} = 0b11000000010011100;
+  let Inst{14-12} = imm3;
+  let Inst{11-5}  = 0b0011111;
+  let Inst{4-0}   = Rt;
+}
+
+//===----------------------------------------------------------------------===//
+// SME2 Lookup Table Expand
+class sme2_luti_vector_index<bits<2> sz, RegisterOperand vector_ty,
+                             AsmVectorIndexOpnd index_ty, string mnemonic>
+    : I<(outs vector_ty:$Zd),
+        (ins ZT0R:$ZTt, ZPRAny:$Zn, index_ty:$i),
+        mnemonic, "\t$Zd, $ZTt, $Zn$i",
+        "", []>, Sched<[]> {
+  bits<5> Zn;
+  bits<5> Zd;
+  let Inst{31-19} = 0b1100000011001;
+  let Inst{13-12} = sz;
+  let Inst{11-10} = 0b00;
+  let Inst{9-5}   = Zn;
+  let Inst{4-0}   = Zd;
+}
+
+class sme2_luti2_vector_index<bits<2> sz, RegisterOperand vector_ty,
+                              string mnemonic>
+    : sme2_luti_vector_index<sz, vector_ty, VectorIndexB, mnemonic> {
+  bits<4> i;
+  let Inst{18}    = 0b1;
+  let Inst{17-14} = i;
+}
+
+multiclass sme2_luti2_vector_index<string mnemonic> {
+  def _B : sme2_luti2_vector_index<0b00, ZPR8, mnemonic>;
+  def _H : sme2_luti2_vector_index<0b01, ZPR16, mnemonic>;
+  def _S : sme2_luti2_vector_index<0b10, ZPR32, mnemonic>;
+}
+
+class sme2_luti4_vector_index<bits<2> sz, RegisterOperand vector_ty,
+                              string mnemonic>
+    : sme2_luti_vector_index<sz, vector_ty, VectorIndexH, mnemonic> {
+  bits<3> i;
+  let Inst{18-17} = 0b01;
+  let Inst{16-14} = i;
+}
+
+multiclass sme2_luti4_vector_index<string mnemonic> {
+  def _B : sme2_luti4_vector_index<0b00, ZPR8, mnemonic>;
+  def _H : sme2_luti4_vector_index<0b01, ZPR16, mnemonic>;
+  def _S : sme2_luti4_vector_index<0b10, ZPR32, mnemonic>;
+}
+class sme2_luti_vector_vg2_index<bits<2> sz, RegisterOperand vector_ty,
+                                 AsmVectorIndexOpnd index_ty, string mnemonic>
+    : I<(outs vector_ty:$Zd),
+        (ins ZT0R:$ZTt, ZPRAny:$Zn, index_ty:$i),
+        mnemonic, "\t$Zd, $ZTt, $Zn$i",
+        "", []>, Sched<[]> {
+  bits<5> Zn;
+  bits<4> Zd;
+  let Inst{31-19} = 0b1100000010001;
+  let Inst{14}    = 0b1;
+  let Inst{13-12} = sz;
+  let Inst{11-10} = 0b00;
+  let Inst{9-5}   = Zn;
+  let Inst{4-1}   = Zd;
+  let Inst{0}     = 0b0;
+}
+
+class sme2_luti2_vector_vg2_index<bits<2> sz, RegisterOperand vector_ty,
+                                  string mnemonic>
+    : sme2_luti_vector_vg2_index<sz, vector_ty, VectorIndexH, mnemonic> {
+  bits<3> i;
+  let Inst{18}    = 0b1;
+  let Inst{17-15} = i;
+}
+
+multiclass sme2_luti2_vector_vg2_index<string mnemonic> {
+  def _B : sme2_luti2_vector_vg2_index<0b00, ZZ_b_mul_r, mnemonic>;
+  def _H : sme2_luti2_vector_vg2_index<0b01, ZZ_h_mul_r, mnemonic>;
+  def _S : sme2_luti2_vector_vg2_index<0b10, ZZ_s_mul_r, mnemonic>;
+}
+
+class sme2_luti4_vector_vg2_index<bits<2> sz, RegisterOperand vector_ty,
+                                 string mnemonic>
+    : sme2_luti_vector_vg2_index<sz, vector_ty, VectorIndexS, mnemonic> {
+  bits<2> i;
+  let Inst{18-17} = 0b01;
+  let Inst{16-15} = i;
+}
+
+multiclass sme2_luti4_vector_vg2_index<string mnemonic> {
+  def _B : sme2_luti4_vector_vg2_index<0b00, ZZ_b_mul_r, mnemonic>;
+  def _H : sme2_luti4_vector_vg2_index<0b01, ZZ_h_mul_r, mnemonic>;
+  def _S : sme2_luti4_vector_vg2_index<0b10, ZZ_s_mul_r, mnemonic>;
+}
+
+class sme2_luti_vector_vg4_index<bits<2> sz, RegisterOperand vector_ty,
+                                 AsmVectorIndexOpnd index_ty, string mnemonic>
+    : I<(outs vector_ty:$Zd),
+        (ins ZT0R:$ZTt, ZPRAny:$Zn, index_ty:$i),
+        mnemonic, "\t$Zd, $ZTt, $Zn$i",
+        "", []>, Sched<[]> {
+  bits<5> Zn;
+  bits<3> Zd;
+  let Inst{31-19} = 0b1100000010001;
+  let Inst{15-14} = 0b10;
+  let Inst{13-12} = sz;
+  let Inst{11-10} = 0b00;
+  let Inst{9-5}   = Zn;
+  let Inst{4-2}   = Zd;
+  let Inst{1-0}   = 0b00;
+}
+
+class sme2_luti2_vector_vg4_index<bits<2> sz, RegisterOperand vector_ty,
+                                  string mnemonic>
+    : sme2_luti_vector_vg4_index<sz, vector_ty, VectorIndexS, mnemonic> {
+  bits<2> i;
+  let Inst{18}    = 0b1;
+  let Inst{17-16} = i;
+}
+
+multiclass sme2_luti2_vector_vg4_index<string mnemonic> {
+  def _B : sme2_luti2_vector_vg4_index<0b00, ZZZZ_b_mul_r, mnemonic>;
+  def _H : sme2_luti2_vector_vg4_index<0b01, ZZZZ_h_mul_r, mnemonic>;
+  def _S : sme2_luti2_vector_vg4_index<0b10, ZZZZ_s_mul_r, mnemonic>;
+}
+
+class sme2_luti4_vector_vg4_index<bits<2> sz, RegisterOperand vector_ty,
+                                  string mnemonic>
+    : sme2_luti_vector_vg4_index<sz, vector_ty, VectorIndexD, mnemonic> {
+  bits<1> i;
+  let Inst{18-17} = 0b01;
+  let Inst{16}    = i;
+}
+
+multiclass sme2_luti4_vector_vg4_index<string mnemonic> {
+  def _H : sme2_luti4_vector_vg4_index<0b01, ZZZZ_h_mul_r, mnemonic>;
+  def _S : sme2_luti4_vector_vg4_index<0b10, ZZZZ_s_mul_r, mnemonic>;
+}

llvm/test/MC/AArch64/SME2/ldr-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2  2>&1 < %s| FileCheck %s
+
+ldr zt1, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be zt0 register
+// CHECK-NEXT: ldr zt1, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/ldr.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+ldr     zt0, [x0]  // 11100001-00011111-10000000-00000000
+// CHECK-INST: ldr     zt0, [x0]
+// CHECK-ENCODING: [0x00,0x80,0x1f,0xe1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: e11f8000 <unknown>
+
+ldr     zt0, [x10]  // 11100001-00011111-10000001-01000000
+// CHECK-INST: ldr     zt0, [x10]
+// CHECK-ENCODING: [0x40,0x81,0x1f,0xe1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: e11f8140 <unknown>
+
+ldr     zt0, [x13]  // 11100001-00011111-10000001-10100000
+// CHECK-INST: ldr     zt0, [x13]
+// CHECK-ENCODING: [0xa0,0x81,0x1f,0xe1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: e11f81a0 <unknown>
+
+ldr     zt0, [sp]  // 11100001-00011111-10000011-11100000
+// CHECK-INST: ldr     zt0, [sp]
+// CHECK-ENCODING: [0xe0,0x83,0x1f,0xe1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: e11f83e0 <unknown>
+

llvm/test/MC/AArch64/SME2/luti2-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid lane indices
+
+luti2 z0.h, zt0, z0[16]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 15].
+// CHECK-NEXT: luti2 z0.h, zt0, z0[16]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+luti2 z0.s, zt0, z0[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 15].
+// CHECK-NEXT: luti2 z0.s, zt0, z0[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+luti2 {z0.b-z1.b}, zt0, z0[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: luti2 {z0.b-z1.b}, zt0, z0[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+luti2 {z0.h-z1.h}, zt0, z0[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: luti2 {z0.h-z1.h}, zt0, z0[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+luti2 {z0.s-z3.s}, zt0, z0[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: luti2 {z0.s-z3.s}, zt0, z0[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+luti2 {z0.b-z3.b}, zt0, z0[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: luti2 {z0.b-z3.b}, zt0, z0[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector lists
+
+luti2 {z0.h-z2.h}, zt0, z0[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: luti2 {z0.h-z2.h}, zt0, z0[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+luti2 {z1.s-z2.s}, zt0, z0[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: luti2 {z1.s-z2.s}, zt0, z0[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+luti2 {z1.s-z4.s}, zt0, z0[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: luti2 {z1.s-z4.s}, zt0, z0[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+luti2 {z0.d-z1.d}, zt0, z0[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: luti2 {z0.d-z1.d}, zt0, z0[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/luti2.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+luti2   z0.h, zt0, z0[0]  // 11000000-11001100-00010000-00000000
+// CHECK-INST: luti2   z0.h, zt0, z0[0]
+// CHECK-ENCODING: [0x00,0x10,0xcc,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0cc1000 <unknown>
+
+luti2   z21.h, zt0, z10[5]  // 11000000-11001101-01010001-01010101
+// CHECK-INST: luti2   z21.h, zt0, z10[5]
+// CHECK-ENCODING: [0x55,0x51,0xcd,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0cd5155 <unknown>
+
+luti2   z23.h, zt0, z13[3]  // 11000000-11001100-11010001-10110111
+// CHECK-INST: luti2   z23.h, zt0, z13[3]
+// CHECK-ENCODING: [0xb7,0xd1,0xcc,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0ccd1b7 <unknown>
+
+luti2   z31.h, zt0, z31[15]  // 11000000-11001111-11010011-11111111
+// CHECK-INST: luti2   z31.h, zt0, z31[15]
+// CHECK-ENCODING: [0xff,0xd3,0xcf,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0cfd3ff <unknown>
+
+
+luti2   z0.s, zt0, z0[0]  // 11000000-11001100-00100000-00000000
+// CHECK-INST: luti2   z0.s, zt0, z0[0]
+// CHECK-ENCODING: [0x00,0x20,0xcc,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0cc2000 <unknown>
+
+luti2   z21.s, zt0, z10[5]  // 11000000-11001101-01100001-01010101
+// CHECK-INST: luti2   z21.s, zt0, z10[5]
+// CHECK-ENCODING: [0x55,0x61,0xcd,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0cd6155 <unknown>
+
+luti2   z23.s, zt0, z13[3]  // 11000000-11001100-11100001-10110111
+// CHECK-INST: luti2   z23.s, zt0, z13[3]
+// CHECK-ENCODING: [0xb7,0xe1,0xcc,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0cce1b7 <unknown>
+
+luti2   z31.s, zt0, z31[15]  // 11000000-11001111-11100011-11111111
+// CHECK-INST: luti2   z31.s, zt0, z31[15]
+// CHECK-ENCODING: [0xff,0xe3,0xcf,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0cfe3ff <unknown>
+
+
+luti2   z0.b, zt0, z0[0]  // 11000000-11001100-00000000-00000000
+// CHECK-INST: luti2   z0.b, zt0, z0[0]
+// CHECK-ENCODING: [0x00,0x00,0xcc,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0cc0000 <unknown>
+
+luti2   z21.b, zt0, z10[5]  // 11000000-11001101-01000001-01010101
+// CHECK-INST: luti2   z21.b, zt0, z10[5]
+// CHECK-ENCODING: [0x55,0x41,0xcd,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0cd4155 <unknown>
+
+luti2   z23.b, zt0, z13[3]  // 11000000-11001100-11000001-10110111
+// CHECK-INST: luti2   z23.b, zt0, z13[3]
+// CHECK-ENCODING: [0xb7,0xc1,0xcc,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0ccc1b7 <unknown>
+
+luti2   z31.b, zt0, z31[15]  // 11000000-11001111-11000011-11111111
+// CHECK-INST: luti2   z31.b, zt0, z31[15]
+// CHECK-ENCODING: [0xff,0xc3,0xcf,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0cfc3ff <unknown>
+
+
+luti2   {z0.h - z1.h}, zt0, z0[0]  // 11000000-10001100-01010000-00000000
+// CHECK-INST: luti2   { z0.h, z1.h }, zt0, z0[0]
+// CHECK-ENCODING: [0x00,0x50,0x8c,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08c5000 <unknown>
+
+luti2   {z20.h - z21.h}, zt0, z10[2]  // 11000000-10001101-01010001-01010100
+// CHECK-INST: luti2   { z20.h, z21.h }, zt0, z10[2]
+// CHECK-ENCODING: [0x54,0x51,0x8d,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08d5154 <unknown>
+
+luti2   {z22.h - z23.h}, zt0, z13[1]  // 11000000-10001100-11010001-10110110
+// CHECK-INST: luti2   { z22.h, z23.h }, zt0, z13[1]
+// CHECK-ENCODING: [0xb6,0xd1,0x8c,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08cd1b6 <unknown>
+
+luti2   {z30.h - z31.h}, zt0, z31[7]  // 11000000-10001111-11010011-11111110
+// CHECK-INST: luti2   { z30.h, z31.h }, zt0, z31[7]
+// CHECK-ENCODING: [0xfe,0xd3,0x8f,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08fd3fe <unknown>
+
+
+luti2   {z0.s - z1.s}, zt0, z0[0]  // 11000000-10001100-01100000-00000000
+// CHECK-INST: luti2   { z0.s, z1.s }, zt0, z0[0]
+// CHECK-ENCODING: [0x00,0x60,0x8c,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08c6000 <unknown>
+
+luti2   {z20.s - z21.s}, zt0, z10[2]  // 11000000-10001101-01100001-01010100
+// CHECK-INST: luti2   { z20.s, z21.s }, zt0, z10[2]
+// CHECK-ENCODING: [0x54,0x61,0x8d,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08d6154 <unknown>
+
+luti2   {z22.s - z23.s}, zt0, z13[1]  // 11000000-10001100-11100001-10110110
+// CHECK-INST: luti2   { z22.s, z23.s }, zt0, z13[1]
+// CHECK-ENCODING: [0xb6,0xe1,0x8c,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08ce1b6 <unknown>
+
+luti2   {z30.s - z31.s}, zt0, z31[7]  // 11000000-10001111-11100011-11111110
+// CHECK-INST: luti2   { z30.s, z31.s }, zt0, z31[7]
+// CHECK-ENCODING: [0xfe,0xe3,0x8f,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08fe3fe <unknown>
+
+
+luti2   {z0.b - z1.b}, zt0, z0[0]  // 11000000-10001100-01000000-00000000
+// CHECK-INST: luti2   { z0.b, z1.b }, zt0, z0[0]
+// CHECK-ENCODING: [0x00,0x40,0x8c,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08c4000 <unknown>
+
+luti2   {z20.b - z21.b}, zt0, z10[2]  // 11000000-10001101-01000001-01010100
+// CHECK-INST: luti2   { z20.b, z21.b }, zt0, z10[2]
+// CHECK-ENCODING: [0x54,0x41,0x8d,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08d4154 <unknown>
+
+luti2   {z22.b - z23.b}, zt0, z13[1]  // 11000000-10001100-11000001-10110110
+// CHECK-INST: luti2   { z22.b, z23.b }, zt0, z13[1]
+// CHECK-ENCODING: [0xb6,0xc1,0x8c,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08cc1b6 <unknown>
+
+luti2   {z30.b - z31.b}, zt0, z31[7]  // 11000000-10001111-11000011-11111110
+// CHECK-INST: luti2   { z30.b, z31.b }, zt0, z31[7]
+// CHECK-ENCODING: [0xfe,0xc3,0x8f,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08fc3fe <unknown>
+
+
+luti2   {z0.h - z3.h}, zt0, z0[0]  // 11000000-10001100-10010000-00000000
+// CHECK-INST: luti2   { z0.h - z3.h }, zt0, z0[0]
+// CHECK-ENCODING: [0x00,0x90,0x8c,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08c9000 <unknown>
+
+luti2   {z20.h - z23.h}, zt0, z10[1]  // 11000000-10001101-10010001-01010100
+// CHECK-INST: luti2   { z20.h - z23.h }, zt0, z10[1]
+// CHECK-ENCODING: [0x54,0x91,0x8d,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08d9154 <unknown>
+
+luti2   {z20.h - z23.h}, zt0, z13[0]  // 11000000-10001100-10010001-10110100
+// CHECK-INST: luti2   { z20.h - z23.h }, zt0, z13[0]
+// CHECK-ENCODING: [0xb4,0x91,0x8c,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08c91b4 <unknown>
+
+luti2   {z28.h - z31.h}, zt0, z31[3]  // 11000000-10001111-10010011-11111100
+// CHECK-INST: luti2   { z28.h - z31.h }, zt0, z31[3]
+// CHECK-ENCODING: [0xfc,0x93,0x8f,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08f93fc <unknown>
+
+
+luti2   {z0.s - z3.s}, zt0, z0[0]  // 11000000-10001100-10100000-00000000
+// CHECK-INST: luti2   { z0.s - z3.s }, zt0, z0[0]
+// CHECK-ENCODING: [0x00,0xa0,0x8c,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08ca000 <unknown>
+
+luti2   {z20.s - z23.s}, zt0, z10[1]  // 11000000-10001101-10100001-01010100
+// CHECK-INST: luti2   { z20.s - z23.s }, zt0, z10[1]
+// CHECK-ENCODING: [0x54,0xa1,0x8d,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08da154 <unknown>
+
+luti2   {z20.s - z23.s}, zt0, z13[0]  // 11000000-10001100-10100001-10110100
+// CHECK-INST: luti2   { z20.s - z23.s }, zt0, z13[0]
+// CHECK-ENCODING: [0xb4,0xa1,0x8c,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08ca1b4 <unknown>
+
+luti2   {z28.s - z31.s}, zt0, z31[3]  // 11000000-10001111-10100011-11111100
+// CHECK-INST: luti2   { z28.s - z31.s }, zt0, z31[3]
+// CHECK-ENCODING: [0xfc,0xa3,0x8f,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08fa3fc <unknown>
+
+
+luti2   {z0.b - z3.b}, zt0, z0[0]  // 11000000-10001100-10000000-00000000
+// CHECK-INST: luti2   { z0.b - z3.b }, zt0, z0[0]
+// CHECK-ENCODING: [0x00,0x80,0x8c,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08c8000 <unknown>
+
+luti2   {z20.b - z23.b}, zt0, z10[1]  // 11000000-10001101-10000001-01010100
+// CHECK-INST: luti2   { z20.b - z23.b }, zt0, z10[1]
+// CHECK-ENCODING: [0x54,0x81,0x8d,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08d8154 <unknown>
+
+luti2   {z20.b - z23.b}, zt0, z13[0]  // 11000000-10001100-10000001-10110100
+// CHECK-INST: luti2   { z20.b - z23.b }, zt0, z13[0]
+// CHECK-ENCODING: [0xb4,0x81,0x8c,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08c81b4 <unknown>
+
+luti2   {z28.b - z31.b}, zt0, z31[3]  // 11000000-10001111-10000011-11111100
+// CHECK-INST: luti2   { z28.b - z31.b }, zt0, z31[3]
+// CHECK-ENCODING: [0xfc,0x83,0x8f,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08f83fc <unknown>
+

llvm/test/MC/AArch64/SME2/luti4-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid lane indices
+
+luti4 z0.h, zt0, z0[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: luti4 z0.h, zt0, z0[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+luti4 z0.s, zt0, z0[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: luti4 z0.s, zt0, z0[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+luti4 {z0.b-z1.b}, zt0, z0[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: luti4 {z0.b-z1.b}, zt0, z0[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+luti4 {z0.h-z1.h}, zt0, z0[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: luti4 {z0.h-z1.h}, zt0, z0[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+luti4 {z0.s-z3.s}, zt0, z0[2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
+// CHECK-NEXT: luti4 {z0.s-z3.s}, zt0, z0[2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+luti4 {z0.h-z3.h}, zt0, z0[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
+// CHECK-NEXT: luti4 {z0.h-z3.h}, zt0, z0[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector lists
+
+luti4 {z0.h-z2.h}, zt0, z0[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: luti4 {z0.h-z2.h}, zt0, z0[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+luti4 {z1.s-z2.s}, zt0, z0[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: luti4 {z1.s-z2.s}, zt0, z0[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+luti4 {z1.s-z4.s}, zt0, z0[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: luti4 {z1.s-z4.s}, zt0, z0[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+luti4 {z0.d-z1.d}, zt0, z0[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: luti4 {z0.d-z1.d}, zt0, z0[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/luti4.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+luti4   z0.h, zt0, z0[0]  // 11000000-11001010-00010000-00000000
+// CHECK-INST: luti4   z0.h, zt0, z0[0]
+// CHECK-ENCODING: [0x00,0x10,0xca,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0ca1000 <unknown>
+
+luti4   z21.h, zt0, z10[5]  // 11000000-11001011-01010001-01010101
+// CHECK-INST: luti4   z21.h, zt0, z10[5]
+// CHECK-ENCODING: [0x55,0x51,0xcb,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0cb5155 <unknown>
+
+luti4   z23.h, zt0, z13[3]  // 11000000-11001010-11010001-10110111
+// CHECK-INST: luti4   z23.h, zt0, z13[3]
+// CHECK-ENCODING: [0xb7,0xd1,0xca,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0cad1b7 <unknown>
+
+luti4   z31.h, zt0, z31[7]  // 11000000-11001011-11010011-11111111
+// CHECK-INST: luti4   z31.h, zt0, z31[7]
+// CHECK-ENCODING: [0xff,0xd3,0xcb,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0cbd3ff <unknown>
+
+
+luti4   z0.s, zt0, z0[0]  // 11000000-11001010-00100000-00000000
+// CHECK-INST: luti4   z0.s, zt0, z0[0]
+// CHECK-ENCODING: [0x00,0x20,0xca,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0ca2000 <unknown>
+
+luti4   z21.s, zt0, z10[5]  // 11000000-11001011-01100001-01010101
+// CHECK-INST: luti4   z21.s, zt0, z10[5]
+// CHECK-ENCODING: [0x55,0x61,0xcb,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0cb6155 <unknown>
+
+luti4   z23.s, zt0, z13[3]  // 11000000-11001010-11100001-10110111
+// CHECK-INST: luti4   z23.s, zt0, z13[3]
+// CHECK-ENCODING: [0xb7,0xe1,0xca,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0cae1b7 <unknown>
+
+luti4   z31.s, zt0, z31[7]  // 11000000-11001011-11100011-11111111
+// CHECK-INST: luti4   z31.s, zt0, z31[7]
+// CHECK-ENCODING: [0xff,0xe3,0xcb,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0cbe3ff <unknown>
+
+
+luti4   z0.b, zt0, z0[0]  // 11000000-11001010-00000000-00000000
+// CHECK-INST: luti4   z0.b, zt0, z0[0]
+// CHECK-ENCODING: [0x00,0x00,0xca,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0ca0000 <unknown>
+
+luti4   z21.b, zt0, z10[5]  // 11000000-11001011-01000001-01010101
+// CHECK-INST: luti4   z21.b, zt0, z10[5]
+// CHECK-ENCODING: [0x55,0x41,0xcb,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0cb4155 <unknown>
+
+luti4   z23.b, zt0, z13[3]  // 11000000-11001010-11000001-10110111
+// CHECK-INST: luti4   z23.b, zt0, z13[3]
+// CHECK-ENCODING: [0xb7,0xc1,0xca,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0cac1b7 <unknown>
+
+luti4   z31.b, zt0, z31[7]  // 11000000-11001011-11000011-11111111
+// CHECK-INST: luti4   z31.b, zt0, z31[7]
+// CHECK-ENCODING: [0xff,0xc3,0xcb,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0cbc3ff <unknown>
+
+
+luti4   {z0.h - z1.h}, zt0, z0[0]  // 11000000-10001010-01010000-00000000
+// CHECK-INST: luti4   { z0.h, z1.h }, zt0, z0[0]
+// CHECK-ENCODING: [0x00,0x50,0x8a,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08a5000 <unknown>
+
+luti4   {z20.h - z21.h}, zt0, z10[2]  // 11000000-10001011-01010001-01010100
+// CHECK-INST: luti4   { z20.h, z21.h }, zt0, z10[2]
+// CHECK-ENCODING: [0x54,0x51,0x8b,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08b5154 <unknown>
+
+luti4   {z22.h - z23.h}, zt0, z13[1]  // 11000000-10001010-11010001-10110110
+// CHECK-INST: luti4   { z22.h, z23.h }, zt0, z13[1]
+// CHECK-ENCODING: [0xb6,0xd1,0x8a,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08ad1b6 <unknown>
+
+luti4   {z30.h - z31.h}, zt0, z31[3]  // 11000000-10001011-11010011-11111110
+// CHECK-INST: luti4   { z30.h, z31.h }, zt0, z31[3]
+// CHECK-ENCODING: [0xfe,0xd3,0x8b,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08bd3fe <unknown>
+
+
+luti4   {z0.s - z1.s}, zt0, z0[0]  // 11000000-10001010-01100000-00000000
+// CHECK-INST: luti4   { z0.s, z1.s }, zt0, z0[0]
+// CHECK-ENCODING: [0x00,0x60,0x8a,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08a6000 <unknown>
+
+luti4   {z20.s - z21.s}, zt0, z10[2]  // 11000000-10001011-01100001-01010100
+// CHECK-INST: luti4   { z20.s, z21.s }, zt0, z10[2]
+// CHECK-ENCODING: [0x54,0x61,0x8b,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08b6154 <unknown>
+
+luti4   {z22.s - z23.s}, zt0, z13[1]  // 11000000-10001010-11100001-10110110
+// CHECK-INST: luti4   { z22.s, z23.s }, zt0, z13[1]
+// CHECK-ENCODING: [0xb6,0xe1,0x8a,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08ae1b6 <unknown>
+
+luti4   {z30.s - z31.s}, zt0, z31[3]  // 11000000-10001011-11100011-11111110
+// CHECK-INST: luti4   { z30.s, z31.s }, zt0, z31[3]
+// CHECK-ENCODING: [0xfe,0xe3,0x8b,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08be3fe <unknown>
+
+
+luti4   {z0.b - z1.b}, zt0, z0[0]  // 11000000-10001010-01000000-00000000
+// CHECK-INST: luti4   { z0.b, z1.b }, zt0, z0[0]
+// CHECK-ENCODING: [0x00,0x40,0x8a,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08a4000 <unknown>
+
+luti4   {z20.b - z21.b}, zt0, z10[2]  // 11000000-10001011-01000001-01010100
+// CHECK-INST: luti4   { z20.b, z21.b }, zt0, z10[2]
+// CHECK-ENCODING: [0x54,0x41,0x8b,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08b4154 <unknown>
+
+luti4   {z22.b - z23.b}, zt0, z13[1]  // 11000000-10001010-11000001-10110110
+// CHECK-INST: luti4   { z22.b, z23.b }, zt0, z13[1]
+// CHECK-ENCODING: [0xb6,0xc1,0x8a,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08ac1b6 <unknown>
+
+luti4   {z30.b - z31.b}, zt0, z31[3]  // 11000000-10001011-11000011-11111110
+// CHECK-INST: luti4   { z30.b, z31.b }, zt0, z31[3]
+// CHECK-ENCODING: [0xfe,0xc3,0x8b,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08bc3fe <unknown>
+
+
+luti4   {z0.h - z3.h}, zt0, z0[0]  // 11000000-10001010-10010000-00000000
+// CHECK-INST: luti4   { z0.h - z3.h }, zt0, z0[0]
+// CHECK-ENCODING: [0x00,0x90,0x8a,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08a9000 <unknown>
+
+luti4   {z20.h - z23.h}, zt0, z10[1]  // 11000000-10001011-10010001-01010100
+// CHECK-INST: luti4   { z20.h - z23.h }, zt0, z10[1]
+// CHECK-ENCODING: [0x54,0x91,0x8b,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08b9154 <unknown>
+
+luti4   {z20.h - z23.h}, zt0, z13[0]  // 11000000-10001010-10010001-10110100
+// CHECK-INST: luti4   { z20.h - z23.h }, zt0, z13[0]
+// CHECK-ENCODING: [0xb4,0x91,0x8a,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08a91b4 <unknown>
+
+luti4   {z28.h - z31.h}, zt0, z31[1]  // 11000000-10001011-10010011-11111100
+// CHECK-INST: luti4   { z28.h - z31.h }, zt0, z31[1]
+// CHECK-ENCODING: [0xfc,0x93,0x8b,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08b93fc <unknown>
+
+
+luti4   {z0.s - z3.s}, zt0, z0[0]  // 11000000-10001010-10100000-00000000
+// CHECK-INST: luti4   { z0.s - z3.s }, zt0, z0[0]
+// CHECK-ENCODING: [0x00,0xa0,0x8a,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08aa000 <unknown>
+
+luti4   {z20.s - z23.s}, zt0, z10[1]  // 11000000-10001011-10100001-01010100
+// CHECK-INST: luti4   { z20.s - z23.s }, zt0, z10[1]
+// CHECK-ENCODING: [0x54,0xa1,0x8b,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08ba154 <unknown>
+
+luti4   {z20.s - z23.s}, zt0, z13[0]  // 11000000-10001010-10100001-10110100
+// CHECK-INST: luti4   { z20.s - z23.s }, zt0, z13[0]
+// CHECK-ENCODING: [0xb4,0xa1,0x8a,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08aa1b4 <unknown>
+
+luti4   {z28.s - z31.s}, zt0, z31[1]  // 11000000-10001011-10100011-11111100
+// CHECK-INST: luti4   { z28.s - z31.s }, zt0, z31[1]
+// CHECK-ENCODING: [0xfc,0xa3,0x8b,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c08ba3fc <unknown>
+

llvm/test/MC/AArch64/SME2/movt-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s| FileCheck %s
+
+// index must be a multiple of 8 in range [0, 56].
+// --------------------------------------------------------------------------//
+
+movt x0, zt0[57]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 56].
+// CHECK-NEXT: movt x0, zt0[57]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movt x0, zt0[58]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 56].
+// CHECK-NEXT: movt x0, zt0[58]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movt x0, zt0[64]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 56].
+// CHECK-NEXT: movt x0, zt0[64]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movt x0, zt0[72]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 56].
+// CHECK-NEXT: movt x0, zt0[72]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid zt0 register
+
+movt x0, zt1[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
+// CHECK-NEXT: movt x0, zt1[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/movt.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+movt    x0, zt0[0]  // 11000000-01001100-00000011-11100000
+// CHECK-INST: movt    x0, zt0[0]
+// CHECK-ENCODING: [0xe0,0x03,0x4c,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c04c03e0 <unknown>
+
+movt    x21, zt0[40]  // 11000000-01001100-01010011-11110101
+// CHECK-INST: movt    x21, zt0[40]
+// CHECK-ENCODING: [0xf5,0x53,0x4c,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c04c53f5 <unknown>
+
+movt    x23, zt0[48]  // 11000000-01001100-01100011-11110111
+// CHECK-INST: movt    x23, zt0[48]
+// CHECK-ENCODING: [0xf7,0x63,0x4c,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c04c63f7 <unknown>
+
+movt    xzr, zt0[56]  // 11000000-01001100-01110011-11111111
+// CHECK-INST: movt    xzr, zt0[56]
+// CHECK-ENCODING: [0xff,0x73,0x4c,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c04c73ff <unknown>
+
+
+movt    zt0[0], x0  // 11000000-01001110-00000011-11100000
+// CHECK-INST: movt    zt0[0], x0
+// CHECK-ENCODING: [0xe0,0x03,0x4e,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c04e03e0 <unknown>
+
+movt    zt0[40], x21  // 11000000-01001110-01010011-11110101
+// CHECK-INST: movt    zt0[40], x21
+// CHECK-ENCODING: [0xf5,0x53,0x4e,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c04e53f5 <unknown>
+
+movt    zt0[48], x23  // 11000000-01001110-01100011-11110111
+// CHECK-INST: movt    zt0[48], x23
+// CHECK-ENCODING: [0xf7,0x63,0x4e,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c04e63f7 <unknown>
+
+movt    zt0[56], xzr  // 11000000-01001110-01110011-11111111
+// CHECK-INST: movt    zt0[56], xzr
+// CHECK-ENCODING: [0xff,0x73,0x4e,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c04e73ff <unknown>
+

llvm/test/MC/AArch64/SME2/str-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2  2>&1 < %s| FileCheck %s
+
+str zt, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be zt0 register
+// CHECK-NEXT: str zt, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/str.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+str     zt0, [x0]  // 11100001-00111111-10000000-00000000
+// CHECK-INST: str     zt0, [x0]
+// CHECK-ENCODING: [0x00,0x80,0x3f,0xe1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: e13f8000 <unknown>
+
+str     zt0, [x10]  // 11100001-00111111-10000001-01000000
+// CHECK-INST: str     zt0, [x10]
+// CHECK-ENCODING: [0x40,0x81,0x3f,0xe1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: e13f8140 <unknown>
+
+str     zt0, [x13]  // 11100001-00111111-10000001-10100000
+// CHECK-INST: str     zt0, [x13]
+// CHECK-ENCODING: [0xa0,0x81,0x3f,0xe1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: e13f81a0 <unknown>
+
+str     zt0, [sp]  // 11100001-00111111-10000011-11100000
+// CHECK-INST: str     zt0, [sp]
+// CHECK-ENCODING: [0xe0,0x83,0x3f,0xe1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: e13f83e0 <unknown>
+

llvm/test/MC/AArch64/SME2/zero.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+zero    {zt0}  // 11000000-01001000-00000000-00000001
+// CHECK-INST: zero    { zt0 }
+// CHECK-ENCODING: [0x01,0x00,0x48,0xc0]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c0480001 <unknown>
+