[AArch64]SME2 Single and multiple vectors SVE Destructive two/four registers[part2]

[CarolineConcatto]

Summary

This patch adds the assembly/disassembly for the following instruction:
INT:

SMAX (multiple and single vector): Multi-vector signed maximum by vector.
     (multiple vectors): Multi-vector signed maximum.
SMIN (multiple and single vector): Multi-vector signed minimum by vector.
     (multiple vectors): Multi-vector signed minimum.
UMAX (multiple and single vector): Multi-vector unsigned maximum by vector.
     (multiple vectors): Multi-vector unsigned maximum.
UMIN (multiple and single vector): Multi-vector unsigned minimum by vector.
     (multiple vectors): Multi-vector unsigned minimum.
SRSHL (multiple and single vector): Multi-vector signed rounding shift left by vector.
      (multiple vectors): Multi-vector signed rounding shift left.
URSHL (multiple and single vector): Multi-vector unsigned rounding shift left by vector.
      (multiple vectors): Multi-vector unsigned rounding shift left.

FP:

FMAX (multiple and single vector): Multi-vector floating-point maximum by vector.
     (multiple vectors): Multi-vector floating-point maximum.
FMAXNM (multiple and single vector): Multi-vector floating-point maximum number by vector.
       (multiple vectors): Multi-vector floating-point maximum number.
FMIN (multiple and single vector): Multi-vector floating-point minimum by vector.
     (multiple vectors): Multi-vector floating-point minimum.
FMINNM (multiple and single vector): Multi-vector floating-point minimum number by vector.
       (multiple vectors): Multi-vector floating-point minimum number.

The reference can be found here:

https://developer.arm.com/documentation/ddi0602/2022-09

It also updates ADD and SQDMULH

Depends on: D135563

[CarolineConcatto]

The output of the tests "CHECK-INST:" need to be updated, but it is still possible to review the patch

[CarolineConcatto]

-Rebase

[paulwalker-arm]

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

374–384

Just related to layout but it's more typical to group instructions based on the multiclass rather instruction name.

llvm/lib/Target/AArch64/SMEInstrFormats.td

1875–1876

There doesn't look to be much commonality between the derived classes and the splitting of the Inst fields makes it hard to spot bugs. I guess I'm asking why the base class is advantageous over implementing sme2_max_min_vector_vg2_single, sme2_max_min_vector_vg4_single,... as isolated instruction classes.

1897

Is the line wrapping here necessary? Typically we only follow the 80 character limit for these td files when it comes to comments and class declarations.

[CarolineConcatto]

-Fix tests that were not updated correct

[CarolineConcatto]

• address review comments

[CarolineConcatto]

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

374–384

Do you want me to group them in this patch by group of instructions?
Sorry, but I don't understand what you would like me to fix.
I can group them here, and do another NFC for the other instructions, otherwise things will get a bit moew random.

llvm/lib/Target/AArch64/SMEInstrFormats.td

1875–1876

I created a class for each group now.
I hope that is better now to review.

[paulwalker-arm]

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

374–384

If you look at AArch64SVEInstrInfo.td you'll see that typically we group things based on class names, so in this case I'd expect

defm SMAX_VG2_2ZZ  : sme2_int_max_min_vector_vg2_single<"smax", 0b00>;
defm UMAX_VG2_2ZZ  : sme2_int_max_min_vector_vg2_single<"umax", 0b01>;
defm SMIN_VG2_2ZZ  : sme2_int_max_min_vector_vg2_single<"smin", 0b10>;
defm UMIN_VG2_2ZZ  : sme2_int_max_min_vector_vg2_single<"umin", 0b11>;

defm SMAX_VG4_4ZZ  : sme2_int_max_min_vector_vg4_single<"smax", 0b00>;
defm UMAX_VG4_4ZZ  : sme2_int_max_min_vector_vg4_single<"umax", 0b01>;
defm SMIN_VG4_4ZZ  : sme2_int_max_min_vector_vg4_single<"smin", 0b10>;
defm UMIN_VG4_4ZZ  : sme2_int_max_min_vector_vg4_single<"umin", 0b11>;

However this is purely stylistic and I can see AArch64SMEInstrInfo.td uses a mixture of styles so this can be cleaned up in a following patch or ignored given I suppose there's no rule to say both should follow the same format.

llvm/lib/Target/AArch64/SMEInstrFormats.td

1875–1876

Thanks Carol, this helps a lot. The similarities are clearer which prompted me to look at the encoding groups and I think you've perhaps gone one level too far down? I can see the encoding group "SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers)" which these instructions below, amongst others which all use the same format and so perhaps you can have one instruction class which all the similar instructions (min, max, fmin, fmax, shift, add...) can use. Sure the opcode space is sparse but that's fine. It'll just mean it's easier to add a new instruction within this group later on.

The same goes for the "Four registers" variant where I see "SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers)", so again one instruction class can likely be used for all the instructions it contains.

[paulwalker-arm]

llvm/lib/Target/AArch64/SMEInstrFormats.td

1875–1876

Just to avoid confusion here. I'm not saying we don't need the multiclasses like sme2_fp_max_min_vector_vg2_single and sme2_int_max_min_vector_vg2_single. We need those to account for the differences in supported element sizes. However, I think they can inherit from the same "SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers)" instruction class.

[CarolineConcatto]

• group all SVE destructive instructions

[CarolineConcatto]

Remove unwanted changes

[CarolineConcatto]

llvm/lib/Target/AArch64/SMEInstrFormats.td

1875–1876

Hey Paul,

So I believe all the SVE destructive instructions are using common classes.
Is that what you meant?

[paulwalker-arm]

Thanks @CarolineConcatto, this is a much nicer structure and in keeping with how we typically add new instructions.

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

377

Should this be SMAX_VG4_4Z4Z? If yes then you'll need to check all new defs in this patch because I've seen this potentially incorrect naming several times.

Whilst mentioning consistency the choice of whether to use _VG# seems arbitrary or perhaps I'm misinterpreting it's meaning. For example SRSHL_2Z2Z looks like it should have _VG2 but doesn't. That said, given we specify the register types within the instructions (i.e. _2Z2Z) I'm wondering if most all the _VG# usages are redundant?

Redundancy is likely a question for later but I do think you should be naming the instructions consistently.

llvm/lib/Target/AArch64/SMEInstrFormats.td

1439–1442

Is there value in breaking this up? instead of just having Inst{10-5} = op{6-1}.

1475–1478

As above, do these need to be split?

1511–1513

Can you make f part of the opcode? much like you did for the _single variants.

1546–1548

As above, can these be packed together?

[CarolineConcatto]

-Address comments review

• Fix inconsistency In the instructions name
• Remove f from the class

[CarolineConcatto]

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

377

I agree that the naming needs to be consistent. I missed that.
Thank you for noticing. I will double-check the following patches for name consistency.

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

 defm FMLA_VG2_M2Z2Z_S : sme2_mla_add_sub_array_vg2_multi_S<"fmla", 0b00>;
 defm FMLA_VG4_M4Z4Z_S : sme2_mla_add_sub_array_vg4_multi_S<"fmla", 0b00>;
 
 defm FMLS_VG2_M2ZZ_S  : sme2_mla_add_sub_array_vg2_single_S<"fmls", 0b01>;
 defm FMLS_VG4_M4ZZ_S  : sme2_mla_add_sub_array_vg4_single_S<"fmls", 0b01>;
 defm FMLS_VG2_M2Z2Z_S : sme2_mla_add_sub_array_vg2_multi_S<"fmls", 0b01>;
 defm FMLS_VG4_M4Z4Z_S : sme2_mla_add_sub_array_vg4_multi_S<"fmls", 0b01>;
 
-defm ADD_VG2_2ZZ  : sme2_sqdmulh_add_vector_vg2_single<"add", 0b011000>;
-defm ADD_VG4_4ZZ  : sme2_sqdmulh_add_vector_vg4_single<"add", 0b011000>;
+defm ADD_VG2_2ZZ  : sme2_int_sve_destructive_vector_vg2_single<"add", 0b0110000>;
+defm ADD_VG4_4ZZ  : sme2_int_sve_destructive_vector_vg4_single<"add", 0b0110000>;
 
 defm ADDA_VG2_M2Z2Z_S : sme2_multivec_accum_add_sub_vg2_S<"add", 0b10>;
 defm ADDA_VG4_M4Z4Z_S : sme2_multivec_accum_add_sub_vg4_S<"add", 0b10>;
 
 defm SUBA_VG2_M2Z2Z_S : sme2_multivec_accum_add_sub_vg2_S<"sub", 0b11>;
 defm SUBA_VG4_M4Z4Z_S : sme2_multivec_accum_add_sub_vg4_S<"sub", 0b11>;
 
 defm FADD_VG2_M2Z2Z_S : sme2_multivec_accum_add_sub_vg2_S<"fadd", 0b00>;
 defm FADD_VG4_M4Z4Z_S : sme2_multivec_accum_add_sub_vg4_S<"fadd", 0b00>;
 
 defm FSUB_VG2_M2Z2Z_S : sme2_multivec_accum_add_sub_vg2_S<"fsub", 0b01>;
 defm FSUB_VG4_M4Z4Z_S : sme2_multivec_accum_add_sub_vg4_S<"fsub", 0b01>;
 
-defm SQDMULH_2ZZ : sme2_sqdmulh_add_vector_vg2_single<"sqdmulh", 0b100000>;
-defm SQDMULH_4ZZ : sme2_sqdmulh_add_vector_vg4_single<"sqdmulh", 0b100000>;
-defm SQDMULH_2Z2Z2Z : sme2_sqdmulh_vector_vg2_multi<"sqdmulh">;
-defm SQDMULH_4Z4Z4Z : sme2_sqdmulh_vector_vg4_multi<"sqdmulh">;
+defm SQDMULH_2Z2ZZ : sme2_int_sve_destructive_vector_vg2_single<"sqdmulh", 0b1000000>;
+defm SQDMULH_4Z4ZZ : sme2_int_sve_destructive_vector_vg4_single<"sqdmulh", 0b1000000>;
+defm SQDMULH_2Z2Z2Z : sme2_int_sve_destructive_vector_vg2_multi<"sqdmulh", 0b100000>;
+defm SQDMULH_4Z4Z4Z : sme2_int_sve_destructive_vector_vg4_multi<"sqdmulh", 0b100000>;
 
 defm FMLAL_MZZI      : sme2_mla_long_array_index<"fmlal",  0b10,   0b00>;
 defm FMLAL_VG2_M2ZZI : sme2_fp_mla_long_array_vg2_index<"fmlal",   0b00>;
 defm FMLAL_VG4_M4ZZI : sme2_fp_mla_long_array_vg4_index<"fmlal",   0b00>;
 defm FMLAL_MZZ       : sme2_mla_long_array_single<"fmlal", 0b00,   0b00>;
 defm FMLAL_VG2_M2ZZ  : sme2_fp_mla_long_array_vg2_single<"fmlal",  0b00>;
 defm FMLAL_VG4_M4ZZ  : sme2_fp_mla_long_array_vg4_single<"fmlal",  0b00>;
 defm FMLAL_VG2_M2Z2Z : sme2_fp_mla_long_array_vg2_multi<"fmlal",   0b00>;

 def FCVTZS_4Z4Z_StoS : sme2_fp_cvt_vg4_multi<"fcvtzs", 0b010>;
 def FCVTZU_2Z2Z_StoS : sme2_fp_cvt_vg2_multi<"fcvtzu", 0b011>;
 def FCVTZU_4Z4Z_StoS : sme2_fp_cvt_vg4_multi<"fcvtzu", 0b011>;
 def SCVTF_2Z2Z_StoS  : sme2_fp_cvt_vg2_multi<"scvtf", 0b100>;
 def SCVTF_4Z4Z_StoS  : sme2_fp_cvt_vg4_multi<"scvtf", 0b100>;
 def UCVTF_2Z2Z_StoS  : sme2_fp_cvt_vg2_multi<"ucvtf", 0b101>;
 def UCVTF_4Z4Z_StoS  : sme2_fp_cvt_vg4_multi<"ucvtf", 0b101>;
 
+defm SMAX_VG2_2ZZ  : sme2_int_sve_destructive_vector_vg2_single<"smax", 0b0000000>;
+defm SMAX_VG4_4ZZ  : sme2_int_sve_destructive_vector_vg4_single<"smax", 0b0000000>;
+defm SMAX_VG2_2Z2Z : sme2_int_sve_destructive_vector_vg2_multi<"smax",  0b000000>;
+defm SMAX_VG4_4Z2Z : sme2_int_sve_destructive_vector_vg4_multi<"smax",  0b000000>;
+
+defm UMAX_VG2_2ZZ  : sme2_int_sve_destructive_vector_vg2_single<"umax", 0b0000001>;
+defm UMAX_VG4_4ZZ  : sme2_int_sve_destructive_vector_vg4_single<"umax", 0b0000001>;
+defm UMAX_VG2_2Z2Z : sme2_int_sve_destructive_vector_vg2_multi<"umax",  0b000001>;
+defm UMAX_VG4_4Z2Z : sme2_int_sve_destructive_vector_vg4_multi<"umax",  0b000001>;
+
+defm SMIN_VG2_2ZZ  : sme2_int_sve_destructive_vector_vg2_single<"smin", 0b0000010>;
+defm SMIN_VG4_4ZZ  : sme2_int_sve_destructive_vector_vg4_single<"smin", 0b0000010>;
+defm SMIN_VG2_2Z2Z : sme2_int_sve_destructive_vector_vg2_multi<"smin",  0b000010>;
+defm SMIN_VG4_4Z2Z : sme2_int_sve_destructive_vector_vg4_multi<"smin",  0b000010>;
+
+defm UMIN_VG2_2ZZ  : sme2_int_sve_destructive_vector_vg2_single<"umin", 0b0000011>;
+defm UMIN_VG4_4ZZ  : sme2_int_sve_destructive_vector_vg4_single<"umin", 0b0000011>;
+defm UMIN_VG2_2Z2Z : sme2_int_sve_destructive_vector_vg2_multi<"umin",  0b000011>;
+defm UMIN_VG4_4Z2Z : sme2_int_sve_destructive_vector_vg4_multi<"umin",  0b000011>;
+
+defm FMAX_VG2_2ZZ  : sme2_fp_sve_destructive_vector_vg2_single<"fmax", 0b0010000>;
+defm FMAX_VG4_4ZZ  : sme2_fp_sve_destructive_vector_vg4_single<"fmax", 0b0010000>;
+defm FMAX_VG2_2Z2Z : sme2_fp_sve_destructive_vector_vg2_multi<"fmax",  0b000000>;
+defm FMAX_VG4_4Z2Z : sme2_fp_sve_destructive_vector_vg4_multi<"fmax",  0b000000>;
+
+defm FMIN_VG2_2ZZ  : sme2_fp_sve_destructive_vector_vg2_single<"fmin", 0b0010001>;
+defm FMIN_VG4_4ZZ  : sme2_fp_sve_destructive_vector_vg4_single<"fmin", 0b0010001>;
+defm FMIN_VG2_2Z2Z : sme2_fp_sve_destructive_vector_vg2_multi<"fmin",  0b000001>;
+defm FMIN_VG4_4Z2Z : sme2_fp_sve_destructive_vector_vg4_multi<"fmin",  0b000001>;
+
+defm FMAXNM_VG2_2ZZ  : sme2_fp_sve_destructive_vector_vg2_single<"fmaxnm", 0b0010010>;
+defm FMAXNM_VG4_4ZZ  : sme2_fp_sve_destructive_vector_vg4_single<"fmaxnm", 0b0010010>;
+defm FMAXNM_VG2_2Z2Z : sme2_fp_sve_destructive_vector_vg2_multi<"fmaxnm",  0b000010>;
+defm FMAXNM_VG4_4Z2Z : sme2_fp_sve_destructive_vector_vg4_multi<"fmaxnm",  0b000010>;
+
+defm FMINNM_VG2_2ZZ  : sme2_fp_sve_destructive_vector_vg2_single<"fminnm", 0b0010011>;
+defm FMINNM_VG4_4ZZ  : sme2_fp_sve_destructive_vector_vg4_single<"fminnm", 0b0010011>;
+defm FMINNM_VG2_2Z2Z : sme2_fp_sve_destructive_vector_vg2_multi<"fminnm",  0b000011>;
+defm FMINNM_VG4_4Z2Z : sme2_fp_sve_destructive_vector_vg4_multi<"fminnm",  0b000011>;
+
+defm SRSHL_2ZZ:  sme2_int_sve_destructive_vector_vg2_single<"srshl", 0b0100010>;
+defm SRSHL_4ZZ:  sme2_int_sve_destructive_vector_vg4_single<"srshl", 0b0100010>;
+defm SRSHL_2Z4Z:  sme2_int_sve_destructive_vector_vg2_multi<"srshl", 0b010010>;
+defm SRSHL_4Z4Z:  sme2_int_sve_destructive_vector_vg4_multi<"srshl", 0b010010>;
+
+defm URSHL_2ZZ:  sme2_int_sve_destructive_vector_vg2_single<"urshl", 0b0100011>;
+defm URSHL_4ZZ:  sme2_int_sve_destructive_vector_vg4_single<"urshl", 0b0100011>;
+defm URSHL_2Z4Z:  sme2_int_sve_destructive_vector_vg2_multi<"urshl", 0b010011>;
+defm URSHL_4Z4Z:  sme2_int_sve_destructive_vector_vg4_multi<"urshl", 0b010011>;
+
 }
 
 
 let Predicates = [HasSME2, HasSMEI16I64] in {
 defm ADD_VG2_M2ZZ_D  : sme2_mla_add_sub_array_vg2_single_D<"add", 0b10>;
 defm ADD_VG4_M4ZZ_D  : sme2_mla_add_sub_array_vg4_single_D<"add", 0b10>;
 defm ADD_VG2_M2Z2Z_D : sme2_mla_add_sub_array_vg2_multi_D<"add", 0b10>;
 defm ADD_VG4_M4Z4Z_D : sme2_mla_add_sub_array_vg4_multi_D<"add", 0b10>;

llvm/lib/Target/AArch64/SMEInstrFormats.td

multiclass sme2_multivec_accum_add_sub_vg4_D<string mnemonic, bits<2> op> {
   def : InstAlias<mnemonic # "\t$ZAdn[$Rv, $imm3], $Zm",
                  (!cast<Instruction>(NAME) MatrixOp64:$ZAdn,  MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, ZZZZ_d_mul_r:$Zm), 0>;
 }
 
 //===----------------------------------------------------------------------===//
 // SME2 Multi-vector - Multiple and Single SVE Destructive
 // Two and Four registers
 
-class sme2_sqdmulh_add_vector_vg2_single<bits<2> sz, bits<6> op,
+class sme2_sve_destructive_vector_vg2_single<bits<2> sz, bits<7> op,
                                              RegisterOperand vector_ty,
-                                         ZPRRegOp zpr_ty, string mnemonic>
+                                             RegisterOperand zpr_ty,
+                                             string mnemonic>
     : I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, zpr_ty:$Zm),
         mnemonic, "\t$Zdn, $_Zdn, $Zm",
         "", []>, Sched<[]> {
   bits<4> Zm;
   bits<4> Zdn;
   let Inst{31-24} = 0b11000001;
   let Inst{23-22} = sz;
   let Inst{21-20} = 0b10;
   let Inst{19-16} = Zm;
   let Inst{15-11} = 0b10100;
-  let Inst{10-5}  = op;
+  let Inst{10-9}  = op{6-5};
+  let Inst{8}     = op{4}; //f
+  let Inst{7-5}   = op{3-1};
   let Inst{4-1}   = Zdn;
-  let Inst{0}     = 0b0;
+  let Inst{0}     = op{0};
+
   let Constraints = "$Zdn = $_Zdn";
 }
 
-multiclass sme2_sqdmulh_add_vector_vg2_single<string mnemonic, bits<6> op> {
-  def _B : sme2_sqdmulh_add_vector_vg2_single<0b00, op, ZZ_b_mul_r, ZPR4b8, mnemonic>;
-  def _H : sme2_sqdmulh_add_vector_vg2_single<0b01, op, ZZ_h_mul_r, ZPR4b16, mnemonic>;
-  def _S : sme2_sqdmulh_add_vector_vg2_single<0b10, op, ZZ_s_mul_r, ZPR4b32, mnemonic>;
-  def _D : sme2_sqdmulh_add_vector_vg2_single<0b11, op, ZZ_d_mul_r, ZPR4b64, mnemonic>;
+multiclass sme2_fp_sve_destructive_vector_vg2_single<string mnemonic, bits<7> op> {
+  def _H : sme2_sve_destructive_vector_vg2_single<0b01, op, ZZ_h_mul_r, ZPR4b16, mnemonic>;
+  def _S : sme2_sve_destructive_vector_vg2_single<0b10, op, ZZ_s_mul_r, ZPR4b32, mnemonic>;
+  def _D : sme2_sve_destructive_vector_vg2_single<0b11, op, ZZ_d_mul_r, ZPR4b64, mnemonic>;
+}
+
+multiclass sme2_int_sve_destructive_vector_vg2_single<string mnemonic, bits<7> op> {
+  def _B : sme2_sve_destructive_vector_vg2_single<0b00, op, ZZ_b_mul_r, ZPR4b8, mnemonic>;
+  def _H : sme2_sve_destructive_vector_vg2_single<0b01, op, ZZ_h_mul_r, ZPR4b16, mnemonic>;
+  def _S : sme2_sve_destructive_vector_vg2_single<0b10, op, ZZ_s_mul_r, ZPR4b32, mnemonic>;
+  def _D : sme2_sve_destructive_vector_vg2_single<0b11, op, ZZ_d_mul_r, ZPR4b64, mnemonic>;
 }
 
-class sme2_sqdmulh_add_vector_vg4_single<bits<2> sz, bits<6> op,
+class sme2_sve_destructive_vector_vg4_single<bits<2> sz, bits<7> op,
                                              RegisterOperand vector_ty,
-                                         ZPRRegOp zpr_ty, string mnemonic>
+                                             RegisterOperand zpr_ty,
+                                             string mnemonic>
     : I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, zpr_ty:$Zm),
         mnemonic, "\t$Zdn, $_Zdn, $Zm",
         "", []>, Sched<[]> {
   bits<4> Zm;
   bits<3> Zdn;
   let Inst{31-24} = 0b11000001;
   let Inst{23-22} = sz;
   let Inst{21-20} = 0b10;
   let Inst{19-16} = Zm;
   let Inst{15-11} = 0b10101;
-  let Inst{10-5}  = op;
+  let Inst{10-9}  = op{6-5};
+  let Inst{8}     = op{4}; //f
+  let Inst{7-5}   = op{3-1};
   let Inst{4-2}   = Zdn;
-  let Inst{1-0}   = 0b00;
+  let Inst{1}     = 0b0;
+  let Inst{0}     = op{0};
+
   let Constraints = "$Zdn = $_Zdn";
 }
 
-multiclass sme2_sqdmulh_add_vector_vg4_single<string mnemonic, bits<6> op> {
-  def _B : sme2_sqdmulh_add_vector_vg4_single<0b00, op, ZZZZ_b_mul_r, ZPR4b8, mnemonic>;
-  def _H : sme2_sqdmulh_add_vector_vg4_single<0b01, op, ZZZZ_h_mul_r, ZPR4b16, mnemonic>;
-  def _S : sme2_sqdmulh_add_vector_vg4_single<0b10, op, ZZZZ_s_mul_r, ZPR4b32, mnemonic>;
-  def _D : sme2_sqdmulh_add_vector_vg4_single<0b11, op, ZZZZ_d_mul_r, ZPR4b64, mnemonic>;
+multiclass sme2_fp_sve_destructive_vector_vg4_single<string mnemonic, bits<7> op> {
+  def _H : sme2_sve_destructive_vector_vg4_single<0b01, op, ZZZZ_h_mul_r, ZPR4b16, mnemonic>;
+  def _S : sme2_sve_destructive_vector_vg4_single<0b10, op, ZZZZ_s_mul_r, ZPR4b32, mnemonic>;
+  def _D : sme2_sve_destructive_vector_vg4_single<0b11, op, ZZZZ_d_mul_r, ZPR4b64, mnemonic>;
 }
 
+multiclass sme2_int_sve_destructive_vector_vg4_single<string mnemonic, bits<7> op> {
+  def _B : sme2_sve_destructive_vector_vg4_single<0b00, op, ZZZZ_b_mul_r, ZPR4b8, mnemonic>;
+  def _H : sme2_sve_destructive_vector_vg4_single<0b01, op, ZZZZ_h_mul_r, ZPR4b16, mnemonic>;
+  def _S : sme2_sve_destructive_vector_vg4_single<0b10, op, ZZZZ_s_mul_r, ZPR4b32, mnemonic>;
+  def _D : sme2_sve_destructive_vector_vg4_single<0b11, op, ZZZZ_d_mul_r, ZPR4b64, mnemonic>;
+}
 
-class sme2_sqdmulh_vector_vg2_multi<bits<2> sz, RegisterOperand vector_ty,
+class sme2_sve_destructive_vector_vg2_multi<bits<2> sz, bit f, bits<6> op,
+                                            RegisterOperand vector_ty,
                                             string mnemonic>
     : I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, vector_ty:$Zm),
         mnemonic, "\t$Zdn, $_Zdn, $Zm",
         "", []>, Sched<[]> {
   bits<4> Zm;
   bits<4> Zdn;
   let Inst{31-24} = 0b11000001;
   let Inst{23-22} = sz;
   let Inst{21}    = 0b1;
   let Inst{20-17} = Zm;
-  let Inst{16-5}  = 0b010110100000;
+  let Inst{16-11} = 0b010110;
+  let Inst{10-9}  = op{5-4};
+  let Inst{8}     = f;
+  let Inst{7-5}   = op{3-1};
   let Inst{4-1}   = Zdn;
-  let Inst{0}     = 0b0;
+  let Inst{0}     = op{0};
+
   let Constraints = "$Zdn = $_Zdn";
 }
 
-multiclass sme2_sqdmulh_vector_vg2_multi<string mnemonic> {
-  def _B : sme2_sqdmulh_vector_vg2_multi<0b00, ZZ_b_mul_r, mnemonic>;
-  def _H : sme2_sqdmulh_vector_vg2_multi<0b01, ZZ_h_mul_r, mnemonic>;
-  def _S : sme2_sqdmulh_vector_vg2_multi<0b10, ZZ_s_mul_r, mnemonic>;
-  def _D : sme2_sqdmulh_vector_vg2_multi<0b11, ZZ_d_mul_r, mnemonic>;
+multiclass sme2_fp_sve_destructive_vector_vg2_multi<string mnemonic, bits<6> op> {
+  def _H : sme2_sve_destructive_vector_vg2_multi<0b01, 0b1, op, ZZ_h_mul_r, mnemonic>;
+  def _S : sme2_sve_destructive_vector_vg2_multi<0b10, 0b1, op, ZZ_s_mul_r, mnemonic>;
+  def _D : sme2_sve_destructive_vector_vg2_multi<0b11, 0b1, op, ZZ_d_mul_r, mnemonic>;
 }
 
-class sme2_sqdmulh_vector_vg4_multi<bits<2> sz, RegisterOperand vector_ty,
+multiclass sme2_int_sve_destructive_vector_vg2_multi<string mnemonic, bits<6> op> {
+  def _B : sme2_sve_destructive_vector_vg2_multi<0b00, 0b0, op, ZZ_b_mul_r, mnemonic>;
+  def _H : sme2_sve_destructive_vector_vg2_multi<0b01, 0b0, op, ZZ_h_mul_r, mnemonic>;
+  def _S : sme2_sve_destructive_vector_vg2_multi<0b10, 0b0, op, ZZ_s_mul_r, mnemonic>;
+  def _D : sme2_sve_destructive_vector_vg2_multi<0b11, 0b0, op, ZZ_d_mul_r, mnemonic>;
+}
+
+class sme2_sve_destructive_vector_vg4_multi<bits<2> sz, bit f, bits<6> op,
+                                            RegisterOperand vector_ty,
                                             string mnemonic>
     : I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, vector_ty:$Zm),
         mnemonic, "\t$Zdn, $_Zdn, $Zm",
         "", []>, Sched<[]> {
   bits<3> Zm;
   bits<3> Zdn;
   let Inst{31-24} = 0b11000001;
   let Inst{23-22} = sz;
   let Inst{21}    = 0b1;
   let Inst{20-18} = Zm;
-  let Inst{17-5}  = 0b0010111100000;
+  let Inst{17-11} = 0b0010111;
+  let Inst{10-9}  = op{5-4};
+  let Inst{8}     = f;
+  let Inst{7-5}   = op{3-1};
   let Inst{4-2}   = Zdn;
-  let Inst{1-0}   = 0b00;
+  let Inst{1}     = 0b0;
+  let Inst{0}     = op{0};
+
   let Constraints = "$Zdn = $_Zdn";
 }
 
-multiclass sme2_sqdmulh_vector_vg4_multi<string mnemonic> {
-  def _B : sme2_sqdmulh_vector_vg4_multi<0b00, ZZZZ_b_mul_r, mnemonic>;
-  def _H : sme2_sqdmulh_vector_vg4_multi<0b01, ZZZZ_h_mul_r, mnemonic>;
-  def _S : sme2_sqdmulh_vector_vg4_multi<0b10, ZZZZ_s_mul_r, mnemonic>;
-  def _D : sme2_sqdmulh_vector_vg4_multi<0b11, ZZZZ_d_mul_r, mnemonic>;
+multiclass sme2_fp_sve_destructive_vector_vg4_multi<string mnemonic, bits<6> op> {
+  def _H : sme2_sve_destructive_vector_vg4_multi<0b01, 0b1, op, ZZZZ_h_mul_r, mnemonic>;
+  def _S : sme2_sve_destructive_vector_vg4_multi<0b10, 0b1, op, ZZZZ_s_mul_r, mnemonic>;
+  def _D : sme2_sve_destructive_vector_vg4_multi<0b11, 0b1, op, ZZZZ_d_mul_r, mnemonic>;
 }
 
+multiclass sme2_int_sve_destructive_vector_vg4_multi<string mnemonic, bits<6> op> {
+  def _B : sme2_sve_destructive_vector_vg4_multi<0b00, 0b0, op, ZZZZ_b_mul_r, mnemonic>;
+  def _H : sme2_sve_destructive_vector_vg4_multi<0b01, 0b0, op, ZZZZ_h_mul_r, mnemonic>;
+  def _S : sme2_sve_destructive_vector_vg4_multi<0b10, 0b0, op, ZZZZ_s_mul_r, mnemonic>;
+  def _D : sme2_sve_destructive_vector_vg4_multi<0b11, 0b0, op, ZZZZ_d_mul_r, mnemonic>;
+}
+
+
 //===----------------------------------------------------------------------===//
 // SME2 Multi-vector - Index/Single/Multi Array Vectors FMA sources
 
 class sme2_mla_long_array_index_base<bits<2> op0, bits<2> op, Operand index_ty,
                                      RegisterOperand multi_vector_ty,
                                      string mnemonic, string vg_acronym="">
     : I<(outs MatrixOp32:$ZAda),
         (ins MatrixOp32:$_ZAda, MatrixIndexGPR32Op8_11:$Rv, index_ty:$imm, multi_vector_ty:$Zn, ZPR4b16:$Zm, VectorIndexH:$i3),
class sme2_fp_cvt_vg4_multi<string mnemonic, bits<3> op>
   let Inst{31-18} = 0b11000001001100;
   let Inst{17-16} = op{2-1};
   let Inst{15-10} = 0b111000;
   let Inst{9-7}   = Zn;
   let Inst{6}     = 0b0;
   let Inst{5}     = op{0};
   let Inst{4-2}   = Zd;
   let Inst{1-0}   = 0b00;
 }

llvm/test/MC/AArch64/SME2/fmax-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+fmax {z0.d, z1.d}, {z0.d-z2.d}, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmax {z0.d, z1.d}, {z0.d-z2.d}, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmax {z1.s-z2.s}, {z0.s, z1.s}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
+// CHECK-NEXT: fmax {z1.s-z2.s}, {z0.s, z1.s}, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid single register
+
+fmax {z0.h, z1.h}, {z2.h-z3.h}, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fmax {z0.h, z1.h}, {z2.h-z3.h}, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+fmax {z0.h, z1.h}, {z2.h-z3.h}, z14.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fmax {z0.h, z1.h}, {z2.h-z3.h}, z14.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/fmax.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+fmax    {z0.d, z1.d}, {z0.d, z1.d}, z0.d  // 11000001-11100000-10100001-00000000
+// CHECK-INST: fmax    { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x00,0xa1,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a100 <unknown>
+
+fmax    {z20.d, z21.d}, {z20.d, z21.d}, z5.d  // 11000001-11100101-10100001-00010100
+// CHECK-INST: fmax    { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x14,0xa1,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a114 <unknown>
+
+fmax    {z22.d, z23.d}, {z22.d, z23.d}, z8.d  // 11000001-11101000-10100001-00010110
+// CHECK-INST: fmax    { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x16,0xa1,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a116 <unknown>
+
+fmax    {z30.d, z31.d}, {z30.d, z31.d}, z15.d  // 11000001-11101111-10100001-00011110
+// CHECK-INST: fmax    { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x1e,0xa1,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa11e <unknown>
+
+
+fmax    {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d}  // 11000001-11100000-10110001-00000000
+// CHECK-INST: fmax    { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x00,0xb1,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b100 <unknown>
+
+fmax    {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d}  // 11000001-11110100-10110001-00010100
+// CHECK-INST: fmax    { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x14,0xb1,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b114 <unknown>
+
+fmax    {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d}  // 11000001-11101000-10110001-00010110
+// CHECK-INST: fmax    { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x16,0xb1,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b116 <unknown>
+
+fmax    {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d}  // 11000001-11111110-10110001-00011110
+// CHECK-INST: fmax    { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x1e,0xb1,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1feb11e <unknown>
+
+
+fmax    {z0.h, z1.h}, {z0.h, z1.h}, z0.h  // 11000001-01100000-10100001-00000000
+// CHECK-INST: fmax    { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x00,0xa1,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a100 <unknown>
+
+fmax    {z20.h, z21.h}, {z20.h, z21.h}, z5.h  // 11000001-01100101-10100001-00010100
+// CHECK-INST: fmax    { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x14,0xa1,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a114 <unknown>
+
+fmax    {z22.h, z23.h}, {z22.h, z23.h}, z8.h  // 11000001-01101000-10100001-00010110
+// CHECK-INST: fmax    { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x16,0xa1,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a116 <unknown>
+
+fmax    {z30.h, z31.h}, {z30.h, z31.h}, z15.h  // 11000001-01101111-10100001-00011110
+// CHECK-INST: fmax    { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x1e,0xa1,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa11e <unknown>
+
+
+fmax    {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h}  // 11000001-01100000-10110001-00000000
+// CHECK-INST: fmax    { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x00,0xb1,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b100 <unknown>
+
+fmax    {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h}  // 11000001-01110100-10110001-00010100
+// CHECK-INST: fmax    { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x14,0xb1,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b114 <unknown>
+
+fmax    {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h}  // 11000001-01101000-10110001-00010110
+// CHECK-INST: fmax    { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x16,0xb1,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b116 <unknown>
+
+fmax    {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h}  // 11000001-01111110-10110001-00011110
+// CHECK-INST: fmax    { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x1e,0xb1,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17eb11e <unknown>
+
+
+fmax    {z0.s, z1.s}, {z0.s, z1.s}, z0.s  // 11000001-10100000-10100001-00000000
+// CHECK-INST: fmax    { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x00,0xa1,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a100 <unknown>
+
+fmax    {z20.s, z21.s}, {z20.s, z21.s}, z5.s  // 11000001-10100101-10100001-00010100
+// CHECK-INST: fmax    { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x14,0xa1,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a114 <unknown>
+
+fmax    {z22.s, z23.s}, {z22.s, z23.s}, z8.s  // 11000001-10101000-10100001-00010110
+// CHECK-INST: fmax    { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x16,0xa1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a116 <unknown>
+
+fmax    {z30.s, z31.s}, {z30.s, z31.s}, z15.s  // 11000001-10101111-10100001-00011110
+// CHECK-INST: fmax    { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x1e,0xa1,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa11e <unknown>
+
+
+fmax    {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s}  // 11000001-10100000-10110001-00000000
+// CHECK-INST: fmax    { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x00,0xb1,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b100 <unknown>
+
+fmax    {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s}  // 11000001-10110100-10110001-00010100
+// CHECK-INST: fmax    { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x14,0xb1,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b114 <unknown>
+
+fmax    {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s}  // 11000001-10101000-10110001-00010110
+// CHECK-INST: fmax    { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x16,0xb1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b116 <unknown>
+
+fmax    {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s}  // 11000001-10111110-10110001-00011110
+// CHECK-INST: fmax    { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x1e,0xb1,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1beb11e <unknown>
+
+
+fmax    {z0.d - z3.d}, {z0.d - z3.d}, z0.d  // 11000001-11100000-10101001-00000000
+// CHECK-INST: fmax    { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x00,0xa9,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a900 <unknown>
+
+fmax    {z20.d - z23.d}, {z20.d - z23.d}, z5.d  // 11000001-11100101-10101001-00010100
+// CHECK-INST: fmax    { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x14,0xa9,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a914 <unknown>
+
+fmax    {z20.d - z23.d}, {z20.d - z23.d}, z8.d  // 11000001-11101000-10101001-00010100
+// CHECK-INST: fmax    { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x14,0xa9,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a914 <unknown>
+
+fmax    {z28.d - z31.d}, {z28.d - z31.d}, z15.d  // 11000001-11101111-10101001-00011100
+// CHECK-INST: fmax    { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x1c,0xa9,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa91c <unknown>
+
+
+fmax    {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d}  // 11000001-11100000-10111001-00000000
+// CHECK-INST: fmax    { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x00,0xb9,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b900 <unknown>
+
+fmax    {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d}  // 11000001-11110100-10111001-00010100
+// CHECK-INST: fmax    { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x14,0xb9,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b914 <unknown>
+
+fmax    {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d}  // 11000001-11101000-10111001-00010100
+// CHECK-INST: fmax    { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x14,0xb9,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b914 <unknown>
+
+fmax    {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d}  // 11000001-11111100-10111001-00011100
+// CHECK-INST: fmax    { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x1c,0xb9,0xfc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fcb91c <unknown>
+
+
+fmax    {z0.h - z3.h}, {z0.h - z3.h}, z0.h  // 11000001-01100000-10101001-00000000
+// CHECK-INST: fmax    { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x00,0xa9,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a900 <unknown>
+
+fmax    {z20.h - z23.h}, {z20.h - z23.h}, z5.h  // 11000001-01100101-10101001-00010100
+// CHECK-INST: fmax    { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x14,0xa9,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a914 <unknown>
+
+fmax    {z20.h - z23.h}, {z20.h - z23.h}, z8.h  // 11000001-01101000-10101001-00010100
+// CHECK-INST: fmax    { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x14,0xa9,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a914 <unknown>
+
+fmax    {z28.h - z31.h}, {z28.h - z31.h}, z15.h  // 11000001-01101111-10101001-00011100
+// CHECK-INST: fmax    { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x1c,0xa9,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa91c <unknown>
+
+
+fmax    {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-01100000-10111001-00000000
+// CHECK-INST: fmax    { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x00,0xb9,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b900 <unknown>
+
+fmax    {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h}  // 11000001-01110100-10111001-00010100
+// CHECK-INST: fmax    { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x14,0xb9,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b914 <unknown>
+
+fmax    {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h}  // 11000001-01101000-10111001-00010100
+// CHECK-INST: fmax    { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x14,0xb9,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b914 <unknown>
+
+fmax    {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-01111100-10111001-00011100
+// CHECK-INST: fmax    { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x1c,0xb9,0x7c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17cb91c <unknown>
+
+
+fmax    {z0.s - z3.s}, {z0.s - z3.s}, z0.s  // 11000001-10100000-10101001-00000000
+// CHECK-INST: fmax    { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x00,0xa9,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a900 <unknown>
+
+fmax    {z20.s - z23.s}, {z20.s - z23.s}, z5.s  // 11000001-10100101-10101001-00010100
+// CHECK-INST: fmax    { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x14,0xa9,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a914 <unknown>
+
+fmax    {z20.s - z23.s}, {z20.s - z23.s}, z8.s  // 11000001-10101000-10101001-00010100
+// CHECK-INST: fmax    { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x14,0xa9,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a914 <unknown>
+
+fmax    {z28.s - z31.s}, {z28.s - z31.s}, z15.s  // 11000001-10101111-10101001-00011100
+// CHECK-INST: fmax    { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x1c,0xa9,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa91c <unknown>
+
+
+fmax    {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s}  // 11000001-10100000-10111001-00000000
+// CHECK-INST: fmax    { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x00,0xb9,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b900 <unknown>
+
+fmax    {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s}  // 11000001-10110100-10111001-00010100
+// CHECK-INST: fmax    { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x14,0xb9,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b914 <unknown>
+
+fmax    {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s}  // 11000001-10101000-10111001-00010100
+// CHECK-INST: fmax    { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x14,0xb9,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b914 <unknown>
+
+fmax    {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s}  // 11000001-10111100-10111001-00011100
+// CHECK-INST: fmax    { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x1c,0xb9,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bcb91c <unknown>
+

llvm/test/MC/AArch64/SME2/fmaxnm-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+fmaxnm {z0.d, z1.d}, {z0.d-z2.d}, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmaxnm {z0.d, z1.d}, {z0.d-z2.d}, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmaxnm {z1.s-z2.s}, {z0.s, z1.s}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
+// CHECK-NEXT: fmaxnm {z1.s-z2.s}, {z0.s, z1.s}, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid single register
+
+fmaxnm {z0.h, z1.h}, {z2.h-z3.h}, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fmaxnm {z0.h, z1.h}, {z2.h-z3.h}, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+fmaxnm {z0.h, z1.h}, {z2.h-z3.h}, z14.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fmaxnm {z0.h, z1.h}, {z2.h-z3.h}, z14.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/fmaxnm.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+fmaxnm  {z0.d, z1.d}, {z0.d, z1.d}, z0.d  // 11000001-11100000-10100001-00100000
+// CHECK-INST: fmaxnm  { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x20,0xa1,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a120 <unknown>
+
+fmaxnm  {z20.d, z21.d}, {z20.d, z21.d}, z5.d  // 11000001-11100101-10100001-00110100
+// CHECK-INST: fmaxnm  { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x34,0xa1,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a134 <unknown>
+
+fmaxnm  {z22.d, z23.d}, {z22.d, z23.d}, z8.d  // 11000001-11101000-10100001-00110110
+// CHECK-INST: fmaxnm  { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x36,0xa1,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a136 <unknown>
+
+fmaxnm  {z30.d, z31.d}, {z30.d, z31.d}, z15.d  // 11000001-11101111-10100001-00111110
+// CHECK-INST: fmaxnm  { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x3e,0xa1,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa13e <unknown>
+
+
+fmaxnm  {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d}  // 11000001-11100000-10110001-00100000
+// CHECK-INST: fmaxnm  { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x20,0xb1,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b120 <unknown>
+
+fmaxnm  {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d}  // 11000001-11110100-10110001-00110100
+// CHECK-INST: fmaxnm  { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x34,0xb1,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b134 <unknown>
+
+fmaxnm  {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d}  // 11000001-11101000-10110001-00110110
+// CHECK-INST: fmaxnm  { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x36,0xb1,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b136 <unknown>
+
+fmaxnm  {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d}  // 11000001-11111110-10110001-00111110
+// CHECK-INST: fmaxnm  { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x3e,0xb1,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1feb13e <unknown>
+
+
+fmaxnm  {z0.h, z1.h}, {z0.h, z1.h}, z0.h  // 11000001-01100000-10100001-00100000
+// CHECK-INST: fmaxnm  { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x20,0xa1,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a120 <unknown>
+
+fmaxnm  {z20.h, z21.h}, {z20.h, z21.h}, z5.h  // 11000001-01100101-10100001-00110100
+// CHECK-INST: fmaxnm  { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x34,0xa1,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a134 <unknown>
+
+fmaxnm  {z22.h, z23.h}, {z22.h, z23.h}, z8.h  // 11000001-01101000-10100001-00110110
+// CHECK-INST: fmaxnm  { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x36,0xa1,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a136 <unknown>
+
+fmaxnm  {z30.h, z31.h}, {z30.h, z31.h}, z15.h  // 11000001-01101111-10100001-00111110
+// CHECK-INST: fmaxnm  { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x3e,0xa1,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa13e <unknown>
+
+
+fmaxnm  {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h}  // 11000001-01100000-10110001-00100000
+// CHECK-INST: fmaxnm  { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x20,0xb1,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b120 <unknown>
+
+fmaxnm  {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h}  // 11000001-01110100-10110001-00110100
+// CHECK-INST: fmaxnm  { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x34,0xb1,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b134 <unknown>
+
+fmaxnm  {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h}  // 11000001-01101000-10110001-00110110
+// CHECK-INST: fmaxnm  { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x36,0xb1,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b136 <unknown>
+
+fmaxnm  {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h}  // 11000001-01111110-10110001-00111110
+// CHECK-INST: fmaxnm  { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x3e,0xb1,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17eb13e <unknown>
+
+
+fmaxnm  {z0.s, z1.s}, {z0.s, z1.s}, z0.s  // 11000001-10100000-10100001-00100000
+// CHECK-INST: fmaxnm  { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x20,0xa1,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a120 <unknown>
+
+fmaxnm  {z20.s, z21.s}, {z20.s, z21.s}, z5.s  // 11000001-10100101-10100001-00110100
+// CHECK-INST: fmaxnm  { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x34,0xa1,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a134 <unknown>
+
+fmaxnm  {z22.s, z23.s}, {z22.s, z23.s}, z8.s  // 11000001-10101000-10100001-00110110
+// CHECK-INST: fmaxnm  { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x36,0xa1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a136 <unknown>
+
+fmaxnm  {z30.s, z31.s}, {z30.s, z31.s}, z15.s  // 11000001-10101111-10100001-00111110
+// CHECK-INST: fmaxnm  { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x3e,0xa1,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa13e <unknown>
+
+
+fmaxnm  {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s}  // 11000001-10100000-10110001-00100000
+// CHECK-INST: fmaxnm  { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x20,0xb1,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b120 <unknown>
+
+fmaxnm  {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s}  // 11000001-10110100-10110001-00110100
+// CHECK-INST: fmaxnm  { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x34,0xb1,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b134 <unknown>
+
+fmaxnm  {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s}  // 11000001-10101000-10110001-00110110
+// CHECK-INST: fmaxnm  { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x36,0xb1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b136 <unknown>
+
+fmaxnm  {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s}  // 11000001-10111110-10110001-00111110
+// CHECK-INST: fmaxnm  { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x3e,0xb1,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1beb13e <unknown>
+
+
+fmaxnm  {z0.d - z3.d}, {z0.d - z3.d}, z0.d  // 11000001-11100000-10101001-00100000
+// CHECK-INST: fmaxnm  { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x20,0xa9,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a920 <unknown>
+
+fmaxnm  {z20.d - z23.d}, {z20.d - z23.d}, z5.d  // 11000001-11100101-10101001-00110100
+// CHECK-INST: fmaxnm  { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x34,0xa9,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a934 <unknown>
+
+fmaxnm  {z20.d - z23.d}, {z20.d - z23.d}, z8.d  // 11000001-11101000-10101001-00110100
+// CHECK-INST: fmaxnm  { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x34,0xa9,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a934 <unknown>
+
+fmaxnm  {z28.d - z31.d}, {z28.d - z31.d}, z15.d  // 11000001-11101111-10101001-00111100
+// CHECK-INST: fmaxnm  { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x3c,0xa9,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa93c <unknown>
+
+
+fmaxnm  {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d}  // 11000001-11100000-10111001-00100000
+// CHECK-INST: fmaxnm  { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x20,0xb9,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b920 <unknown>
+
+fmaxnm  {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d}  // 11000001-11110100-10111001-00110100
+// CHECK-INST: fmaxnm  { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x34,0xb9,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b934 <unknown>
+
+fmaxnm  {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d}  // 11000001-11101000-10111001-00110100
+// CHECK-INST: fmaxnm  { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x34,0xb9,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b934 <unknown>
+
+fmaxnm  {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d}  // 11000001-11111100-10111001-00111100
+// CHECK-INST: fmaxnm  { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x3c,0xb9,0xfc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fcb93c <unknown>
+
+
+fmaxnm  {z0.h - z3.h}, {z0.h - z3.h}, z0.h  // 11000001-01100000-10101001-00100000
+// CHECK-INST: fmaxnm  { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x20,0xa9,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a920 <unknown>
+
+fmaxnm  {z20.h - z23.h}, {z20.h - z23.h}, z5.h  // 11000001-01100101-10101001-00110100
+// CHECK-INST: fmaxnm  { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x34,0xa9,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a934 <unknown>
+
+fmaxnm  {z20.h - z23.h}, {z20.h - z23.h}, z8.h  // 11000001-01101000-10101001-00110100
+// CHECK-INST: fmaxnm  { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x34,0xa9,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a934 <unknown>
+
+fmaxnm  {z28.h - z31.h}, {z28.h - z31.h}, z15.h  // 11000001-01101111-10101001-00111100
+// CHECK-INST: fmaxnm  { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x3c,0xa9,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa93c <unknown>
+
+
+fmaxnm  {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-01100000-10111001-00100000
+// CHECK-INST: fmaxnm  { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x20,0xb9,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b920 <unknown>
+
+fmaxnm  {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h}  // 11000001-01110100-10111001-00110100
+// CHECK-INST: fmaxnm  { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x34,0xb9,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b934 <unknown>
+
+fmaxnm  {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h}  // 11000001-01101000-10111001-00110100
+// CHECK-INST: fmaxnm  { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x34,0xb9,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b934 <unknown>
+
+fmaxnm  {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-01111100-10111001-00111100
+// CHECK-INST: fmaxnm  { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x3c,0xb9,0x7c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17cb93c <unknown>
+
+
+fmaxnm  {z0.s - z3.s}, {z0.s - z3.s}, z0.s  // 11000001-10100000-10101001-00100000
+// CHECK-INST: fmaxnm  { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x20,0xa9,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a920 <unknown>
+
+fmaxnm  {z20.s - z23.s}, {z20.s - z23.s}, z5.s  // 11000001-10100101-10101001-00110100
+// CHECK-INST: fmaxnm  { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x34,0xa9,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a934 <unknown>
+
+fmaxnm  {z20.s - z23.s}, {z20.s - z23.s}, z8.s  // 11000001-10101000-10101001-00110100
+// CHECK-INST: fmaxnm  { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x34,0xa9,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a934 <unknown>
+
+fmaxnm  {z28.s - z31.s}, {z28.s - z31.s}, z15.s  // 11000001-10101111-10101001-00111100
+// CHECK-INST: fmaxnm  { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x3c,0xa9,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa93c <unknown>
+
+
+fmaxnm  {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s}  // 11000001-10100000-10111001-00100000
+// CHECK-INST: fmaxnm  { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x20,0xb9,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b920 <unknown>
+
+fmaxnm  {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s}  // 11000001-10110100-10111001-00110100
+// CHECK-INST: fmaxnm  { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x34,0xb9,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b934 <unknown>
+
+fmaxnm  {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s}  // 11000001-10101000-10111001-00110100
+// CHECK-INST: fmaxnm  { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x34,0xb9,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b934 <unknown>
+
+fmaxnm  {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s}  // 11000001-10111100-10111001-00111100
+// CHECK-INST: fmaxnm  { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x3c,0xb9,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bcb93c <unknown>
+

llvm/test/MC/AArch64/SME2/fmin-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+fmin {z0.d, z1.d}, {z0.d-z2.d}, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmin {z0.d, z1.d}, {z0.d-z2.d}, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmin {z1.s-z2.s}, {z0.s, z1.s}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
+// CHECK-NEXT: fmin {z1.s-z2.s}, {z0.s, z1.s}, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid single register
+
+fmin {z0.h, z1.h}, {z2.h-z3.h}, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fmin {z0.h, z1.h}, {z2.h-z3.h}, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+fmin {z0.h, z1.h}, {z2.h-z3.h}, z14.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fmin {z0.h, z1.h}, {z2.h-z3.h}, z14.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/fmin.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+fmin    {z0.d, z1.d}, {z0.d, z1.d}, z0.d  // 11000001-11100000-10100001-00000001
+// CHECK-INST: fmin    { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x01,0xa1,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a101 <unknown>
+
+fmin    {z20.d, z21.d}, {z20.d, z21.d}, z5.d  // 11000001-11100101-10100001-00010101
+// CHECK-INST: fmin    { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x15,0xa1,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a115 <unknown>
+
+fmin    {z22.d, z23.d}, {z22.d, z23.d}, z8.d  // 11000001-11101000-10100001-00010111
+// CHECK-INST: fmin    { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x17,0xa1,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a117 <unknown>
+
+fmin    {z30.d, z31.d}, {z30.d, z31.d}, z15.d  // 11000001-11101111-10100001-00011111
+// CHECK-INST: fmin    { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x1f,0xa1,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa11f <unknown>
+
+
+fmin    {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d}  // 11000001-11100000-10110001-00000001
+// CHECK-INST: fmin    { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x01,0xb1,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b101 <unknown>
+
+fmin    {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d}  // 11000001-11110100-10110001-00010101
+// CHECK-INST: fmin    { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x15,0xb1,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b115 <unknown>
+
+fmin    {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d}  // 11000001-11101000-10110001-00010111
+// CHECK-INST: fmin    { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x17,0xb1,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b117 <unknown>
+
+fmin    {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d}  // 11000001-11111110-10110001-00011111
+// CHECK-INST: fmin    { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x1f,0xb1,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1feb11f <unknown>
+
+
+fmin    {z0.h, z1.h}, {z0.h, z1.h}, z0.h  // 11000001-01100000-10100001-00000001
+// CHECK-INST: fmin    { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x01,0xa1,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a101 <unknown>
+
+fmin    {z20.h, z21.h}, {z20.h, z21.h}, z5.h  // 11000001-01100101-10100001-00010101
+// CHECK-INST: fmin    { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x15,0xa1,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a115 <unknown>
+
+fmin    {z22.h, z23.h}, {z22.h, z23.h}, z8.h  // 11000001-01101000-10100001-00010111
+// CHECK-INST: fmin    { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x17,0xa1,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a117 <unknown>
+
+fmin    {z30.h, z31.h}, {z30.h, z31.h}, z15.h  // 11000001-01101111-10100001-00011111
+// CHECK-INST: fmin    { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x1f,0xa1,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa11f <unknown>
+
+
+fmin    {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h}  // 11000001-01100000-10110001-00000001
+// CHECK-INST: fmin    { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x01,0xb1,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b101 <unknown>
+
+fmin    {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h}  // 11000001-01110100-10110001-00010101
+// CHECK-INST: fmin    { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x15,0xb1,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b115 <unknown>
+
+fmin    {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h}  // 11000001-01101000-10110001-00010111
+// CHECK-INST: fmin    { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x17,0xb1,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b117 <unknown>
+
+fmin    {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h}  // 11000001-01111110-10110001-00011111
+// CHECK-INST: fmin    { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x1f,0xb1,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17eb11f <unknown>
+
+
+fmin    {z0.s, z1.s}, {z0.s, z1.s}, z0.s  // 11000001-10100000-10100001-00000001
+// CHECK-INST: fmin    { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x01,0xa1,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a101 <unknown>
+
+fmin    {z20.s, z21.s}, {z20.s, z21.s}, z5.s  // 11000001-10100101-10100001-00010101
+// CHECK-INST: fmin    { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x15,0xa1,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a115 <unknown>
+
+fmin    {z22.s, z23.s}, {z22.s, z23.s}, z8.s  // 11000001-10101000-10100001-00010111
+// CHECK-INST: fmin    { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x17,0xa1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a117 <unknown>
+
+fmin    {z30.s, z31.s}, {z30.s, z31.s}, z15.s  // 11000001-10101111-10100001-00011111
+// CHECK-INST: fmin    { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x1f,0xa1,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa11f <unknown>
+
+
+fmin    {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s}  // 11000001-10100000-10110001-00000001
+// CHECK-INST: fmin    { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x01,0xb1,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b101 <unknown>
+
+fmin    {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s}  // 11000001-10110100-10110001-00010101
+// CHECK-INST: fmin    { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x15,0xb1,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b115 <unknown>
+
+fmin    {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s}  // 11000001-10101000-10110001-00010111
+// CHECK-INST: fmin    { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x17,0xb1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b117 <unknown>
+
+fmin    {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s}  // 11000001-10111110-10110001-00011111
+// CHECK-INST: fmin    { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x1f,0xb1,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1beb11f <unknown>
+
+
+fmin    {z0.d - z3.d}, {z0.d - z3.d}, z0.d  // 11000001-11100000-10101001-00000001
+// CHECK-INST: fmin    { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x01,0xa9,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a901 <unknown>
+
+fmin    {z20.d - z23.d}, {z20.d - z23.d}, z5.d  // 11000001-11100101-10101001-00010101
+// CHECK-INST: fmin    { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x15,0xa9,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a915 <unknown>
+
+fmin    {z20.d - z23.d}, {z20.d - z23.d}, z8.d  // 11000001-11101000-10101001-00010101
+// CHECK-INST: fmin    { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x15,0xa9,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a915 <unknown>
+
+fmin    {z28.d - z31.d}, {z28.d - z31.d}, z15.d  // 11000001-11101111-10101001-00011101
+// CHECK-INST: fmin    { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x1d,0xa9,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa91d <unknown>
+
+
+fmin    {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d}  // 11000001-11100000-10111001-00000001
+// CHECK-INST: fmin    { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x01,0xb9,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b901 <unknown>
+
+fmin    {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d}  // 11000001-11110100-10111001-00010101
+// CHECK-INST: fmin    { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x15,0xb9,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b915 <unknown>
+
+fmin    {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d}  // 11000001-11101000-10111001-00010101
+// CHECK-INST: fmin    { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x15,0xb9,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b915 <unknown>
+
+fmin    {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d}  // 11000001-11111100-10111001-00011101
+// CHECK-INST: fmin    { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x1d,0xb9,0xfc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fcb91d <unknown>
+
+
+fmin    {z0.h - z3.h}, {z0.h - z3.h}, z0.h  // 11000001-01100000-10101001-00000001
+// CHECK-INST: fmin    { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x01,0xa9,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a901 <unknown>
+
+fmin    {z20.h - z23.h}, {z20.h - z23.h}, z5.h  // 11000001-01100101-10101001-00010101
+// CHECK-INST: fmin    { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x15,0xa9,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a915 <unknown>
+
+fmin    {z20.h - z23.h}, {z20.h - z23.h}, z8.h  // 11000001-01101000-10101001-00010101
+// CHECK-INST: fmin    { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x15,0xa9,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a915 <unknown>
+
+fmin    {z28.h - z31.h}, {z28.h - z31.h}, z15.h  // 11000001-01101111-10101001-00011101
+// CHECK-INST: fmin    { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x1d,0xa9,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa91d <unknown>
+
+
+fmin    {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-01100000-10111001-00000001
+// CHECK-INST: fmin    { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x01,0xb9,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b901 <unknown>
+
+fmin    {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h}  // 11000001-01110100-10111001-00010101
+// CHECK-INST: fmin    { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x15,0xb9,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b915 <unknown>
+
+fmin    {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h}  // 11000001-01101000-10111001-00010101
+// CHECK-INST: fmin    { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x15,0xb9,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b915 <unknown>
+
+fmin    {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-01111100-10111001-00011101
+// CHECK-INST: fmin    { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x1d,0xb9,0x7c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17cb91d <unknown>
+
+
+fmin    {z0.s - z3.s}, {z0.s - z3.s}, z0.s  // 11000001-10100000-10101001-00000001
+// CHECK-INST: fmin    { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x01,0xa9,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a901 <unknown>
+
+fmin    {z20.s - z23.s}, {z20.s - z23.s}, z5.s  // 11000001-10100101-10101001-00010101
+// CHECK-INST: fmin    { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x15,0xa9,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a915 <unknown>
+
+fmin    {z20.s - z23.s}, {z20.s - z23.s}, z8.s  // 11000001-10101000-10101001-00010101
+// CHECK-INST: fmin    { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x15,0xa9,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a915 <unknown>
+
+fmin    {z28.s - z31.s}, {z28.s - z31.s}, z15.s  // 11000001-10101111-10101001-00011101
+// CHECK-INST: fmin    { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x1d,0xa9,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa91d <unknown>
+
+
+fmin    {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s}  // 11000001-10100000-10111001-00000001
+// CHECK-INST: fmin    { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x01,0xb9,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b901 <unknown>
+
+fmin    {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s}  // 11000001-10110100-10111001-00010101
+// CHECK-INST: fmin    { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x15,0xb9,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b915 <unknown>
+
+fmin    {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s}  // 11000001-10101000-10111001-00010101
+// CHECK-INST: fmin    { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x15,0xb9,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b915 <unknown>
+
+fmin    {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s}  // 11000001-10111100-10111001-00011101
+// CHECK-INST: fmin    { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x1d,0xb9,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bcb91d <unknown>
+

llvm/test/MC/AArch64/SME2/fminnm-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+fminnm {z0.d, z1.d}, {z0.d-z2.d}, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fminnm {z0.d, z1.d}, {z0.d-z2.d}, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fminnm {z1.s-z2.s}, {z0.s, z1.s}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
+// CHECK-NEXT: fminnm {z1.s-z2.s}, {z0.s, z1.s}, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid single register
+
+fminnm {z0.h, z1.h}, {z2.h-z3.h}, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fminnm {z0.h, z1.h}, {z2.h-z3.h}, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+fminnm {z0.h, z1.h}, {z2.h-z3.h}, z14.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fminnm {z0.h, z1.h}, {z2.h-z3.h}, z14.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/fminnm.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+fminnm  {z0.d, z1.d}, {z0.d, z1.d}, z0.d  // 11000001-11100000-10100001-00100001
+// CHECK-INST: fminnm  { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x21,0xa1,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a121 <unknown>
+
+fminnm  {z20.d, z21.d}, {z20.d, z21.d}, z5.d  // 11000001-11100101-10100001-00110101
+// CHECK-INST: fminnm  { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x35,0xa1,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a135 <unknown>
+
+fminnm  {z22.d, z23.d}, {z22.d, z23.d}, z8.d  // 11000001-11101000-10100001-00110111
+// CHECK-INST: fminnm  { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x37,0xa1,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a137 <unknown>
+
+fminnm  {z30.d, z31.d}, {z30.d, z31.d}, z15.d  // 11000001-11101111-10100001-00111111
+// CHECK-INST: fminnm  { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x3f,0xa1,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa13f <unknown>
+
+
+fminnm  {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d}  // 11000001-11100000-10110001-00100001
+// CHECK-INST: fminnm  { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x21,0xb1,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b121 <unknown>
+
+fminnm  {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d}  // 11000001-11110100-10110001-00110101
+// CHECK-INST: fminnm  { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x35,0xb1,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b135 <unknown>
+
+fminnm  {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d}  // 11000001-11101000-10110001-00110111
+// CHECK-INST: fminnm  { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x37,0xb1,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b137 <unknown>
+
+fminnm  {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d}  // 11000001-11111110-10110001-00111111
+// CHECK-INST: fminnm  { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x3f,0xb1,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1feb13f <unknown>
+
+
+fminnm  {z0.h, z1.h}, {z0.h, z1.h}, z0.h  // 11000001-01100000-10100001-00100001
+// CHECK-INST: fminnm  { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x21,0xa1,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a121 <unknown>
+
+fminnm  {z20.h, z21.h}, {z20.h, z21.h}, z5.h  // 11000001-01100101-10100001-00110101
+// CHECK-INST: fminnm  { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x35,0xa1,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a135 <unknown>
+
+fminnm  {z22.h, z23.h}, {z22.h, z23.h}, z8.h  // 11000001-01101000-10100001-00110111
+// CHECK-INST: fminnm  { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x37,0xa1,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a137 <unknown>
+
+fminnm  {z30.h, z31.h}, {z30.h, z31.h}, z15.h  // 11000001-01101111-10100001-00111111
+// CHECK-INST: fminnm  { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x3f,0xa1,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa13f <unknown>
+
+
+fminnm  {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h}  // 11000001-01100000-10110001-00100001
+// CHECK-INST: fminnm  { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x21,0xb1,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b121 <unknown>
+
+fminnm  {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h}  // 11000001-01110100-10110001-00110101
+// CHECK-INST: fminnm  { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x35,0xb1,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b135 <unknown>
+
+fminnm  {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h}  // 11000001-01101000-10110001-00110111
+// CHECK-INST: fminnm  { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x37,0xb1,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b137 <unknown>
+
+fminnm  {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h}  // 11000001-01111110-10110001-00111111
+// CHECK-INST: fminnm  { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x3f,0xb1,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17eb13f <unknown>
+
+
+fminnm  {z0.s, z1.s}, {z0.s, z1.s}, z0.s  // 11000001-10100000-10100001-00100001
+// CHECK-INST: fminnm  { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x21,0xa1,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a121 <unknown>
+
+fminnm  {z20.s, z21.s}, {z20.s, z21.s}, z5.s  // 11000001-10100101-10100001-00110101
+// CHECK-INST: fminnm  { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x35,0xa1,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a135 <unknown>
+
+fminnm  {z22.s, z23.s}, {z22.s, z23.s}, z8.s  // 11000001-10101000-10100001-00110111
+// CHECK-INST: fminnm  { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x37,0xa1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a137 <unknown>
+
+fminnm  {z30.s, z31.s}, {z30.s, z31.s}, z15.s  // 11000001-10101111-10100001-00111111
+// CHECK-INST: fminnm  { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x3f,0xa1,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa13f <unknown>
+
+
+fminnm  {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s}  // 11000001-10100000-10110001-00100001
+// CHECK-INST: fminnm  { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x21,0xb1,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b121 <unknown>
+
+fminnm  {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s}  // 11000001-10110100-10110001-00110101
+// CHECK-INST: fminnm  { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x35,0xb1,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b135 <unknown>
+
+fminnm  {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s}  // 11000001-10101000-10110001-00110111
+// CHECK-INST: fminnm  { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x37,0xb1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b137 <unknown>
+
+fminnm  {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s}  // 11000001-10111110-10110001-00111111
+// CHECK-INST: fminnm  { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x3f,0xb1,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1beb13f <unknown>
+
+
+fminnm  {z0.d - z3.d}, {z0.d - z3.d}, z0.d  // 11000001-11100000-10101001-00100001
+// CHECK-INST: fminnm  { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x21,0xa9,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a921 <unknown>
+
+fminnm  {z20.d - z23.d}, {z20.d - z23.d}, z5.d  // 11000001-11100101-10101001-00110101
+// CHECK-INST: fminnm  { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x35,0xa9,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a935 <unknown>
+
+fminnm  {z20.d - z23.d}, {z20.d - z23.d}, z8.d  // 11000001-11101000-10101001-00110101
+// CHECK-INST: fminnm  { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x35,0xa9,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a935 <unknown>
+
+fminnm  {z28.d - z31.d}, {z28.d - z31.d}, z15.d  // 11000001-11101111-10101001-00111101
+// CHECK-INST: fminnm  { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x3d,0xa9,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa93d <unknown>
+
+
+fminnm  {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d}  // 11000001-11100000-10111001-00100001
+// CHECK-INST: fminnm  { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x21,0xb9,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b921 <unknown>
+
+fminnm  {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d}  // 11000001-11110100-10111001-00110101
+// CHECK-INST: fminnm  { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x35,0xb9,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b935 <unknown>
+
+fminnm  {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d}  // 11000001-11101000-10111001-00110101
+// CHECK-INST: fminnm  { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x35,0xb9,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b935 <unknown>
+
+fminnm  {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d}  // 11000001-11111100-10111001-00111101
+// CHECK-INST: fminnm  { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x3d,0xb9,0xfc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fcb93d <unknown>
+
+
+fminnm  {z0.h - z3.h}, {z0.h - z3.h}, z0.h  // 11000001-01100000-10101001-00100001
+// CHECK-INST: fminnm  { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x21,0xa9,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a921 <unknown>
+
+fminnm  {z20.h - z23.h}, {z20.h - z23.h}, z5.h  // 11000001-01100101-10101001-00110101
+// CHECK-INST: fminnm  { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x35,0xa9,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a935 <unknown>
+
+fminnm  {z20.h - z23.h}, {z20.h - z23.h}, z8.h  // 11000001-01101000-10101001-00110101
+// CHECK-INST: fminnm  { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x35,0xa9,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a935 <unknown>
+
+fminnm  {z28.h - z31.h}, {z28.h - z31.h}, z15.h  // 11000001-01101111-10101001-00111101
+// CHECK-INST: fminnm  { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x3d,0xa9,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa93d <unknown>
+
+
+fminnm  {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-01100000-10111001-00100001
+// CHECK-INST: fminnm  { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x21,0xb9,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b921 <unknown>
+
+fminnm  {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h}  // 11000001-01110100-10111001-00110101
+// CHECK-INST: fminnm  { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x35,0xb9,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b935 <unknown>
+
+fminnm  {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h}  // 11000001-01101000-10111001-00110101
+// CHECK-INST: fminnm  { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x35,0xb9,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b935 <unknown>
+
+fminnm  {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-01111100-10111001-00111101
+// CHECK-INST: fminnm  { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x3d,0xb9,0x7c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17cb93d <unknown>
+
+
+fminnm  {z0.s - z3.s}, {z0.s - z3.s}, z0.s  // 11000001-10100000-10101001-00100001
+// CHECK-INST: fminnm  { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x21,0xa9,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a921 <unknown>
+
+fminnm  {z20.s - z23.s}, {z20.s - z23.s}, z5.s  // 11000001-10100101-10101001-00110101
+// CHECK-INST: fminnm  { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x35,0xa9,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a935 <unknown>
+
+fminnm  {z20.s - z23.s}, {z20.s - z23.s}, z8.s  // 11000001-10101000-10101001-00110101
+// CHECK-INST: fminnm  { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x35,0xa9,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a935 <unknown>
+
+fminnm  {z28.s - z31.s}, {z28.s - z31.s}, z15.s  // 11000001-10101111-10101001-00111101
+// CHECK-INST: fminnm  { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x3d,0xa9,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa93d <unknown>
+
+
+fminnm  {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s}  // 11000001-10100000-10111001-00100001
+// CHECK-INST: fminnm  { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x21,0xb9,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b921 <unknown>
+
+fminnm  {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s}  // 11000001-10110100-10111001-00110101
+// CHECK-INST: fminnm  { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x35,0xb9,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b935 <unknown>
+
+fminnm  {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s}  // 11000001-10101000-10111001-00110101
+// CHECK-INST: fminnm  { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x35,0xb9,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b935 <unknown>
+
+fminnm  {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s}  // 11000001-10111100-10111001-00111101
+// CHECK-INST: fminnm  { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x3d,0xb9,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bcb93d <unknown>
+

llvm/test/MC/AArch64/SME2/smax-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+smax {z0.h, z1.h}, {z0.h-z2.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smax {z0.h, z1.h}, {z0.h-z2.h}, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smax {z1.d-z2.d}, {z0.d, z1.d}, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
+// CHECK-NEXT: smax {z1.d-z2.d}, {z0.d, z1.d}, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid single register
+
+smax {z0.b, z1.b}, {z2.b-z3.b}, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
+// CHECK-NEXT: smax {z0.b, z1.b}, {z2.b-z3.b}, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+smax {z0.b, z1.b}, {z2.b-z3.b}, z14.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
+// CHECK-NEXT: smax {z0.b, z1.b}, {z2.b-z3.b}, z14.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/smax.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+smax    {z0.h, z1.h}, {z0.h, z1.h}, z0.h  // 11000001-01100000-10100000-00000000
+// CHECK-INST: smax    { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x00,0xa0,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a000 <unknown>
+
+smax    {z20.h, z21.h}, {z20.h, z21.h}, z5.h  // 11000001-01100101-10100000-00010100
+// CHECK-INST: smax    { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x14,0xa0,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a014 <unknown>
+
+smax    {z22.h, z23.h}, {z22.h, z23.h}, z8.h  // 11000001-01101000-10100000-00010110
+// CHECK-INST: smax    { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x16,0xa0,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a016 <unknown>
+
+smax    {z30.h, z31.h}, {z30.h, z31.h}, z15.h  // 11000001-01101111-10100000-00011110
+// CHECK-INST: smax    { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x1e,0xa0,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa01e <unknown>
+
+
+smax    {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h}  // 11000001-01100000-10110000-00000000
+// CHECK-INST: smax    { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x00,0xb0,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b000 <unknown>
+
+smax    {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h}  // 11000001-01110100-10110000-00010100
+// CHECK-INST: smax    { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x14,0xb0,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b014 <unknown>
+
+smax    {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h}  // 11000001-01101000-10110000-00010110
+// CHECK-INST: smax    { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x16,0xb0,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b016 <unknown>
+
+smax    {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h}  // 11000001-01111110-10110000-00011110
+// CHECK-INST: smax    { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x1e,0xb0,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17eb01e <unknown>
+
+
+smax    {z0.s, z1.s}, {z0.s, z1.s}, z0.s  // 11000001-10100000-10100000-00000000
+// CHECK-INST: smax    { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x00,0xa0,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a000 <unknown>
+
+smax    {z20.s, z21.s}, {z20.s, z21.s}, z5.s  // 11000001-10100101-10100000-00010100
+// CHECK-INST: smax    { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x14,0xa0,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a014 <unknown>
+
+smax    {z22.s, z23.s}, {z22.s, z23.s}, z8.s  // 11000001-10101000-10100000-00010110
+// CHECK-INST: smax    { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x16,0xa0,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a016 <unknown>
+
+smax    {z30.s, z31.s}, {z30.s, z31.s}, z15.s  // 11000001-10101111-10100000-00011110
+// CHECK-INST: smax    { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x1e,0xa0,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa01e <unknown>
+
+
+smax    {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s}  // 11000001-10100000-10110000-00000000
+// CHECK-INST: smax    { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x00,0xb0,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b000 <unknown>
+
+smax    {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s}  // 11000001-10110100-10110000-00010100
+// CHECK-INST: smax    { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x14,0xb0,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b014 <unknown>
+
+smax    {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s}  // 11000001-10101000-10110000-00010110
+// CHECK-INST: smax    { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x16,0xb0,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b016 <unknown>
+
+smax    {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s}  // 11000001-10111110-10110000-00011110
+// CHECK-INST: smax    { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x1e,0xb0,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1beb01e <unknown>
+
+
+smax    {z0.d, z1.d}, {z0.d, z1.d}, z0.d  // 11000001-11100000-10100000-00000000
+// CHECK-INST: smax    { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x00,0xa0,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a000 <unknown>
+
+smax    {z20.d, z21.d}, {z20.d, z21.d}, z5.d  // 11000001-11100101-10100000-00010100
+// CHECK-INST: smax    { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x14,0xa0,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a014 <unknown>
+
+smax    {z22.d, z23.d}, {z22.d, z23.d}, z8.d  // 11000001-11101000-10100000-00010110
+// CHECK-INST: smax    { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x16,0xa0,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a016 <unknown>
+
+smax    {z30.d, z31.d}, {z30.d, z31.d}, z15.d  // 11000001-11101111-10100000-00011110
+// CHECK-INST: smax    { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x1e,0xa0,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa01e <unknown>
+
+
+smax    {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d}  // 11000001-11100000-10110000-00000000
+// CHECK-INST: smax    { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x00,0xb0,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b000 <unknown>
+
+smax    {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d}  // 11000001-11110100-10110000-00010100
+// CHECK-INST: smax    { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x14,0xb0,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b014 <unknown>
+
+smax    {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d}  // 11000001-11101000-10110000-00010110
+// CHECK-INST: smax    { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x16,0xb0,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b016 <unknown>
+
+smax    {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d}  // 11000001-11111110-10110000-00011110
+// CHECK-INST: smax    { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x1e,0xb0,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1feb01e <unknown>
+
+
+smax    {z0.b, z1.b}, {z0.b, z1.b}, z0.b  // 11000001-00100000-10100000-00000000
+// CHECK-INST: smax    { z0.b, z1.b }, { z0.b, z1.b }, z0.b
+// CHECK-ENCODING: [0x00,0xa0,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a000 <unknown>
+
+smax    {z20.b, z21.b}, {z20.b, z21.b}, z5.b  // 11000001-00100101-10100000-00010100
+// CHECK-INST: smax    { z20.b, z21.b }, { z20.b, z21.b }, z5.b
+// CHECK-ENCODING: [0x14,0xa0,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a014 <unknown>
+
+smax    {z22.b, z23.b}, {z22.b, z23.b}, z8.b  // 11000001-00101000-10100000-00010110
+// CHECK-INST: smax    { z22.b, z23.b }, { z22.b, z23.b }, z8.b
+// CHECK-ENCODING: [0x16,0xa0,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a016 <unknown>
+
+smax    {z30.b, z31.b}, {z30.b, z31.b}, z15.b  // 11000001-00101111-10100000-00011110
+// CHECK-INST: smax    { z30.b, z31.b }, { z30.b, z31.b }, z15.b
+// CHECK-ENCODING: [0x1e,0xa0,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa01e <unknown>
+
+
+smax    {z0.b, z1.b}, {z0.b, z1.b}, {z0.b, z1.b}  // 11000001-00100000-10110000-00000000
+// CHECK-INST: smax    { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }
+// CHECK-ENCODING: [0x00,0xb0,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120b000 <unknown>
+
+smax    {z20.b, z21.b}, {z20.b, z21.b}, {z20.b, z21.b}  // 11000001-00110100-10110000-00010100
+// CHECK-INST: smax    { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }
+// CHECK-ENCODING: [0x14,0xb0,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134b014 <unknown>
+
+smax    {z22.b, z23.b}, {z22.b, z23.b}, {z8.b, z9.b}  // 11000001-00101000-10110000-00010110
+// CHECK-INST: smax    { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }
+// CHECK-ENCODING: [0x16,0xb0,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128b016 <unknown>
+
+smax    {z30.b, z31.b}, {z30.b, z31.b}, {z30.b, z31.b}  // 11000001-00111110-10110000-00011110
+// CHECK-INST: smax    { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }
+// CHECK-ENCODING: [0x1e,0xb0,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13eb01e <unknown>
+
+
+smax    {z0.h - z3.h}, {z0.h - z3.h}, z0.h  // 11000001-01100000-10101000-00000000
+// CHECK-INST: smax    { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x00,0xa8,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a800 <unknown>
+
+smax    {z20.h - z23.h}, {z20.h - z23.h}, z5.h  // 11000001-01100101-10101000-00010100
+// CHECK-INST: smax    { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x14,0xa8,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a814 <unknown>
+
+smax    {z20.h - z23.h}, {z20.h - z23.h}, z8.h  // 11000001-01101000-10101000-00010100
+// CHECK-INST: smax    { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x14,0xa8,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a814 <unknown>
+
+smax    {z28.h - z31.h}, {z28.h - z31.h}, z15.h  // 11000001-01101111-10101000-00011100
+// CHECK-INST: smax    { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x1c,0xa8,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa81c <unknown>
+
+
+smax    {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-01100000-10111000-00000000
+// CHECK-INST: smax    { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x00,0xb8,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b800 <unknown>
+
+smax    {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h}  // 11000001-01110100-10111000-00010100
+// CHECK-INST: smax    { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x14,0xb8,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b814 <unknown>
+
+smax    {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h}  // 11000001-01101000-10111000-00010100
+// CHECK-INST: smax    { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x14,0xb8,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b814 <unknown>
+
+smax    {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-01111100-10111000-00011100
+// CHECK-INST: smax    { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x1c,0xb8,0x7c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17cb81c <unknown>
+
+
+smax    {z0.s - z3.s}, {z0.s - z3.s}, z0.s  // 11000001-10100000-10101000-00000000
+// CHECK-INST: smax    { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x00,0xa8,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a800 <unknown>
+
+smax    {z20.s - z23.s}, {z20.s - z23.s}, z5.s  // 11000001-10100101-10101000-00010100
+// CHECK-INST: smax    { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x14,0xa8,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a814 <unknown>
+
+smax    {z20.s - z23.s}, {z20.s - z23.s}, z8.s  // 11000001-10101000-10101000-00010100
+// CHECK-INST: smax    { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x14,0xa8,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a814 <unknown>
+
+smax    {z28.s - z31.s}, {z28.s - z31.s}, z15.s  // 11000001-10101111-10101000-00011100
+// CHECK-INST: smax    { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x1c,0xa8,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa81c <unknown>
+
+
+smax    {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s}  // 11000001-10100000-10111000-00000000
+// CHECK-INST: smax    { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x00,0xb8,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b800 <unknown>
+
+smax    {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s}  // 11000001-10110100-10111000-00010100
+// CHECK-INST: smax    { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x14,0xb8,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b814 <unknown>
+
+smax    {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s}  // 11000001-10101000-10111000-00010100
+// CHECK-INST: smax    { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x14,0xb8,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b814 <unknown>
+
+smax    {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s}  // 11000001-10111100-10111000-00011100
+// CHECK-INST: smax    { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x1c,0xb8,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bcb81c <unknown>
+
+
+smax    {z0.d - z3.d}, {z0.d - z3.d}, z0.d  // 11000001-11100000-10101000-00000000
+// CHECK-INST: smax    { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x00,0xa8,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a800 <unknown>
+
+smax    {z20.d - z23.d}, {z20.d - z23.d}, z5.d  // 11000001-11100101-10101000-00010100
+// CHECK-INST: smax    { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x14,0xa8,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a814 <unknown>
+
+smax    {z20.d - z23.d}, {z20.d - z23.d}, z8.d  // 11000001-11101000-10101000-00010100
+// CHECK-INST: smax    { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x14,0xa8,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a814 <unknown>
+
+smax    {z28.d - z31.d}, {z28.d - z31.d}, z15.d  // 11000001-11101111-10101000-00011100
+// CHECK-INST: smax    { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x1c,0xa8,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa81c <unknown>
+
+
+smax    {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d}  // 11000001-11100000-10111000-00000000
+// CHECK-INST: smax    { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x00,0xb8,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b800 <unknown>
+
+smax    {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d}  // 11000001-11110100-10111000-00010100
+// CHECK-INST: smax    { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x14,0xb8,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b814 <unknown>
+
+smax    {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d}  // 11000001-11101000-10111000-00010100
+// CHECK-INST: smax    { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x14,0xb8,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b814 <unknown>
+
+smax    {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d}  // 11000001-11111100-10111000-00011100
+// CHECK-INST: smax    { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x1c,0xb8,0xfc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fcb81c <unknown>
+
+
+smax    {z0.b - z3.b}, {z0.b - z3.b}, z0.b  // 11000001-00100000-10101000-00000000
+// CHECK-INST: smax    { z0.b - z3.b }, { z0.b - z3.b }, z0.b
+// CHECK-ENCODING: [0x00,0xa8,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a800 <unknown>
+
+smax    {z20.b - z23.b}, {z20.b - z23.b}, z5.b  // 11000001-00100101-10101000-00010100
+// CHECK-INST: smax    { z20.b - z23.b }, { z20.b - z23.b }, z5.b
+// CHECK-ENCODING: [0x14,0xa8,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a814 <unknown>
+
+smax    {z20.b - z23.b}, {z20.b - z23.b}, z8.b  // 11000001-00101000-10101000-00010100
+// CHECK-INST: smax    { z20.b - z23.b }, { z20.b - z23.b }, z8.b
+// CHECK-ENCODING: [0x14,0xa8,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a814 <unknown>
+
+smax    {z28.b - z31.b}, {z28.b - z31.b}, z15.b  // 11000001-00101111-10101000-00011100
+// CHECK-INST: smax    { z28.b - z31.b }, { z28.b - z31.b }, z15.b
+// CHECK-ENCODING: [0x1c,0xa8,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa81c <unknown>
+
+
+smax    {z0.b - z3.b}, {z0.b - z3.b}, {z0.b - z3.b}  // 11000001-00100000-10111000-00000000
+// CHECK-INST: smax    { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }
+// CHECK-ENCODING: [0x00,0xb8,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120b800 <unknown>
+
+smax    {z20.b - z23.b}, {z20.b - z23.b}, {z20.b - z23.b}  // 11000001-00110100-10111000-00010100
+// CHECK-INST: smax    { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }
+// CHECK-ENCODING: [0x14,0xb8,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134b814 <unknown>
+
+smax    {z20.b - z23.b}, {z20.b - z23.b}, {z8.b - z11.b}  // 11000001-00101000-10111000-00010100
+// CHECK-INST: smax    { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }
+// CHECK-ENCODING: [0x14,0xb8,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128b814 <unknown>
+
+smax    {z28.b - z31.b}, {z28.b - z31.b}, {z28.b - z31.b}  // 11000001-00111100-10111000-00011100
+// CHECK-INST: smax    { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }
+// CHECK-ENCODING: [0x1c,0xb8,0x3c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13cb81c <unknown>
+

llvm/test/MC/AArch64/SME2/smin-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+smin {z0.h, z1.h}, {z0.h-z2.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smin {z0.h, z1.h}, {z0.h-z2.h}, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smin {z1.d-z2.d}, {z0.d, z1.d}, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
+// CHECK-NEXT: smin {z1.d-z2.d}, {z0.d, z1.d}, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid single register
+
+smin {z0.b, z1.b}, {z2.b-z3.b}, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
+// CHECK-NEXT: smin {z0.b, z1.b}, {z2.b-z3.b}, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+smin {z0.b, z1.b}, {z2.b-z3.b}, z14.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
+// CHECK-NEXT: smin {z0.b, z1.b}, {z2.b-z3.b}, z14.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/smin.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+smin    {z0.h, z1.h}, {z0.h, z1.h}, z0.h  // 11000001-01100000-10100000-00100000
+// CHECK-INST: smin    { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x20,0xa0,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a020 <unknown>
+
+smin    {z20.h, z21.h}, {z20.h, z21.h}, z5.h  // 11000001-01100101-10100000-00110100
+// CHECK-INST: smin    { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x34,0xa0,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a034 <unknown>
+
+smin    {z22.h, z23.h}, {z22.h, z23.h}, z8.h  // 11000001-01101000-10100000-00110110
+// CHECK-INST: smin    { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x36,0xa0,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a036 <unknown>
+
+smin    {z30.h, z31.h}, {z30.h, z31.h}, z15.h  // 11000001-01101111-10100000-00111110
+// CHECK-INST: smin    { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x3e,0xa0,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa03e <unknown>
+
+
+smin    {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h}  // 11000001-01100000-10110000-00100000
+// CHECK-INST: smin    { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x20,0xb0,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b020 <unknown>
+
+smin    {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h}  // 11000001-01110100-10110000-00110100
+// CHECK-INST: smin    { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x34,0xb0,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b034 <unknown>
+
+smin    {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h}  // 11000001-01101000-10110000-00110110
+// CHECK-INST: smin    { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x36,0xb0,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b036 <unknown>
+
+smin    {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h}  // 11000001-01111110-10110000-00111110
+// CHECK-INST: smin    { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x3e,0xb0,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17eb03e <unknown>
+
+
+smin    {z0.s, z1.s}, {z0.s, z1.s}, z0.s  // 11000001-10100000-10100000-00100000
+// CHECK-INST: smin    { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x20,0xa0,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a020 <unknown>
+
+smin    {z20.s, z21.s}, {z20.s, z21.s}, z5.s  // 11000001-10100101-10100000-00110100
+// CHECK-INST: smin    { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x34,0xa0,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a034 <unknown>
+
+smin    {z22.s, z23.s}, {z22.s, z23.s}, z8.s  // 11000001-10101000-10100000-00110110
+// CHECK-INST: smin    { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x36,0xa0,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a036 <unknown>
+
+smin    {z30.s, z31.s}, {z30.s, z31.s}, z15.s  // 11000001-10101111-10100000-00111110
+// CHECK-INST: smin    { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x3e,0xa0,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa03e <unknown>
+
+
+smin    {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s}  // 11000001-10100000-10110000-00100000
+// CHECK-INST: smin    { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x20,0xb0,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b020 <unknown>
+
+smin    {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s}  // 11000001-10110100-10110000-00110100
+// CHECK-INST: smin    { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x34,0xb0,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b034 <unknown>
+
+smin    {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s}  // 11000001-10101000-10110000-00110110
+// CHECK-INST: smin    { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x36,0xb0,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b036 <unknown>
+
+smin    {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s}  // 11000001-10111110-10110000-00111110
+// CHECK-INST: smin    { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x3e,0xb0,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1beb03e <unknown>
+
+
+smin    {z0.d, z1.d}, {z0.d, z1.d}, z0.d  // 11000001-11100000-10100000-00100000
+// CHECK-INST: smin    { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x20,0xa0,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a020 <unknown>
+
+smin    {z20.d, z21.d}, {z20.d, z21.d}, z5.d  // 11000001-11100101-10100000-00110100
+// CHECK-INST: smin    { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x34,0xa0,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a034 <unknown>
+
+smin    {z22.d, z23.d}, {z22.d, z23.d}, z8.d  // 11000001-11101000-10100000-00110110
+// CHECK-INST: smin    { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x36,0xa0,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a036 <unknown>
+
+smin    {z30.d, z31.d}, {z30.d, z31.d}, z15.d  // 11000001-11101111-10100000-00111110
+// CHECK-INST: smin    { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x3e,0xa0,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa03e <unknown>
+
+
+smin    {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d}  // 11000001-11100000-10110000-00100000
+// CHECK-INST: smin    { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x20,0xb0,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b020 <unknown>
+
+smin    {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d}  // 11000001-11110100-10110000-00110100
+// CHECK-INST: smin    { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x34,0xb0,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b034 <unknown>
+
+smin    {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d}  // 11000001-11101000-10110000-00110110
+// CHECK-INST: smin    { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x36,0xb0,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b036 <unknown>
+
+smin    {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d}  // 11000001-11111110-10110000-00111110
+// CHECK-INST: smin    { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x3e,0xb0,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1feb03e <unknown>
+
+
+smin    {z0.b, z1.b}, {z0.b, z1.b}, z0.b  // 11000001-00100000-10100000-00100000
+// CHECK-INST: smin    { z0.b, z1.b }, { z0.b, z1.b }, z0.b
+// CHECK-ENCODING: [0x20,0xa0,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a020 <unknown>
+
+smin    {z20.b, z21.b}, {z20.b, z21.b}, z5.b  // 11000001-00100101-10100000-00110100
+// CHECK-INST: smin    { z20.b, z21.b }, { z20.b, z21.b }, z5.b
+// CHECK-ENCODING: [0x34,0xa0,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a034 <unknown>
+
+smin    {z22.b, z23.b}, {z22.b, z23.b}, z8.b  // 11000001-00101000-10100000-00110110
+// CHECK-INST: smin    { z22.b, z23.b }, { z22.b, z23.b }, z8.b
+// CHECK-ENCODING: [0x36,0xa0,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a036 <unknown>
+
+smin    {z30.b, z31.b}, {z30.b, z31.b}, z15.b  // 11000001-00101111-10100000-00111110
+// CHECK-INST: smin    { z30.b, z31.b }, { z30.b, z31.b }, z15.b
+// CHECK-ENCODING: [0x3e,0xa0,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa03e <unknown>
+
+
+smin    {z0.b, z1.b}, {z0.b, z1.b}, {z0.b, z1.b}  // 11000001-00100000-10110000-00100000
+// CHECK-INST: smin    { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }
+// CHECK-ENCODING: [0x20,0xb0,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120b020 <unknown>
+
+smin    {z20.b, z21.b}, {z20.b, z21.b}, {z20.b, z21.b}  // 11000001-00110100-10110000-00110100
+// CHECK-INST: smin    { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }
+// CHECK-ENCODING: [0x34,0xb0,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134b034 <unknown>
+
+smin    {z22.b, z23.b}, {z22.b, z23.b}, {z8.b, z9.b}  // 11000001-00101000-10110000-00110110
+// CHECK-INST: smin    { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }
+// CHECK-ENCODING: [0x36,0xb0,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128b036 <unknown>
+
+smin    {z30.b, z31.b}, {z30.b, z31.b}, {z30.b, z31.b}  // 11000001-00111110-10110000-00111110
+// CHECK-INST: smin    { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }
+// CHECK-ENCODING: [0x3e,0xb0,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13eb03e <unknown>
+
+
+smin    {z0.h - z3.h}, {z0.h - z3.h}, z0.h  // 11000001-01100000-10101000-00100000
+// CHECK-INST: smin    { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x20,0xa8,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a820 <unknown>
+
+smin    {z20.h - z23.h}, {z20.h - z23.h}, z5.h  // 11000001-01100101-10101000-00110100
+// CHECK-INST: smin    { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x34,0xa8,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a834 <unknown>
+
+smin    {z20.h - z23.h}, {z20.h - z23.h}, z8.h  // 11000001-01101000-10101000-00110100
+// CHECK-INST: smin    { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x34,0xa8,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a834 <unknown>
+
+smin    {z28.h - z31.h}, {z28.h - z31.h}, z15.h  // 11000001-01101111-10101000-00111100
+// CHECK-INST: smin    { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x3c,0xa8,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa83c <unknown>
+
+
+smin    {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-01100000-10111000-00100000
+// CHECK-INST: smin    { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x20,0xb8,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b820 <unknown>
+
+smin    {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h}  // 11000001-01110100-10111000-00110100
+// CHECK-INST: smin    { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x34,0xb8,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b834 <unknown>
+
+smin    {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h}  // 11000001-01101000-10111000-00110100
+// CHECK-INST: smin    { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x34,0xb8,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b834 <unknown>
+
+smin    {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-01111100-10111000-00111100
+// CHECK-INST: smin    { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x3c,0xb8,0x7c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17cb83c <unknown>
+
+
+smin    {z0.s - z3.s}, {z0.s - z3.s}, z0.s  // 11000001-10100000-10101000-00100000
+// CHECK-INST: smin    { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x20,0xa8,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a820 <unknown>
+
+smin    {z20.s - z23.s}, {z20.s - z23.s}, z5.s  // 11000001-10100101-10101000-00110100
+// CHECK-INST: smin    { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x34,0xa8,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a834 <unknown>
+
+smin    {z20.s - z23.s}, {z20.s - z23.s}, z8.s  // 11000001-10101000-10101000-00110100
+// CHECK-INST: smin    { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x34,0xa8,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a834 <unknown>
+
+smin    {z28.s - z31.s}, {z28.s - z31.s}, z15.s  // 11000001-10101111-10101000-00111100
+// CHECK-INST: smin    { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x3c,0xa8,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa83c <unknown>
+
+
+smin    {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s}  // 11000001-10100000-10111000-00100000
+// CHECK-INST: smin    { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x20,0xb8,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b820 <unknown>
+
+smin    {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s}  // 11000001-10110100-10111000-00110100
+// CHECK-INST: smin    { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x34,0xb8,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b834 <unknown>
+
+smin    {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s}  // 11000001-10101000-10111000-00110100
+// CHECK-INST: smin    { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x34,0xb8,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b834 <unknown>
+
+smin    {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s}  // 11000001-10111100-10111000-00111100
+// CHECK-INST: smin    { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x3c,0xb8,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bcb83c <unknown>
+
+
+smin    {z0.d - z3.d}, {z0.d - z3.d}, z0.d  // 11000001-11100000-10101000-00100000
+// CHECK-INST: smin    { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x20,0xa8,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a820 <unknown>
+
+smin    {z20.d - z23.d}, {z20.d - z23.d}, z5.d  // 11000001-11100101-10101000-00110100
+// CHECK-INST: smin    { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x34,0xa8,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a834 <unknown>
+
+smin    {z20.d - z23.d}, {z20.d - z23.d}, z8.d  // 11000001-11101000-10101000-00110100
+// CHECK-INST: smin    { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x34,0xa8,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a834 <unknown>
+
+smin    {z28.d - z31.d}, {z28.d - z31.d}, z15.d  // 11000001-11101111-10101000-00111100
+// CHECK-INST: smin    { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x3c,0xa8,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa83c <unknown>
+
+
+smin    {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d}  // 11000001-11100000-10111000-00100000
+// CHECK-INST: smin    { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x20,0xb8,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b820 <unknown>
+
+smin    {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d}  // 11000001-11110100-10111000-00110100
+// CHECK-INST: smin    { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x34,0xb8,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b834 <unknown>
+
+smin    {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d}  // 11000001-11101000-10111000-00110100
+// CHECK-INST: smin    { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x34,0xb8,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b834 <unknown>
+
+smin    {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d}  // 11000001-11111100-10111000-00111100
+// CHECK-INST: smin    { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x3c,0xb8,0xfc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fcb83c <unknown>
+
+
+smin    {z0.b - z3.b}, {z0.b - z3.b}, z0.b  // 11000001-00100000-10101000-00100000
+// CHECK-INST: smin    { z0.b - z3.b }, { z0.b - z3.b }, z0.b
+// CHECK-ENCODING: [0x20,0xa8,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a820 <unknown>
+
+smin    {z20.b - z23.b}, {z20.b - z23.b}, z5.b  // 11000001-00100101-10101000-00110100
+// CHECK-INST: smin    { z20.b - z23.b }, { z20.b - z23.b }, z5.b
+// CHECK-ENCODING: [0x34,0xa8,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a834 <unknown>
+
+smin    {z20.b - z23.b}, {z20.b - z23.b}, z8.b  // 11000001-00101000-10101000-00110100
+// CHECK-INST: smin    { z20.b - z23.b }, { z20.b - z23.b }, z8.b
+// CHECK-ENCODING: [0x34,0xa8,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a834 <unknown>
+
+smin    {z28.b - z31.b}, {z28.b - z31.b}, z15.b  // 11000001-00101111-10101000-00111100
+// CHECK-INST: smin    { z28.b - z31.b }, { z28.b - z31.b }, z15.b
+// CHECK-ENCODING: [0x3c,0xa8,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa83c <unknown>
+
+
+smin    {z0.b - z3.b}, {z0.b - z3.b}, {z0.b - z3.b}  // 11000001-00100000-10111000-00100000
+// CHECK-INST: smin    { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }
+// CHECK-ENCODING: [0x20,0xb8,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120b820 <unknown>
+
+smin    {z20.b - z23.b}, {z20.b - z23.b}, {z20.b - z23.b}  // 11000001-00110100-10111000-00110100
+// CHECK-INST: smin    { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }
+// CHECK-ENCODING: [0x34,0xb8,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134b834 <unknown>
+
+smin    {z20.b - z23.b}, {z20.b - z23.b}, {z8.b - z11.b}  // 11000001-00101000-10111000-00110100
+// CHECK-INST: smin    { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }
+// CHECK-ENCODING: [0x34,0xb8,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128b834 <unknown>
+
+smin    {z28.b - z31.b}, {z28.b - z31.b}, {z28.b - z31.b}  // 11000001-00111100-10111000-00111100
+// CHECK-INST: smin    { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }
+// CHECK-ENCODING: [0x3c,0xb8,0x3c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13cb83c <unknown>
+

llvm/test/MC/AArch64/SME2/srshl-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+srshl {z0.h-z2.h}, {z0.h-z1.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: srshl {z0.h-z2.h}, {z0.h-z1.h}, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+srshl {z0.s-z1.s}, {z2.s-z4.s}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: srshl {z0.s-z1.s}, {z2.s-z4.s}, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+srshl {z20.d-z23.d}, {z20.d-z23.d}, {z8.d-z12.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: srshl {z20.d-z23.d}, {z20.d-z23.d}, {z8.d-z12.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+srshl {z29.b-z30.b}, {z30.b-z31.b}, z15.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: srshl {z29.b-z30.b}, {z30.b-z31.b}, z15.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+srshl {z20.h-z23.h}, {z21.h-z24.h}, {z8.h-z11.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: srshl {z20.h-z23.h}, {z21.h-z24.h}, {z8.h-z11.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+srshl {z28.b-z31.b}, {z28.b-z31.b}, {z27.b-z30.b}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: srshl {z28.b-z31.b}, {z28.b-z31.b}, {z27.b-z30.b}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Single Register
+
+srshl {z20.h-z21.h}, {z20.h-z21.h}, z16.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: srshl {z20.h-z21.h}, {z20.h-z21.h}, z16.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+srshl {z0.d-z3.d}, {z0.d-z3.d}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d
+// CHECK-NEXT: srshl {z0.d-z3.d}, {z0.d-z3.d}, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/srshl.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+srshl   {z0.h, z1.h}, {z0.h, z1.h}, z0.h  // 11000001-01100000-10100010-00100000
+// CHECK-INST: srshl   { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x20,0xa2,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a220 <unknown>
+
+srshl   {z20.h, z21.h}, {z20.h, z21.h}, z5.h  // 11000001-01100101-10100010-00110100
+// CHECK-INST: srshl   { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x34,0xa2,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a234 <unknown>
+
+srshl   {z22.h, z23.h}, {z22.h, z23.h}, z8.h  // 11000001-01101000-10100010-00110110
+// CHECK-INST: srshl   { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x36,0xa2,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a236 <unknown>
+
+srshl   {z30.h, z31.h}, {z30.h, z31.h}, z15.h  // 11000001-01101111-10100010-00111110
+// CHECK-INST: srshl   { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x3e,0xa2,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa23e <unknown>
+
+
+srshl   {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h}  // 11000001-01100000-10110010-00100000
+// CHECK-INST: srshl   { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x20,0xb2,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b220 <unknown>
+
+srshl   {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h}  // 11000001-01110100-10110010-00110100
+// CHECK-INST: srshl   { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x34,0xb2,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b234 <unknown>
+
+srshl   {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h}  // 11000001-01101000-10110010-00110110
+// CHECK-INST: srshl   { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x36,0xb2,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b236 <unknown>
+
+srshl   {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h}  // 11000001-01111110-10110010-00111110
+// CHECK-INST: srshl   { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x3e,0xb2,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17eb23e <unknown>
+
+
+srshl   {z0.s, z1.s}, {z0.s, z1.s}, z0.s  // 11000001-10100000-10100010-00100000
+// CHECK-INST: srshl   { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x20,0xa2,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a220 <unknown>
+
+srshl   {z20.s, z21.s}, {z20.s, z21.s}, z5.s  // 11000001-10100101-10100010-00110100
+// CHECK-INST: srshl   { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x34,0xa2,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a234 <unknown>
+
+srshl   {z22.s, z23.s}, {z22.s, z23.s}, z8.s  // 11000001-10101000-10100010-00110110
+// CHECK-INST: srshl   { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x36,0xa2,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a236 <unknown>
+
+srshl   {z30.s, z31.s}, {z30.s, z31.s}, z15.s  // 11000001-10101111-10100010-00111110
+// CHECK-INST: srshl   { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x3e,0xa2,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa23e <unknown>
+
+
+srshl   {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s}  // 11000001-10100000-10110010-00100000
+// CHECK-INST: srshl   { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x20,0xb2,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b220 <unknown>
+
+srshl   {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s}  // 11000001-10110100-10110010-00110100
+// CHECK-INST: srshl   { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x34,0xb2,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b234 <unknown>
+
+srshl   {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s}  // 11000001-10101000-10110010-00110110
+// CHECK-INST: srshl   { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x36,0xb2,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b236 <unknown>
+
+srshl   {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s}  // 11000001-10111110-10110010-00111110
+// CHECK-INST: srshl   { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x3e,0xb2,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1beb23e <unknown>
+
+
+srshl   {z0.d, z1.d}, {z0.d, z1.d}, z0.d  // 11000001-11100000-10100010-00100000
+// CHECK-INST: srshl   { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x20,0xa2,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a220 <unknown>
+
+srshl   {z20.d, z21.d}, {z20.d, z21.d}, z5.d  // 11000001-11100101-10100010-00110100
+// CHECK-INST: srshl   { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x34,0xa2,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a234 <unknown>
+
+srshl   {z22.d, z23.d}, {z22.d, z23.d}, z8.d  // 11000001-11101000-10100010-00110110
+// CHECK-INST: srshl   { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x36,0xa2,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a236 <unknown>
+
+srshl   {z30.d, z31.d}, {z30.d, z31.d}, z15.d  // 11000001-11101111-10100010-00111110
+// CHECK-INST: srshl   { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x3e,0xa2,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa23e <unknown>
+
+
+srshl   {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d}  // 11000001-11100000-10110010-00100000
+// CHECK-INST: srshl   { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x20,0xb2,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b220 <unknown>
+
+srshl   {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d}  // 11000001-11110100-10110010-00110100
+// CHECK-INST: srshl   { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x34,0xb2,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b234 <unknown>
+
+srshl   {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d}  // 11000001-11101000-10110010-00110110
+// CHECK-INST: srshl   { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x36,0xb2,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b236 <unknown>
+
+srshl   {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d}  // 11000001-11111110-10110010-00111110
+// CHECK-INST: srshl   { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x3e,0xb2,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1feb23e <unknown>
+
+
+srshl   {z0.b, z1.b}, {z0.b, z1.b}, z0.b  // 11000001-00100000-10100010-00100000
+// CHECK-INST: srshl   { z0.b, z1.b }, { z0.b, z1.b }, z0.b
+// CHECK-ENCODING: [0x20,0xa2,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a220 <unknown>
+
+srshl   {z20.b, z21.b}, {z20.b, z21.b}, z5.b  // 11000001-00100101-10100010-00110100
+// CHECK-INST: srshl   { z20.b, z21.b }, { z20.b, z21.b }, z5.b
+// CHECK-ENCODING: [0x34,0xa2,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a234 <unknown>
+
+srshl   {z22.b, z23.b}, {z22.b, z23.b}, z8.b  // 11000001-00101000-10100010-00110110
+// CHECK-INST: srshl   { z22.b, z23.b }, { z22.b, z23.b }, z8.b
+// CHECK-ENCODING: [0x36,0xa2,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a236 <unknown>
+
+srshl   {z30.b, z31.b}, {z30.b, z31.b}, z15.b  // 11000001-00101111-10100010-00111110
+// CHECK-INST: srshl   { z30.b, z31.b }, { z30.b, z31.b }, z15.b
+// CHECK-ENCODING: [0x3e,0xa2,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa23e <unknown>
+
+
+srshl   {z0.b, z1.b}, {z0.b, z1.b}, {z0.b, z1.b}  // 11000001-00100000-10110010-00100000
+// CHECK-INST: srshl   { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }
+// CHECK-ENCODING: [0x20,0xb2,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120b220 <unknown>
+
+srshl   {z20.b, z21.b}, {z20.b, z21.b}, {z20.b, z21.b}  // 11000001-00110100-10110010-00110100
+// CHECK-INST: srshl   { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }
+// CHECK-ENCODING: [0x34,0xb2,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134b234 <unknown>
+
+srshl   {z22.b, z23.b}, {z22.b, z23.b}, {z8.b, z9.b}  // 11000001-00101000-10110010-00110110
+// CHECK-INST: srshl   { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }
+// CHECK-ENCODING: [0x36,0xb2,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128b236 <unknown>
+
+srshl   {z30.b, z31.b}, {z30.b, z31.b}, {z30.b, z31.b}  // 11000001-00111110-10110010-00111110
+// CHECK-INST: srshl   { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }
+// CHECK-ENCODING: [0x3e,0xb2,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13eb23e <unknown>
+
+
+srshl   {z0.h - z3.h}, {z0.h - z3.h}, z0.h  // 11000001-01100000-10101010-00100000
+// CHECK-INST: srshl   { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x20,0xaa,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160aa20 <unknown>
+
+srshl   {z20.h - z23.h}, {z20.h - z23.h}, z5.h  // 11000001-01100101-10101010-00110100
+// CHECK-INST: srshl   { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x34,0xaa,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165aa34 <unknown>
+
+srshl   {z20.h - z23.h}, {z20.h - z23.h}, z8.h  // 11000001-01101000-10101010-00110100
+// CHECK-INST: srshl   { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x34,0xaa,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168aa34 <unknown>
+
+srshl   {z28.h - z31.h}, {z28.h - z31.h}, z15.h  // 11000001-01101111-10101010-00111100
+// CHECK-INST: srshl   { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x3c,0xaa,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16faa3c <unknown>
+
+
+srshl   {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-01100000-10111010-00100000
+// CHECK-INST: srshl   { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x20,0xba,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160ba20 <unknown>
+
+srshl   {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h}  // 11000001-01110100-10111010-00110100
+// CHECK-INST: srshl   { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x34,0xba,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174ba34 <unknown>
+
+srshl   {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h}  // 11000001-01101000-10111010-00110100
+// CHECK-INST: srshl   { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x34,0xba,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168ba34 <unknown>
+
+srshl   {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-01111100-10111010-00111100
+// CHECK-INST: srshl   { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x3c,0xba,0x7c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17cba3c <unknown>
+
+
+srshl   {z0.s - z3.s}, {z0.s - z3.s}, z0.s  // 11000001-10100000-10101010-00100000
+// CHECK-INST: srshl   { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x20,0xaa,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0aa20 <unknown>
+
+srshl   {z20.s - z23.s}, {z20.s - z23.s}, z5.s  // 11000001-10100101-10101010-00110100
+// CHECK-INST: srshl   { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x34,0xaa,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5aa34 <unknown>
+
+srshl   {z20.s - z23.s}, {z20.s - z23.s}, z8.s  // 11000001-10101000-10101010-00110100
+// CHECK-INST: srshl   { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x34,0xaa,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8aa34 <unknown>
+
+srshl   {z28.s - z31.s}, {z28.s - z31.s}, z15.s  // 11000001-10101111-10101010-00111100
+// CHECK-INST: srshl   { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x3c,0xaa,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afaa3c <unknown>
+
+
+srshl   {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s}  // 11000001-10100000-10111010-00100000
+// CHECK-INST: srshl   { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x20,0xba,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0ba20 <unknown>
+
+srshl   {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s}  // 11000001-10110100-10111010-00110100
+// CHECK-INST: srshl   { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x34,0xba,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4ba34 <unknown>
+
+srshl   {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s}  // 11000001-10101000-10111010-00110100
+// CHECK-INST: srshl   { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x34,0xba,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8ba34 <unknown>
+
+srshl   {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s}  // 11000001-10111100-10111010-00111100
+// CHECK-INST: srshl   { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x3c,0xba,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bcba3c <unknown>
+
+
+srshl   {z0.d - z3.d}, {z0.d - z3.d}, z0.d  // 11000001-11100000-10101010-00100000
+// CHECK-INST: srshl   { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x20,0xaa,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0aa20 <unknown>
+
+srshl   {z20.d - z23.d}, {z20.d - z23.d}, z5.d  // 11000001-11100101-10101010-00110100
+// CHECK-INST: srshl   { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x34,0xaa,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5aa34 <unknown>
+
+srshl   {z20.d - z23.d}, {z20.d - z23.d}, z8.d  // 11000001-11101000-10101010-00110100
+// CHECK-INST: srshl   { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x34,0xaa,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8aa34 <unknown>
+
+srshl   {z28.d - z31.d}, {z28.d - z31.d}, z15.d  // 11000001-11101111-10101010-00111100
+// CHECK-INST: srshl   { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x3c,0xaa,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efaa3c <unknown>
+
+
+srshl   {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d}  // 11000001-11100000-10111010-00100000
+// CHECK-INST: srshl   { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x20,0xba,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0ba20 <unknown>
+
+srshl   {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d}  // 11000001-11110100-10111010-00110100
+// CHECK-INST: srshl   { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x34,0xba,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4ba34 <unknown>
+
+srshl   {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d}  // 11000001-11101000-10111010-00110100
+// CHECK-INST: srshl   { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x34,0xba,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8ba34 <unknown>
+
+srshl   {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d}  // 11000001-11111100-10111010-00111100
+// CHECK-INST: srshl   { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x3c,0xba,0xfc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fcba3c <unknown>
+
+
+srshl   {z0.b - z3.b}, {z0.b - z3.b}, z0.b  // 11000001-00100000-10101010-00100000
+// CHECK-INST: srshl   { z0.b - z3.b }, { z0.b - z3.b }, z0.b
+// CHECK-ENCODING: [0x20,0xaa,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120aa20 <unknown>
+
+srshl   {z20.b - z23.b}, {z20.b - z23.b}, z5.b  // 11000001-00100101-10101010-00110100
+// CHECK-INST: srshl   { z20.b - z23.b }, { z20.b - z23.b }, z5.b
+// CHECK-ENCODING: [0x34,0xaa,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125aa34 <unknown>
+
+srshl   {z20.b - z23.b}, {z20.b - z23.b}, z8.b  // 11000001-00101000-10101010-00110100
+// CHECK-INST: srshl   { z20.b - z23.b }, { z20.b - z23.b }, z8.b
+// CHECK-ENCODING: [0x34,0xaa,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128aa34 <unknown>
+
+srshl   {z28.b - z31.b}, {z28.b - z31.b}, z15.b  // 11000001-00101111-10101010-00111100
+// CHECK-INST: srshl   { z28.b - z31.b }, { z28.b - z31.b }, z15.b
+// CHECK-ENCODING: [0x3c,0xaa,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12faa3c <unknown>
+
+
+srshl   {z0.b - z3.b}, {z0.b - z3.b}, {z0.b - z3.b}  // 11000001-00100000-10111010-00100000
+// CHECK-INST: srshl   { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }
+// CHECK-ENCODING: [0x20,0xba,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120ba20 <unknown>
+
+srshl   {z20.b - z23.b}, {z20.b - z23.b}, {z20.b - z23.b}  // 11000001-00110100-10111010-00110100
+// CHECK-INST: srshl   { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }
+// CHECK-ENCODING: [0x34,0xba,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134ba34 <unknown>
+
+srshl   {z20.b - z23.b}, {z20.b - z23.b}, {z8.b - z11.b}  // 11000001-00101000-10111010-00110100
+// CHECK-INST: srshl   { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }
+// CHECK-ENCODING: [0x34,0xba,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128ba34 <unknown>
+
+srshl   {z28.b - z31.b}, {z28.b - z31.b}, {z28.b - z31.b}  // 11000001-00111100-10111010-00111100
+// CHECK-INST: srshl   { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }
+// CHECK-ENCODING: [0x3c,0xba,0x3c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13cba3c <unknown>
+

llvm/test/MC/AArch64/SME2/sub-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i16i64 2>&1 < %s | FileCheck %s
 
 // --------------------------------------------------------------------------//
 // Out of range index offset
 
-sub za.s[w8, 8], {z20.s-z21.s}, z10.s
+sub za.s[w8, 8], {z20.s, z21.s}, z10.s
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
-// CHECK-NEXT: sub za.s[w8, 8], {z20.s-z21.s}, z10.s
+// CHECK-NEXT: sub za.s[w8, 8], {z20.s, z21.s}, z10.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 sub za.d[w8, -1, vgx4], {z0.s-z3.s}, z0.s
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
 // CHECK-NEXT: sub za.d[w8, -1, vgx4], {z0.s-z3.s}, z0.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 sub za.d[w8, 8, vgx4], {z0.s-z3.s}

 // --------------------------------------------------------------------------//
 // Invalid vector select register
 
 sub za.d[w7, 0], {z0.d-z3.d}, z0.d
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
 // CHECK-NEXT: sub za.d[w7, 0], {z0.d-z3.d}, z0.d
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
-sub za.s[w12, 0], {z0.s-z1.s}, z0.s
+sub za.s[w12, 0], {z0.s, z1.s}, z0.s
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
-// CHECK-NEXT: sub za.s[w12, 0], {z0.s-z1.s}, z0.s
+// CHECK-NEXT: sub za.s[w12, 0], {z0.s, z1.s}, z0.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // --------------------------------------------------------------------------//
 // Invalid Matrix Operand
 
 sub za.h[w8, #0], {z0.h-z3.h}, z4.h
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .d
 // CHECK-NEXT: sub za.h[w8, #0], {z0.h-z3.h}, z4.h
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 sub za.h[w8, 0, vgx2], {z0.s, z1.s}
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .d
 // CHECK-NEXT: za.h[w8, 0, vgx2], {z0.s, z1.s}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // --------------------------------------------------------------------------//
 // Invalid vector grouping
 
-sub za.s[w8, 0, vgx4], {z0.s-z1.s}, z0.s
+sub za.s[w8, 0, vgx4], {z0.s, z1.s}, z0.s
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: za.s[w8, 0, vgx4], {z0.s-z1.s}, z0.s
+// CHECK-NEXT: za.s[w8, 0, vgx4], {z0.s, z1.s}, z0.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 sub za.d[w8, 0, vgx2], {z0.d-z3.d}, z0.d
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: za.d[w8, 0, vgx2], {z0.d-z3.d}, z0.d
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // --------------------------------------------------------------------------//

llvm/test/MC/AArch64/SME2/sub.s

 // CHECK-UNKNOWN: c1f4595d <unknown>
 
 sub     za.d[w11, 7, vgx2], {z12.d, z13.d}, {z8.d, z9.d}  // 11000001, 11101000, 01111001, 10011111
 // CHECK-INST: sub     za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }
 // CHECK-ENCODING: [0x9f,0x79,0xe8,0xc1]
 // CHECK-ERROR: instruction requires: sme2
 // CHECK-UNKNOWN: c1e8799f <unknown>
 
-sub     za.d[w11, 7], {z12.d - z13.d}, {z8.d - z9.d}  // 11000001-11101000-01111001-10011111
+sub     za.d[w11, 7], {z12.d - z13.d}, {z8.d, z9.d}  // 11000001-11101000-01111001-10011111
 // CHECK-INST: sub     za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }
 // CHECK-ENCODING: [0x9f,0x79,0xe8,0xc1]
 // CHECK-ERROR: instruction requires: sme2
 // CHECK-UNKNOWN: c1e8799f <unknown>
 
 sub     za.d[w11, 7, vgx2], {z30.d, z31.d}, {z30.d, z31.d}  // 11000001, 11111110, 01111011, 11011111
 // CHECK-INST: sub     za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }
 // CHECK-ENCODING: [0xdf,0x7b,0xfe,0xc1]

 // CHECK-UNKNOWN: c1fe1add <unknown>
 
 sub     za.d[w11, 2, vgx2], {z8.d, z9.d}, {z0.d, z1.d}  // 11000001, 11100000, 01111001, 00011010
 // CHECK-INST: sub     za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }
 // CHECK-ENCODING: [0x1a,0x79,0xe0,0xc1]
 // CHECK-ERROR: instruction requires: sme2
 // CHECK-UNKNOWN: c1e0791a <unknown>
 
-sub     za.d[w11, 2], {z8.d - z9.d}, {z0.d - z1.d}  // 11000001-11100000-01111001-00011010
+sub     za.d[w11, 2], {z8.d, z9.d}, {z0.d - z1.d}  // 11000001-11100000-01111001-00011010
 // CHECK-INST: sub     za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }
 // CHECK-ENCODING: [0x1a,0x79,0xe0,0xc1]
 // CHECK-ERROR: instruction requires: sme2
 // CHECK-UNKNOWN: c1e0791a <unknown>
 
 sub     za.d[w9, 7, vgx2], {z12.d, z13.d}, {z10.d, z11.d}  // 11000001, 11101010, 00111001, 10011111
 // CHECK-INST: sub     za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }
 // CHECK-ENCODING: [0x9f,0x39,0xea,0xc1]

llvm/test/MC/AArch64/SME2/umax-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+umax {z0.h, z1.h}, {z0.h-z2.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umax {z0.h, z1.h}, {z0.h-z2.h}, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umax {z1.d-z2.d}, {z0.d, z1.d}, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
+// CHECK-NEXT: umax {z1.d-z2.d}, {z0.d, z1.d}, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid single register
+
+umax {z0.b, z1.b}, {z2.b-z3.b}, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
+// CHECK-NEXT: umax {z0.b, z1.b}, {z2.b-z3.b}, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+umax {z0.b, z1.b}, {z2.b-z3.b}, z14.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
+// CHECK-NEXT: umax {z0.b, z1.b}, {z2.b-z3.b}, z14.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/umax.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+umax    {z0.h, z1.h}, {z0.h, z1.h}, z0.h  // 11000001-01100000-10100000-00000001
+// CHECK-INST: umax    { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x01,0xa0,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a001 <unknown>
+
+umax    {z20.h, z21.h}, {z20.h, z21.h}, z5.h  // 11000001-01100101-10100000-00010101
+// CHECK-INST: umax    { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x15,0xa0,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a015 <unknown>
+
+umax    {z22.h, z23.h}, {z22.h, z23.h}, z8.h  // 11000001-01101000-10100000-00010111
+// CHECK-INST: umax    { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x17,0xa0,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a017 <unknown>
+
+umax    {z30.h, z31.h}, {z30.h, z31.h}, z15.h  // 11000001-01101111-10100000-00011111
+// CHECK-INST: umax    { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x1f,0xa0,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa01f <unknown>
+
+
+umax    {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h}  // 11000001-01100000-10110000-00000001
+// CHECK-INST: umax    { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x01,0xb0,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b001 <unknown>
+
+umax    {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h}  // 11000001-01110100-10110000-00010101
+// CHECK-INST: umax    { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x15,0xb0,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b015 <unknown>
+
+umax    {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h}  // 11000001-01101000-10110000-00010111
+// CHECK-INST: umax    { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x17,0xb0,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b017 <unknown>
+
+umax    {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h}  // 11000001-01111110-10110000-00011111
+// CHECK-INST: umax    { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x1f,0xb0,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17eb01f <unknown>
+
+
+umax    {z0.s, z1.s}, {z0.s, z1.s}, z0.s  // 11000001-10100000-10100000-00000001
+// CHECK-INST: umax    { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x01,0xa0,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a001 <unknown>
+
+umax    {z20.s, z21.s}, {z20.s, z21.s}, z5.s  // 11000001-10100101-10100000-00010101
+// CHECK-INST: umax    { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x15,0xa0,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a015 <unknown>
+
+umax    {z22.s, z23.s}, {z22.s, z23.s}, z8.s  // 11000001-10101000-10100000-00010111
+// CHECK-INST: umax    { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x17,0xa0,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a017 <unknown>
+
+umax    {z30.s, z31.s}, {z30.s, z31.s}, z15.s  // 11000001-10101111-10100000-00011111
+// CHECK-INST: umax    { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x1f,0xa0,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa01f <unknown>
+
+
+umax    {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s}  // 11000001-10100000-10110000-00000001
+// CHECK-INST: umax    { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x01,0xb0,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b001 <unknown>
+
+umax    {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s}  // 11000001-10110100-10110000-00010101
+// CHECK-INST: umax    { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x15,0xb0,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b015 <unknown>
+
+umax    {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s}  // 11000001-10101000-10110000-00010111
+// CHECK-INST: umax    { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x17,0xb0,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b017 <unknown>
+
+umax    {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s}  // 11000001-10111110-10110000-00011111
+// CHECK-INST: umax    { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x1f,0xb0,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1beb01f <unknown>
+
+
+umax    {z0.d, z1.d}, {z0.d, z1.d}, z0.d  // 11000001-11100000-10100000-00000001
+// CHECK-INST: umax    { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x01,0xa0,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a001 <unknown>
+
+umax    {z20.d, z21.d}, {z20.d, z21.d}, z5.d  // 11000001-11100101-10100000-00010101
+// CHECK-INST: umax    { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x15,0xa0,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a015 <unknown>
+
+umax    {z22.d, z23.d}, {z22.d, z23.d}, z8.d  // 11000001-11101000-10100000-00010111
+// CHECK-INST: umax    { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x17,0xa0,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a017 <unknown>
+
+umax    {z30.d, z31.d}, {z30.d, z31.d}, z15.d  // 11000001-11101111-10100000-00011111
+// CHECK-INST: umax    { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x1f,0xa0,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa01f <unknown>
+
+
+umax    {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d}  // 11000001-11100000-10110000-00000001
+// CHECK-INST: umax    { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x01,0xb0,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b001 <unknown>
+
+umax    {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d}  // 11000001-11110100-10110000-00010101
+// CHECK-INST: umax    { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x15,0xb0,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b015 <unknown>
+
+umax    {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d}  // 11000001-11101000-10110000-00010111
+// CHECK-INST: umax    { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x17,0xb0,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b017 <unknown>
+
+umax    {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d}  // 11000001-11111110-10110000-00011111
+// CHECK-INST: umax    { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x1f,0xb0,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1feb01f <unknown>
+
+
+umax    {z0.b, z1.b}, {z0.b, z1.b}, z0.b  // 11000001-00100000-10100000-00000001
+// CHECK-INST: umax    { z0.b, z1.b }, { z0.b, z1.b }, z0.b
+// CHECK-ENCODING: [0x01,0xa0,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a001 <unknown>
+
+umax    {z20.b, z21.b}, {z20.b, z21.b}, z5.b  // 11000001-00100101-10100000-00010101
+// CHECK-INST: umax    { z20.b, z21.b }, { z20.b, z21.b }, z5.b
+// CHECK-ENCODING: [0x15,0xa0,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a015 <unknown>
+
+umax    {z22.b, z23.b}, {z22.b, z23.b}, z8.b  // 11000001-00101000-10100000-00010111
+// CHECK-INST: umax    { z22.b, z23.b }, { z22.b, z23.b }, z8.b
+// CHECK-ENCODING: [0x17,0xa0,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a017 <unknown>
+
+umax    {z30.b, z31.b}, {z30.b, z31.b}, z15.b  // 11000001-00101111-10100000-00011111
+// CHECK-INST: umax    { z30.b, z31.b }, { z30.b, z31.b }, z15.b
+// CHECK-ENCODING: [0x1f,0xa0,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa01f <unknown>
+
+
+umax    {z0.b, z1.b}, {z0.b, z1.b}, {z0.b, z1.b}  // 11000001-00100000-10110000-00000001
+// CHECK-INST: umax    { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }
+// CHECK-ENCODING: [0x01,0xb0,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120b001 <unknown>
+
+umax    {z20.b, z21.b}, {z20.b, z21.b}, {z20.b, z21.b}  // 11000001-00110100-10110000-00010101
+// CHECK-INST: umax    { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }
+// CHECK-ENCODING: [0x15,0xb0,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134b015 <unknown>
+
+umax    {z22.b, z23.b}, {z22.b, z23.b}, {z8.b, z9.b}  // 11000001-00101000-10110000-00010111
+// CHECK-INST: umax    { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }
+// CHECK-ENCODING: [0x17,0xb0,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128b017 <unknown>
+
+umax    {z30.b, z31.b}, {z30.b, z31.b}, {z30.b, z31.b}  // 11000001-00111110-10110000-00011111
+// CHECK-INST: umax    { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }
+// CHECK-ENCODING: [0x1f,0xb0,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13eb01f <unknown>
+
+
+umax    {z0.h - z3.h}, {z0.h - z3.h}, z0.h  // 11000001-01100000-10101000-00000001
+// CHECK-INST: umax    { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x01,0xa8,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a801 <unknown>
+
+umax    {z20.h - z23.h}, {z20.h - z23.h}, z5.h  // 11000001-01100101-10101000-00010101
+// CHECK-INST: umax    { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x15,0xa8,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a815 <unknown>
+
+umax    {z20.h - z23.h}, {z20.h - z23.h}, z8.h  // 11000001-01101000-10101000-00010101
+// CHECK-INST: umax    { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x15,0xa8,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a815 <unknown>
+
+umax    {z28.h - z31.h}, {z28.h - z31.h}, z15.h  // 11000001-01101111-10101000-00011101
+// CHECK-INST: umax    { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x1d,0xa8,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa81d <unknown>
+
+
+umax    {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-01100000-10111000-00000001
+// CHECK-INST: umax    { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x01,0xb8,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b801 <unknown>
+
+umax    {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h}  // 11000001-01110100-10111000-00010101
+// CHECK-INST: umax    { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x15,0xb8,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b815 <unknown>
+
+umax    {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h}  // 11000001-01101000-10111000-00010101
+// CHECK-INST: umax    { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x15,0xb8,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b815 <unknown>
+
+umax    {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-01111100-10111000-00011101
+// CHECK-INST: umax    { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x1d,0xb8,0x7c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17cb81d <unknown>
+
+
+umax    {z0.s - z3.s}, {z0.s - z3.s}, z0.s  // 11000001-10100000-10101000-00000001
+// CHECK-INST: umax    { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x01,0xa8,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a801 <unknown>
+
+umax    {z20.s - z23.s}, {z20.s - z23.s}, z5.s  // 11000001-10100101-10101000-00010101
+// CHECK-INST: umax    { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x15,0xa8,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a815 <unknown>
+
+umax    {z20.s - z23.s}, {z20.s - z23.s}, z8.s  // 11000001-10101000-10101000-00010101
+// CHECK-INST: umax    { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x15,0xa8,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a815 <unknown>
+
+umax    {z28.s - z31.s}, {z28.s - z31.s}, z15.s  // 11000001-10101111-10101000-00011101
+// CHECK-INST: umax    { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x1d,0xa8,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa81d <unknown>
+
+
+umax    {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s}  // 11000001-10100000-10111000-00000001
+// CHECK-INST: umax    { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x01,0xb8,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b801 <unknown>
+
+umax    {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s}  // 11000001-10110100-10111000-00010101
+// CHECK-INST: umax    { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x15,0xb8,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b815 <unknown>
+
+umax    {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s}  // 11000001-10101000-10111000-00010101
+// CHECK-INST: umax    { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x15,0xb8,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b815 <unknown>
+
+umax    {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s}  // 11000001-10111100-10111000-00011101
+// CHECK-INST: umax    { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x1d,0xb8,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bcb81d <unknown>
+
+
+umax    {z0.d - z3.d}, {z0.d - z3.d}, z0.d  // 11000001-11100000-10101000-00000001
+// CHECK-INST: umax    { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x01,0xa8,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a801 <unknown>
+
+umax    {z20.d - z23.d}, {z20.d - z23.d}, z5.d  // 11000001-11100101-10101000-00010101
+// CHECK-INST: umax    { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x15,0xa8,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a815 <unknown>
+
+umax    {z20.d - z23.d}, {z20.d - z23.d}, z8.d  // 11000001-11101000-10101000-00010101
+// CHECK-INST: umax    { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x15,0xa8,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a815 <unknown>
+
+umax    {z28.d - z31.d}, {z28.d - z31.d}, z15.d  // 11000001-11101111-10101000-00011101
+// CHECK-INST: umax    { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x1d,0xa8,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa81d <unknown>
+
+
+umax    {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d}  // 11000001-11100000-10111000-00000001
+// CHECK-INST: umax    { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x01,0xb8,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b801 <unknown>
+
+umax    {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d}  // 11000001-11110100-10111000-00010101
+// CHECK-INST: umax    { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x15,0xb8,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b815 <unknown>
+
+umax    {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d}  // 11000001-11101000-10111000-00010101
+// CHECK-INST: umax    { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x15,0xb8,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b815 <unknown>
+
+umax    {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d}  // 11000001-11111100-10111000-00011101
+// CHECK-INST: umax    { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x1d,0xb8,0xfc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fcb81d <unknown>
+
+
+umax    {z0.b - z3.b}, {z0.b - z3.b}, z0.b  // 11000001-00100000-10101000-00000001
+// CHECK-INST: umax    { z0.b - z3.b }, { z0.b - z3.b }, z0.b
+// CHECK-ENCODING: [0x01,0xa8,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a801 <unknown>
+
+umax    {z20.b - z23.b}, {z20.b - z23.b}, z5.b  // 11000001-00100101-10101000-00010101
+// CHECK-INST: umax    { z20.b - z23.b }, { z20.b - z23.b }, z5.b
+// CHECK-ENCODING: [0x15,0xa8,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a815 <unknown>
+
+umax    {z20.b - z23.b}, {z20.b - z23.b}, z8.b  // 11000001-00101000-10101000-00010101
+// CHECK-INST: umax    { z20.b - z23.b }, { z20.b - z23.b }, z8.b
+// CHECK-ENCODING: [0x15,0xa8,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a815 <unknown>
+
+umax    {z28.b - z31.b}, {z28.b - z31.b}, z15.b  // 11000001-00101111-10101000-00011101
+// CHECK-INST: umax    { z28.b - z31.b }, { z28.b - z31.b }, z15.b
+// CHECK-ENCODING: [0x1d,0xa8,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa81d <unknown>
+
+
+umax    {z0.b - z3.b}, {z0.b - z3.b}, {z0.b - z3.b}  // 11000001-00100000-10111000-00000001
+// CHECK-INST: umax    { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }
+// CHECK-ENCODING: [0x01,0xb8,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120b801 <unknown>
+
+umax    {z20.b - z23.b}, {z20.b - z23.b}, {z20.b - z23.b}  // 11000001-00110100-10111000-00010101
+// CHECK-INST: umax    { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }
+// CHECK-ENCODING: [0x15,0xb8,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134b815 <unknown>
+
+umax    {z20.b - z23.b}, {z20.b - z23.b}, {z8.b - z11.b}  // 11000001-00101000-10111000-00010101
+// CHECK-INST: umax    { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }
+// CHECK-ENCODING: [0x15,0xb8,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128b815 <unknown>
+
+umax    {z28.b - z31.b}, {z28.b - z31.b}, {z28.b - z31.b}  // 11000001-00111100-10111000-00011101
+// CHECK-INST: umax    { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }
+// CHECK-ENCODING: [0x1d,0xb8,0x3c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13cb81d <unknown>
+

llvm/test/MC/AArch64/SME2/umin-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+umin {z0.h, z1.h}, {z0.h-z2.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umin {z0.h, z1.h}, {z0.h-z2.h}, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umin {z1.d-z2.d}, {z0.d, z1.d}, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
+// CHECK-NEXT: umin {z1.d-z2.d}, {z0.d, z1.d}, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid single register
+
+umin {z0.b, z1.b}, {z2.b-z3.b}, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
+// CHECK-NEXT: umin {z0.b, z1.b}, {z2.b-z3.b}, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+umin {z0.b, z1.b}, {z2.b-z3.b}, z14.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
+// CHECK-NEXT: umin {z0.b, z1.b}, {z2.b-z3.b}, z14.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/umin.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+umin    {z0.h, z1.h}, {z0.h, z1.h}, z0.h  // 11000001-01100000-10100000-00100001
+// CHECK-INST: umin    { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x21,0xa0,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a021 <unknown>
+
+umin    {z20.h, z21.h}, {z20.h, z21.h}, z5.h  // 11000001-01100101-10100000-00110101
+// CHECK-INST: umin    { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x35,0xa0,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a035 <unknown>
+
+umin    {z22.h, z23.h}, {z22.h, z23.h}, z8.h  // 11000001-01101000-10100000-00110111
+// CHECK-INST: umin    { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x37,0xa0,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a037 <unknown>
+
+umin    {z30.h, z31.h}, {z30.h, z31.h}, z15.h  // 11000001-01101111-10100000-00111111
+// CHECK-INST: umin    { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x3f,0xa0,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa03f <unknown>
+
+
+umin    {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h}  // 11000001-01100000-10110000-00100001
+// CHECK-INST: umin    { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x21,0xb0,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b021 <unknown>
+
+umin    {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h}  // 11000001-01110100-10110000-00110101
+// CHECK-INST: umin    { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x35,0xb0,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b035 <unknown>
+
+umin    {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h}  // 11000001-01101000-10110000-00110111
+// CHECK-INST: umin    { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x37,0xb0,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b037 <unknown>
+
+umin    {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h}  // 11000001-01111110-10110000-00111111
+// CHECK-INST: umin    { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x3f,0xb0,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17eb03f <unknown>
+
+
+umin    {z0.s, z1.s}, {z0.s, z1.s}, z0.s  // 11000001-10100000-10100000-00100001
+// CHECK-INST: umin    { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x21,0xa0,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a021 <unknown>
+
+umin    {z20.s, z21.s}, {z20.s, z21.s}, z5.s  // 11000001-10100101-10100000-00110101
+// CHECK-INST: umin    { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x35,0xa0,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a035 <unknown>
+
+umin    {z22.s, z23.s}, {z22.s, z23.s}, z8.s  // 11000001-10101000-10100000-00110111
+// CHECK-INST: umin    { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x37,0xa0,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a037 <unknown>
+
+umin    {z30.s, z31.s}, {z30.s, z31.s}, z15.s  // 11000001-10101111-10100000-00111111
+// CHECK-INST: umin    { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x3f,0xa0,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa03f <unknown>
+
+
+umin    {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s}  // 11000001-10100000-10110000-00100001
+// CHECK-INST: umin    { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x21,0xb0,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b021 <unknown>
+
+umin    {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s}  // 11000001-10110100-10110000-00110101
+// CHECK-INST: umin    { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x35,0xb0,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b035 <unknown>
+
+umin    {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s}  // 11000001-10101000-10110000-00110111
+// CHECK-INST: umin    { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x37,0xb0,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b037 <unknown>
+
+umin    {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s}  // 11000001-10111110-10110000-00111111
+// CHECK-INST: umin    { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x3f,0xb0,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1beb03f <unknown>
+
+
+umin    {z0.d, z1.d}, {z0.d, z1.d}, z0.d  // 11000001-11100000-10100000-00100001
+// CHECK-INST: umin    { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x21,0xa0,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a021 <unknown>
+
+umin    {z20.d, z21.d}, {z20.d, z21.d}, z5.d  // 11000001-11100101-10100000-00110101
+// CHECK-INST: umin    { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x35,0xa0,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a035 <unknown>
+
+umin    {z22.d, z23.d}, {z22.d, z23.d}, z8.d  // 11000001-11101000-10100000-00110111
+// CHECK-INST: umin    { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x37,0xa0,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a037 <unknown>
+
+umin    {z30.d, z31.d}, {z30.d, z31.d}, z15.d  // 11000001-11101111-10100000-00111111
+// CHECK-INST: umin    { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x3f,0xa0,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa03f <unknown>
+
+
+umin    {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d}  // 11000001-11100000-10110000-00100001
+// CHECK-INST: umin    { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x21,0xb0,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b021 <unknown>
+
+umin    {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d}  // 11000001-11110100-10110000-00110101
+// CHECK-INST: umin    { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x35,0xb0,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b035 <unknown>
+
+umin    {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d}  // 11000001-11101000-10110000-00110111
+// CHECK-INST: umin    { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x37,0xb0,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b037 <unknown>
+
+umin    {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d}  // 11000001-11111110-10110000-00111111
+// CHECK-INST: umin    { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x3f,0xb0,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1feb03f <unknown>
+
+
+umin    {z0.b, z1.b}, {z0.b, z1.b}, z0.b  // 11000001-00100000-10100000-00100001
+// CHECK-INST: umin    { z0.b, z1.b }, { z0.b, z1.b }, z0.b
+// CHECK-ENCODING: [0x21,0xa0,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a021 <unknown>
+
+umin    {z20.b, z21.b}, {z20.b, z21.b}, z5.b  // 11000001-00100101-10100000-00110101
+// CHECK-INST: umin    { z20.b, z21.b }, { z20.b, z21.b }, z5.b
+// CHECK-ENCODING: [0x35,0xa0,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a035 <unknown>
+
+umin    {z22.b, z23.b}, {z22.b, z23.b}, z8.b  // 11000001-00101000-10100000-00110111
+// CHECK-INST: umin    { z22.b, z23.b }, { z22.b, z23.b }, z8.b
+// CHECK-ENCODING: [0x37,0xa0,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a037 <unknown>
+
+umin    {z30.b, z31.b}, {z30.b, z31.b}, z15.b  // 11000001-00101111-10100000-00111111
+// CHECK-INST: umin    { z30.b, z31.b }, { z30.b, z31.b }, z15.b
+// CHECK-ENCODING: [0x3f,0xa0,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa03f <unknown>
+
+
+umin    {z0.b, z1.b}, {z0.b, z1.b}, {z0.b, z1.b}  // 11000001-00100000-10110000-00100001
+// CHECK-INST: umin    { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }
+// CHECK-ENCODING: [0x21,0xb0,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120b021 <unknown>
+
+umin    {z20.b, z21.b}, {z20.b, z21.b}, {z20.b, z21.b}  // 11000001-00110100-10110000-00110101
+// CHECK-INST: umin    { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }
+// CHECK-ENCODING: [0x35,0xb0,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134b035 <unknown>
+
+umin    {z22.b, z23.b}, {z22.b, z23.b}, {z8.b, z9.b}  // 11000001-00101000-10110000-00110111
+// CHECK-INST: umin    { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }
+// CHECK-ENCODING: [0x37,0xb0,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128b037 <unknown>
+
+umin    {z30.b, z31.b}, {z30.b, z31.b}, {z30.b, z31.b}  // 11000001-00111110-10110000-00111111
+// CHECK-INST: umin    { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }
+// CHECK-ENCODING: [0x3f,0xb0,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13eb03f <unknown>
+
+
+umin    {z0.h - z3.h}, {z0.h - z3.h}, z0.h  // 11000001-01100000-10101000-00100001
+// CHECK-INST: umin    { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x21,0xa8,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a821 <unknown>
+
+umin    {z20.h - z23.h}, {z20.h - z23.h}, z5.h  // 11000001-01100101-10101000-00110101
+// CHECK-INST: umin    { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x35,0xa8,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a835 <unknown>
+
+umin    {z20.h - z23.h}, {z20.h - z23.h}, z8.h  // 11000001-01101000-10101000-00110101
+// CHECK-INST: umin    { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x35,0xa8,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a835 <unknown>
+
+umin    {z28.h - z31.h}, {z28.h - z31.h}, z15.h  // 11000001-01101111-10101000-00111101
+// CHECK-INST: umin    { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x3d,0xa8,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa83d <unknown>
+
+
+umin    {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-01100000-10111000-00100001
+// CHECK-INST: umin    { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x21,0xb8,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b821 <unknown>
+
+umin    {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h}  // 11000001-01110100-10111000-00110101
+// CHECK-INST: umin    { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x35,0xb8,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b835 <unknown>
+
+umin    {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h}  // 11000001-01101000-10111000-00110101
+// CHECK-INST: umin    { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x35,0xb8,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b835 <unknown>
+
+umin    {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-01111100-10111000-00111101
+// CHECK-INST: umin    { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x3d,0xb8,0x7c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17cb83d <unknown>
+
+
+umin    {z0.s - z3.s}, {z0.s - z3.s}, z0.s  // 11000001-10100000-10101000-00100001
+// CHECK-INST: umin    { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x21,0xa8,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a821 <unknown>
+
+umin    {z20.s - z23.s}, {z20.s - z23.s}, z5.s  // 11000001-10100101-10101000-00110101
+// CHECK-INST: umin    { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x35,0xa8,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a835 <unknown>
+
+umin    {z20.s - z23.s}, {z20.s - z23.s}, z8.s  // 11000001-10101000-10101000-00110101
+// CHECK-INST: umin    { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x35,0xa8,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a835 <unknown>
+
+umin    {z28.s - z31.s}, {z28.s - z31.s}, z15.s  // 11000001-10101111-10101000-00111101
+// CHECK-INST: umin    { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x3d,0xa8,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa83d <unknown>
+
+
+umin    {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s}  // 11000001-10100000-10111000-00100001
+// CHECK-INST: umin    { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x21,0xb8,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b821 <unknown>
+
+umin    {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s}  // 11000001-10110100-10111000-00110101
+// CHECK-INST: umin    { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x35,0xb8,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b835 <unknown>
+
+umin    {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s}  // 11000001-10101000-10111000-00110101
+// CHECK-INST: umin    { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x35,0xb8,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b835 <unknown>
+
+umin    {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s}  // 11000001-10111100-10111000-00111101
+// CHECK-INST: umin    { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x3d,0xb8,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bcb83d <unknown>
+
+
+umin    {z0.d - z3.d}, {z0.d - z3.d}, z0.d  // 11000001-11100000-10101000-00100001
+// CHECK-INST: umin    { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x21,0xa8,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a821 <unknown>
+
+umin    {z20.d - z23.d}, {z20.d - z23.d}, z5.d  // 11000001-11100101-10101000-00110101
+// CHECK-INST: umin    { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x35,0xa8,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a835 <unknown>
+
+umin    {z20.d - z23.d}, {z20.d - z23.d}, z8.d  // 11000001-11101000-10101000-00110101
+// CHECK-INST: umin    { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x35,0xa8,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a835 <unknown>
+
+umin    {z28.d - z31.d}, {z28.d - z31.d}, z15.d  // 11000001-11101111-10101000-00111101
+// CHECK-INST: umin    { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x3d,0xa8,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa83d <unknown>
+
+
+umin    {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d}  // 11000001-11100000-10111000-00100001
+// CHECK-INST: umin    { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x21,0xb8,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b821 <unknown>
+
+umin    {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d}  // 11000001-11110100-10111000-00110101
+// CHECK-INST: umin    { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x35,0xb8,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b835 <unknown>
+
+umin    {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d}  // 11000001-11101000-10111000-00110101
+// CHECK-INST: umin    { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x35,0xb8,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b835 <unknown>
+
+umin    {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d}  // 11000001-11111100-10111000-00111101
+// CHECK-INST: umin    { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x3d,0xb8,0xfc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fcb83d <unknown>
+
+
+umin    {z0.b - z3.b}, {z0.b - z3.b}, z0.b  // 11000001-00100000-10101000-00100001
+// CHECK-INST: umin    { z0.b - z3.b }, { z0.b - z3.b }, z0.b
+// CHECK-ENCODING: [0x21,0xa8,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a821 <unknown>
+
+umin    {z20.b - z23.b}, {z20.b - z23.b}, z5.b  // 11000001-00100101-10101000-00110101
+// CHECK-INST: umin    { z20.b - z23.b }, { z20.b - z23.b }, z5.b
+// CHECK-ENCODING: [0x35,0xa8,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a835 <unknown>
+
+umin    {z20.b - z23.b}, {z20.b - z23.b}, z8.b  // 11000001-00101000-10101000-00110101
+// CHECK-INST: umin    { z20.b - z23.b }, { z20.b - z23.b }, z8.b
+// CHECK-ENCODING: [0x35,0xa8,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a835 <unknown>
+
+umin    {z28.b - z31.b}, {z28.b - z31.b}, z15.b  // 11000001-00101111-10101000-00111101
+// CHECK-INST: umin    { z28.b - z31.b }, { z28.b - z31.b }, z15.b
+// CHECK-ENCODING: [0x3d,0xa8,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa83d <unknown>
+
+
+umin    {z0.b - z3.b}, {z0.b - z3.b}, {z0.b - z3.b}  // 11000001-00100000-10111000-00100001
+// CHECK-INST: umin    { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }
+// CHECK-ENCODING: [0x21,0xb8,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120b821 <unknown>
+
+umin    {z20.b - z23.b}, {z20.b - z23.b}, {z20.b - z23.b}  // 11000001-00110100-10111000-00110101
+// CHECK-INST: umin    { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }
+// CHECK-ENCODING: [0x35,0xb8,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134b835 <unknown>
+
+umin    {z20.b - z23.b}, {z20.b - z23.b}, {z8.b - z11.b}  // 11000001-00101000-10111000-00110101
+// CHECK-INST: umin    { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }
+// CHECK-ENCODING: [0x35,0xb8,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128b835 <unknown>
+
+umin    {z28.b - z31.b}, {z28.b - z31.b}, {z28.b - z31.b}  // 11000001-00111100-10111000-00111101
+// CHECK-INST: umin    { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }
+// CHECK-ENCODING: [0x3d,0xb8,0x3c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13cb83d <unknown>
+

llvm/test/MC/AArch64/SME2/urshl-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+urshl {z0.h-z2.h}, {z0.h-z1.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: urshl {z0.h-z2.h}, {z0.h-z1.h}, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+urshl {z0.s-z1.s}, {z2.s-z4.s}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: urshl {z0.s-z1.s}, {z2.s-z4.s}, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+urshl {z20.d-z23.d}, {z20.d-z23.d}, {z8.d-z12.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: urshl {z20.d-z23.d}, {z20.d-z23.d}, {z8.d-z12.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+urshl {z29.b-z30.b}, {z30.b-z31.b}, z15.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: urshl {z29.b-z30.b}, {z30.b-z31.b}, z15.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+urshl {z20.h-z23.h}, {z21.h-z24.h}, {z8.h-z11.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: urshl {z20.h-z23.h}, {z21.h-z24.h}, {z8.h-z11.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+urshl {z28.b-z31.b}, {z28.b-z31.b}, {z27.b-z30.b}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: urshl {z28.b-z31.b}, {z28.b-z31.b}, {z27.b-z30.b}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Single Register
+
+urshl {z20.h-z21.h}, {z20.h-z21.h}, z16.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: urshl {z20.h-z21.h}, {z20.h-z21.h}, z16.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+urshl {z0.d-z3.d}, {z0.d-z3.d}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d
+// CHECK-NEXT: urshl {z0.d-z3.d}, {z0.d-z3.d}, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/urshl.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+urshl   {z0.h, z1.h}, {z0.h, z1.h}, z0.h  // 11000001-01100000-10100010-00100001
+// CHECK-INST: urshl   { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x21,0xa2,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a221 <unknown>
+
+urshl   {z20.h, z21.h}, {z20.h, z21.h}, z5.h  // 11000001-01100101-10100010-00110101
+// CHECK-INST: urshl   { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x35,0xa2,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a235 <unknown>
+
+urshl   {z22.h, z23.h}, {z22.h, z23.h}, z8.h  // 11000001-01101000-10100010-00110111
+// CHECK-INST: urshl   { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x37,0xa2,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a237 <unknown>
+
+urshl   {z30.h, z31.h}, {z30.h, z31.h}, z15.h  // 11000001-01101111-10100010-00111111
+// CHECK-INST: urshl   { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x3f,0xa2,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa23f <unknown>
+
+
+urshl   {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h}  // 11000001-01100000-10110010-00100001
+// CHECK-INST: urshl   { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x21,0xb2,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b221 <unknown>
+
+urshl   {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h}  // 11000001-01110100-10110010-00110101
+// CHECK-INST: urshl   { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x35,0xb2,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b235 <unknown>
+
+urshl   {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h}  // 11000001-01101000-10110010-00110111
+// CHECK-INST: urshl   { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x37,0xb2,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b237 <unknown>
+
+urshl   {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h}  // 11000001-01111110-10110010-00111111
+// CHECK-INST: urshl   { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x3f,0xb2,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17eb23f <unknown>
+
+
+urshl   {z0.s, z1.s}, {z0.s, z1.s}, z0.s  // 11000001-10100000-10100010-00100001
+// CHECK-INST: urshl   { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x21,0xa2,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a221 <unknown>
+
+urshl   {z20.s, z21.s}, {z20.s, z21.s}, z5.s  // 11000001-10100101-10100010-00110101
+// CHECK-INST: urshl   { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x35,0xa2,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a235 <unknown>
+
+urshl   {z22.s, z23.s}, {z22.s, z23.s}, z8.s  // 11000001-10101000-10100010-00110111
+// CHECK-INST: urshl   { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x37,0xa2,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a237 <unknown>
+
+urshl   {z30.s, z31.s}, {z30.s, z31.s}, z15.s  // 11000001-10101111-10100010-00111111
+// CHECK-INST: urshl   { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x3f,0xa2,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa23f <unknown>
+
+
+urshl   {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s}  // 11000001-10100000-10110010-00100001
+// CHECK-INST: urshl   { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x21,0xb2,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b221 <unknown>
+
+urshl   {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s}  // 11000001-10110100-10110010-00110101
+// CHECK-INST: urshl   { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x35,0xb2,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b235 <unknown>
+
+urshl   {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s}  // 11000001-10101000-10110010-00110111
+// CHECK-INST: urshl   { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x37,0xb2,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b237 <unknown>
+
+urshl   {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s}  // 11000001-10111110-10110010-00111111
+// CHECK-INST: urshl   { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x3f,0xb2,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1beb23f <unknown>
+
+
+urshl   {z0.d, z1.d}, {z0.d, z1.d}, z0.d  // 11000001-11100000-10100010-00100001
+// CHECK-INST: urshl   { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x21,0xa2,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a221 <unknown>
+
+urshl   {z20.d, z21.d}, {z20.d, z21.d}, z5.d  // 11000001-11100101-10100010-00110101
+// CHECK-INST: urshl   { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x35,0xa2,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a235 <unknown>
+
+urshl   {z22.d, z23.d}, {z22.d, z23.d}, z8.d  // 11000001-11101000-10100010-00110111
+// CHECK-INST: urshl   { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x37,0xa2,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a237 <unknown>
+
+urshl   {z30.d, z31.d}, {z30.d, z31.d}, z15.d  // 11000001-11101111-10100010-00111111
+// CHECK-INST: urshl   { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x3f,0xa2,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa23f <unknown>
+
+
+urshl   {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d}  // 11000001-11100000-10110010-00100001
+// CHECK-INST: urshl   { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x21,0xb2,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b221 <unknown>
+
+urshl   {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d}  // 11000001-11110100-10110010-00110101
+// CHECK-INST: urshl   { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x35,0xb2,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b235 <unknown>
+
+urshl   {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d}  // 11000001-11101000-10110010-00110111
+// CHECK-INST: urshl   { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x37,0xb2,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b237 <unknown>
+
+urshl   {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d}  // 11000001-11111110-10110010-00111111
+// CHECK-INST: urshl   { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x3f,0xb2,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1feb23f <unknown>
+
+
+urshl   {z0.b, z1.b}, {z0.b, z1.b}, z0.b  // 11000001-00100000-10100010-00100001
+// CHECK-INST: urshl   { z0.b, z1.b }, { z0.b, z1.b }, z0.b
+// CHECK-ENCODING: [0x21,0xa2,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a221 <unknown>
+
+urshl   {z20.b, z21.b}, {z20.b, z21.b}, z5.b  // 11000001-00100101-10100010-00110101
+// CHECK-INST: urshl   { z20.b, z21.b }, { z20.b, z21.b }, z5.b
+// CHECK-ENCODING: [0x35,0xa2,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a235 <unknown>
+
+urshl   {z22.b, z23.b}, {z22.b, z23.b}, z8.b  // 11000001-00101000-10100010-00110111
+// CHECK-INST: urshl   { z22.b, z23.b }, { z22.b, z23.b }, z8.b
+// CHECK-ENCODING: [0x37,0xa2,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a237 <unknown>
+
+urshl   {z30.b, z31.b}, {z30.b, z31.b}, z15.b  // 11000001-00101111-10100010-00111111
+// CHECK-INST: urshl   { z30.b, z31.b }, { z30.b, z31.b }, z15.b
+// CHECK-ENCODING: [0x3f,0xa2,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa23f <unknown>
+
+
+urshl   {z0.b, z1.b}, {z0.b, z1.b}, {z0.b, z1.b}  // 11000001-00100000-10110010-00100001
+// CHECK-INST: urshl   { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }
+// CHECK-ENCODING: [0x21,0xb2,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120b221 <unknown>
+
+urshl   {z20.b, z21.b}, {z20.b, z21.b}, {z20.b, z21.b}  // 11000001-00110100-10110010-00110101
+// CHECK-INST: urshl   { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }
+// CHECK-ENCODING: [0x35,0xb2,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134b235 <unknown>
+
+urshl   {z22.b, z23.b}, {z22.b, z23.b}, {z8.b, z9.b}  // 11000001-00101000-10110010-00110111
+// CHECK-INST: urshl   { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }
+// CHECK-ENCODING: [0x37,0xb2,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128b237 <unknown>
+
+urshl   {z30.b, z31.b}, {z30.b, z31.b}, {z30.b, z31.b}  // 11000001-00111110-10110010-00111111
+// CHECK-INST: urshl   { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }
+// CHECK-ENCODING: [0x3f,0xb2,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13eb23f <unknown>
+
+
+urshl   {z0.h - z3.h}, {z0.h - z3.h}, z0.h  // 11000001-01100000-10101010-00100001
+// CHECK-INST: urshl   { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x21,0xaa,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160aa21 <unknown>
+
+urshl   {z20.h - z23.h}, {z20.h - z23.h}, z5.h  // 11000001-01100101-10101010-00110101
+// CHECK-INST: urshl   { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x35,0xaa,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165aa35 <unknown>
+
+urshl   {z20.h - z23.h}, {z20.h - z23.h}, z8.h  // 11000001-01101000-10101010-00110101
+// CHECK-INST: urshl   { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x35,0xaa,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168aa35 <unknown>
+
+urshl   {z28.h - z31.h}, {z28.h - z31.h}, z15.h  // 11000001-01101111-10101010-00111101
+// CHECK-INST: urshl   { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x3d,0xaa,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16faa3d <unknown>
+
+
+urshl   {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-01100000-10111010-00100001
+// CHECK-INST: urshl   { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x21,0xba,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160ba21 <unknown>
+
+urshl   {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h}  // 11000001-01110100-10111010-00110101
+// CHECK-INST: urshl   { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x35,0xba,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174ba35 <unknown>
+
+urshl   {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h}  // 11000001-01101000-10111010-00110101
+// CHECK-INST: urshl   { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x35,0xba,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168ba35 <unknown>
+
+urshl   {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-01111100-10111010-00111101
+// CHECK-INST: urshl   { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x3d,0xba,0x7c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17cba3d <unknown>
+
+
+urshl   {z0.s - z3.s}, {z0.s - z3.s}, z0.s  // 11000001-10100000-10101010-00100001
+// CHECK-INST: urshl   { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x21,0xaa,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0aa21 <unknown>
+
+urshl   {z20.s - z23.s}, {z20.s - z23.s}, z5.s  // 11000001-10100101-10101010-00110101
+// CHECK-INST: urshl   { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x35,0xaa,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5aa35 <unknown>
+
+urshl   {z20.s - z23.s}, {z20.s - z23.s}, z8.s  // 11000001-10101000-10101010-00110101
+// CHECK-INST: urshl   { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x35,0xaa,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8aa35 <unknown>
+
+urshl   {z28.s - z31.s}, {z28.s - z31.s}, z15.s  // 11000001-10101111-10101010-00111101
+// CHECK-INST: urshl   { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x3d,0xaa,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afaa3d <unknown>
+
+
+urshl   {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s}  // 11000001-10100000-10111010-00100001
+// CHECK-INST: urshl   { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x21,0xba,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0ba21 <unknown>
+
+urshl   {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s}  // 11000001-10110100-10111010-00110101
+// CHECK-INST: urshl   { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x35,0xba,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4ba35 <unknown>
+
+urshl   {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s}  // 11000001-10101000-10111010-00110101
+// CHECK-INST: urshl   { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x35,0xba,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8ba35 <unknown>
+
+urshl   {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s}  // 11000001-10111100-10111010-00111101
+// CHECK-INST: urshl   { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x3d,0xba,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bcba3d <unknown>
+
+
+urshl   {z0.d - z3.d}, {z0.d - z3.d}, z0.d  // 11000001-11100000-10101010-00100001
+// CHECK-INST: urshl   { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x21,0xaa,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0aa21 <unknown>
+
+urshl   {z20.d - z23.d}, {z20.d - z23.d}, z5.d  // 11000001-11100101-10101010-00110101
+// CHECK-INST: urshl   { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x35,0xaa,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5aa35 <unknown>
+
+urshl   {z20.d - z23.d}, {z20.d - z23.d}, z8.d  // 11000001-11101000-10101010-00110101
+// CHECK-INST: urshl   { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x35,0xaa,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8aa35 <unknown>
+
+urshl   {z28.d - z31.d}, {z28.d - z31.d}, z15.d  // 11000001-11101111-10101010-00111101
+// CHECK-INST: urshl   { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x3d,0xaa,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efaa3d <unknown>
+
+
+urshl   {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d}  // 11000001-11100000-10111010-00100001
+// CHECK-INST: urshl   { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x21,0xba,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0ba21 <unknown>
+
+urshl   {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d}  // 11000001-11110100-10111010-00110101
+// CHECK-INST: urshl   { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x35,0xba,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4ba35 <unknown>
+
+urshl   {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d}  // 11000001-11101000-10111010-00110101
+// CHECK-INST: urshl   { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x35,0xba,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8ba35 <unknown>
+
+urshl   {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d}  // 11000001-11111100-10111010-00111101
+// CHECK-INST: urshl   { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x3d,0xba,0xfc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fcba3d <unknown>
+
+
+urshl   {z0.b - z3.b}, {z0.b - z3.b}, z0.b  // 11000001-00100000-10101010-00100001
+// CHECK-INST: urshl   { z0.b - z3.b }, { z0.b - z3.b }, z0.b
+// CHECK-ENCODING: [0x21,0xaa,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120aa21 <unknown>
+
+urshl   {z20.b - z23.b}, {z20.b - z23.b}, z5.b  // 11000001-00100101-10101010-00110101
+// CHECK-INST: urshl   { z20.b - z23.b }, { z20.b - z23.b }, z5.b
+// CHECK-ENCODING: [0x35,0xaa,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125aa35 <unknown>
+
+urshl   {z20.b - z23.b}, {z20.b - z23.b}, z8.b  // 11000001-00101000-10101010-00110101
+// CHECK-INST: urshl   { z20.b - z23.b }, { z20.b - z23.b }, z8.b
+// CHECK-ENCODING: [0x35,0xaa,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128aa35 <unknown>
+
+urshl   {z28.b - z31.b}, {z28.b - z31.b}, z15.b  // 11000001-00101111-10101010-00111101
+// CHECK-INST: urshl   { z28.b - z31.b }, { z28.b - z31.b }, z15.b
+// CHECK-ENCODING: [0x3d,0xaa,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12faa3d <unknown>
+
+
+urshl   {z0.b - z3.b}, {z0.b - z3.b}, {z0.b - z3.b}  // 11000001-00100000-10111010-00100001
+// CHECK-INST: urshl   { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }
+// CHECK-ENCODING: [0x21,0xba,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120ba21 <unknown>
+
+urshl   {z20.b - z23.b}, {z20.b - z23.b}, {z20.b - z23.b}  // 11000001-00110100-10111010-00110101
+// CHECK-INST: urshl   { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }
+// CHECK-ENCODING: [0x35,0xba,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134ba35 <unknown>
+
+urshl   {z20.b - z23.b}, {z20.b - z23.b}, {z8.b - z11.b}  // 11000001-00101000-10111010-00110101
+// CHECK-INST: urshl   { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }
+// CHECK-ENCODING: [0x35,0xba,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128ba35 <unknown>
+
+urshl   {z28.b - z31.b}, {z28.b - z31.b}, {z28.b - z31.b}  // 11000001-00111100-10111010-00111101
+// CHECK-INST: urshl   { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }
+// CHECK-ENCODING: [0x3d,0xba,0x3c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13cba3d <unknown>
+
+