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Differential D135575

[AArch64]SME2 Multi-vector-Multiple Vectors SQDMULH instructions
ClosedPublic

Authored by CarolineConcatto on Oct 10 2022, 6:21 AM.

Details

Reviewers
sdesmalen
aemerson
paulwalker-arm
david-arm
kmclaughlin
Commits
rGd3c8aa7a43a9: [AArch64]SME2 Multi-vector-Multiple Vectors SQDMULH instructions
Summary

This patch adds the assembly/disassembly for the following instruction:

SQDMULH (multiple vectors): Multi-vector signed saturating doubling multiply high.

For 2 and 4 ZA registers

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09/SME-Instructions/SQDMULH--multiple-vectors---Multi-vector-signed-saturating-doubling-multiply-high-?lang=en

Depends on: D135563

Diff Detail

Event Timeline

CarolineConcatto created this revision.Oct 10 2022, 6:21 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 10 2022, 6:21 AM
Herald added subscribers: hiraditya, kristof.beyls, tschuett. · View Herald Transcript
CarolineConcatto requested review of this revision.Oct 10 2022, 6:21 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 10 2022, 6:21 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B191259: Diff 466481.Oct 10 2022, 6:22 AM
Matt added a subscriber: Matt.Oct 10 2022, 10:52 PM
CarolineConcatto retitled this revision from [AArch64]SME2 Multi-vector-Multiple Vectors SVE Destructive to [AArch64]SME2 Multi-vector-Multiple Vectors SQDMULH instructions.Oct 19 2022, 6:42 AM
CarolineConcatto edited the summary of this revision. (Show Details)
CarolineConcatto added reviewers: sdesmalen, aemerson, paulwalker-arm, david-arm, kmclaughlin.
sdesmalen added a comment.Oct 19 2022, 9:27 AM

Do you have any sqdmulh-diagnostics.s with negative tests for these instructions?

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
287

This should be: 2Z2Z2Z
And the suffix below should be: 4Z4Z4Z

289

Out of interest, why are the multiple and single vector variants of sqdmulh not part of this patch?

CarolineConcatto added a parent revision: D135683: [AArch64]SME2 single-multi and multi-multi INT/FP dot product instructions.Oct 20 2022, 3:29 AM
CarolineConcatto mentioned this in D136150: [AArch64]SME2 Single and Multi vector Shift and Multiply instructions.Oct 20 2022, 10:24 AM
CarolineConcatto updated this revision to Diff 469281.Oct 20 2022, 10:30 AM
  • address review comments
Harbormaster completed remote builds in B193273: Diff 469281.Oct 20 2022, 10:30 AM
CarolineConcatto added a comment.Oct 21 2022, 1:39 AM

Do you have any sqdmulh-diagnostics.s with negative tests for these instructions?
Yes, in sqdmulh-diagnostics.s. I added more tests

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
289

No special reason. I just did not wanted this patch
https://reviews.llvm.org/D135563
to become too big.
It is not simple, for myself, to get a balance correct.

sdesmalen accepted this revision.Oct 21 2022, 3:44 AM

Thanks for the addressing the comments.

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
289

Okay, that's fine.

This revision is now accepted and ready to land.Oct 21 2022, 3:44 AM
This revision was landed with ongoing or failed builds.Oct 21 2022, 7:36 AM
Closed by commit rGd3c8aa7a43a9: [AArch64]SME2 Multi-vector-Multiple Vectors SQDMULH instructions (authored by CarolineConcatto). · Explain Why
This revision was automatically updated to reflect the committed changes.
CarolineConcatto added a commit: rGd3c8aa7a43a9: [AArch64]SME2 Multi-vector-Multiple Vectors SQDMULH instructions.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
3 lines
48 lines
test/
MC/
AArch64/
SME2/
19 lines
201 lines

Diff 469281

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

Show First 20 Lines • Show All 278 Lines • ▼ Show 20 Lines
defm FADD_VG2_M2Z2Z_S : sme2_multivec_accum_add_sub_vg2_S<"fadd", 0b00>; defm FADD_VG2_M2Z2Z_S : sme2_multivec_accum_add_sub_vg2_S<"fadd", 0b00>;
defm FADD_VG4_M4Z4Z_S : sme2_multivec_accum_add_sub_vg4_S<"fadd", 0b00>; defm FADD_VG4_M4Z4Z_S : sme2_multivec_accum_add_sub_vg4_S<"fadd", 0b00>;
defm FSUB_VG2_M2Z2Z_S : sme2_multivec_accum_add_sub_vg2_S<"fsub", 0b01>; defm FSUB_VG2_M2Z2Z_S : sme2_multivec_accum_add_sub_vg2_S<"fsub", 0b01>;
defm FSUB_VG4_M4Z4Z_S : sme2_multivec_accum_add_sub_vg4_S<"fsub", 0b01>; defm FSUB_VG4_M4Z4Z_S : sme2_multivec_accum_add_sub_vg4_S<"fsub", 0b01>;
defm SQDMULH_2ZZ : sme2_sqdmulh_add_vector_vg2_single<"sqdmulh", 0b100000>; defm SQDMULH_2ZZ : sme2_sqdmulh_add_vector_vg2_single<"sqdmulh", 0b100000>;
defm SQDMULH_4ZZ : sme2_sqdmulh_add_vector_vg4_single<"sqdmulh", 0b100000>; defm SQDMULH_4ZZ : sme2_sqdmulh_add_vector_vg4_single<"sqdmulh", 0b100000>;
defm SQDMULH_2Z2Z2Z : sme2_sqdmulh_vector_vg2_multi<"sqdmulh">;
sdesmalenUnsubmitted
Not Done
ReplyInline Actions

This should be: 2Z2Z2Z
And the suffix below should be: 4Z4Z4Z

sdesmalen: This should be: 2Z2Z2Z And the suffix below should be: 4Z4Z4Z
defm SQDMULH_4Z4Z4Z : sme2_sqdmulh_vector_vg4_multi<"sqdmulh">;
sdesmalenUnsubmitted
Not Done
ReplyInline Actions

Out of interest, why are the multiple and single vector variants of sqdmulh not part of this patch?

sdesmalen: Out of interest, why are the multiple and single vector variants of sqdmulh not part of this…
CarolineConcattoAuthorUnsubmitted
Done
ReplyInline Actions

No special reason. I just did not wanted this patch
https://reviews.llvm.org/D135563
to become too big.
It is not simple, for myself, to get a balance correct.

CarolineConcatto: No special reason. I just did not wanted this patch https://reviews.llvm.org/D135563 to become…
sdesmalenUnsubmitted
Not Done
ReplyInline Actions

Okay, that's fine.

sdesmalen: Okay, that's fine.
} }
let Predicates = [HasSME2, HasSMEI16I64] in { let Predicates = [HasSME2, HasSMEI16I64] in {
defm ADD_VG2_M2ZZ_D : sme2_mla_add_sub_array_vg2_single_D<"add", 0b10>; defm ADD_VG2_M2ZZ_D : sme2_mla_add_sub_array_vg2_single_D<"add", 0b10>;
defm ADD_VG4_M4ZZ_D : sme2_mla_add_sub_array_vg4_single_D<"add", 0b10>; defm ADD_VG4_M4ZZ_D : sme2_mla_add_sub_array_vg4_single_D<"add", 0b10>;
defm ADD_VG2_M2Z2Z_D : sme2_mla_add_sub_array_vg2_multi_D<"add", 0b10>; defm ADD_VG2_M2Z2Z_D : sme2_mla_add_sub_array_vg2_multi_D<"add", 0b10>;
defm ADD_VG4_M4Z4Z_D : sme2_mla_add_sub_array_vg4_multi_D<"add", 0b10>; defm ADD_VG4_M4Z4Z_D : sme2_mla_add_sub_array_vg4_multi_D<"add", 0b10>;
Show All 30 Lines

llvm/lib/Target/AArch64/SMEInstrFormats.td

Show First 20 Lines • Show All 1,468 Lines • ▼ Show 20 Lines
multiclass sme2_sqdmulh_add_vector_vg4_single<string mnemonic, bits<6> op> { multiclass sme2_sqdmulh_add_vector_vg4_single<string mnemonic, bits<6> op> {
def _B : sme2_sqdmulh_add_vector_vg4_single<0b00, op, ZZZZ_b_mul_r, ZPR4b8, mnemonic>; def _B : sme2_sqdmulh_add_vector_vg4_single<0b00, op, ZZZZ_b_mul_r, ZPR4b8, mnemonic>;
def _H : sme2_sqdmulh_add_vector_vg4_single<0b01, op, ZZZZ_h_mul_r, ZPR4b16, mnemonic>; def _H : sme2_sqdmulh_add_vector_vg4_single<0b01, op, ZZZZ_h_mul_r, ZPR4b16, mnemonic>;
def _S : sme2_sqdmulh_add_vector_vg4_single<0b10, op, ZZZZ_s_mul_r, ZPR4b32, mnemonic>; def _S : sme2_sqdmulh_add_vector_vg4_single<0b10, op, ZZZZ_s_mul_r, ZPR4b32, mnemonic>;
def _D : sme2_sqdmulh_add_vector_vg4_single<0b11, op, ZZZZ_d_mul_r, ZPR4b64, mnemonic>; def _D : sme2_sqdmulh_add_vector_vg4_single<0b11, op, ZZZZ_d_mul_r, ZPR4b64, mnemonic>;
} }
class sme2_sqdmulh_vector_vg2_multi<bits<2> sz, RegisterOperand vector_ty,
string mnemonic>
: I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, vector_ty:$Zm),
mnemonic, "\t$Zdn, $_Zdn, $Zm",
"", []>, Sched<[]> {
bits<4> Zm;
bits<4> Zdn;
let Inst{31-24} = 0b11000001;
let Inst{23-22} = sz;
let Inst{21} = 0b1;
let Inst{20-17} = Zm;
let Inst{16-5} = 0b010110100000;
let Inst{4-1} = Zdn;
let Inst{0} = 0b0;
let Constraints = "$Zdn = $_Zdn";
}
multiclass sme2_sqdmulh_vector_vg2_multi<string mnemonic> {
def _B : sme2_sqdmulh_vector_vg2_multi<0b00, ZZ_b_mul_r, mnemonic>;
def _H : sme2_sqdmulh_vector_vg2_multi<0b01, ZZ_h_mul_r, mnemonic>;
def _S : sme2_sqdmulh_vector_vg2_multi<0b10, ZZ_s_mul_r, mnemonic>;
def _D : sme2_sqdmulh_vector_vg2_multi<0b11, ZZ_d_mul_r, mnemonic>;
}
class sme2_sqdmulh_vector_vg4_multi<bits<2> sz, RegisterOperand vector_ty,
string mnemonic>
: I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, vector_ty:$Zm),
mnemonic, "\t$Zdn, $_Zdn, $Zm",
"", []>, Sched<[]> {
bits<3> Zm;
bits<3> Zdn;
let Inst{31-24} = 0b11000001;
let Inst{23-22} = sz;
let Inst{21} = 0b1;
let Inst{20-18} = Zm;
let Inst{17-5} = 0b0010111100000;
let Inst{4-2} = Zdn;
let Inst{1-0} = 0b00;
let Constraints = "$Zdn = $_Zdn";
}
multiclass sme2_sqdmulh_vector_vg4_multi<string mnemonic> {
def _B : sme2_sqdmulh_vector_vg4_multi<0b00, ZZZZ_b_mul_r, mnemonic>;
def _H : sme2_sqdmulh_vector_vg4_multi<0b01, ZZZZ_h_mul_r, mnemonic>;
def _S : sme2_sqdmulh_vector_vg4_multi<0b10, ZZZZ_s_mul_r, mnemonic>;
def _D : sme2_sqdmulh_vector_vg4_multi<0b11, ZZZZ_d_mul_r, mnemonic>;
}

llvm/test/MC/AArch64/SME2/sqdmulh-diagnostics.s

Show All 22 Lines
// CHECK-NEXT: sqdmulh {z28.b-z29.b}, {z1.b-z2.b}, z15.b // CHECK-NEXT: sqdmulh {z28.b-z29.b}, {z1.b-z2.b}, z15.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmulh {z28.h-z29.h}, {z1.h-z2.h}, z15.b sqdmulh {z28.h-z29.h}, {z1.h-z2.h}, z15.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
// CHECK-NEXT: sqdmulh {z28.h-z29.h}, {z1.h-z2.h}, z15.b // CHECK-NEXT: sqdmulh {z28.h-z29.h}, {z1.h-z2.h}, z15.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmulh {z1.d-z4.d}, {z1.d-z4.d}, {z8.d-z11.d}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: sqdmulh {z1.d-z4.d}, {z1.d-z4.d}, {z8.d-z11.d}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmulh {z1.d-z2.d}, {z1.d-z2.d}, {z2.d-z3.d}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
// CHECK-NEXT: sqdmulh {z1.d-z2.d}, {z1.d-z2.d}, {z2.d-z3.d}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid single vector register // Invalid single vector register
sqdmulh {z28.b-z29.b}, {z0.b-z1.b}, z16.b sqdmulh {z28.b-z29.b}, {z0.b-z1.b}, z16.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
// CHECK-NEXT: sqdmulh {z28.b-z29.b}, {z0.b-z1.b}, z16.b // CHECK-NEXT: sqdmulh {z28.b-z29.b}, {z0.b-z1.b}, z16.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Show All 33 Lines
// CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z0.s,z1.s,z2.s}, z15.s // CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z0.s,z1.s,z2.s}, z15.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmulh {z0.s,z1.s}, {z0.d,z1.d}, z15.s sqdmulh {z0.s,z1.s}, {z0.d,z1.d}, z15.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z0.d,z1.d}, z15.s // CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z0.d,z1.d}, z15.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmulh {z2.d,z3.d}, {z0.d,z1.d}, {z4.d,z5.d}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
// CHECK-NEXT: sqdmulh {z2.d,z3.d}, {z0.d,z1.d}, {z4.d,z5.d}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmulh {z0.d-z3.d}, {z4.d-z7.d}, {z0.d-z3.d}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
// CHECK-NEXT: sqdmulh {z0.d-z3.d}, {z4.d-z7.d}, {z0.d-z3.d}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/sqdmulh.s

Show All 31 Lines
sqdmulh {z30.h - z31.h}, {z30.h - z31.h}, z15.h // 11000001-01101111-10100100-00011110 sqdmulh {z30.h - z31.h}, {z30.h - z31.h}, z15.h // 11000001-01101111-10100100-00011110
// CHECK-INST: sqdmulh { z30.h, z31.h }, { z30.h, z31.h }, z15.h // CHECK-INST: sqdmulh { z30.h, z31.h }, { z30.h, z31.h }, z15.h
// CHECK-ENCODING: [0x1e,0xa4,0x6f,0xc1] // CHECK-ENCODING: [0x1e,0xa4,0x6f,0xc1]
// CHECK-ERROR: instruction requires: sme2 // CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c16fa41e <unknown> // CHECK-UNKNOWN: c16fa41e <unknown>
sqdmulh {z0.h - z1.h}, {z0.h - z1.h}, {z0.h - z1.h} // 11000001-01100000-10110100-00000000
// CHECK-INST: sqdmulh { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
// CHECK-ENCODING: [0x00,0xb4,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160b400 <unknown>
sqdmulh {z20.h - z21.h}, {z20.h - z21.h}, {z20.h - z21.h} // 11000001-01110100-10110100-00010100
// CHECK-INST: sqdmulh { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
// CHECK-ENCODING: [0x14,0xb4,0x74,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c174b414 <unknown>
sqdmulh {z22.h - z23.h}, {z22.h - z23.h}, {z8.h - z9.h} // 11000001-01101000-10110100-00010110
// CHECK-INST: sqdmulh { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
// CHECK-ENCODING: [0x16,0xb4,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168b416 <unknown>
sqdmulh {z30.h - z31.h}, {z30.h - z31.h}, {z30.h - z31.h} // 11000001-01111110-10110100-00011110
// CHECK-INST: sqdmulh { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
// CHECK-ENCODING: [0x1e,0xb4,0x7e,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c17eb41e <unknown>
sqdmulh {z0.s - z1.s}, {z0.s - z1.s}, z0.s // 11000001-10100000-10100100-00000000 sqdmulh {z0.s - z1.s}, {z0.s - z1.s}, z0.s // 11000001-10100000-10100100-00000000
// CHECK-INST: sqdmulh { z0.s, z1.s }, { z0.s, z1.s }, z0.s // CHECK-INST: sqdmulh { z0.s, z1.s }, { z0.s, z1.s }, z0.s
// CHECK-ENCODING: [0x00,0xa4,0xa0,0xc1] // CHECK-ENCODING: [0x00,0xa4,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2 // CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0a400 <unknown> // CHECK-UNKNOWN: c1a0a400 <unknown>
sqdmulh {z20.s - z21.s}, {z20.s - z21.s}, z5.s // 11000001-10100101-10100100-00010100 sqdmulh {z20.s - z21.s}, {z20.s - z21.s}, z5.s // 11000001-10100101-10100100-00010100
// CHECK-INST: sqdmulh { z20.s, z21.s }, { z20.s, z21.s }, z5.s // CHECK-INST: sqdmulh { z20.s, z21.s }, { z20.s, z21.s }, z5.s
Show All 9 Lines
sqdmulh {z30.s - z31.s}, {z30.s - z31.s}, z15.s // 11000001-10101111-10100100-00011110 sqdmulh {z30.s - z31.s}, {z30.s - z31.s}, z15.s // 11000001-10101111-10100100-00011110
// CHECK-INST: sqdmulh { z30.s, z31.s }, { z30.s, z31.s }, z15.s // CHECK-INST: sqdmulh { z30.s, z31.s }, { z30.s, z31.s }, z15.s
// CHECK-ENCODING: [0x1e,0xa4,0xaf,0xc1] // CHECK-ENCODING: [0x1e,0xa4,0xaf,0xc1]
// CHECK-ERROR: instruction requires: sme2 // CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1afa41e <unknown> // CHECK-UNKNOWN: c1afa41e <unknown>
sqdmulh {z0.s - z1.s}, {z0.s - z1.s}, {z0.s - z1.s} // 11000001-10100000-10110100-00000000
// CHECK-INST: sqdmulh { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
// CHECK-ENCODING: [0x00,0xb4,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0b400 <unknown>
sqdmulh {z20.s - z21.s}, {z20.s - z21.s}, {z20.s - z21.s} // 11000001-10110100-10110100-00010100
// CHECK-INST: sqdmulh { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
// CHECK-ENCODING: [0x14,0xb4,0xb4,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b4b414 <unknown>
sqdmulh {z22.s - z23.s}, {z22.s - z23.s}, {z8.s - z9.s} // 11000001-10101000-10110100-00010110
// CHECK-INST: sqdmulh { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
// CHECK-ENCODING: [0x16,0xb4,0xa8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a8b416 <unknown>
sqdmulh {z30.s - z31.s}, {z30.s - z31.s}, {z30.s - z31.s} // 11000001-10111110-10110100-00011110
// CHECK-INST: sqdmulh { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
// CHECK-ENCODING: [0x1e,0xb4,0xbe,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1beb41e <unknown>
sqdmulh {z0.d - z1.d}, {z0.d - z1.d}, z0.d // 11000001-11100000-10100100-00000000 sqdmulh {z0.d - z1.d}, {z0.d - z1.d}, z0.d // 11000001-11100000-10100100-00000000
// CHECK-INST: sqdmulh { z0.d, z1.d }, { z0.d, z1.d }, z0.d // CHECK-INST: sqdmulh { z0.d, z1.d }, { z0.d, z1.d }, z0.d
// CHECK-ENCODING: [0x00,0xa4,0xe0,0xc1] // CHECK-ENCODING: [0x00,0xa4,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2 // CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0a400 <unknown> // CHECK-UNKNOWN: c1e0a400 <unknown>
sqdmulh {z20.d - z21.d}, {z20.d - z21.d}, z5.d // 11000001-11100101-10100100-00010100 sqdmulh {z20.d - z21.d}, {z20.d - z21.d}, z5.d // 11000001-11100101-10100100-00010100
// CHECK-INST: sqdmulh { z20.d, z21.d }, { z20.d, z21.d }, z5.d // CHECK-INST: sqdmulh { z20.d, z21.d }, { z20.d, z21.d }, z5.d
Show All 9 Lines
sqdmulh {z30.d - z31.d}, {z30.d - z31.d}, z15.d // 11000001-11101111-10100100-00011110 sqdmulh {z30.d - z31.d}, {z30.d - z31.d}, z15.d // 11000001-11101111-10100100-00011110
// CHECK-INST: sqdmulh { z30.d, z31.d }, { z30.d, z31.d }, z15.d // CHECK-INST: sqdmulh { z30.d, z31.d }, { z30.d, z31.d }, z15.d
// CHECK-ENCODING: [0x1e,0xa4,0xef,0xc1] // CHECK-ENCODING: [0x1e,0xa4,0xef,0xc1]
// CHECK-ERROR: instruction requires: sme2 // CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1efa41e <unknown> // CHECK-UNKNOWN: c1efa41e <unknown>
sqdmulh {z0.d - z1.d}, {z0.d - z1.d}, {z0.d - z1.d} // 11000001-11100000-10110100-00000000
// CHECK-INST: sqdmulh { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
// CHECK-ENCODING: [0x00,0xb4,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0b400 <unknown>
sqdmulh {z20.d - z21.d}, {z20.d - z21.d}, {z20.d - z21.d} // 11000001-11110100-10110100-00010100
// CHECK-INST: sqdmulh { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
// CHECK-ENCODING: [0x14,0xb4,0xf4,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f4b414 <unknown>
sqdmulh {z22.d - z23.d}, {z22.d - z23.d}, {z8.d - z9.d} // 11000001-11101000-10110100-00010110
// CHECK-INST: sqdmulh { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
// CHECK-ENCODING: [0x16,0xb4,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8b416 <unknown>
sqdmulh {z30.d - z31.d}, {z30.d - z31.d}, {z30.d - z31.d} // 11000001-11111110-10110100-00011110
// CHECK-INST: sqdmulh { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
// CHECK-ENCODING: [0x1e,0xb4,0xfe,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1feb41e <unknown>
sqdmulh {z0.b - z1.b}, {z0.b - z1.b}, z0.b // 11000001-00100000-10100100-00000000 sqdmulh {z0.b - z1.b}, {z0.b - z1.b}, z0.b // 11000001-00100000-10100100-00000000
// CHECK-INST: sqdmulh { z0.b, z1.b }, { z0.b, z1.b }, z0.b // CHECK-INST: sqdmulh { z0.b, z1.b }, { z0.b, z1.b }, z0.b
// CHECK-ENCODING: [0x00,0xa4,0x20,0xc1] // CHECK-ENCODING: [0x00,0xa4,0x20,0xc1]
// CHECK-ERROR: instruction requires: sme2 // CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c120a400 <unknown> // CHECK-UNKNOWN: c120a400 <unknown>
sqdmulh {z20.b - z21.b}, {z20.b - z21.b}, z5.b // 11000001-00100101-10100100-00010100 sqdmulh {z20.b - z21.b}, {z20.b - z21.b}, z5.b // 11000001-00100101-10100100-00010100
// CHECK-INST: sqdmulh { z20.b, z21.b }, { z20.b, z21.b }, z5.b // CHECK-INST: sqdmulh { z20.b, z21.b }, { z20.b, z21.b }, z5.b
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sqdmulh {z30.b - z31.b}, {z30.b - z31.b}, z15.b // 11000001-00101111-10100100-00011110 sqdmulh {z30.b - z31.b}, {z30.b - z31.b}, z15.b // 11000001-00101111-10100100-00011110
// CHECK-INST: sqdmulh { z30.b, z31.b }, { z30.b, z31.b }, z15.b // CHECK-INST: sqdmulh { z30.b, z31.b }, { z30.b, z31.b }, z15.b
// CHECK-ENCODING: [0x1e,0xa4,0x2f,0xc1] // CHECK-ENCODING: [0x1e,0xa4,0x2f,0xc1]
// CHECK-ERROR: instruction requires: sme2 // CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c12fa41e <unknown> // CHECK-UNKNOWN: c12fa41e <unknown>
sqdmulh {z0.b - z1.b}, {z0.b - z1.b}, {z0.b - z1.b} // 11000001-00100000-10110100-00000000
// CHECK-INST: sqdmulh { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }
// CHECK-ENCODING: [0x00,0xb4,0x20,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c120b400 <unknown>
sqdmulh {z20.b - z21.b}, {z20.b - z21.b}, {z20.b - z21.b} // 11000001-00110100-10110100-00010100
// CHECK-INST: sqdmulh { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }
// CHECK-ENCODING: [0x14,0xb4,0x34,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c134b414 <unknown>
sqdmulh {z22.b - z23.b}, {z22.b - z23.b}, {z8.b - z9.b} // 11000001-00101000-10110100-00010110
// CHECK-INST: sqdmulh { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }
// CHECK-ENCODING: [0x16,0xb4,0x28,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c128b416 <unknown>
sqdmulh {z30.b - z31.b}, {z30.b - z31.b}, {z30.b - z31.b} // 11000001-00111110-10110100-00011110
// CHECK-INST: sqdmulh { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }
// CHECK-ENCODING: [0x1e,0xb4,0x3e,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c13eb41e <unknown>
sqdmulh {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-01100000-10101100-00000000 sqdmulh {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-01100000-10101100-00000000
// CHECK-INST: sqdmulh { z0.h - z3.h }, { z0.h - z3.h }, z0.h // CHECK-INST: sqdmulh { z0.h - z3.h }, { z0.h - z3.h }, z0.h
// CHECK-ENCODING: [0x00,0xac,0x60,0xc1] // CHECK-ENCODING: [0x00,0xac,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2 // CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160ac00 <unknown> // CHECK-UNKNOWN: c160ac00 <unknown>
sqdmulh {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-01100101-10101100-00010100 sqdmulh {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-01100101-10101100-00010100
// CHECK-INST: sqdmulh { z20.h - z23.h }, { z20.h - z23.h }, z5.h // CHECK-INST: sqdmulh { z20.h - z23.h }, { z20.h - z23.h }, z5.h
Show All 9 Lines
sqdmulh {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-01101111-10101100-00011100 sqdmulh {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-01101111-10101100-00011100
// CHECK-INST: sqdmulh { z28.h - z31.h }, { z28.h - z31.h }, z15.h // CHECK-INST: sqdmulh { z28.h - z31.h }, { z28.h - z31.h }, z15.h
// CHECK-ENCODING: [0x1c,0xac,0x6f,0xc1] // CHECK-ENCODING: [0x1c,0xac,0x6f,0xc1]
// CHECK-ERROR: instruction requires: sme2 // CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c16fac1c <unknown> // CHECK-UNKNOWN: c16fac1c <unknown>
sqdmulh {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-01100000-10111100-00000000
// CHECK-INST: sqdmulh { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
// CHECK-ENCODING: [0x00,0xbc,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160bc00 <unknown>
sqdmulh {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-01110100-10111100-00010100
// CHECK-INST: sqdmulh { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
// CHECK-ENCODING: [0x14,0xbc,0x74,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c174bc14 <unknown>
sqdmulh {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-01101000-10111100-00010100
// CHECK-INST: sqdmulh { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
// CHECK-ENCODING: [0x14,0xbc,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168bc14 <unknown>
sqdmulh {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-01111100-10111100-00011100
// CHECK-INST: sqdmulh { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
// CHECK-ENCODING: [0x1c,0xbc,0x7c,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c17cbc1c <unknown>
sqdmulh {z0.s - z3.s}, {z0.s - z3.s}, z0.s // 11000001-10100000-10101100-00000000 sqdmulh {z0.s - z3.s}, {z0.s - z3.s}, z0.s // 11000001-10100000-10101100-00000000
// CHECK-INST: sqdmulh { z0.s - z3.s }, { z0.s - z3.s }, z0.s // CHECK-INST: sqdmulh { z0.s - z3.s }, { z0.s - z3.s }, z0.s
// CHECK-ENCODING: [0x00,0xac,0xa0,0xc1] // CHECK-ENCODING: [0x00,0xac,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2 // CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0ac00 <unknown> // CHECK-UNKNOWN: c1a0ac00 <unknown>
sqdmulh {z20.s - z23.s}, {z20.s - z23.s}, z5.s // 11000001-10100101-10101100-00010100 sqdmulh {z20.s - z23.s}, {z20.s - z23.s}, z5.s // 11000001-10100101-10101100-00010100
// CHECK-INST: sqdmulh { z20.s - z23.s }, { z20.s - z23.s }, z5.s // CHECK-INST: sqdmulh { z20.s - z23.s }, { z20.s - z23.s }, z5.s
Show All 9 Lines
sqdmulh {z28.s - z31.s}, {z28.s - z31.s}, z15.s // 11000001-10101111-10101100-00011100 sqdmulh {z28.s - z31.s}, {z28.s - z31.s}, z15.s // 11000001-10101111-10101100-00011100
// CHECK-INST: sqdmulh { z28.s - z31.s }, { z28.s - z31.s }, z15.s // CHECK-INST: sqdmulh { z28.s - z31.s }, { z28.s - z31.s }, z15.s
// CHECK-ENCODING: [0x1c,0xac,0xaf,0xc1] // CHECK-ENCODING: [0x1c,0xac,0xaf,0xc1]
// CHECK-ERROR: instruction requires: sme2 // CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1afac1c <unknown> // CHECK-UNKNOWN: c1afac1c <unknown>
sqdmulh {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100000-10111100-00000000
// CHECK-INST: sqdmulh { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
// CHECK-ENCODING: [0x00,0xbc,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0bc00 <unknown>
sqdmulh {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s} // 11000001-10110100-10111100-00010100
// CHECK-INST: sqdmulh { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
// CHECK-ENCODING: [0x14,0xbc,0xb4,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b4bc14 <unknown>
sqdmulh {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s} // 11000001-10101000-10111100-00010100
// CHECK-INST: sqdmulh { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
// CHECK-ENCODING: [0x14,0xbc,0xa8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a8bc14 <unknown>
sqdmulh {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111100-10111100-00011100
// CHECK-INST: sqdmulh { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
// CHECK-ENCODING: [0x1c,0xbc,0xbc,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1bcbc1c <unknown>
sqdmulh {z0.d - z3.d}, {z0.d - z3.d}, z0.d // 11000001-11100000-10101100-00000000 sqdmulh {z0.d - z3.d}, {z0.d - z3.d}, z0.d // 11000001-11100000-10101100-00000000
// CHECK-INST: sqdmulh { z0.d - z3.d }, { z0.d - z3.d }, z0.d // CHECK-INST: sqdmulh { z0.d - z3.d }, { z0.d - z3.d }, z0.d
// CHECK-ENCODING: [0x00,0xac,0xe0,0xc1] // CHECK-ENCODING: [0x00,0xac,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2 // CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0ac00 <unknown> // CHECK-UNKNOWN: c1e0ac00 <unknown>
sqdmulh {z20.d - z23.d}, {z20.d - z23.d}, z5.d // 11000001-11100101-10101100-00010100 sqdmulh {z20.d - z23.d}, {z20.d - z23.d}, z5.d // 11000001-11100101-10101100-00010100
// CHECK-INST: sqdmulh { z20.d - z23.d }, { z20.d - z23.d }, z5.d // CHECK-INST: sqdmulh { z20.d - z23.d }, { z20.d - z23.d }, z5.d
Show All 9 Lines
sqdmulh {z28.d - z31.d}, {z28.d - z31.d}, z15.d // 11000001-11101111-10101100-00011100 sqdmulh {z28.d - z31.d}, {z28.d - z31.d}, z15.d // 11000001-11101111-10101100-00011100
// CHECK-INST: sqdmulh { z28.d - z31.d }, { z28.d - z31.d }, z15.d // CHECK-INST: sqdmulh { z28.d - z31.d }, { z28.d - z31.d }, z15.d
// CHECK-ENCODING: [0x1c,0xac,0xef,0xc1] // CHECK-ENCODING: [0x1c,0xac,0xef,0xc1]
// CHECK-ERROR: instruction requires: sme2 // CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1efac1c <unknown> // CHECK-UNKNOWN: c1efac1c <unknown>
sqdmulh {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100000-10111100-00000000
// CHECK-INST: sqdmulh { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
// CHECK-ENCODING: [0x00,0xbc,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0bc00 <unknown>
sqdmulh {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d} // 11000001-11110100-10111100-00010100
// CHECK-INST: sqdmulh { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
// CHECK-ENCODING: [0x14,0xbc,0xf4,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f4bc14 <unknown>
sqdmulh {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d} // 11000001-11101000-10111100-00010100
// CHECK-INST: sqdmulh { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
// CHECK-ENCODING: [0x14,0xbc,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8bc14 <unknown>
sqdmulh {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111100-10111100-00011100
// CHECK-INST: sqdmulh { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
// CHECK-ENCODING: [0x1c,0xbc,0xfc,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1fcbc1c <unknown>
sqdmulh {z0.b - z3.b}, {z0.b - z3.b}, z0.b // 11000001-00100000-10101100-00000000 sqdmulh {z0.b - z3.b}, {z0.b - z3.b}, z0.b // 11000001-00100000-10101100-00000000
// CHECK-INST: sqdmulh { z0.b - z3.b }, { z0.b - z3.b }, z0.b // CHECK-INST: sqdmulh { z0.b - z3.b }, { z0.b - z3.b }, z0.b
// CHECK-ENCODING: [0x00,0xac,0x20,0xc1] // CHECK-ENCODING: [0x00,0xac,0x20,0xc1]
// CHECK-ERROR: instruction requires: sme2 // CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c120ac00 <unknown> // CHECK-UNKNOWN: c120ac00 <unknown>
sqdmulh {z20.b - z23.b}, {z20.b - z23.b}, z5.b // 11000001-00100101-10101100-00010100 sqdmulh {z20.b - z23.b}, {z20.b - z23.b}, z5.b // 11000001-00100101-10101100-00010100
// CHECK-INST: sqdmulh { z20.b - z23.b }, { z20.b - z23.b }, z5.b // CHECK-INST: sqdmulh { z20.b - z23.b }, { z20.b - z23.b }, z5.b
// CHECK-ENCODING: [0x14,0xac,0x25,0xc1] // CHECK-ENCODING: [0x14,0xac,0x25,0xc1]
// CHECK-ERROR: instruction requires: sme2 // CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c125ac14 <unknown> // CHECK-UNKNOWN: c125ac14 <unknown>
sqdmulh {z20.b - z23.b}, {z20.b - z23.b}, z8.b // 11000001-00101000-10101100-00010100 sqdmulh {z20.b - z23.b}, {z20.b - z23.b}, z8.b // 11000001-00101000-10101100-00010100
// CHECK-INST: sqdmulh { z20.b - z23.b }, { z20.b - z23.b }, z8.b // CHECK-INST: sqdmulh { z20.b - z23.b }, { z20.b - z23.b }, z8.b
// CHECK-ENCODING: [0x14,0xac,0x28,0xc1] // CHECK-ENCODING: [0x14,0xac,0x28,0xc1]
// CHECK-ERROR: instruction requires: sme2 // CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c128ac14 <unknown> // CHECK-UNKNOWN: c128ac14 <unknown>
sqdmulh {z28.b - z31.b}, {z28.b - z31.b}, z15.b // 11000001-00101111-10101100-00011100 sqdmulh {z28.b - z31.b}, {z28.b - z31.b}, z15.b // 11000001-00101111-10101100-00011100
// CHECK-INST: sqdmulh { z28.b - z31.b }, { z28.b - z31.b }, z15.b // CHECK-INST: sqdmulh { z28.b - z31.b }, { z28.b - z31.b }, z15.b
// CHECK-ENCODING: [0x1c,0xac,0x2f,0xc1] // CHECK-ENCODING: [0x1c,0xac,0x2f,0xc1]
// CHECK-ERROR: instruction requires: sme2 // CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c12fac1c <unknown> // CHECK-UNKNOWN: c12fac1c <unknown>
sqdmulh {z0.b - z3.b}, {z0.b - z3.b}, {z0.b - z3.b} // 11000001-00100000-10111100-00000000
// CHECK-INST: sqdmulh { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }
// CHECK-ENCODING: [0x00,0xbc,0x20,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c120bc00 <unknown>
sqdmulh {z20.b - z23.b}, {z20.b - z23.b}, {z20.b - z23.b} // 11000001-00110100-10111100-00010100
// CHECK-INST: sqdmulh { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }
// CHECK-ENCODING: [0x14,0xbc,0x34,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c134bc14 <unknown>
sqdmulh {z20.b - z23.b}, {z20.b - z23.b}, {z8.b - z11.b} // 11000001-00101000-10111100-00010100
// CHECK-INST: sqdmulh { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }
// CHECK-ENCODING: [0x14,0xbc,0x28,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c128bc14 <unknown>
sqdmulh {z28.b - z31.b}, {z28.b - z31.b}, {z28.b - z31.b} // 11000001-00111100-10111100-00011100
// CHECK-INST: sqdmulh { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }
// CHECK-ENCODING: [0x1c,0xbc,0x3c,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c13cbc1c <unknown>