[RISCV] Combine comparison and logic ops.

[iabg-sc]

Summary

Two comparison operations and a logical operation are combined into selection using MIN or MAX and comparison operation.
For optimization to be applied conditions have to be satisfied:

1. In comparison operations has to be the one common operand.
2. Supports only signed and unsigned integers.
3. Comparison has to be the same with respect to common operand.
4. There are no more users of comparison except logic operation.
5. Every combination of comparison and AND, OR are supported.

It will convert

%l0 = %a < %c
%l1 = %b < %c
%res = %l0 or %l1

into

%sel = min(%a, %b)
%res = %sel < %c

It supports several comparison operations (<, <=, >, >=), signed, unsigned values and different order of operands if they do not violate conditions.

[iabg-sc]

Fix commit message

[craig.topper]

llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll

6

oprimization -> optimization

241

I don't think this is correct for FP. "fcmp ult" returns true if either operand is a nan. fmin will return a non-nan input unless both are nan. So for this code, if %a is nan, %b and %c are non-nan the original code returned true. But the rewritten code will only compare %b and %c and ignore %a.

[jrtc27]

[test] normally means you’re only touching tests. The rest of the subject is also poor, you don’t have an actual active verb, just a participle

[iabg-sc]

Floating point operands are not supported. Typos fix.

[anton-afanasyev]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8304

please adjust comment: no float

[iabg-sc]

'.' was removed from commit message

[iabg-sc]

comment about float support was removed

[iabg-sc]

llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll

241

Yes, indeed. Since the behavior with NaNs cannot be preserved these cases should be prohibited.

[iabg-sc]

@asb, @craig.topper, @reames could you please review?

[iabg-sc]

Hi!
Could you please review?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8215

Drop curly braces

8219

Drop curly braces

8223

Why do we need to get the underlying SDNode* explicitly? SDValue has a operator->.

8258

Does this get reported as unused in release builds?

8319

Drop curly braces

8335

All of the less conditions have bit 1 set and bit 2 clear. All the greater have bit 1 clear and bit 2 set. That's by design. Can we use that?

[craig.topper]

llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll

11

below is misspelled

[iabg-sc]

Comparison operations are checked via bit fields.
SDNodes were removed. Now all actions only on SDValues.
Some cosmetic changes.

[iabg-sc]

Thanks for the suggestions. Here is the patch with fixes mentioned before.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8215

This is required by the definition of ISD::AND/OR. It can be an assert.

8226

I'm not sure the std::finds and std::distance added much over manually checking the 4 permutations.

8267

pattern*

8297

If the compares a common operand, then all of the operands must be the same type.

[iabg-sc]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8226

Perhaps searching for common and other operands is easy to do manually. It can be done with two ifs. But verifying the found operands will be look like copy-paste with different indices. Now this verifying is hidden inside algorithms, and only crucial conditions, when something goes terribly wrong, are checked with assert.
I think there are two different approaches:

1 - Find correct indices by value properties. Therefore, I do not need to check this properties as they are stated. This is that I did.
2 - By indices find values and verify their properties. But in this case indices are stated and addition checks are required.

[iabg-sc]

Removed unnecessary checks. Fixed typos.

[iabg-sc]

Hi!
Could you please review?

[iabg-sc]

Rebased to upstream

[iabg-sc]

Hi!
Could you please review?

[iabg-sc]

New approach

Implemented new approach to determine common operands in comparison operations.

[iabg-sc]

Hi!
Could you please review?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8305

Why at instead of [Pos]?

8311

std::optional

8316

std::nullopt

8348

std::optional

8360

std::nullopt

8363

V0 and V1 are SDValue. We should use .getOpcode() instead of ->getOpcode().

8367

.getOperand(0)

8425

I'm not sure the enum makes sense if you have to assert that it isn't once of the values. Can't we just have a bool IsUnsigned?

8437

LLVM is pretty conservative about the use of auto. Use unsigned here.

8447

use EVT instead of auto.

8451

Seems like rather than an enum we can have

bool IsUnsigned = ISD::isUnsignedIntSetCC(RefOpcode);
assert((IsUnsigned || ISD::isSignedIntSetCC(RefOpcode)) &&
       "Operation neither with signed or unsigned integers.");
``

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8263

possition -> position

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8375

Why std::move? There's nothing in CmpOpInfo that is heap allocated is there?

[iabg-sc]

Minor changes for code readability.

[iabg-sc]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8451

Thanks. It is more clear. Initially enum was used, because there could be fp operations too.

[iabg-sc]

Thanks for the review. Could you please look on this version?

[iabg-sc]

Hi!
Could you please review?

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (!N0.hasOneUse() || !N1.hasOneUse())
     return SDValue();
 
   SDValue N01 = N0.getOperand(1);
   SDValue N11 = N1.getOperand(1);
 
   // For AND, SimplifyDemandedBits may have turned one of the (xor X, 1) into
   // (xor X, -1) based on the upper bits of the other operand being 0. If the
   // operation is And, allow one of the Xors to use -1.
   if (isOneConstant(N01)) {
     if (!isOneConstant(N11) && !(IsAnd && isAllOnesConstant(N11)))
       return SDValue();
   } else if (isOneConstant(N11)) {
     // N01 and N11 being 1 was already handled. Handle N11==1 and N01==-1.
     if (!(IsAnd && isAllOnesConstant(N01)))
       return SDValue();
   } else
     return SDValue();
 
   EVT VT = N->getValueType(0);
 
   SDValue N00 = N0.getOperand(0);
   SDValue N10 = N1.getOperand(0);
 
   // The LHS of the xors needs to be 0/1.
   APInt Mask = APInt::getBitsSetFrom(VT.getSizeInBits(), 1);
   if (!DAG.MaskedValueIsZero(N00, Mask) || !DAG.MaskedValueIsZero(N10, Mask))
     return SDValue();
 
   // Invert the opcode and insert a new xor.
   SDLoc DL(N);
   unsigned Opc = IsAnd ? ISD::OR : ISD::AND;
   SDValue Logic = DAG.getNode(Opc, DL, VT, N00, N10);
   return DAG.getNode(ISD::XOR, DL, VT, Logic, DAG.getConstant(1, DL, VT));
 }
 
+// Helper class contains information about comparison operation.
+// The first two operands of this operation are compared values and the
+// last one is the operation.
+// Compared values are stored in Ops.
+// Comparison operation is stored in CCode.
+class CmpOpInfo {
+  static unsigned constexpr Size = 2u;
+
+  // Type for storing operands of compare operation.
+  using OpsArray = std::array<SDValue, Size>;
+  OpsArray Ops;
+
+  using const_iterator = OpsArray::const_iterator;
+  const_iterator begin() const { return Ops.begin(); }
+  const_iterator end() const { return Ops.end(); }
+
+  ISD::CondCode CCode;
+
+  unsigned CommonPos{Size};
+  unsigned DifferPos{Size};
+
+  // Sets CommonPos and DifferPos based on incoming position
+  // of common operand CPos.
+  void setPositions(const_iterator CPos) {
+    assert(CPos != Ops.end() && "Common operand has to be in OpsArray.\n");
+    CommonPos = CPos == Ops.begin() ? 0 : 1;
+    DifferPos = 1 - CommonPos;
+    assert((DifferPos == 0 || DifferPos == 1) &&
+           "Positions can be only 0 or 1.");
+  }
+
+  // Private constructor of comparison info based on comparison operator.
+  // It is private because CmpOpInfo only reasonable relative to other
+  // comparison operator. Therefore, infos about comparison operation
+  // have to be collected simultaneously via CmpOpInfo::getInfoAbout().
+  CmpOpInfo(const SDValue &CmpOp)
+      : Ops{CmpOp.getOperand(0), CmpOp.getOperand(1)},
+        CCode{cast<CondCodeSDNode>(CmpOp.getOperand(2))->get()} {}
+
+  // Finds common operand of Op1 and Op2 and finishes filling CmpOpInfos.
+  // Returns true if common operand is found. Otherwise - false.
+  static bool establishCorrespondence(CmpOpInfo &Op1, CmpOpInfo &Op2) {
+    const auto CommonOpIt1 =
+        std::find_first_of(Op1.begin(), Op1.end(), Op2.begin(), Op2.end());
+    if (CommonOpIt1 == Op1.end())
+      return false;
+
+    const auto CommonOpIt2 = std::find(Op2.begin(), Op2.end(), *CommonOpIt1);
+    assert(CommonOpIt2 != Op2.end() &&
+           "Cannot find common operand in the second comparison operation.");
+
+    Op1.setPositions(CommonOpIt1);
+    Op2.setPositions(CommonOpIt2);
+
+    return true;
+  }
+
+public:
+  CmpOpInfo(const CmpOpInfo &) = default;
+  CmpOpInfo(CmpOpInfo &&) = default;
+
+  SDValue const &operator[](unsigned Pos) const {
+    assert(Pos < Size && "Out of range\n");
+    return Ops[Pos];
+  }
+
+  // Creates infos about comparison operations CmpOp0 and CmpOp1.
+  // If there is no common operand returns None. Otherwise, returns
+  // correspondence info about comparison operations.
+  static std::optional<std::pair<CmpOpInfo, CmpOpInfo>>
+  getInfoAbout(SDValue const &CmpOp0, SDValue const &CmpOp1) {
+    CmpOpInfo Op0{CmpOp0};
+    CmpOpInfo Op1{CmpOp1};
+    if (!establishCorrespondence(Op0, Op1))
+      return std::nullopt;
+    return std::make_pair(Op0, Op1);
+  }
+
+  // Returns position of common operand.
+  unsigned getCPos() const { return CommonPos; }
+
+  // Returns position of differ operand.
+  unsigned getDPos() const { return DifferPos; }
+
+  // Returns common operand.
+  SDValue const &getCOp() const { return operator[](CommonPos); }
+
+  // Returns differ operand.
+  SDValue const &getDOp() const { return operator[](DifferPos); }
+
+  // Returns consition code of comparison operation.
+  ISD::CondCode getCondCode() const { return CCode; }
+};
+
+// Verifies conditions to apply an optimization.
+// Returns Reference comparison code and three operands A, B, C.
+// Conditions for optimization:
+//   One operand of the compasions has to be common.
+//   This operand is written to C.
+//   Two others operands are differend. They are written to A and B.
+//   Comparisons has to be similar with respect to common operand C.
+//     e.g. A < C; C > B are similar
+//      but A < C; B > C are not.
+//   Reference comparison code is the comparison code if
+//   common operand is right placed.
+//     e.g. C > A will be swapped to A < C.
+static std::optional<std::tuple<ISD::CondCode, SDValue, SDValue, SDValue>>
+verifyCompareConds(SDNode *N, SelectionDAG &DAG) {
+  LLVM_DEBUG(
+      dbgs() << "Checking conditions for comparison operation combining.\n";);
+
+  SDValue V0 = N->getOperand(0);
+  SDValue V1 = N->getOperand(1);
+  assert(V0.getValueType() == V1.getValueType() &&
+         "Operations must have the same value type.");
+
+  // Condition 1. Operations have to be used only in logic operation.
+  if (!V0.hasOneUse() || !V1.hasOneUse())
+    return std::nullopt;
+
+  // Condition 2. Operands have to be comparison operations.
+  if (V0.getOpcode() != ISD::SETCC || V1.getOpcode() != ISD::SETCC)
+    return std::nullopt;
+
+  // Condition 3.1. Operations only with integers.
+  if (!V0.getOperand(0).getValueType().isInteger())
+    return std::nullopt;
+
+  const auto ComparisonInfo = CmpOpInfo::getInfoAbout(V0, V1);
+  // Condition 3.2. Common operand has to be in comparison.
+  if (!ComparisonInfo)
+    return std::nullopt;
+
+  const auto [Op0, Op1] = ComparisonInfo.value();
+
+  LLVM_DEBUG(dbgs() << "Shared operands are on positions: " << Op0.getCPos()
+                    << " and " << Op1.getCPos() << '\n';);
+  // If common operand at the first position then swap operation to convert to
+  // strict pattern. Common operand has to be right hand side.
+  ISD::CondCode RefCond = Op0.getCondCode();
+  ISD::CondCode AssistCode = Op1.getCondCode();
+  if (!Op0.getCPos())
+    RefCond = ISD::getSetCCSwappedOperands(RefCond);
+  if (!Op1.getCPos())
+    AssistCode = ISD::getSetCCSwappedOperands(AssistCode);
+  LLVM_DEBUG(dbgs() << "Reference condition is: " << RefCond << '\n';);
+  // If there are different comparison operations then do not perform an
+  // optimization. a < c; c < b -> will be changed to b > c.
+  if (RefCond != AssistCode)
+    return std::nullopt;
+
+  // Conditions can be only similar to Less or Greater. (>, >=, <, <=)
+  // Applying this mask to the operation will determine Less and Greater
+  // operations.
+  const unsigned CmpMask = 0b110;
+  const unsigned MaskedOpcode = CmpMask & RefCond;
+  // If masking gave 0b110, then this is an operation NE, O or TRUE.
+  if (MaskedOpcode == CmpMask)
+    return std::nullopt;
+  // If masking gave 00000, then this is an operation E, O or FALSE.
+  if (MaskedOpcode == 0)
+    return std::nullopt;
+  // Everything else is similar to Less or Greater.
+
+  SDValue A = Op0.getDOp();
+  SDValue B = Op1.getDOp();
+  SDValue C = Op0.getCOp();
+
+  LLVM_DEBUG(
+      dbgs() << "The conditions for combining comparisons are satisfied.\n";);
+  return std::make_tuple(RefCond, A, B, C);
+}
+
+static ISD::NodeType getSelectionCode(bool IsUnsigned, bool IsAnd,
+                                      bool IsGreaterOp) {
+  // Codes of selection operation. The first index selects signed or unsigned,
+  // the second index selects MIN/MAX.
+  static constexpr ISD::NodeType SelectionCodes[2][2] = {
+      {ISD::SMIN, ISD::SMAX}, {ISD::UMIN, ISD::UMAX}};
+  const bool ChooseSelCode = IsAnd ^ IsGreaterOp;
+  return SelectionCodes[IsUnsigned][ChooseSelCode];
+}
+
+// Combines two comparison operation and logic operation to one selection
+// operation(min, max) and logic operation. Returns new constructed Node if
+// conditions for optimization are satisfied.
+static SDValue combineCmpOp(SDNode *N, SelectionDAG &DAG,
+                            const RISCVSubtarget &Subtarget) {
+  if (!Subtarget.hasStdExtZbb())
+    return SDValue();
+
+  const unsigned BitOpcode = N->getOpcode();
+  assert((BitOpcode == ISD::AND || BitOpcode == ISD::OR) &&
+         "This optimization can be used only with AND/OR operations");
+
+  const auto Props = verifyCompareConds(N, DAG);
+  // If conditions are invalidated then do not perform an optimization.
+  if (!Props)
+    return SDValue();
+
+  const auto [RefOpcode, A, B, C] = Props.value();
+  const EVT CmpOpVT = A.getValueType();
+
+  const bool IsGreaterOp = RefOpcode & 0b10;
+  const bool IsUnsigned = ISD::isUnsignedIntSetCC(RefOpcode);
+  assert((IsUnsigned || ISD::isSignedIntSetCC(RefOpcode)) &&
+         "Operation neither with signed or unsigned integers.");
+
+  const bool IsAnd = BitOpcode == ISD::AND;
+  const ISD::NodeType PickCode =
+      getSelectionCode(IsUnsigned, IsAnd, IsGreaterOp);
+
+  SDLoc DL(N);
+  SDValue Pick = DAG.getNode(PickCode, DL, CmpOpVT, A, B);
+  SDValue Cmp =
+      DAG.getSetCC(DL, N->getOperand(0).getValueType(), Pick, C, RefOpcode);
+
+  return Cmp;
+}
+
 static SDValue performANDCombine(SDNode *N,
                                  TargetLowering::DAGCombinerInfo &DCI,
                                  const RISCVSubtarget &Subtarget) {
   SelectionDAG &DAG = DCI.DAG;
 
   SDValue N0 = N->getOperand(0);
   // Pre-promote (i32 (and (srl X, Y), 1)) on RV64 with Zbs without zero
   // extending X. This is safe since we only need the LSB after the shift and
   // shift amounts larger than 31 would produce poison. If we wait until
   // type legalization, we'll create RISCVISD::SRLW and we can't recover it
   // to use a BEXT instruction.
   if (Subtarget.is64Bit() && Subtarget.hasStdExtZbs() &&
       N->getValueType(0) == MVT::i32 && isOneConstant(N->getOperand(1)) &&
       N0.getOpcode() == ISD::SRL && !isa<ConstantSDNode>(N0.getOperand(1)) &&
       N0.hasOneUse()) {
     SDLoc DL(N);
     SDValue Op0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N0.getOperand(0));
     SDValue Op1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N0.getOperand(1));
     SDValue Srl = DAG.getNode(ISD::SRL, DL, MVT::i64, Op0, Op1);
     SDValue And = DAG.getNode(ISD::AND, DL, MVT::i64, Srl,
                               DAG.getConstant(1, DL, MVT::i64));
     return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, And);
   }
 
+  if (SDValue V = combineCmpOp(N, DAG, Subtarget))
+    return V;
+
   if (SDValue V = combineBinOpToReduce(N, DAG))
     return V;
 
   if (DCI.isAfterLegalizeDAG())
     if (SDValue V = combineDeMorganOfBoolean(N, DAG))
       return V;
 
   // fold (and (select lhs, rhs, cc, -1, y), x) ->
   //      (select lhs, rhs, cc, x, (and x, y))
   return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ true);
 }
 
 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
                                 const RISCVSubtarget &Subtarget) {
   SelectionDAG &DAG = DCI.DAG;
 
+  if (SDValue V = combineCmpOp(N, DAG, Subtarget))
+    return V;
+
   if (SDValue V = combineBinOpToReduce(N, DAG))
     return V;
 
   if (DCI.isAfterLegalizeDAG())
     if (SDValue V = combineDeMorganOfBoolean(N, DAG))
       return V;
 
   // fold (or (select cond, 0, y), x) ->

llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc  -mtriple=riscv64 -mattr=+zbb -O3 < %s \
 ; RUN:  | FileCheck %s --check-prefixes=CHECK,CHECK-RV64I
 ; RUN: llc  -mtriple=riscv64 -mattr=+zbb,+f -target-abi=lp64f -O3 < %s \
 ; RUN:  | FileCheck %s --check-prefixes=CHECK,CHECK-RV64IF
 ; Tests aimed to check optimization which combines
 ; two comparison operations and logic operation into
 ; one select(min/max) operation and one comparison
 ; operaion.
 
 ; 4 patterns below will be converted to umin+less.
 define i1 @ulo(i64 %c, i64 %a, i64 %b) {
 ; CHECK-LABEL: ulo:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sltu a1, a1, a0
-; CHECK-NEXT:    sltu a0, a2, a0
-; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    minu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a1, a0
 ; CHECK-NEXT:    ret
   %l0 = icmp ult i64 %a, %c
   %l1 = icmp ult i64 %b, %c
   %res = or i1 %l0, %l1
   ret i1 %res
 }
 
 define i1 @ulo_swap1(i64 %c, i64 %a, i64 %b) {
 ; CHECK-LABEL: ulo_swap1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sltu a1, a1, a0
-; CHECK-NEXT:    sltu a0, a2, a0
-; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    minu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a1, a0
 ; CHECK-NEXT:    ret
   %l0 = icmp ugt i64 %c, %a
   %l1 = icmp ult i64 %b, %c
   %res = or i1 %l0, %l1
   ret i1 %res
 }
 
 define i1 @ulo_swap2(i64 %c, i64 %a, i64 %b) {
 ; CHECK-LABEL: ulo_swap2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sltu a1, a1, a0
-; CHECK-NEXT:    sltu a0, a2, a0
-; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    minu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a1, a0
 ; CHECK-NEXT:    ret
   %l0 = icmp ult i64 %a, %c
   %l1 = icmp ugt i64 %c, %b
   %res = or i1 %l0, %l1
   ret i1 %res
 }
 
 define i1 @ulo_swap12(i64 %c, i64 %a, i64 %b) {
 ; CHECK-LABEL: ulo_swap12:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sltu a1, a1, a0
-; CHECK-NEXT:    sltu a0, a2, a0
-; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    minu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a1, a0
 ; CHECK-NEXT:    ret
   %l0 = icmp ugt i64 %c, %a
   %l1 = icmp ugt i64 %c, %b
   %res = or i1 %l0, %l1
   ret i1 %res
 }
 
 ; 4 patterns below will be converted to umax+less.
 define i1 @ula(i64 %c, i64 %a, i64 %b) {
 ; CHECK-LABEL: ula:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sltu a1, a1, a0
-; CHECK-NEXT:    sltu a0, a2, a0
-; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    maxu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a1, a0
 ; CHECK-NEXT:    ret
   %l0 = icmp ult i64 %a, %c
   %l1 = icmp ult i64 %b, %c
   %res = and i1 %l0, %l1
   ret i1 %res
 }
 
 define i1 @ula_swap1(i64 %c, i64 %a, i64 %b) {
 ; CHECK-LABEL: ula_swap1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sltu a1, a1, a0
-; CHECK-NEXT:    sltu a0, a2, a0
-; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    maxu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a1, a0
 ; CHECK-NEXT:    ret
   %l0 = icmp ugt i64 %c, %a
   %l1 = icmp ult i64 %b, %c
   %res = and i1 %l0, %l1
   ret i1 %res
 }
 
 define i1 @ula_swap2(i64 %c, i64 %a, i64 %b) {
 ; CHECK-LABEL: ula_swap2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sltu a1, a1, a0
-; CHECK-NEXT:    sltu a0, a2, a0
-; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    maxu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a1, a0
 ; CHECK-NEXT:    ret
   %l0 = icmp ult i64 %a, %c
   %l1 = icmp ugt i64 %c, %b
   %res = and i1 %l0, %l1
   ret i1 %res
 }
 
 define i1 @ula_swap12(i64 %c, i64 %a, i64 %b) {
 ; CHECK-LABEL: ula_swap12:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sltu a1, a1, a0
-; CHECK-NEXT:    sltu a0, a2, a0
-; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    maxu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a1, a0
 ; CHECK-NEXT:    ret
   %l0 = icmp ugt i64 %c, %a
   %l1 = icmp ugt i64 %c, %b
   %res = and i1 %l0, %l1
   ret i1 %res
 }
 
 ; 4 patterns below will be converted to umax+greater
 ; (greater will be converted to setult somehow)
 define i1 @ugo(i64 %c, i64 %a, i64 %b) {
 ; CHECK-LABEL: ugo:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sltu a1, a0, a1
-; CHECK-NEXT:    sltu a0, a0, a2
-; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    maxu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a0, a1
 ; CHECK-NEXT:    ret
   %l0 = icmp ugt i64 %a, %c
   %l1 = icmp ugt i64 %b, %c
   %res = or i1 %l0, %l1
   ret i1 %res
 }
 
 define i1 @ugo_swap1(i64 %c, i64 %a, i64 %b) {
 ; CHECK-LABEL: ugo_swap1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sltu a1, a0, a1
-; CHECK-NEXT:    sltu a0, a0, a2
-; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    maxu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a0, a1
 ; CHECK-NEXT:    ret
   %l0 = icmp ult i64 %c, %a
   %l1 = icmp ugt i64 %b, %c
   %res = or i1 %l0, %l1
   ret i1 %res
 }
 
 define i1 @ugo_swap2(i64 %c, i64 %a, i64 %b) {
 ; CHECK-LABEL: ugo_swap2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sltu a1, a0, a1
-; CHECK-NEXT:    sltu a0, a0, a2
-; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    maxu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a0, a1
 ; CHECK-NEXT:    ret
   %l0 = icmp ugt i64 %a, %c
   %l1 = icmp ult i64 %c, %b
   %res = or i1 %l0, %l1
   ret i1 %res
 }
 
 define i1 @ugo_swap12(i64 %c, i64 %a, i64 %b) {
 ; CHECK-LABEL: ugo_swap12:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sltu a1, a0, a1
-; CHECK-NEXT:    sltu a0, a0, a2
-; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    maxu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a0, a1
 ; CHECK-NEXT:    ret
   %l0 = icmp ult i64 %c, %a
   %l1 = icmp ult i64 %c, %b
   %res = or i1 %l0, %l1
   ret i1 %res
 }
 
 ; Pattern below will be converted to umin+greater or equal
 ; (greater will be converted to setult somehow)
 define i1 @ugea(i64 %c, i64 %a, i64 %b) {
 ; CHECK-LABEL: ugea:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sltu a1, a1, a0
-; CHECK-NEXT:    sltu a0, a2, a0
-; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    minu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a1, a0
 ; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    ret
   %l0 = icmp uge i64 %a, %c
   %l1 = icmp uge i64 %b, %c
   %res = and i1 %l0, %l1
   ret i1 %res
 }
 
 ; Pattern below will be converted to umin+greater
 ; (greater will be converted to setult somehow)
 define i1 @uga(i64 %c, i64 %a, i64 %b) {
 ; CHECK-LABEL: uga:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sltu a1, a0, a1
-; CHECK-NEXT:    sltu a0, a0, a2
-; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    minu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a0, a1
 ; CHECK-NEXT:    ret
   %l0 = icmp ugt i64 %a, %c
   %l1 = icmp ugt i64 %b, %c
   %res = and i1 %l0, %l1
   ret i1 %res
 }
 
 ; Patterns below will be converted to smax+less.
 ; Sign check.
 define i1 @sla(i64 %c, i64 %a, i64 %b) {
 ; CHECK-LABEL: sla:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    slt a1, a1, a0
-; CHECK-NEXT:    slt a0, a2, a0
-; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    max a1, a1, a2
+; CHECK-NEXT:    slt a0, a1, a0
 ; CHECK-NEXT:    ret
   %l0 = icmp slt i64 %a, %c
   %l1 = icmp slt i64 %b, %c
   %res = and i1 %l0, %l1
   ret i1 %res
 }
 
+; Negative test
 ; Float check.
 define i1 @flo(float %c, float %a, float %b) {
 ; CHECK-RV64I-LABEL: flo:
 ; CHECK-RV64I:       # %bb.0:
 ; CHECK-RV64I-NEXT:    addi sp, sp, -32
 ; CHECK-RV64I-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; CHECK-RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill

 ; CHECK-RV64I-NEXT:    ret
 ;
 ; CHECK-RV64IF-LABEL: flo:
 ; CHECK-RV64IF:       # %bb.0:
 ; CHECK-RV64IF-NEXT:    fle.s a0, fa0, fa1
 ; CHECK-RV64IF-NEXT:    fle.s a1, fa0, fa2
 ; CHECK-RV64IF-NEXT:    and a0, a0, a1
 ; CHECK-RV64IF-NEXT:    xori a0, a0, 1
 ; CHECK-RV64IF-NEXT:    ret
   %l0 = fcmp ult float %a, %c
   %l1 = fcmp ult float %b, %c
   %res = or i1 %l0, %l1
   ret i1 %res
 }
 
+; Negative test
 ; Double check.
 define i1 @dlo(double %c, double %a, double %b) {
 ; CHECK-LABEL: dlo:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -32
 ; CHECK-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill

 ; CHECK-NEXT:    addi sp, sp, 32
 ; CHECK-NEXT:    ret
   %l0 = fcmp ult double %a, %c
   %l1 = fcmp ult double %b, %c
   %res = or i1 %l0, %l1
   ret i1 %res
 }
 
+; Negative test
 ; More than one user
 define i1 @multi_user(i64 %c, i64 %a, i64 %b) {
 ; CHECK-LABEL: multi_user:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    sltu a1, a1, a0
 ; CHECK-NEXT:    sltu a0, a2, a0
 ; CHECK-NEXT:    or a0, a1, a0
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    ret
   %l0 = icmp ugt i64 %c, %a
   %l1 = icmp ult i64 %b, %c
   %res = or i1 %l0, %l1
 
   %out = and i1 %l0, %res
   ret i1 %out
 }
 
+; Negative test
 ; No same comparations
 define i1 @no_same_ops(i64 %c, i64 %a, i64 %b) {
 ; CHECK-LABEL: no_same_ops:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    sltu a1, a0, a1
 ; CHECK-NEXT:    sltu a0, a2, a0
 ; CHECK-NEXT:    or a0, a1, a0
 ; CHECK-NEXT:    ret
   %l0 = icmp ult i64 %c, %a
   %l1 = icmp ugt i64 %c, %b
   %res = or i1 %l0, %l1
   ret i1 %res
 }