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anton-afanasyev (Anton Afanasyev)
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Sep 30 2018, 2:53 PM (46 w, 1 d)

Recent Activity

Today

anton-afanasyev committed rG3f3a2573c307: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks (authored by anton-afanasyev).
[Support][Time profiler] Make FE codegen blocks to be inside frontend blocks
Mon, Aug 19, 4:00 PM
anton-afanasyev committed rL369308: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.
[Support][Time profiler] Make FE codegen blocks to be inside frontend blocks
Mon, Aug 19, 3:57 PM
anton-afanasyev closed D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.
Mon, Aug 19, 3:57 PM · Restricted Project, Restricted Project

Fri, Aug 16

anton-afanasyev added a comment to D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.

Ping!

Fri, Aug 16, 10:04 AM · Restricted Project, Restricted Project

Wed, Aug 14

anton-afanasyev added inline comments to D66132: [CodeGen] Add `shouldDoPartialRedundancyElimination()` to `TargetInstrInfo` (PRR42405).
Wed, Aug 14, 1:27 AM · Restricted Project
anton-afanasyev updated the diff for D66132: [CodeGen] Add `shouldDoPartialRedundancyElimination()` to `TargetInstrInfo` (PRR42405).

Rename

Wed, Aug 14, 1:27 AM · Restricted Project
anton-afanasyev retitled D66132: [CodeGen] Add `shouldDoPartialRedundancyElimination()` to `TargetInstrInfo` (PRR42405) from [CodeGen] Add `isSpeculativeExecutionForbidden()` to `TargetInstrInfo` (PRR42405) to [CodeGen] Add `shouldDoPartialRedundancyElimination()` to `TargetInstrInfo` (PRR42405).
Wed, Aug 14, 1:27 AM · Restricted Project

Tue, Aug 13

anton-afanasyev retitled D66132: [CodeGen] Add `shouldDoPartialRedundancyElimination()` to `TargetInstrInfo` (PRR42405) from [CodeGen] Add `isSpeculativeExecutionForbidden()` to `TargetTransformInfo` (PRR42405) to [CodeGen] Add `isSpeculativeExecutionForbidden()` to `TargetInstrInfo` (PRR42405).
Tue, Aug 13, 9:30 AM · Restricted Project
anton-afanasyev added a comment to D66132: [CodeGen] Add `shouldDoPartialRedundancyElimination()` to `TargetInstrInfo` (PRR42405).

After reading through https://bugs.llvm.org/show_bug.cgi?id=42405 i'm not confident that this is the correct solution.
It reads to me as-if this speculative execution in PRE being done with no proper legality checks.
In particular, i'd think you want to check a white-list in MachineCSE::isPRECandidate(),
much like llvm::isSafeToSpeculativelyExecute() is for middle-end.

Unless i'm really looking in the wrong place, there is no such thing here?

Tue, Aug 13, 6:34 AM · Restricted Project
anton-afanasyev added a comment to D66132: [CodeGen] Add `shouldDoPartialRedundancyElimination()` to `TargetInstrInfo` (PRR42405).

I feel like this is lacking words.
What problem is this addressing?
Is it correctness-one or performance?
The current hook feels a little bit weird.
Does it mean to completely ban speculative execution?
If then there is a lot more places where it should be used, and not using it there may be surprising.
Or does it only mean to ban PRE? But then, what was the original problem?
Or should it be per-MI hook?
etc

Tue, Aug 13, 5:08 AM · Restricted Project
anton-afanasyev updated the diff for D66132: [CodeGen] Add `shouldDoPartialRedundancyElimination()` to `TargetInstrInfo` (PRR42405).

Update comment

Tue, Aug 13, 3:26 AM · Restricted Project
anton-afanasyev updated the summary of D66132: [CodeGen] Add `shouldDoPartialRedundancyElimination()` to `TargetInstrInfo` (PRR42405).
Tue, Aug 13, 3:17 AM · Restricted Project
anton-afanasyev created D66132: [CodeGen] Add `shouldDoPartialRedundancyElimination()` to `TargetInstrInfo` (PRR42405).
Tue, Aug 13, 3:13 AM · Restricted Project

Fri, Aug 9

anton-afanasyev added a comment to D56772: [MIR] Add simple PRE pass to MachineCSE.

Hi @LuoYuanke, I've benchmarked the effect of the revertion my and @lkail patches.
The benchmark showed some increase of the exec_time:

~/llvm/test-suite/utils/compare.py  --filter-short -m exec_time ~/llvm/test-suite-results/results_rel_base.json ~/llvm/test-suite-results/results_rel_base2.json vs ~/llvm/test-suite-results/results_rel_exp.json  ~/llvm/test-suite-results/results_rel_exp2.json
Fri, Aug 9, 10:52 AM · Restricted Project

Tue, Aug 6

anton-afanasyev added a comment to D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.

Ping!

Tue, Aug 6, 2:58 AM · Restricted Project, Restricted Project

Wed, Jul 31

anton-afanasyev added a comment to D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.

Ping!

Wed, Jul 31, 8:38 AM · Restricted Project, Restricted Project

Wed, Jul 24

anton-afanasyev committed rG4fdcabf259c4: [Support] Fix `-ftime-trace-granularity` option (authored by anton-afanasyev).
[Support] Fix `-ftime-trace-granularity` option
Wed, Jul 24, 8:00 AM
anton-afanasyev committed rL366911: [Support] Fix `-ftime-trace-granularity` option.
[Support] Fix `-ftime-trace-granularity` option
Wed, Jul 24, 7:59 AM
anton-afanasyev closed D65202: [Support] Fix `-ftime-trace-granularity` option.
Wed, Jul 24, 7:58 AM · Restricted Project, Restricted Project
anton-afanasyev added a comment to D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.

Hi @lebedev.ri, could you please lgtm this or elaborate on possible issue with this?

Wed, Jul 24, 7:53 AM · Restricted Project, Restricted Project
anton-afanasyev added inline comments to D65202: [Support] Fix `-ftime-trace-granularity` option.
Wed, Jul 24, 7:15 AM · Restricted Project, Restricted Project
anton-afanasyev updated the diff for D65202: [Support] Fix `-ftime-trace-granularity` option.

Remove default repeat

Wed, Jul 24, 6:38 AM · Restricted Project, Restricted Project
anton-afanasyev added inline comments to D65202: [Support] Fix `-ftime-trace-granularity` option.
Wed, Jul 24, 6:38 AM · Restricted Project, Restricted Project
anton-afanasyev updated subscribers of D65202: [Support] Fix `-ftime-trace-granularity` option.
Wed, Jul 24, 6:26 AM · Restricted Project, Restricted Project
anton-afanasyev added a comment to D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.

Hi all! Could it be accepted or reviewed more?

Wed, Jul 24, 6:23 AM · Restricted Project, Restricted Project
anton-afanasyev added inline comments to D65202: [Support] Fix `-ftime-trace-granularity` option.
Wed, Jul 24, 6:01 AM · Restricted Project, Restricted Project
anton-afanasyev updated the diff for D65202: [Support] Fix `-ftime-trace-granularity` option.

Update

Wed, Jul 24, 6:01 AM · Restricted Project, Restricted Project
anton-afanasyev added inline comments to D60663: Time profiler: small fixes and optimizations.
Wed, Jul 24, 5:16 AM · Restricted Project, Restricted Project
anton-afanasyev created D65202: [Support] Fix `-ftime-trace-granularity` option.
Wed, Jul 24, 5:15 AM · Restricted Project, Restricted Project

Tue, Jul 23

anton-afanasyev added a comment to D56772: [MIR] Add simple PRE pass to MachineCSE.

@anton-afanasyev
Hi,
Do you have any performance data for the patch? I'd like to know what benchmark has performance gain with your patch. https://reviews.llvm.org/D64394 fixed perlbench regression, but I wonder what the performance gain do we achieve with the 2 patch?

Tue, Jul 23, 8:27 AM · Restricted Project

Jul 19 2019

anton-afanasyev added a comment to D56772: [MIR] Add simple PRE pass to MachineCSE.

Btw, this fix (https://reviews.llvm.org/D64394) was commited recently.

Jul 19 2019, 1:26 PM · Restricted Project
anton-afanasyev added a comment to D56772: [MIR] Add simple PRE pass to MachineCSE.

@anton-afanasyev
Hi,
Did you look into the SPEC cpu2017/500.perlbench_r issue? There is some significant performance drop on X86 with the patch. I ask you to revert the patch first, and when the SPEC2017 regression is fixed, we can submit the patch again. How do you think?

Jul 19 2019, 12:42 AM · Restricted Project

Jul 18 2019

anton-afanasyev updated subscribers of D63934: [MIR] Improve PRE condition of MachineCSE optimization.

Hi all! I've figured out that my current implementation of PRE is incorrect and it needs to be either corrected, restricted or reverted.
The issue is that current PRE can actually hoist instruction executing it speculatively for some CFG paths which potentially leads to perf degradation. However I believe that current heuristic PRE is rather useful if it is restricted enough. Good restriction (apart from this revision) is implemented by @lkail here: https://reviews.llvm.org/D64394, it is based on basic block frequencies comparision.

Jul 18 2019, 5:25 PM · Restricted Project
anton-afanasyev added a comment to D64394: [MachineCSE][MachinePRE] Do not hoist common computations into hot BBs.

Btw, this change breaks multiple (more than two) hoisting to common dominator. I've tested this patch for the original test case taken from here: https://bugs.llvm.org/show_bug.cgi?id=38917. There are several comparisons giving 96 > 40 + 10, 96 > 29 + 10, 96 > 18 + 10 (so no hoisting at all), meanwhile 96 < 97 = 40 + 29 + 18 + 10.
However I do not see easy solution for this issue.

Jul 18 2019, 5:07 PM · Restricted Project
anton-afanasyev added inline comments to D64394: [MachineCSE][MachinePRE] Do not hoist common computations into hot BBs.
Jul 18 2019, 3:20 PM · Restricted Project

Jul 16 2019

anton-afanasyev added a comment to D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.

Ping!

Jul 16 2019, 4:00 AM · Restricted Project, Restricted Project

Jul 14 2019

anton-afanasyev added a comment to D63934: [MIR] Improve PRE condition of MachineCSE optimization.

Thanks Anton.
Can you please keep us updated with any progress in this regard?

Jul 14 2019, 2:21 AM · Restricted Project

Jul 10 2019

anton-afanasyev added a comment to D63934: [MIR] Improve PRE condition of MachineCSE optimization.

Just to make sure I understand the change correctly:
This can still hoist instructions outside of their BB and execute them speculatively even if you can't prove that all possible paths execute the instruction, am I right?

Jul 10 2019, 7:59 AM · Restricted Project

Jul 9 2019

anton-afanasyev added a comment to D63860: [MachineCSE] Extend CSE heuristic.

Hi @piotr, have you tried regression benchmarking with this patch? For instance, test suite.

Hi Anton, Yes, I have just run regression testing on the test-suite and the tests pass ("Expected Passes : 917").

Jul 9 2019, 11:08 AM · Restricted Project

Jul 8 2019

anton-afanasyev updated the diff for D63934: [MIR] Improve PRE condition of MachineCSE optimization.

Add small fix

Jul 8 2019, 3:19 PM · Restricted Project
anton-afanasyev added inline comments to D63934: [MIR] Improve PRE condition of MachineCSE optimization.
Jul 8 2019, 3:19 PM · Restricted Project
anton-afanasyev added a comment to D63860: [MachineCSE] Extend CSE heuristic.

Hi @piotr, have you tried regression benchmarking with this patch? For instance, test suite.

Jul 8 2019, 12:11 AM · Restricted Project

Jul 5 2019

anton-afanasyev added a comment to D63934: [MIR] Improve PRE condition of MachineCSE optimization.

Ping!
This patch fixes https://llvm.org/pr42405 implicitly.

Jul 5 2019, 10:03 AM · Restricted Project

Jul 4 2019

anton-afanasyev added a comment to D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.

I've upload json-file and printscreen of its visualization (used https://speedscope.app). This is an example of how this patch works, making two Frontend sections.

Jul 4 2019, 8:58 AM · Restricted Project, Restricted Project

Jun 28 2019

anton-afanasyev updated the diff for D63934: [MIR] Improve PRE condition of MachineCSE optimization.

Added test

Jun 28 2019, 1:48 PM · Restricted Project
anton-afanasyev added a comment to D63934: [MIR] Improve PRE condition of MachineCSE optimization.

(is this missing a test?)

Jun 28 2019, 8:19 AM · Restricted Project
anton-afanasyev created D63934: [MIR] Improve PRE condition of MachineCSE optimization.
Jun 28 2019, 8:08 AM · Restricted Project
anton-afanasyev added a comment to D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.

Is it ok now? I doubt that main code refactoring is a good way when adding support timer code. So ended with more robust solution, though it leads to two Frontend sections.

Jun 28 2019, 12:18 AM · Restricted Project, Restricted Project

Jun 26 2019

anton-afanasyev added a comment to rL362901: [MIR] Add simple PRE pass to MachineCSE.

The bug is reported by @aymanmus here: https://llvm.org/pr42405

Jun 26 2019, 4:04 AM
anton-afanasyev added a comment to rL362901: [MIR] Add simple PRE pass to MachineCSE.

Hi Anton,

Attached is an mir test for a reproducer to a bug that we encountered that appears to be an incorrect behavior of MachineCSE pass after this change was committed.
Can you please take a look ASAP?

You can run it using the following command:
llc -mtriple=aarch64-none-linux-gnu -run-pass=machine-cse -asm-verbose=1 -verify-machineinstrs reproducer.mir -o after-pass
You can see that the divide instruction was pulled out of the if-if-else and it can divide by 0 when the original code doesn't allow this.

Thanks,
Ayman Musa

Jun 26 2019, 3:36 AM

Jun 24 2019

anton-afanasyev added inline comments to D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.
Jun 24 2019, 4:25 AM · Restricted Project, Restricted Project
anton-afanasyev updated the diff for D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.

Changed comment

Jun 24 2019, 4:24 AM · Restricted Project, Restricted Project

Jun 23 2019

anton-afanasyev added inline comments to D56772: [MIR] Add simple PRE pass to MachineCSE.
Jun 23 2019, 2:59 PM · Restricted Project

Jun 21 2019

anton-afanasyev added inline comments to D56772: [MIR] Add simple PRE pass to MachineCSE.
Jun 21 2019, 8:19 AM · Restricted Project
anton-afanasyev added a comment to rL362901: [MIR] Add simple PRE pass to MachineCSE.

@anton-afanasyev: FYI, we're still seeing this and it presents itself as a miscompile.
We're still working on getting a test case but it's proving to be very difficult.

Jun 21 2019, 7:02 AM
anton-afanasyev added a comment to D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.

Also, first "Frontend" section contains "ParseTemplate" and "PerformPendingInstantiations" sections.

Jun 21 2019, 6:39 AM · Restricted Project, Restricted Project
anton-afanasyev added a comment to D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.

Hm, i started writing previous comment before you posted your last comment, so i didn't see the last update.
This looks less intrusive, yes, but two observations:

  1. You now have two "Frontend" sections - first one being for lexing time
  2. That lexing section is not within the "Frontend" section, even though it is for sure part of frontend of the compiler. Like i said, i'm not sure what the right solution here is.
Jun 21 2019, 6:27 AM · Restricted Project, Restricted Project
anton-afanasyev updated the diff for D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.

Hi @lebedev.ri, I've turned back to the solution with one TimeTraceScope for "Frontend" inside BackendConsumer::HandleTranslationUnit(), since it looks more robust. This admits several (two for now) "Frontend" sections, but I see no problem with this. Other solutions have to rely on BackendConsumer and ASTConsumer calling correct relations, which are not guaranteed (though it is looking correct for now).

Jun 21 2019, 5:35 AM · Restricted Project, Restricted Project

Jun 19 2019

anton-afanasyev updated the diff for D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.

Updated, changed test

Jun 19 2019, 2:29 PM · Restricted Project, Restricted Project

Jun 18 2019

anton-afanasyev added inline comments to D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.
Jun 18 2019, 4:16 PM · Restricted Project, Restricted Project
anton-afanasyev added a comment to D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.

Hmm, i'm only now noticing how fraglie this looks.
How do we know that clang::ParseAST will only ever be called with BackendConsumer ASTConsumer?
How do we know that BackendConsumer will only ever be ASTConsumer from clang::ParseAST?

Jun 18 2019, 4:12 PM · Restricted Project, Restricted Project
anton-afanasyev updated the diff for D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.

Updated

Jun 18 2019, 3:22 PM · Restricted Project, Restricted Project
anton-afanasyev added inline comments to D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.
Jun 18 2019, 3:22 PM · Restricted Project, Restricted Project
anton-afanasyev updated the diff for D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.

Updated

Jun 18 2019, 3:07 PM · Restricted Project, Restricted Project
anton-afanasyev added inline comments to D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.
Jun 18 2019, 3:07 PM · Restricted Project, Restricted Project
anton-afanasyev added inline comments to D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.
Jun 18 2019, 4:10 AM · Restricted Project, Restricted Project
anton-afanasyev updated the diff for D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.

Updated

Jun 18 2019, 4:10 AM · Restricted Project, Restricted Project

Jun 14 2019

anton-afanasyev updated the diff for D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.

Small fix

Jun 14 2019, 3:44 AM · Restricted Project, Restricted Project
anton-afanasyev created D63325: [Support][Time profiler] Make FE codegen blocks to be inside frontend blocks.
Jun 14 2019, 3:38 AM · Restricted Project, Restricted Project

Jun 12 2019

anton-afanasyev added a comment to rL362901: [MIR] Add simple PRE pass to MachineCSE.

@anton-afanasyev:
The test failures occur in Halide generated code, with the HVX backend. They are not public.
r363164 does not fix the tests; it does change an erroneous output to another erroneous one.

Jun 12 2019, 2:38 PM
anton-afanasyev added a comment to rL362901: [MIR] Add simple PRE pass to MachineCSE.

@asbirlea Btw, this fix was commited for the issue noted here: https://reviews.llvm.org/D56772#1537772

Jun 12 2019, 1:29 PM
anton-afanasyev added a comment to rL362901: [MIR] Add simple PRE pass to MachineCSE.

FYI, we're seeing test failures due to this revision. Currently trying to isolate a testcase, but it may be challenging to minimize if the failures are due to a miscompile.

Jun 12 2019, 1:00 PM
anton-afanasyev closed D56772: [MIR] Add simple PRE pass to MachineCSE.

Last issue fixed by this revision: https://reviews.llvm.org/D63148

Jun 12 2019, 6:53 AM · Restricted Project
anton-afanasyev committed rG339b39b77337: [MIR] Skip hoisting to basic block which may throw exception or return (authored by anton-afanasyev).
[MIR] Skip hoisting to basic block which may throw exception or return
Jun 12 2019, 6:50 AM
anton-afanasyev committed rL363164: [MIR] Skip hoisting to basic block which may throw exception or return.
[MIR] Skip hoisting to basic block which may throw exception or return
Jun 12 2019, 6:48 AM
anton-afanasyev closed D63148: [MIR] Skip hoisting to throwable or return machine basic blocks.
Jun 12 2019, 6:48 AM · Restricted Project

Jun 11 2019

anton-afanasyev updated the diff for D63148: [MIR] Skip hoisting to throwable or return machine basic blocks.

Update description

Jun 11 2019, 11:43 AM · Restricted Project
anton-afanasyev updated the diff for D63148: [MIR] Skip hoisting to throwable or return machine basic blocks.

Add test

Jun 11 2019, 10:47 AM · Restricted Project
anton-afanasyev added a comment to D63148: [MIR] Skip hoisting to throwable or return machine basic blocks.

Missing a test

Jun 11 2019, 10:47 AM · Restricted Project
anton-afanasyev added a comment to D56772: [MIR] Add simple PRE pass to MachineCSE.

Hi @john.brawn , here is the fix, could you please look to it: https://reviews.llvm.org/D63148

Jun 11 2019, 10:08 AM · Restricted Project
anton-afanasyev created D63148: [MIR] Skip hoisting to throwable or return machine basic blocks.
Jun 11 2019, 10:05 AM · Restricted Project
anton-afanasyev added a comment to D56772: [MIR] Add simple PRE pass to MachineCSE.

The issue actually is not with this instruction, but it's related to exception handling. Hoisted instruction is inserted before getFirstTerminator(), but there could be EH_LABEL's which are not terminators, but could change control flow.

Jun 11 2019, 8:23 AM · Restricted Project
anton-afanasyev added a comment to D56772: [MIR] Add simple PRE pass to MachineCSE.

This is causing incorrect code generation for this piece of IR:

target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-arm-none-eabi"

@var = hidden local_unnamed_addr global i32 0, align 4
@_ZTIi = external dso_local constant i8*
declare dso_local void @_Z2fnv() local_unnamed_addr #1
declare dso_local i32 @__gxx_personality_v0(...)
declare i32 @llvm.eh.typeid.for(i8*) #2
declare dso_local i8* @__cxa_begin_catch(i8*) local_unnamed_addr
declare dso_local void @__cxa_end_catch() local_unnamed_addr

define hidden i32 @_Z7examplev() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
entry:
  invoke void @_Z2fnv()
          to label %try.cont unwind label %lpad

lpad:                                             ; preds = %entry
  %0 = landingpad { i8*, i32 }
          catch i8* bitcast (i8** @_ZTIi to i8*)
          catch i8* null
  %1 = extractvalue { i8*, i32 } %0, 0
  %2 = extractvalue { i8*, i32 } %0, 1
  %3 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*))
  %matches = icmp eq i32 %2, %3
  %4 = tail call i8* @__cxa_begin_catch(i8* %1)
  %5 = load i32, i32* @var, align 4
  br i1 %matches, label %catch1, label %catch

catch1:                                           ; preds = %lpad
  %or3 = or i32 %5, 4
  store i32 %or3, i32* @var, align 4
  tail call void @__cxa_end_catch()
  br label %try.cont

try.cont:                                         ; preds = %entry, %catch1, %catch
  %6 = load i32, i32* @var, align 4
  ret i32 %6

catch:                                            ; preds = %lpad
  %or = or i32 %5, 8
  store i32 %or, i32* @var, align 4
  tail call void @__cxa_end_catch()
  br label %try.cont
}

As part of the accesses to var an ADRP instruction is being generated and MachineCSE is hoisting it to the entry block, but it gets hoisted to after the call to fn so when we catch an exception the ADRP hasn't been executed so the loads and stores use an undefined base register.

Jun 11 2019, 4:44 AM · Restricted Project
anton-afanasyev committed rG7599da571886: [Support][Test] Time profiler: add regression test (authored by anton-afanasyev).
[Support][Test] Time profiler: add regression test
Jun 11 2019, 1:24 AM
anton-afanasyev committed rL363036: [Support][Test] Time profiler: add regression test.
[Support][Test] Time profiler: add regression test
Jun 11 2019, 1:24 AM

Jun 9 2019

anton-afanasyev closed D56772: [MIR] Add simple PRE pass to MachineCSE.

Closed by commit https://reviews.llvm.org/rL362901

Jun 9 2019, 6:33 AM · Restricted Project
anton-afanasyev committed rG623d9ba068e6: [MIR] Add simple PRE pass to MachineCSE (authored by anton-afanasyev).
[MIR] Add simple PRE pass to MachineCSE
Jun 9 2019, 5:14 AM
anton-afanasyev committed rL362901: [MIR] Add simple PRE pass to MachineCSE.
[MIR] Add simple PRE pass to MachineCSE
Jun 9 2019, 5:14 AM

Jun 7 2019

anton-afanasyev added a comment to D61914: [Support][Test] Time profiler: add regression test.

cfe/trunk/test/Driver/check-time-trace.cpp appears to fail on Darwin. Did you mean to pass the target explicitly ?

Jun 7 2019, 2:01 PM · Restricted Project, Restricted Project
anton-afanasyev committed rG07e3f3d9e467: Revert "[Support][Test] Time profiler: add regression test" (authored by anton-afanasyev).
Revert "[Support][Test] Time profiler: add regression test"
Jun 7 2019, 11:38 AM
anton-afanasyev added a reverting change for rG44282a60c90f: [Support][Test] Time profiler: add regression test: rG07e3f3d9e467: Revert "[Support][Test] Time profiler: add regression test".
Jun 7 2019, 11:38 AM
anton-afanasyev committed rL362824: Revert "[Support][Test] Time profiler: add regression test".
Revert "[Support][Test] Time profiler: add regression test"
Jun 7 2019, 11:33 AM
anton-afanasyev committed rG44282a60c90f: [Support][Test] Time profiler: add regression test (authored by anton-afanasyev).
[Support][Test] Time profiler: add regression test
Jun 7 2019, 11:12 AM
anton-afanasyev committed rL362821: [Support][Test] Time profiler: add regression test.
[Support][Test] Time profiler: add regression test
Jun 7 2019, 11:12 AM
anton-afanasyev committed rGf2ddd608367b: [Support][Test] Time profiler: add regression test (authored by anton-afanasyev).
[Support][Test] Time profiler: add regression test
Jun 7 2019, 5:57 AM
anton-afanasyev committed rL362792: [Support][Test] Time profiler: add regression test.
[Support][Test] Time profiler: add regression test
Jun 7 2019, 5:57 AM
anton-afanasyev closed D61914: [Support][Test] Time profiler: add regression test.
Jun 7 2019, 5:57 AM · Restricted Project, Restricted Project
anton-afanasyev added a comment to D61914: [Support][Test] Time profiler: add regression test.

Could you please move the test to a more approriate location? (ie. clang/trunk/test/Driver/)

Jun 7 2019, 4:13 AM · Restricted Project, Restricted Project
anton-afanasyev updated the diff for D61914: [Support][Test] Time profiler: add regression test.

Updated

Jun 7 2019, 4:13 AM · Restricted Project, Restricted Project

Jun 3 2019

anton-afanasyev abandoned D62067: [Support] Time profiler: support new PassManager.
Jun 3 2019, 8:15 AM · Restricted Project