[RISCV] Combine comparison and logic ops.

[iabg-sc]

Summary

Two comparison operations and a logical operation are combined into selection using MIN or MAX and comparison operation.
For optimization to be applied conditions have to be satisfied:

1. In comparison operations has to be the one common operand.
2. Supports only signed and unsigned integers.
3. Comparison has to be the same with respect to common operand.
4. There are no more users of comparison except logic operation.
5. Every combination of comparison and AND, OR are supported.

It will convert

%l0 = %a < %c
%l1 = %b < %c
%res = %l0 or %l1

into

%sel = min(%a, %b)
%res = %sel < %c

It supports several comparison operations (<, <=, >, >=), signed, unsigned values and different order of operands if they do not violate conditions.

[iabg-sc]

Fix commit message

[craig.topper]

llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll

6

oprimization -> optimization

241

I don't think this is correct for FP. "fcmp ult" returns true if either operand is a nan. fmin will return a non-nan input unless both are nan. So for this code, if %a is nan, %b and %c are non-nan the original code returned true. But the rewritten code will only compare %b and %c and ignore %a.

[jrtc27]

[test] normally means you’re only touching tests. The rest of the subject is also poor, you don’t have an actual active verb, just a participle

[iabg-sc]

Floating point operands are not supported. Typos fix.

[anton-afanasyev]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8404

please adjust comment: no float

[iabg-sc]

'.' was removed from commit message

[iabg-sc]

comment about float support was removed

[iabg-sc]

llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll

241

Yes, indeed. Since the behavior with NaNs cannot be preserved these cases should be prohibited.

[iabg-sc]

@asb, @craig.topper, @reames could you please review?

[iabg-sc]

Hi!
Could you please review?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8315

Drop curly braces

8319

Drop curly braces

8323

Why do we need to get the underlying SDNode* explicitly? SDValue has a operator->.

8358

Does this get reported as unused in release builds?

8419

Drop curly braces

8435

All of the less conditions have bit 1 set and bit 2 clear. All the greater have bit 1 clear and bit 2 set. That's by design. Can we use that?

[craig.topper]

llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll

11

below is misspelled

[iabg-sc]

Comparison operations are checked via bit fields.
SDNodes were removed. Now all actions only on SDValues.
Some cosmetic changes.

[iabg-sc]

Thanks for the suggestions. Here is the patch with fixes mentioned before.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8315

This is required by the definition of ISD::AND/OR. It can be an assert.

8326

I'm not sure the std::finds and std::distance added much over manually checking the 4 permutations.

8367

pattern*

8397

If the compares a common operand, then all of the operands must be the same type.

[iabg-sc]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8326

Perhaps searching for common and other operands is easy to do manually. It can be done with two ifs. But verifying the found operands will be look like copy-paste with different indices. Now this verifying is hidden inside algorithms, and only crucial conditions, when something goes terribly wrong, are checked with assert.
I think there are two different approaches:

1 - Find correct indices by value properties. Therefore, I do not need to check this properties as they are stated. This is that I did.
2 - By indices find values and verify their properties. But in this case indices are stated and addition checks are required.

[iabg-sc]

Removed unnecessary checks. Fixed typos.

[iabg-sc]

Hi!
Could you please review?

[iabg-sc]

Rebased to upstream

[iabg-sc]

Hi!
Could you please review?

[iabg-sc]

New approach

Implemented new approach to determine common operands in comparison operations.

[iabg-sc]

Hi!
Could you please review?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8358

Why at instead of [Pos]?

8364

std::optional

8369

std::nullopt

8401

std::optional

8413

std::nullopt

8416

V0 and V1 are SDValue. We should use .getOpcode() instead of ->getOpcode().

8420

.getOperand(0)

8478

I'm not sure the enum makes sense if you have to assert that it isn't once of the values. Can't we just have a bool IsUnsigned?

8490

LLVM is pretty conservative about the use of auto. Use unsigned here.

8500

use EVT instead of auto.

8504

Seems like rather than an enum we can have

bool IsUnsigned = ISD::isUnsignedIntSetCC(RefOpcode);
assert((IsUnsigned || ISD::isSignedIntSetCC(RefOpcode)) &&
       "Operation neither with signed or unsigned integers.");
``

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8316

possition -> position

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8428

Why std::move? There's nothing in CmpOpInfo that is heap allocated is there?

[iabg-sc]

Minor changes for code readability.

[iabg-sc]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8504

Thanks. It is more clear. Initially enum was used, because there could be fp operations too.

[iabg-sc]

Thanks for the review. Could you please look on this version?

[iabg-sc]

Hi!
Could you please review?

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 #include "llvm/IR/IntrinsicsRISCV.h"
 #include "llvm/IR/PatternMatch.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/KnownBits.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 
+#include <unordered_set>
+
 using namespace llvm;
 
 #define DEBUG_TYPE "riscv-lower"
 
 STATISTIC(NumTailCalls, "Number of tail calls");
 
 RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
                                          const RISCVSubtarget &STI)

 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG) {
   // fold (sub x, (select lhs, rhs, cc, 0, y)) ->
   //      (select lhs, rhs, cc, x, (sub x, y))
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
   return combineSelectAndUse(N, N1, N0, DAG, /*AllOnes*/ false);
 }
 
+// Verifies conditions to apply an optimization.
+// Returns Reference comparison code and three operands A, B, C.
+// Conditions for optimization:
+//   One operand of the compasions has to be common.
+//   This operand is written to C.
+//   Two others operands are differend. They are written to A and B.
+//   Comparisons has to be similar with respect to common operand C.
+//     e.g. A < C; C > B are similar
+//      but A < C; B > C are not.
+//   Reference comparison code is the comparison code if
+//   common operand is right placed.
+//     e.g. C > A will be swapped to A < C.
+static Optional<std::tuple<ISD::CondCode, SDValue, SDValue, SDValue>>
+verifyCompareConds(SDNode *N, SelectionDAG &DAG) {
+  LLVM_DEBUG(
+      dbgs() << "Checking conditions for comparison operation combining.\n";);
+
+  SDValue V0 = N->getOperand(0);
+  SDValue V1 = N->getOperand(1);
+  // Condition 1. Operations have to have same value type.
+  if (V0.getValueType() != V1.getValueType()) {
+    return None;
+  }
+  // Condition 2.1. Operations have to be used only in logic operation.
+  if (!V0.hasOneUse() || !V1.hasOneUse()) {
+    return None;
+  }
+
+  SDNode *N0 = V0.getNode();
+  SDNode *N1 = V1.getNode();
+  // Condition 2.2. Operands have to be comparison operations.
+  if (N0->getOpcode() != ISD::SETCC || N1->getOpcode() != ISD::SETCC) {
+    return None;
+  }
+  // SETCC has three operands: op0, op1, cond. Checks only the first two.
+  // Returns Iterator to condition operand in comparation.
+  auto GetCmpIt = [](SDNode *N) { return N->op_begin() + 2; };
+  // Finds position of the common operand in the first comparison operation.
+  auto CommonOpIt0 = std::find_first_of(N0->op_begin(), GetCmpIt(N0),
+                                        N1->op_begin(), GetCmpIt(N1));
+
+  // Condition 3. Common operand has to be in comparations.
+  if (CommonOpIt0 == GetCmpIt(N0)) {
+    return None;
+  }
+  // Finds common operand for the second comparison operation.
+  auto CommonOpIt1 = std::find(N1->op_begin(), GetCmpIt(N1), *CommonOpIt0);
+  assert(CommonOpIt1 != GetCmpIt(N1) &&
+         "Cannot find common operand in the second comparison operation.");
+
+  // Cast difference_type to int used for the future bit operations.
+  // pair.first is the position of the common operand for the first
+  //  operation(N0).
+  // pair.second is the position of the common operand for the
+  //  second operation(N1).
+  auto CommonPos =
+      std::make_pair<int, int>(std::distance(N0->op_begin(), CommonOpIt0),
+                               std::distance(N1->op_begin(), CommonOpIt1));
+  auto CheckZeroOne = [](std::pair<int, int> P) {
+    return (P.first == 0 || P.first == 1) && (P.second == 0 || P.second == 1);
+  };
+  assert(CheckZeroOne(CommonPos) &&
+         "Position of the operand has to be 0 or 1.");
+
+  // Since Position can be only 0 or 1, inverse positions of the common operand
+  // to get positions of others operands.
+  auto DifferPos =
+      std::make_pair<int, int>(CommonPos.first ^ 1, CommonPos.second ^ 1);
+
+  LLVM_DEBUG(dbgs() << "Shared operands are on positions: " << CommonPos.first
+                    << " and " << CommonPos.second << '\n';);
+  // If common operand at the first position then swap operation to convert to
+  // strict patternt. Common operand has to be right hand side.
+  ISD::CondCode RefCond = cast<CondCodeSDNode>(*GetCmpIt(N0))->get();
+  ISD::CondCode AssistCode = cast<CondCodeSDNode>(*GetCmpIt(N1))->get();
+  if (!CommonPos.first)
+    RefCond = ISD::getSetCCSwappedOperands(RefCond);
+  if (!CommonPos.second)
+    AssistCode = ISD::getSetCCSwappedOperands(AssistCode);
+  LLVM_DEBUG(dbgs() << "Reference condition is: " << RefCond << '\n';);
+  // If there are different comparison operations then do not perform an
+  // optimization. a < c; c < b -> will be changed to b > c.
+  if (RefCond != AssistCode) {
+    return None;
+  }
+
+  SDValue A = N0->getOperand(DifferPos.first);
+  SDValue B = N1->getOperand(DifferPos.second);
+  SDValue C = *CommonOpIt0;
+  // Condition 4. Compare operands has to be the same type.
+  if (A.getValueType() != B.getValueType() ||
+      A.getValueType() != C.getValueType()) {
+    return None;
+  }
+
+  LLVM_DEBUG(
+      dbgs() << "The conditions for comparation combining are satisfied.\n";);
+  return std::make_tuple(RefCond, A, B, C);
+}
+
+enum class OperationType : unsigned { Signed = 0, Unsigned, Float };
+static ISD::NodeType getSelectionCode(OperationType OpT, bool IsAnd,
+                                      bool IsGreaterOp) {
+  // Codes of selection operation. The first index selects signed, unsigned or
+  // float the second index selects MIN/MAX.
+  static constexpr ISD::NodeType SelectionCodes[3][2] = {
+      {ISD::SMIN, ISD::SMAX},
+      {ISD::UMIN, ISD::UMAX},
+      {ISD::FMINNUM, ISD::FMAXNUM}};
+  const bool ChooseSelCode = IsAnd ^ IsGreaterOp;
+  // boolean values will be converted to 0 and 1 and used as indicies in matrix.
+  const unsigned TyIdx = static_cast<unsigned>(OpT);
+  assert(TyIdx < 3 && "Access out of boundaries");
+  return SelectionCodes[TyIdx][ChooseSelCode];
+}
+
+// Checks necessary extensions to perform the combineCmp optimization.
+// Returns false if some extensions are missing.
+static bool checkNecessaryExtensions(SDNode *N,
+                                     const RISCVSubtarget &Subtarget) {
+  // This optimization suitable only with Zbb extension.
+  if (!Subtarget.hasStdExtZbb())
+    return false;
+  // Early calculating type of operand to check necessary extensions.
+  const auto OpEVT = N->getOperand(0).getOperand(0).getValueType();
+  if (OpEVT.isVector())
+    // Do not perform optimization with vectors.
+    return false;
+  const auto OpMVT = OpEVT.getSimpleVT();
+  if (OpMVT == MVT::SimpleValueType::f64 && !Subtarget.hasStdExtD())
+    return false;
+  if (OpMVT == MVT::SimpleValueType::f32 && !Subtarget.hasStdExtF())
+    return false;
+  return true;
+}
+
+// Combines two comparison operation and logic operation to one selection
+// operation(min, max) and logic operation. Returns new constructed Node if
+// conditions for optimization are satisfied.
+static SDValue combineCmpOp(SDNode *N, SelectionDAG &DAG,
+                            const RISCVSubtarget &Subtarget) {
+  if (!checkNecessaryExtensions(N, Subtarget)) {
+    return SDValue();
+  }
+  const auto Props = verifyCompareConds(N, DAG);
+  // If conditions are invalidated then do not perform an optimization.
+  if (!Props) {
+    return SDValue();
+  }
+
+  const auto [RefOpcode, A, B, C] = Props.value();
+  const auto BitOpcode = N->getOpcode();
+  assert((BitOpcode == ISD::AND || BitOpcode == ISD::OR) &&
+         "This optimization can be used only with AND/OR operations");
+  const auto CmpOpVT = A.getValueType();
+
+  // Collection of all Conditions which similar to less.
+  static const std::unordered_set<ISD::CondCode> SetLess = {
+      ISD::SETULT, ISD::SETULE, ISD::SETLT, ISD::SETLE};
+  // Collection of all Conditions which similar to greater.
+  static const std::unordered_set<ISD::CondCode> SetGreater = {
+      ISD::SETUGT, ISD::SETUGE, ISD::SETGT, ISD::SETGE};
+
+  bool IsGreaterOp = SetGreater.count(RefOpcode);
+  if (!IsGreaterOp && !SetLess.count(RefOpcode)) {
+    return SDValue();
+  }
+
+  OperationType TypeOfCmp = OperationType::Signed;
+  if (CmpOpVT.isFloatingPoint())
+    TypeOfCmp = OperationType::Float;
+  else if (ISD::isUnsignedIntSetCC(RefOpcode))
+    TypeOfCmp = OperationType::Unsigned;
+
+  const bool IsAnd = BitOpcode == ISD::AND;
+  const ISD::NodeType PickCode =
+      getSelectionCode(TypeOfCmp, IsAnd, IsGreaterOp);
+
+  SDLoc DL(N);
+  SDValue Pick = DAG.getNode(PickCode, DL, CmpOpVT, A, B);
+  SDValue Cmp =
+      DAG.getSetCC(DL, N->getOperand(0).getValueType(), Pick, C, RefOpcode);
+
+  return Cmp;
+}
+
 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
                                  const RISCVSubtarget &Subtarget) {
   SDValue N0 = N->getOperand(0);
   // Pre-promote (i32 (and (srl X, Y), 1)) on RV64 with Zbs without zero
   // extending X. This is safe since we only need the LSB after the shift and
   // shift amounts larger than 31 would produce poison. If we wait until
   // type legalization, we'll create RISCVISD::SRLW and we can't recover it
   // to use a BEXT instruction.
   if (Subtarget.is64Bit() && Subtarget.hasStdExtZbs() &&
       N->getValueType(0) == MVT::i32 && isOneConstant(N->getOperand(1)) &&
       N0.getOpcode() == ISD::SRL && !isa<ConstantSDNode>(N0.getOperand(1)) &&
       N0.hasOneUse()) {
     SDLoc DL(N);
     SDValue Op0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N0.getOperand(0));
     SDValue Op1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N0.getOperand(1));
     SDValue Srl = DAG.getNode(ISD::SRL, DL, MVT::i64, Op0, Op1);
     SDValue And = DAG.getNode(ISD::AND, DL, MVT::i64, Srl,
                               DAG.getConstant(1, DL, MVT::i64));
     return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, And);
   }
 
+  if (SDValue V = combineCmpOp(N, DAG, Subtarget))
+    return V;
+
   if (SDValue V = combineBinOpToReduce(N, DAG))
     return V;
 
   // fold (and (select lhs, rhs, cc, -1, y), x) ->
   //      (select lhs, rhs, cc, x, (and x, y))
   return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ true);
 }
 
 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
                                 const RISCVSubtarget &Subtarget) {
   if (Subtarget.hasStdExtZbp()) {
     if (auto GREV = combineORToGREV(SDValue(N, 0), DAG, Subtarget))
       return GREV;
     if (auto GORC = combineORToGORC(SDValue(N, 0), DAG, Subtarget))
       return GORC;
     if (auto SHFL = combineORToSHFL(SDValue(N, 0), DAG, Subtarget))
       return SHFL;
   }
 
+  if (SDValue V = combineCmpOp(N, DAG, Subtarget))
+    return V;
+
   if (SDValue V = combineBinOpToReduce(N, DAG))
     return V;
   // fold (or (select cond, 0, y), x) ->
   //      (select cond, x, (or x, y))
   return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false);
 }
 
 static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG) {

llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc  -mtriple=riscv64 -mattr=+zbb -O3 < %s \
+; RUN:  | FileCheck %s --check-prefixes=CHECK,CHECK-RV64I
+; RUN: llc  -mtriple=riscv64 -mattr=+zbb,+f -target-abi=lp64f -O3 < %s \
+; RUN:  | FileCheck %s --check-prefixes=CHECK,CHECK-RV64IF
+; Tests aimed to check oprimization which combines
+; two comparison operations and logic operation into
+; one select(min/max) operation and one comparison
+; operaion.
+
+; 4 patterns bellow will be converted to umin+less.
+define i1 @ulo(i64 %c, i64 %a, i64 %b) {
+; CHECK-LABEL: ulo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    minu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a1, a0
+; CHECK-NEXT:    ret
+  %l0 = icmp ult i64 %a, %c
+  %l1 = icmp ult i64 %b, %c
+  %res = or i1 %l0, %l1
+  ret i1 %res
+}
+
+define i1 @ulo_swap1(i64 %c, i64 %a, i64 %b) {
+; CHECK-LABEL: ulo_swap1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    minu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a1, a0
+; CHECK-NEXT:    ret
+  %l0 = icmp ugt i64 %c, %a
+  %l1 = icmp ult i64 %b, %c
+  %res = or i1 %l0, %l1
+  ret i1 %res
+}
+
+define i1 @ulo_swap2(i64 %c, i64 %a, i64 %b) {
+; CHECK-LABEL: ulo_swap2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    minu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a1, a0
+; CHECK-NEXT:    ret
+  %l0 = icmp ult i64 %a, %c
+  %l1 = icmp ugt i64 %c, %b
+  %res = or i1 %l0, %l1
+  ret i1 %res
+}
+
+define i1 @ulo_swap12(i64 %c, i64 %a, i64 %b) {
+; CHECK-LABEL: ulo_swap12:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    minu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a1, a0
+; CHECK-NEXT:    ret
+  %l0 = icmp ugt i64 %c, %a
+  %l1 = icmp ugt i64 %c, %b
+  %res = or i1 %l0, %l1
+  ret i1 %res
+}
+
+; 4 patterns bellow will be converted to umax+less.
+define i1 @ula(i64 %c, i64 %a, i64 %b) {
+; CHECK-LABEL: ula:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    maxu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a1, a0
+; CHECK-NEXT:    ret
+  %l0 = icmp ult i64 %a, %c
+  %l1 = icmp ult i64 %b, %c
+  %res = and i1 %l0, %l1
+  ret i1 %res
+}
+
+define i1 @ula_swap1(i64 %c, i64 %a, i64 %b) {
+; CHECK-LABEL: ula_swap1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    maxu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a1, a0
+; CHECK-NEXT:    ret
+  %l0 = icmp ugt i64 %c, %a
+  %l1 = icmp ult i64 %b, %c
+  %res = and i1 %l0, %l1
+  ret i1 %res
+}
+
+define i1 @ula_swap2(i64 %c, i64 %a, i64 %b) {
+; CHECK-LABEL: ula_swap2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    maxu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a1, a0
+; CHECK-NEXT:    ret
+  %l0 = icmp ult i64 %a, %c
+  %l1 = icmp ugt i64 %c, %b
+  %res = and i1 %l0, %l1
+  ret i1 %res
+}
+
+define i1 @ula_swap12(i64 %c, i64 %a, i64 %b) {
+; CHECK-LABEL: ula_swap12:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    maxu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a1, a0
+; CHECK-NEXT:    ret
+  %l0 = icmp ugt i64 %c, %a
+  %l1 = icmp ugt i64 %c, %b
+  %res = and i1 %l0, %l1
+  ret i1 %res
+}
+
+; 4 patterns bellow will be converted to umax+greater
+; (greater will be converted to setult somehow)
+define i1 @ugo(i64 %c, i64 %a, i64 %b) {
+; CHECK-LABEL: ugo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    maxu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a0, a1
+; CHECK-NEXT:    ret
+  %l0 = icmp ugt i64 %a, %c
+  %l1 = icmp ugt i64 %b, %c
+  %res = or i1 %l0, %l1
+  ret i1 %res
+}
+
+define i1 @ugo_swap1(i64 %c, i64 %a, i64 %b) {
+; CHECK-LABEL: ugo_swap1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    maxu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a0, a1
+; CHECK-NEXT:    ret
+  %l0 = icmp ult i64 %c, %a
+  %l1 = icmp ugt i64 %b, %c
+  %res = or i1 %l0, %l1
+  ret i1 %res
+}
+
+define i1 @ugo_swap2(i64 %c, i64 %a, i64 %b) {
+; CHECK-LABEL: ugo_swap2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    maxu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a0, a1
+; CHECK-NEXT:    ret
+  %l0 = icmp ugt i64 %a, %c
+  %l1 = icmp ult i64 %c, %b
+  %res = or i1 %l0, %l1
+  ret i1 %res
+}
+
+define i1 @ugo_swap12(i64 %c, i64 %a, i64 %b) {
+; CHECK-LABEL: ugo_swap12:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    maxu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a0, a1
+; CHECK-NEXT:    ret
+  %l0 = icmp ult i64 %c, %a
+  %l1 = icmp ult i64 %c, %b
+  %res = or i1 %l0, %l1
+  ret i1 %res
+}
+
+; Pattern bellow will be converted to umin+greater or equal
+; (greater will be converted to setult somehow)
+define i1 @ugea(i64 %c, i64 %a, i64 %b) {
+; CHECK-LABEL: ugea:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    minu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a1, a0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
+  %l0 = icmp uge i64 %a, %c
+  %l1 = icmp uge i64 %b, %c
+  %res = and i1 %l0, %l1
+  ret i1 %res
+}
+
+; Pattern bellow will be converted to umin+greater
+; (greater will be converted to setult somehow)
+define i1 @uga(i64 %c, i64 %a, i64 %b) {
+; CHECK-LABEL: uga:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    minu a1, a1, a2
+; CHECK-NEXT:    sltu a0, a0, a1
+; CHECK-NEXT:    ret
+  %l0 = icmp ugt i64 %a, %c
+  %l1 = icmp ugt i64 %b, %c
+  %res = and i1 %l0, %l1
+  ret i1 %res
+}
+
+; Patterns bellow will be converted to smax+less.
+; Sign check.
+define i1 @sla(i64 %c, i64 %a, i64 %b) {
+; CHECK-LABEL: sla:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    max a1, a1, a2
+; CHECK-NEXT:    slt a0, a1, a0
+; CHECK-NEXT:    ret
+  %l0 = icmp slt i64 %a, %c
+  %l1 = icmp slt i64 %b, %c
+  %res = and i1 %l0, %l1
+  ret i1 %res
+}
+
+; Patterns bellow will be converted to fmin+less.
+; Float check.
+define i1 @flo(float %c, float %a, float %b) {
+; CHECK-RV64I-LABEL: flo:
+; CHECK-RV64I:       # %bb.0:
+; CHECK-RV64I-NEXT:    addi sp, sp, -32
+; CHECK-RV64I-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; CHECK-RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; CHECK-RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; CHECK-RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
+; CHECK-RV64I-NEXT:    .cfi_offset ra, -8
+; CHECK-RV64I-NEXT:    .cfi_offset s0, -16
+; CHECK-RV64I-NEXT:    .cfi_offset s1, -24
+; CHECK-RV64I-NEXT:    .cfi_offset s2, -32
+; CHECK-RV64I-NEXT:    mv s0, a2
+; CHECK-RV64I-NEXT:    mv s1, a0
+; CHECK-RV64I-NEXT:    mv a0, a1
+; CHECK-RV64I-NEXT:    mv a1, s1
+; CHECK-RV64I-NEXT:    call __gesf2@plt
+; CHECK-RV64I-NEXT:    mv s2, a0
+; CHECK-RV64I-NEXT:    mv a0, s0
+; CHECK-RV64I-NEXT:    mv a1, s1
+; CHECK-RV64I-NEXT:    call __gesf2@plt
+; CHECK-RV64I-NEXT:    or a0, s2, a0
+; CHECK-RV64I-NEXT:    slti a0, a0, 0
+; CHECK-RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; CHECK-RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; CHECK-RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; CHECK-RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
+; CHECK-RV64I-NEXT:    addi sp, sp, 32
+; CHECK-RV64I-NEXT:    ret
+;
+; CHECK-RV64IF-LABEL: flo:
+; CHECK-RV64IF:       # %bb.0:
+; CHECK-RV64IF-NEXT:    fmin.s ft0, fa1, fa2
+; CHECK-RV64IF-NEXT:    fle.s a0, fa0, ft0
+; CHECK-RV64IF-NEXT:    xori a0, a0, 1
+; CHECK-RV64IF-NEXT:    ret
+  %l0 = fcmp ult float %a, %c
+  %l1 = fcmp ult float %b, %c
+  %res = or i1 %l0, %l1
+  ret i1 %res
+}
+
+; Negative test
+; Double check with/without +f extension.
+define i1 @dlo(double %c, double %a, double %b) {
+; CHECK-LABEL: dlo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -32
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -8
+; CHECK-NEXT:    .cfi_offset s0, -16
+; CHECK-NEXT:    .cfi_offset s1, -24
+; CHECK-NEXT:    .cfi_offset s2, -32
+; CHECK-NEXT:    mv s0, a2
+; CHECK-NEXT:    mv s1, a0
+; CHECK-NEXT:    mv a0, a1
+; CHECK-NEXT:    mv a1, s1
+; CHECK-NEXT:    call __gedf2@plt
+; CHECK-NEXT:    mv s2, a0
+; CHECK-NEXT:    mv a0, s0
+; CHECK-NEXT:    mv a1, s1
+; CHECK-NEXT:    call __gedf2@plt
+; CHECK-NEXT:    or a0, s2, a0
+; CHECK-NEXT:    slti a0, a0, 0
+; CHECK-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 32
+; CHECK-NEXT:    ret
+  %l0 = fcmp ult double %a, %c
+  %l1 = fcmp ult double %b, %c
+  %res = or i1 %l0, %l1
+  ret i1 %res
+}
+
+; Negative test
+; More than one user
+define i1 @multi_user(i64 %c, i64 %a, i64 %b) {
+; CHECK-LABEL: multi_user:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sltu a1, a1, a0
+; CHECK-NEXT:    sltu a0, a2, a0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    ret
+  %l0 = icmp ugt i64 %c, %a
+  %l1 = icmp ult i64 %b, %c
+  %res = or i1 %l0, %l1
+
+  %out = and i1 %l0, %res
+  ret i1 %out
+}
+
+; Negative test
+; No same comparations
+define i1 @no_same_ops(i64 %c, i64 %a, i64 %b) {
+; CHECK-LABEL: no_same_ops:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sltu a1, a0, a1
+; CHECK-NEXT:    sltu a0, a2, a0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    ret
+  %l0 = icmp ult i64 %c, %a
+  %l1 = icmp ugt i64 %c, %b
+  %res = or i1 %l0, %l1
+  ret i1 %res
+}
+