[RISCV] Add MC support of RISCV zcmt Extension

[VincentWu]

Summary

This patch add the instructions of zcmt extension.
spac is here
Which includes two instructions (cm.jt&cm.jalt) and a CSR Reg JVT

co-author: @Scott Egerton

[VincentWu]

fix test case

[craig.topper]

llvm/test/MC/RISCV/rv32zcmt-Invalid.s

5 ↗

(On Diff #460266)

Why no invalid test for cm.jalt?

llvm/test/MC/RISCV/rv32zcmt-valid.s

9

What about CHECK-NO-EXT like other tests have?

llvm/test/MC/RISCV/rv64zcmt-Invalid.s

1 ↗

(On Diff #460266)

Why is Invalid capitalized in this test name. It isn't capitalized in other MC tests is it?

1 ↗

(On Diff #460266)

Merge this with the rv32 test.

llvm/test/MC/RISCV/rv64zcmt-valid.s

1 ↗

(On Diff #460266)

Merge this with rv32zcmt-valid.s

[VincentWu]

update & address comments

[reames]

Please add to the review description a link to the appropriate specification. Please update docs/RISCVUsage.rst to add Zcmt, and link to the specification. It's impossible to review e.g. encoding without knowing what you're implementing.

llvm/lib/Target/RISCV/RISCV.td

367

Wait, Zcmt can't be enabled if C is? That seems odd...

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

1 ↗

(On Diff #463097)

We have Zca in RISCVInstrInfoC.td. Not sure it makes sense to have Zcmt in one place, and Zca in another.

Also, did Zca change between 0.7 and 0.7.5? If so, any plans to update that extension?

10 ↗

(On Diff #463097)

It's not just one extension. It is several sub-extensions.

Please reword as "from the Zc* family of code size reduction extensions, version ...

[craig.topper]

llvm/lib/Target/RISCV/RISCV.td

367

I think Zcmt reuses encodings from the FP part of C. That's why C was split into Zca, Zcf, and Zcd.

[craig.topper]

llvm/lib/Target/RISCV/RISCV.td

367

This restriction needs to be enforced in RISCVISAInfo.cpp so that it generates a proper error message.

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

1 ↗

(On Diff #463097)

I think all Zc* should be in RISCVInstrInfoC.td. Zca/Zcf/Zcd already have to be in that file. Might as well put the rest there.

We should mention the Zc* extensions in the header of that file.

llvm/lib/Target/RISCV/RISCVSystemOperands.td

386

This needs an assembler test

[jrtc27]

llvm/lib/Target/RISCV/RISCV.td

366

This is an odd implication, Zcmt works just fine without Zca?

367

Shouldn't the conflict be enforced at a higher level? Otherwise you're silently making +c,+zcmt resolve to +c here.

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

19 ↗

(On Diff #463097)

Blank line

20 ↗

(On Diff #463097)

This should line up?

28 ↗

(On Diff #463097)

I don't think we want this? cm.jt sym isn't a meaningful thing.

llvm/lib/Target/RISCV/RISCVSystemOperands.td

383

Capitalise (and maybe Jump Vector Table, assuming that's what jvt stands for? these headings come from the priv spec but that's woefully outdated for all the new asciidoc extensions...)

[VincentWu]

• update the document
• Throw an error when +c and +zcmt are both specified
• test CSR

llvm/lib/Target/RISCV/RISCV.td

366

the spec says:

The Zcmt extension depends on the Zca and Zicsr extensions.

I think maybe zcmt needs to be aligned using c.nop? That might be one of the reasons why zcmt required zca.

[VincentWu]

update to v1.0

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

135 ↗

(On Diff #497293)

Indent 1 more space

[VincentWu]

rebase

[VincentWu]

address comments

[kito-cheng]

lld/ELF/InputSection.h

404 ↗

(On Diff #510667)

Why we need this change?

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

753

Extension names should be in single quotes.

Should we use 'zcmt' and 'c' extensions are incompatible to match line 863?

[VincentWu]

address comment

[VincentWu]

lld/ELF/InputSection.h

404 ↗

(On Diff #510667)

because zcmt have add a new elf section .riscv.jvt, that extent the size of class InputSection. So we have change it.

but I think it will be better if I move this change to https://reviews.llvm.org/D134600

[kito-cheng]

llvm/lib/Support/RISCVISAInfo.cpp

753

My understanding is Zcmt still compatible with C if no D/Zcd is present.

rv32ic_zcmt in theory is valid combination according to spec[1].

[1] https://github.com/riscv/riscv-code-size-reduction/blob/main/Zc-specification/Zc.adoc#19-zcmt

This extension reuses some encodings from c.fsdsp. Therefore it is incompatible with Zcd, which is included when C and D extensions are both present.

llvm/lib/Target/RISCV/RISCVFeatures.td

354–360 ↗

(On Diff #516043)

I would suggest do not check incompatible stuffs here, let RISCVISAInfo handle that, we already did that for others like Zfinx and F.

[VincentWu]

rebase & address comments

[VincentWu]

paraphrase grammar of error msg

[kito-cheng]

LGTM

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

703

This variable is unused.

751

It wouldn't be incompatible with Zca + D without Zcd would it?

[VincentWu]

address comment

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

753

The ‘or’ in the error message makes it unnecessarily complex for users. Tell them exactly what extensions they used that are in compatible.

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

754

'd' extensions - > 'd' extension

[VincentWu]

address comments

[craig.topper]

LGTM

[jrtc27]

llvm/test/MC/RISCV/rv32zcmt-invalid.s

10

This is wrong; the immediate must be in the range [32, 255]. This needs to be enforced in the assembler and the error needs to reflect that. We also need tests that check these cases (cm.jt with something in [32, 255] and cm.jalt with something in [0, 31]).

clang/test/Preprocessor/riscv-target-features.c

 // CHECK-NOT: __riscv_zknh
 // CHECK-NOT: __riscv_zksh
 // CHECK-NOT: __riscv_zksed
 // CHECK-NOT: __riscv_zkr
 // CHECK-NOT: __riscv_zkt
 // CHECK-NOT: __riscv_zk
 // CHECK-NOT: __riscv_zicbom
 // CHECK-NOT: __riscv_zicboz
+// CHECK-NOT: __riscv_zcmt
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
 // CHECK-M-EXT: __riscv_div 1
 // CHECK-M-EXT: __riscv_m 2000000{{$}}
 // CHECK-M-EXT: __riscv_mul 1

 // RUN: -o - | FileCheck --check-prefix=CHECK-ZICBOZ-EXT %s
 // CHECK-ZICBOZ-EXT: __riscv_zicboz 1000000{{$}}
 
 // RUN: %clang -target riscv32 -march=rv32izicbop -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZICBOP-EXT %s
 // RUN: %clang -target riscv64 -march=rv64izicbop -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZICBOP-EXT %s
 // CHECK-ZICBOP-EXT: __riscv_zicbop 1000000{{$}}
+
+// RUN: %clang -target riscv32 -march=rv32izcmt0p70 -menable-experimental-extensions \
+// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCMT-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izcmt0p70 -menable-experimental-extensions \
+// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCMT-EXT %s
+// CHECK-ZCMT-EXT: __riscv_zca 70000{{$}}
+// CHECK-ZCMT-EXT: __riscv_zcmt 70000{{$}}

llvm/docs/RISCVUsage.rst

+=============================
+User Guide for RISC-V Target
+=============================
+
+.. contents::
+   :local:
+
+Introduction
+============
+
+The RISC-V target provides code generation for processors implementing
+supported variations of the RISC-V specification.  It lives in the
+``llvm/lib/Target/RISCV`` directory.
+
+Base ISAs
+=========
+
+The specification defines four base instruction sets: RV32I, RV32E, RV64I,
+and RV128I. Currently, LLVM fully supports RV32I, and RV64I.  RV32E is
+supported by the assembly-based tools only.  RV128I is not supported.
+
+To specify the target triple:
+
+  .. table:: RISC-V Architectures
+
+     ============ ==============================================================
+     Architecture Description
+     ============ ==============================================================
+     ``riscv32``   RISC-V with XLEN=32 (i.e. RV32I or RV32E)
+     ``riscv64``   RISC-V with XLEN=64 (i.e. RV64I)
+     ============ ==============================================================
+
+To select an E variant ISA (e.g. RV32E instead of RV32I), use the base
+architecture string (e.g. ``riscv32``) with the extension ``e``.
+
+.. _riscv-extensions:
+
+Extensions
+==========
+
+The following table provides a status summary for extensions which have been
+ratified and thus have finalized specifications.  When relevant, detailed notes
+on support follow.
+
+  .. table:: Ratified Extensions by Status
+
+     ===============  =========================================================
+     Extension        Status
+     ===============  =========================================================
+     ``A``            Supported
+     ``C``            Supported
+     ``D``            Supported
+     ``F``            Supported
+     ``M``            Supported
+     ``V``            Supported
+     ``Zba``          Supported
+     ``Zbb``          Supported
+     ``Zbc``          Supported
+     ``Zbkb``         Supported (`See note <#riscv-scalar-crypto-note1>`__)
+     ``Zbkc``         Supported
+     ``Zbkx``         Supported (`See note <#riscv-scalar-crypto-note1>`__)
+     ``Zbs``          Supported
+     ``Zdinx``        Assembly Support
+     ``Zfh``          Supported
+     ``Zfhmin``       Supported
+     ``Zfinx``        Assembly Support
+     ``Zhinx``        Assembly Support
+     ``Zhinxmin``     Assembly Support
+     ``Zicbom``       Assembly Support
+     ``Zicbop``       Assembly Support
+     ``Zicboz``       Assembly Support
+     ``Zihintpause``  Assembly Support
+     ``Zkn``          Supported
+     ``Zknd``         Supported (`See note <#riscv-scalar-crypto-note2>`__)
+     ``Zkne``         Supported (`See note <#riscv-scalar-crypto-note2>`__)
+     ``Zknh``         Supported (`See note <#riscv-scalar-crypto-note2>`__)
+     ``Zksed``        Supported (`See note <#riscv-scalar-crypto-note2>`__)
+     ``Zksh``         Supported (`See note <#riscv-scalar-crypto-note2>`__)
+     ``Zk``           Supported
+     ``Zkr``          Supported
+     ``Zks``          Supported
+     ``Zkt``          Supported
+     ``Zmmul``        Supported
+     ``Zve32x``       (`Partially <#riscv-vlen-32-note>`__) Supported
+     ``Zve32f``       (`Partially <#riscv-vlen-32-note>`__) Supported
+     ``Zve64x``       Supported
+     ``Zve64f``       Supported
+     ``Zve64d``       Supported
+     ``Zvl32b``       (`Partially <#riscv-vlen-32-note>`__) Supported
+     ``Zvl64b``       Supported
+     ``Zvl128b``      Supported
+     ``Zvl256b``      Supported
+     ``Zvl512b``      Supported
+     ``Zvl1024b``     Supported
+     ``Zvl2048b``     Supported
+     ``Zvl4096b``     Supported
+     ``Zvl8192b``     Supported
+     ``Zvl16384b``    Supported
+     ``Zvl32768b``    Supported
+     ``Zvl65536b``    Supported
+     ===============  =========================================================
+
+Assembly Support
+  LLVM supports the associated instructions in assembly.  All assembly related tools (e.g. assembler, disassembler, llvm-objdump, etc..) are supported.  Compiler and linker will accept extension names, and linked binaries will contain appropriate ELF flags and attributes to reflect use of named extension.
+
+Supported
+  Fully supported by the compiler.  This includes everything in Assembly Support, along with - if relevant - C language intrinsics for the instructions and pattern matching by the compiler to recognize idiomatic patterns which can be lowered to the associated instructions.
+
+.. _riscv-scalar-crypto-note1:
+
+``Zbkb``, ``Zbkx``
+  Pattern matching support for these instructions is incomplete.
+
+.. _riscv-scalar-crypto-note2:
+
+``Zknd``, ``Zkne``, ``Zknh``, ``Zksed``, ``Zksh``
+  No pattern matching exists.  As a result, these instructions can only be used from assembler or via intrinsic calls.
+
+.. _riscv-vlen-32-note:
+
+``Zve32x``, ``Zve32f``, ``Zvl32b``
+  LLVM currently assumes a minimum VLEN (vector register width) of 64 bits during compilation, and as a result ``Zve32x`` and ``Zve32f`` are supported only for VLEN>=64.  Assembly support doesn't have this restriction.
+
+Experimental Extensions
+=======================
+
+LLVM supports (to various degrees) a number of experimental extensions.  All experimental extensions have ``experimental-`` as a prefix.  There is explicitly no compatibility promised between versions of the toolchain, and regular users are strongly advised *not* to make use of experimental extensions before they reach ratification.
+
+The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases.  Experimental extensions are expected to either transition to ratified status, or be eventually removed.  The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised.
+
+``experimental-zbe``, ``experimental-zbf``, ``experimental-zbm``, ``experimental-zbp``, ``experimental-zbr``, ``experimental-zbt``
+  LLVM implements the `latest state of the bitmanip working branch <https://github.com/riscv/riscv-bitmanip/tree/main-history>`_, which is largely similar to the 0.93 draft specification but with some instruction naming changes.  These are individual portions of the bitmanip efforts which did *not* get ratified.  Given ratification for these sub-extensions appears stalled; they are a likely candidate for removal in the future.
+
+``experimental-zca``
+  LLVM implements the `0.70 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/V0.70.1-TOOLCHAIN-DEV>`_.
+
+``experimental-zcmt``
+  LLVM implements the `1.0.0-RC5.7 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.0-RC5.7>`_.
+
+``experimental-zihintntl``
+  LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220831-bf5a151>`_.
+
+``experimental-ztso``
+  LLVM implements the `v0.1 proposed specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf>`_ (see Chapter 25).  Using will set appropriate ELF flags and attributes, but does not yet change code generation.
+
+``experimental-zvfh``
+  LLVM implements `this draft text <https://github.com/riscv/riscv-v-spec/pull/780>`_.
+
+To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using.  To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`.  Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.
+
+Specification Documents
+=======================
+For ratified specifications, please refer to the `official RISC-V International
+page <https://riscv.org/technical/specifications/>`_.  Make sure to check the
+`wiki for not yet integrated extensions
+<https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions>`_.
+

llvm/lib/Support/RISCVISAInfo.cpp

static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
 
     {"zbe", RISCVExtensionVersion{0, 93}},
     {"zbf", RISCVExtensionVersion{0, 93}},
     {"zbm", RISCVExtensionVersion{0, 93}},
     {"zbp", RISCVExtensionVersion{0, 93}},
     {"zbr", RISCVExtensionVersion{0, 93}},
     {"zbt", RISCVExtensionVersion{0, 93}},
     {"zca", RISCVExtensionVersion{0, 70}},
+    {"zcmt", RISCVExtensionVersion{0, 70}},
     {"zvfh", RISCVExtensionVersion{0, 1}},
 };
 
 static bool stripExperimentalPrefix(StringRef &Ext) {
   return Ext.consume_front("experimental-");
 }
 
 // This function finds the first character that doesn't belong to a version
if (!isSupportedExtension(Ext)) {
                                Desc.str().c_str(), Ext.str().c_str());
     }
   }
 
   return RISCVISAInfo::postProcessAndChecking(std::move(ISAInfo));
 }
 
 Error RISCVISAInfo::checkDependency() {
   bool IsRv32 = XLen == 32;
+  bool HasC = Exts.count("c") != 0;
   bool HasE = Exts.count("e") != 0;
   bool HasD = Exts.count("d") != 0;
   bool HasF = Exts.count("f") != 0;
   bool HasZfinx = Exts.count("zfinx") != 0;
   bool HasZdinx = Exts.count("zdinx") != 0;
   bool HasVector = Exts.count("zve32x") != 0;
   bool HasZve32f = Exts.count("zve32f") != 0;
   bool HasZve64d = Exts.count("zve64d") != 0;
   bool HasZvl = MinVLen != 0;
+  bool HasZcmt = Exts.count("zcmt") != 0;
 
   if (HasE && !IsRv32)
     return createStringError(
         errc::invalid_argument,
         "standard user-level extension 'e' requires 'rv32'");
 
   // It's illegal to specify the 'd' (double-precision floating point)
   // extension without also specifying the 'f' (single precision
return createStringError(
         "zvfh requires zfh, zfhmin, zhinx or zhinxmin extension to also be "
         "specified");
 
   if (HasZvl && !HasVector)
     return createStringError(
         errc::invalid_argument,
         "zvl*b requires v or zve* extension to also be specified");
 
+  if (HasZcmt && HasC)
+    return createStringError(errc::invalid_argument,
+                             "zcmt is not allowed when c is specified");
+
   // Additional dependency checks.
   // TODO: The 'q' extension requires rv64.
   // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.
 
   return Error::success();
 }
 
 static const char *ImpliedExtsV[] = {"zvl128b", "zve64d", "f", "d"};

 static const char *ImpliedExtsZvl512b[] = {"zvl256b"};
 static const char *ImpliedExtsZvl256b[] = {"zvl128b"};
 static const char *ImpliedExtsZvl128b[] = {"zvl64b"};
 static const char *ImpliedExtsZvl64b[] = {"zvl32b"};
 static const char *ImpliedExtsZk[] = {"zkn", "zkt", "zkr"};
 static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"};
 static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
 static const char *ImpliedExtsZvfh[] = {"zve32f"};
+static const char *ImpliedExtsZcmt[] = {"zca"};
 
 struct ImpliedExtsEntry {
   StringLiteral Name;
   ArrayRef<const char *> Exts;
 
   bool operator<(const ImpliedExtsEntry &Other) const {
     return Name < Other.Name;
   }
 
   bool operator<(StringRef Other) const { return Name < Other; }
 };
 
 // Note: The table needs to be sorted by name.
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
     {{"v"}, {ImpliedExtsV}},
+    {{"zcmt"}, {ImpliedExtsZcmt}},
     {{"zdinx"}, {ImpliedExtsZdinx}},
     {{"zfh"}, {ImpliedExtsZfh}},
     {{"zfhmin"}, {ImpliedExtsZfhmin}},
     {{"zhinx"}, {ImpliedExtsZhinx}},
     {{"zhinxmin"}, {ImpliedExtsZhinxmin}},
     {{"zk"}, {ImpliedExtsZk}},
     {{"zkn"}, {ImpliedExtsZkn}},
     {{"zks"}, {ImpliedExtsZks}},

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

template <unsigned N> bool IsUImm() const {
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     return IsConstantImm && isUInt<N>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
   }
 
   bool isUImm2() { return IsUImm<2>(); }
   bool isUImm3() { return IsUImm<3>(); }
   bool isUImm5() { return IsUImm<5>(); }
   bool isUImm7() { return IsUImm<7>(); }
+  bool isUImm8() { return IsUImm<8>(); }
 
   bool isRnumArg() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
     if (!isImm())
       return false;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     return IsConstantImm && Imm >= INT64_C(0) && Imm <= INT64_C(10) &&
bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidCLUIImm:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, 1, (1 << 5) - 1,
         "immediate must be in [0xfffe0, 0xfffff] or");
   case Match_InvalidUImm7Lsb00:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, 0, (1 << 7) - 4,
         "immediate must be a multiple of 4 bytes in the range");
+  case Match_InvalidUImm8:
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 8) - 1);
   case Match_InvalidUImm8Lsb00:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, 0, (1 << 8) - 4,
         "immediate must be a multiple of 4 bytes in the range");
   case Match_InvalidUImm8Lsb000:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, 0, (1 << 8) - 8,
         "immediate must be a multiple of 8 bytes in the range");

llvm/lib/Target/RISCV/RISCV.td

def HasStdExtZca : Predicate<"Subtarget->hasStdExtZca()">,
                            "'Zca' (part of the C extension, excluding compressed floating point loads/stores)">;
 
 def HasStdExtCOrZca
     : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZca()">,
                 AssemblerPredicate<(any_of FeatureStdExtC, FeatureExtZca),
                                    "'C' (Compressed Instructions) or "
                                    "'Zca' (part of the C extension, excluding compressed floating point loads/stores)">;
 
+def FeatureExtZcmt
+    : SubtargetFeature<"experimental-zcmt", "HasStdExtZcmt", "true",
+                       "'Zcmt' (table jump instuctions for code-size reduction)", 
+                       [FeatureExtZca]>; // TODO: add Zicsr as another dependence
+def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt() && !Subtarget->hasStdExtC()">,
+                           AssemblerPredicate<(all_of FeatureExtZcmt, (not FeatureStdExtC)),
+                           "'Zcmt' (table jump instuctions for code-size reduction)">;
+
 def FeatureNoRVCHints
     : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
                        "Disable RVC Hint Instructions.">;
 def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
                   AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
                                       "RVC Hint Instructions">;
 
 def FeatureStdExtZvl32b : SubtargetFeature<"zvl32b", "ZvlLen", "32",

llvm/lib/Target/RISCV/RISCVInstrInfoC.td

 //===- RISCVInstrInfoC.td - Compressed RISCV instructions -*- tblgen-*-----===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'C', Compressed
+// Instructions extension, and 'Zc*'-1.0.0-RC5.7 family, the code size reduction
+// extensions.
+//
+//===----------------------------------------------------------------------===//
 
 include "RISCVInstrFormatsC.td"
 
 //===----------------------------------------------------------------------===//
 // Operand definitions.
 //===----------------------------------------------------------------------===//
 
 def UImmLog2XLenNonZeroAsmOperand : AsmOperandClass {
def uimm7_lsb00 : Operand<XLenVT>,
   let MCOperandPredicate = [{
     int64_t Imm;
     if (!MCOp.evaluateAsConstantImm(Imm))
       return false;
     return isShiftedUInt<5, 2>(Imm);
   }];
 }
 
+def uimm8 : Operand<XLenVT>,
+            ImmLeaf<XLenVT, [{return isUInt<8>(Imm);}]> {
+  let ParserMatchClass = UImmAsmOperand<8>;
+  let EncoderMethod = "getImmOpValue";
+  let DecoderMethod = "decodeUImmOperand<8>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+  }];
+}
+
 // A 8-bit unsigned immediate where the least significant two bits are zero.
 def uimm8_lsb00 : Operand<XLenVT>,
                   ImmLeaf<XLenVT, [{return isShiftedUInt<6, 2>(Imm);}]> {
   let ParserMatchClass = UImmAsmOperand<8, "Lsb00">;
   let EncoderMethod = "getImmOpValue";
   let DecoderMethod = "decodeUImmOperand<8>";
   let OperandType = "OPERAND_UIMM8_LSB00";
   let OperandNamespace = "RISCVOp";

 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
 def C_UNIMP : RVInst16<(outs), (ins), "c.unimp", "", [], InstFormatOther>,
               Sched<[]> {
   let Inst{15-0} = 0;
 }
 
 } // Predicates = [HasStdExtCOrZca]
 
+let Predicates = [HasStdExtZcmt],
+hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+def CM_JT : RVInst16CJ<0b101, 0b10, (outs), (ins uimm5:$index),
+                      "cm.jt", "$index">{
+  bits<5> index;
+
+  let Inst{12-7} = 0b000000;
+  let Inst{6-2} = index;
+}
+
+def CM_JALT : RVInst16CJ<0b101, 0b10, (outs), (ins uimm8:$index),
+                        "cm.jalt", "$index">{
+  bits<8> index;
+
+  let Inst{12-10} = 0b000;
+  let Inst{9-2} = index;
+}
+} // Predicates = [HasStdExtZcmt]
+
 //===----------------------------------------------------------------------===//
 // HINT Instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtCOrZca, HasRVCHints], hasSideEffects = 0, mayLoad = 0,
     mayStore = 0 in
 {
 

llvm/lib/Target/RISCV/RISCVSchedRocket.td

 // Rocket machine model for scheduling and other instruction cost heuristics.
 def RocketModel : SchedMachineModel {
   let MicroOpBufferSize = 0; // Rocket is in-order.
   let IssueWidth = 1;        // 1 micro-op is dispatched per cycle.
   let LoadLatency = 3;
   let MispredictPenalty = 3;
   let CompleteModel = false;
   let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
-                             HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
-                             HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
-                             HasVInstructions, HasVInstructionsI64];
+                             HasStdExtZcmt, HasStdExtZknd, HasStdExtZkne,
+                             HasStdExtZknh, HasStdExtZksed, HasStdExtZksh,
+                             HasStdExtZkr, HasVInstructions, HasVInstructionsI64];
 }
 
 //===----------------------------------------------------------------------===//
 // Define each kind of processor resource and number available.
 
 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
 // Rocket is in-order.
 

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

 // SiFive7 machine model for scheduling and other instruction cost heuristics.
 def SiFive7Model : SchedMachineModel {
   let MicroOpBufferSize = 0; // Explicitly set to zero since SiFive7 is in-order.
   let IssueWidth = 2;        // 2 micro-ops are dispatched per cycle.
   let LoadLatency = 3;
   let MispredictPenalty = 3;
   let CompleteModel = 0;
   let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
-                             HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
-                             HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
-                             HasVInstructions];
+                             HasStdExtZcmt, HasStdExtZknd, HasStdExtZkne,
+                             HasStdExtZknh, HasStdExtZksed, HasStdExtZksh,
+                             HasStdExtZkr, HasVInstructions];
 }
 
 // The SiFive7 microarchitecture has two pipelines: A and B.
 // Pipe A can handle memory, integer alu and vector operations.
 // Pipe B can handle integer alu, control flow, integer multiply and divide,
 // and floating point computation.
 let SchedModel = SiFive7Model in {
 let BufferSize = 0 in {

llvm/lib/Target/RISCV/RISCVSubtarget.h

private:
   bool HasStdExtZbe = false;
   bool HasStdExtZbf = false;
   bool HasStdExtZbm = false;
   bool HasStdExtZbp = false;
   bool HasStdExtZbr = false;
   bool HasStdExtZbs = false;
   bool HasStdExtZbt = false;
   bool HasStdExtZca = false;
+  bool HasStdExtZcmt = false;
   bool HasStdExtV = false;
   bool HasStdExtZve32x = false;
   bool HasStdExtZve32f = false;
   bool HasStdExtZve64x = false;
   bool HasStdExtZve64f = false;
   bool HasStdExtZve64d = false;
   bool HasStdExtZvfh = false;
   bool HasStdExtZfhmin = false;
public:
   bool hasStdExtZbe() const { return HasStdExtZbe; }
   bool hasStdExtZbf() const { return HasStdExtZbf; }
   bool hasStdExtZbm() const { return HasStdExtZbm; }
   bool hasStdExtZbp() const { return HasStdExtZbp; }
   bool hasStdExtZbr() const { return HasStdExtZbr; }
   bool hasStdExtZbs() const { return HasStdExtZbs; }
   bool hasStdExtZbt() const { return HasStdExtZbt; }
   bool hasStdExtZca() const { return HasStdExtZca; }
+  bool hasStdExtZcmt() const { return HasStdExtZcmt; }
   bool hasStdExtZvl() const { return ZvlLen != 0; }
   bool hasStdExtZvfh() const { return HasStdExtZvfh; }
   bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
   bool hasStdExtZfh() const { return HasStdExtZfh; }
   bool hasStdExtZfinx() const { return HasStdExtZfinx; }
   bool hasStdExtZdinx() const { return HasStdExtZdinx; }
   bool hasStdExtZhinxmin() const { return HasStdExtZhinxmin; }
   bool hasStdExtZhinx() const { return HasStdExtZhinx; }

llvm/lib/Target/RISCV/RISCVSystemOperands.td

foreach i = 0...3 in {
   def : SysReg<"hstateen"#i#"h", !add(0x61C, i)>;
 }
 
 //===-----------------------------------------------
 // Entropy Source CSR
 //===-----------------------------------------------
 
 def SEED : SysReg<"seed", 0x015>;
+
+//===-----------------------------------------------
+// Jump Vector Table CSR
+//===-----------------------------------------------
+
+def : SysReg<"jvt", 0x017>;

llvm/test/CodeGen/RISCV/attributes.ll

 ; RUN: llc -mtriple=riscv32 -mattr=+zkt %s -o - | FileCheck --check-prefix=RV32ZKT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zk %s -o - | FileCheck --check-prefix=RV32ZK %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zkn,+zkr,+zkt %s -o - | FileCheck --check-prefix=RV32COMBINEINTOZK %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o - | FileCheck --check-prefix=RV32COMBINEINTOZKN %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zbkb,+zbkc,+zbkx,+zksed,+zksh %s -o - | FileCheck --check-prefix=RV32COMBINEINTOZKS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV32ZICBOM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV32ZICBOP %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmt %s -o - | FileCheck --check-prefix=RV32ZCMT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefix=RV64MZMMUL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s
 ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zihintpause %s -o - | FileCheck --check-prefix=RV64ZIHINTPAUSE %s

 ; RUN: llc -mtriple=riscv64 -mattr=+zkt %s -o - | FileCheck --check-prefix=RV64ZKT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zk %s -o - | FileCheck --check-prefix=RV64ZK %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zkn,+zkr,+zkt %s -o - | FileCheck --check-prefix=RV64COMBINEINTOZK %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o - | FileCheck --check-prefix=RV64COMBINEINTOZKN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zksed,+zksh %s -o - | FileCheck --check-prefix=RV64COMBINEINTOZKS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmt %s -o - | FileCheck --check-prefix=RV64ZCMT %s
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
 ; RV32ZMMUL: .attribute 5, "rv32i2p0_zmmul1p0"
 ; RV32MZMMUL: .attribute 5, "rv32i2p0_m2p0_zmmul1p0"
 ; RV32A: .attribute 5, "rv32i2p0_a2p0"
 ; RV32F: .attribute 5, "rv32i2p0_f2p0"
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"

 ; RV32ZKT: .attribute 5, "rv32i2p0_zkt1p0"
 ; RV32ZK: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
 ; RV32COMBINEINTOZK: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
 ; RV32COMBINEINTOZKN: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
 ; RV32COMBINEINTOZKS: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
 ; RV32ZICBOM: .attribute 5, "rv32i2p0_zicbom1p0"
 ; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
+; RV32ZCMT: .attribute 5, "rv32i2p0_zca0p70_zcmt0p70"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
 ; RV64MZMMUL: .attribute 5, "rv64i2p0_m2p0_zmmul1p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
 ; RV64F: .attribute 5, "rv64i2p0_f2p0"
 ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
 ; RV64C: .attribute 5, "rv64i2p0_c2p0"

 ; RV64ZKT: .attribute 5, "rv64i2p0_zkt1p0"
 ; RV64ZK: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
 ; RV64COMBINEINTOZK: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
 ; RV64COMBINEINTOZKN: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
 ; RV64COMBINEINTOZKS: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
 ; RV64ZICBOM: .attribute 5, "rv64i2p0_zicbom1p0"
 ; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
+; RV64ZCMT: .attribute 5, "rv64i2p0_zca0p70_zcmt0p70"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
   ret i32 %1
 }

llvm/test/MC/RISCV/attribute-arch.s

 .attribute arch, "rv32iczihintntl0p2"
 # CHECK: attribute      5, "rv32i2p0_c2p0_zihintntl0p2"
 
 .attribute arch, "rv32if_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
 # CHECK: attribute      5, "rv32i2p0_f2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
 
 .attribute arch, "rv32izca0p70"
 # CHECK: attribute      5, "rv32i2p0_zca0p70"
+
+.attribute arch, "rv32izcmt0p70"
+# CHECK: attribute      5, "rv32i2p0_zca0p70_zcmt0p70"

llvm/test/MC/RISCV/rv32zcmt-invalid.s

+# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-zcmt -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-ERROR %s
+# RUN: not llvm-mc -triple=riscv64 -mattr=+experimental-zcmt -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-ERROR %s
+
+# CHECK-ERROR: error: immediate must be an integer in the range [0, 31]
+cm.jt 64
+
+# CHECK-ERROR: error: immediate must be an integer in the range [0, 255]
+cm.jalt 256

llvm/test/MC/RISCV/rv32zcmt-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zcmt\
+# RUN:  -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zcmt\
+# RUN:  -mattr=m < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zcmt\
+# RUN:  -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zcmt\
+# RUN:  -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zcmt\
+# RUN:  -mattr=m < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zcmt\
+# RUN:  -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 \
+# RUN:     -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 \
+# RUN:     -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: cm.jt 1
+# CHECK-ASM: encoding: [0x06,0xa0]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcmt' (table jump instuctions for code-size reduction){{$}}
+cm.jt 1
+
+# CHECK-ASM: cm.jalt 1
+# CHECK-OBJ: cm.jt 1
+# CHECK-ASM: encoding: [0x06,0xa0]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcmt' (table jump instuctions for code-size reduction){{$}}
+cm.jalt 1
+
+# CHECK-ASM-AND-OBJ: cm.jalt 32
+# CHECK-ASM: encoding: [0x82,0xa0]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcmt' (table jump instuctions for code-size reduction){{$}}
+cm.jalt 32

llvm/test/MC/RISCV/rvzcmt-user-csr-name.s

+# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+experimental-zcmt -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zcmt < %s \
+# RUN:     | llvm-objdump -d --mattr=+experimental-zcmt - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+#
+# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -mattr=+experimental-zcmt -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zcmt < %s \
+# RUN:     | llvm-objdump -d --mattr=+experimental-zcmt - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+
+##################################
+# Jump Vector Table CSR
+##################################
+
+# jvt
+# name
+# CHECK-INST: csrrs t1, jvt, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x70,0x01]
+# CHECK-INST-ALIAS: csrr t1, jvt
+# uimm12
+# CHECK-INST: csrrs t2, jvt, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x70,0x01]
+# CHECK-INST-ALIAS: csrr t2, jvt
+# name
+csrrs t1, jvt, zero
+# uimm12
+csrrs t2, 0x017, zero