This is an archive of the discontinued LLVM Phabricator instance.

	Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
	TARGET_BUILTIN(__builtin_riscv_crc32_h, "LiLi", "nc", "experimental-zbr")			TARGET_BUILTIN(__builtin_riscv_crc32_h, "LiLi", "nc", "experimental-zbr")
	TARGET_BUILTIN(__builtin_riscv_crc32_w, "LiLi", "nc", "experimental-zbr")			TARGET_BUILTIN(__builtin_riscv_crc32_w, "LiLi", "nc", "experimental-zbr")
	TARGET_BUILTIN(__builtin_riscv_crc32c_b, "LiLi", "nc", "experimental-zbr")			TARGET_BUILTIN(__builtin_riscv_crc32c_b, "LiLi", "nc", "experimental-zbr")
	TARGET_BUILTIN(__builtin_riscv_crc32c_h, "LiLi", "nc", "experimental-zbr")			TARGET_BUILTIN(__builtin_riscv_crc32c_h, "LiLi", "nc", "experimental-zbr")
	TARGET_BUILTIN(__builtin_riscv_crc32c_w, "LiLi", "nc", "experimental-zbr")			TARGET_BUILTIN(__builtin_riscv_crc32c_w, "LiLi", "nc", "experimental-zbr")
	TARGET_BUILTIN(__builtin_riscv_crc32_d, "LiLi", "nc", "experimental-zbr,64bit")			TARGET_BUILTIN(__builtin_riscv_crc32_d, "LiLi", "nc", "experimental-zbr,64bit")
	TARGET_BUILTIN(__builtin_riscv_crc32c_d, "LiLi", "nc", "experimental-zbr,64bit")			TARGET_BUILTIN(__builtin_riscv_crc32c_d, "LiLi", "nc", "experimental-zbr,64bit")

	// Zbt extension
	TARGET_BUILTIN(__builtin_riscv_fsl_32, "LiLiLiLi", "nc", "experimental-zbt")
	TARGET_BUILTIN(__builtin_riscv_fsr_32, "LiLiLiLi", "nc", "experimental-zbt")
	TARGET_BUILTIN(__builtin_riscv_fsl_64, "WiWiWiWi", "nc", "experimental-zbt,64bit")
	TARGET_BUILTIN(__builtin_riscv_fsr_64, "WiWiWiWi", "nc", "experimental-zbt,64bit")

	// Zbkb extension			// Zbkb extension
	TARGET_BUILTIN(__builtin_riscv_brev8, "LiLi", "nc", "zbkb")			TARGET_BUILTIN(__builtin_riscv_brev8, "LiLi", "nc", "zbkb")
	TARGET_BUILTIN(__builtin_riscv_zip_32, "ZiZi", "nc", "zbkb,32bit")			TARGET_BUILTIN(__builtin_riscv_zip_32, "ZiZi", "nc", "zbkb,32bit")
	TARGET_BUILTIN(__builtin_riscv_unzip_32, "ZiZi", "nc", "zbkb,32bit")			TARGET_BUILTIN(__builtin_riscv_unzip_32, "ZiZi", "nc", "zbkb,32bit")

	// Zknd extension			// Zknd extension
	TARGET_BUILTIN(__builtin_riscv_aes32dsi_32, "ZiZiZiIUc", "nc", "zknd,32bit")			TARGET_BUILTIN(__builtin_riscv_aes32dsi_32, "ZiZiZiIUc", "nc", "zknd,32bit")
	TARGET_BUILTIN(__builtin_riscv_aes32dsmi_32, "ZiZiZiIUc", "nc", "zknd,32bit")			TARGET_BUILTIN(__builtin_riscv_aes32dsmi_32, "ZiZiZiIUc", "nc", "zknd,32bit")
	▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

clang/lib/CodeGen/CGBuiltin.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

//===---- CGBuiltin.cpp - Emit LLVM Code for builtins ---------------------===//		//===---- CGBuiltin.cpp - Emit LLVM Code for builtins ---------------------===//
		Lint: Lint Inline Actions clang-format not found in user’s local PATH; not linting file. Lint: Lint: clang-format not found in user’s local PATH; not linting file.
//		//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.		// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.		// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception		// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//		//
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
//		//
▲ Show 20 Lines • Show All 19,183 Lines • ▼ Show 20 Lines	Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
case RISCV::BI__builtin_riscv_crc32_b:		case RISCV::BI__builtin_riscv_crc32_b:
case RISCV::BI__builtin_riscv_crc32_h:		case RISCV::BI__builtin_riscv_crc32_h:
case RISCV::BI__builtin_riscv_crc32_w:		case RISCV::BI__builtin_riscv_crc32_w:
case RISCV::BI__builtin_riscv_crc32_d:		case RISCV::BI__builtin_riscv_crc32_d:
case RISCV::BI__builtin_riscv_crc32c_b:		case RISCV::BI__builtin_riscv_crc32c_b:
case RISCV::BI__builtin_riscv_crc32c_h:		case RISCV::BI__builtin_riscv_crc32c_h:
case RISCV::BI__builtin_riscv_crc32c_w:		case RISCV::BI__builtin_riscv_crc32c_w:
case RISCV::BI__builtin_riscv_crc32c_d:		case RISCV::BI__builtin_riscv_crc32c_d:
case RISCV::BI__builtin_riscv_fsl_32:
case RISCV::BI__builtin_riscv_fsr_32:
case RISCV::BI__builtin_riscv_fsl_64:
case RISCV::BI__builtin_riscv_fsr_64:
case RISCV::BI__builtin_riscv_brev8:		case RISCV::BI__builtin_riscv_brev8:
case RISCV::BI__builtin_riscv_zip_32:		case RISCV::BI__builtin_riscv_zip_32:
case RISCV::BI__builtin_riscv_unzip_32: {		case RISCV::BI__builtin_riscv_unzip_32: {
switch (BuiltinID) {		switch (BuiltinID) {
default: llvm_unreachable("unexpected builtin ID");		default: llvm_unreachable("unexpected builtin ID");
// Zbb		// Zbb
case RISCV::BI__builtin_riscv_orc_b_32:		case RISCV::BI__builtin_riscv_orc_b_32:
case RISCV::BI__builtin_riscv_orc_b_64:		case RISCV::BI__builtin_riscv_orc_b_64:
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines	case RISCV::BI__builtin_riscv_crc32c_h:
break;		break;
case RISCV::BI__builtin_riscv_crc32c_w:		case RISCV::BI__builtin_riscv_crc32c_w:
ID = Intrinsic::riscv_crc32c_w;		ID = Intrinsic::riscv_crc32c_w;
break;		break;
case RISCV::BI__builtin_riscv_crc32c_d:		case RISCV::BI__builtin_riscv_crc32c_d:
ID = Intrinsic::riscv_crc32c_d;		ID = Intrinsic::riscv_crc32c_d;
break;		break;

// Zbt
case RISCV::BI__builtin_riscv_fsl_32:
case RISCV::BI__builtin_riscv_fsl_64:
ID = Intrinsic::riscv_fsl;
break;
case RISCV::BI__builtin_riscv_fsr_32:
case RISCV::BI__builtin_riscv_fsr_64:
ID = Intrinsic::riscv_fsr;
break;

// Zbkx		// Zbkx
case RISCV::BI__builtin_riscv_xperm8:		case RISCV::BI__builtin_riscv_xperm8:
ID = Intrinsic::riscv_xperm8;		ID = Intrinsic::riscv_xperm8;
break;		break;
case RISCV::BI__builtin_riscv_xperm4:		case RISCV::BI__builtin_riscv_xperm4:
ID = Intrinsic::riscv_xperm4;		ID = Intrinsic::riscv_xperm4;
break;		break;

▲ Show 20 Lines • Show All 134 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbt.c

This file was deleted.

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// RUN: %clang_cc1 -no-opaque-pointers -triple riscv32 -target-feature +experimental-zbt -emit-llvm %s -o - \
	// RUN: \| FileCheck %s -check-prefix=RV32ZBT

	// RV32ZBT-LABEL: @fsl(
	// RV32ZBT-NEXT: entry:
	// RV32ZBT-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
	// RV32ZBT-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
	// RV32ZBT-NEXT: [[RS3_ADDR:%.*]] = alloca i32, align 4
	// RV32ZBT-NEXT: store i32 [[RS1:%.]], i32 [[RS1_ADDR]], align 4
	// RV32ZBT-NEXT: store i32 [[RS2:%.]], i32 [[RS2_ADDR]], align 4
	// RV32ZBT-NEXT: store i32 [[RS3:%.]], i32 [[RS3_ADDR]], align 4
	// RV32ZBT-NEXT: [[TMP0:%.]] = load i32, i32 [[RS1_ADDR]], align 4
	// RV32ZBT-NEXT: [[TMP1:%.]] = load i32, i32 [[RS2_ADDR]], align 4
	// RV32ZBT-NEXT: [[TMP2:%.]] = load i32, i32 [[RS3_ADDR]], align 4
	// RV32ZBT-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.fsl.i32(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
	// RV32ZBT-NEXT: ret i32 [[TMP3]]
	//
	int fsl(int rs1, int rs2, int rs3) {
	return __builtin_riscv_fsl_32(rs1, rs2, rs3);
	}

	// RV32ZBT-LABEL: @fsr(
	// RV32ZBT-NEXT: entry:
	// RV32ZBT-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
	// RV32ZBT-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
	// RV32ZBT-NEXT: [[RS3_ADDR:%.*]] = alloca i32, align 4
	// RV32ZBT-NEXT: store i32 [[RS1:%.]], i32 [[RS1_ADDR]], align 4
	// RV32ZBT-NEXT: store i32 [[RS2:%.]], i32 [[RS2_ADDR]], align 4
	// RV32ZBT-NEXT: store i32 [[RS3:%.]], i32 [[RS3_ADDR]], align 4
	// RV32ZBT-NEXT: [[TMP0:%.]] = load i32, i32 [[RS1_ADDR]], align 4
	// RV32ZBT-NEXT: [[TMP1:%.]] = load i32, i32 [[RS2_ADDR]], align 4
	// RV32ZBT-NEXT: [[TMP2:%.]] = load i32, i32 [[RS3_ADDR]], align 4
	// RV32ZBT-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.fsr.i32(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
	// RV32ZBT-NEXT: ret i32 [[TMP3]]
	//
	int fsr(int rs1, int rs2, int rs3) {
	return __builtin_riscv_fsr_32(rs1, rs2, rs3);
	}

	// RV32ZBT-LABEL: @fsri(
	// RV32ZBT-NEXT: entry:
	// RV32ZBT-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
	// RV32ZBT-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
	// RV32ZBT-NEXT: store i32 [[RS1:%.]], i32 [[RS1_ADDR]], align 4
	// RV32ZBT-NEXT: store i32 [[RS2:%.]], i32 [[RS2_ADDR]], align 4
	// RV32ZBT-NEXT: [[TMP0:%.]] = load i32, i32 [[RS1_ADDR]], align 4
	// RV32ZBT-NEXT: [[TMP1:%.]] = load i32, i32 [[RS2_ADDR]], align 4
	// RV32ZBT-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.fsr.i32(i32 [[TMP0]], i32 [[TMP1]], i32 15)
	// RV32ZBT-NEXT: ret i32 [[TMP2]]
	//
	int fsri(int rs1, int rs2) {
	return __builtin_riscv_fsr_32(rs1, rs2, 15);
	}

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbt.c

This file was deleted.

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// RUN: %clang_cc1 -no-opaque-pointers -triple riscv64 -target-feature +experimental-zbt -emit-llvm %s -o - \
	// RUN: \| FileCheck %s -check-prefix=RV64ZBT

	// RV64ZBT-LABEL: @fsl(
	// RV64ZBT-NEXT: entry:
	// RV64ZBT-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
	// RV64ZBT-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
	// RV64ZBT-NEXT: [[RS3_ADDR:%.*]] = alloca i32, align 4
	// RV64ZBT-NEXT: store i32 [[RS1:%.]], i32 [[RS1_ADDR]], align 4
	// RV64ZBT-NEXT: store i32 [[RS2:%.]], i32 [[RS2_ADDR]], align 4
	// RV64ZBT-NEXT: store i32 [[RS3:%.]], i32 [[RS3_ADDR]], align 4
	// RV64ZBT-NEXT: [[TMP0:%.]] = load i32, i32 [[RS1_ADDR]], align 4
	// RV64ZBT-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64
	// RV64ZBT-NEXT: [[TMP1:%.]] = load i32, i32 [[RS2_ADDR]], align 4
	// RV64ZBT-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64
	// RV64ZBT-NEXT: [[TMP2:%.]] = load i32, i32 [[RS3_ADDR]], align 4
	// RV64ZBT-NEXT: [[CONV2:%.*]] = sext i32 [[TMP2]] to i64
	// RV64ZBT-NEXT: [[TMP3:%.*]] = call i64 @llvm.riscv.fsl.i64(i64 [[CONV]], i64 [[CONV1]], i64 [[CONV2]])
	// RV64ZBT-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP3]] to i32
	// RV64ZBT-NEXT: ret i32 [[CONV3]]
	//
	int fsl(int rs1, int rs2, int rs3) {
	return __builtin_riscv_fsl_32(rs1, rs2, rs3);
	}

	// RV64ZBT-LABEL: @fsr(
	// RV64ZBT-NEXT: entry:
	// RV64ZBT-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
	// RV64ZBT-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
	// RV64ZBT-NEXT: [[RS3_ADDR:%.*]] = alloca i32, align 4
	// RV64ZBT-NEXT: store i32 [[RS1:%.]], i32 [[RS1_ADDR]], align 4
	// RV64ZBT-NEXT: store i32 [[RS2:%.]], i32 [[RS2_ADDR]], align 4
	// RV64ZBT-NEXT: store i32 [[RS3:%.]], i32 [[RS3_ADDR]], align 4
	// RV64ZBT-NEXT: [[TMP0:%.]] = load i32, i32 [[RS1_ADDR]], align 4
	// RV64ZBT-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64
	// RV64ZBT-NEXT: [[TMP1:%.]] = load i32, i32 [[RS2_ADDR]], align 4
	// RV64ZBT-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64
	// RV64ZBT-NEXT: [[TMP2:%.]] = load i32, i32 [[RS3_ADDR]], align 4
	// RV64ZBT-NEXT: [[CONV2:%.*]] = sext i32 [[TMP2]] to i64
	// RV64ZBT-NEXT: [[TMP3:%.*]] = call i64 @llvm.riscv.fsr.i64(i64 [[CONV]], i64 [[CONV1]], i64 [[CONV2]])
	// RV64ZBT-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP3]] to i32
	// RV64ZBT-NEXT: ret i32 [[CONV3]]
	//
	int fsr(int rs1, int rs2, int rs3) {
	return __builtin_riscv_fsr_32(rs1, rs2, rs3);
	}

	// RV64ZBT-LABEL: @fsri(
	// RV64ZBT-NEXT: entry:
	// RV64ZBT-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
	// RV64ZBT-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
	// RV64ZBT-NEXT: store i32 [[RS1:%.]], i32 [[RS1_ADDR]], align 4
	// RV64ZBT-NEXT: store i32 [[RS2:%.]], i32 [[RS2_ADDR]], align 4
	// RV64ZBT-NEXT: [[TMP0:%.]] = load i32, i32 [[RS1_ADDR]], align 4
	// RV64ZBT-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64
	// RV64ZBT-NEXT: [[TMP1:%.]] = load i32, i32 [[RS2_ADDR]], align 4
	// RV64ZBT-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64
	// RV64ZBT-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.fsr.i64(i64 [[CONV]], i64 [[CONV1]], i64 15)
	// RV64ZBT-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
	// RV64ZBT-NEXT: ret i32 [[CONV2]]
	//
	int fsri(int rs1, int rs2) {
	return __builtin_riscv_fsr_32(rs1, rs2, 15);
	}

	// RV64ZBT-LABEL: @fslw(
	// RV64ZBT-NEXT: entry:
	// RV64ZBT-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
	// RV64ZBT-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
	// RV64ZBT-NEXT: [[RS3_ADDR:%.*]] = alloca i64, align 8
	// RV64ZBT-NEXT: store i64 [[RS1:%.]], i64 [[RS1_ADDR]], align 8
	// RV64ZBT-NEXT: store i64 [[RS2:%.]], i64 [[RS2_ADDR]], align 8
	// RV64ZBT-NEXT: store i64 [[RS3:%.]], i64 [[RS3_ADDR]], align 8
	// RV64ZBT-NEXT: [[TMP0:%.]] = load i64, i64 [[RS1_ADDR]], align 8
	// RV64ZBT-NEXT: [[TMP1:%.]] = load i64, i64 [[RS2_ADDR]], align 8
	// RV64ZBT-NEXT: [[TMP2:%.]] = load i64, i64 [[RS3_ADDR]], align 8
	// RV64ZBT-NEXT: [[TMP3:%.*]] = call i64 @llvm.riscv.fsl.i64(i64 [[TMP0]], i64 [[TMP1]], i64 [[TMP2]])
	// RV64ZBT-NEXT: ret i64 [[TMP3]]
	//
	long fslw(long rs1, long rs2, long rs3) {
	return __builtin_riscv_fsl_64(rs1, rs2, rs3);
	}

	// RV64ZBT-LABEL: @fsrw(
	// RV64ZBT-NEXT: entry:
	// RV64ZBT-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
	// RV64ZBT-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
	// RV64ZBT-NEXT: [[RS3_ADDR:%.*]] = alloca i64, align 8
	// RV64ZBT-NEXT: store i64 [[RS1:%.]], i64 [[RS1_ADDR]], align 8
	// RV64ZBT-NEXT: store i64 [[RS2:%.]], i64 [[RS2_ADDR]], align 8
	// RV64ZBT-NEXT: store i64 [[RS3:%.]], i64 [[RS3_ADDR]], align 8
	// RV64ZBT-NEXT: [[TMP0:%.]] = load i64, i64 [[RS1_ADDR]], align 8
	// RV64ZBT-NEXT: [[TMP1:%.]] = load i64, i64 [[RS2_ADDR]], align 8
	// RV64ZBT-NEXT: [[TMP2:%.]] = load i64, i64 [[RS3_ADDR]], align 8
	// RV64ZBT-NEXT: [[TMP3:%.*]] = call i64 @llvm.riscv.fsr.i64(i64 [[TMP0]], i64 [[TMP1]], i64 [[TMP2]])
	// RV64ZBT-NEXT: ret i64 [[TMP3]]
	//
	long fsrw(long rs1, long rs2, long rs3) {
	return __builtin_riscv_fsr_64(rs1, rs2, rs3);
	}

	// RV64ZBT-LABEL: @fsriw(
	// RV64ZBT-NEXT: entry:
	// RV64ZBT-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
	// RV64ZBT-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
	// RV64ZBT-NEXT: store i64 [[RS1:%.]], i64 [[RS1_ADDR]], align 8
	// RV64ZBT-NEXT: store i64 [[RS2:%.]], i64 [[RS2_ADDR]], align 8
	// RV64ZBT-NEXT: [[TMP0:%.]] = load i64, i64 [[RS1_ADDR]], align 8
	// RV64ZBT-NEXT: [[TMP1:%.]] = load i64, i64 [[RS2_ADDR]], align 8
	// RV64ZBT-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.fsr.i64(i64 [[TMP0]], i64 [[TMP1]], i64 15)
	// RV64ZBT-NEXT: ret i64 [[TMP2]]
	//
	long fsriw(long rs1, long rs2) {
	return __builtin_riscv_fsr_64(rs1, rs2, 15);
	}

llvm/docs/RISCVUsage.rst

	Show First 20 Lines • Show All 122 Lines • ▼ Show 20 Lines

	Experimental Extensions			Experimental Extensions
	=======================			=======================

	LLVM supports (to various degrees) a number of experimental extensions. All experimental extensions have ``experimental-`` as a prefix. There is explicitly no compatibility promised between versions of the toolchain, and regular users are strongly advised not to make use of experimental extensions before they reach ratification.			LLVM supports (to various degrees) a number of experimental extensions. All experimental extensions have ``experimental-`` as a prefix. There is explicitly no compatibility promised between versions of the toolchain, and regular users are strongly advised not to make use of experimental extensions before they reach ratification.

	The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases. Experimental extensions are expected to either transition to ratified status, or be eventually removed. The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised.			The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases. Experimental extensions are expected to either transition to ratified status, or be eventually removed. The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised.

	``experimental-zbe``, ``experimental-zbf``, ``experimental-zbm``, ``experimental-zbp``, ``experimental-zbr``, ``experimental-zbt``			``experimental-zbe``, ``experimental-zbf``, ``experimental-zbm``, ``experimental-zbp``, ``experimental-zbr``
	LLVM implements the `latest state of the bitmanip working branch <https://github.com/riscv/riscv-bitmanip/tree/main-history>`_, which is largely similar to the 0.93 draft specification but with some instruction naming changes. These are individual portions of the bitmanip efforts which did not get ratified. Given ratification for these sub-extensions appears stalled; they are a likely candidate for removal in the future.			LLVM implements the `latest state of the bitmanip working branch <https://github.com/riscv/riscv-bitmanip/tree/main-history>`_, which is largely similar to the 0.93 draft specification but with some instruction naming changes. These are individual portions of the bitmanip efforts which did not get ratified. Given ratification for these sub-extensions appears stalled; they are a likely candidate for removal in the future.

	``experimental-zca``			``experimental-zca``
	LLVM implements the `0.70 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/V0.70.1-TOOLCHAIN-DEV>`_.			LLVM implements the `0.70 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/V0.70.1-TOOLCHAIN-DEV>`_.

	``experimental-zihintntl``			``experimental-zihintntl``
	LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220831-bf5a151>`_.			LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220831-bf5a151>`_.

	Show All 15 Lines

llvm/docs/ReleaseNotes.rst

	Show First 20 Lines • Show All 106 Lines • ▼ Show 20 Lines
	Changes to the PowerPC Backend			Changes to the PowerPC Backend
	------------------------------			------------------------------

	* ...			* ...

	Changes to the RISC-V Backend			Changes to the RISC-V Backend
	-----------------------------			-----------------------------

				* Support the unratified Zbt extension has been removed.
				asbUnsubmitted Not Done Reply Inline Actions "Support for the" asb: "Support for the"

	Changes to the WebAssembly Backend			Changes to the WebAssembly Backend
	----------------------------------			----------------------------------

	* ...			* ...

	Changes to the Windows Target			Changes to the Windows Target
	-----------------------------			-----------------------------

	▲ Show 20 Lines • Show All 76 Lines • Show Last 20 Lines

llvm/include/llvm/IR/IntrinsicsRISCV.td

Show First 20 Lines • Show All 123 Lines • ▼ Show 20 Lines	let TargetPrefix = "riscv" in {
def int_riscv_crc32_h : BitManipGPRIntrinsics;		def int_riscv_crc32_h : BitManipGPRIntrinsics;
def int_riscv_crc32_w : BitManipGPRIntrinsics;		def int_riscv_crc32_w : BitManipGPRIntrinsics;
def int_riscv_crc32_d : BitManipGPRIntrinsics;		def int_riscv_crc32_d : BitManipGPRIntrinsics;
def int_riscv_crc32c_b : BitManipGPRIntrinsics;		def int_riscv_crc32c_b : BitManipGPRIntrinsics;
def int_riscv_crc32c_h : BitManipGPRIntrinsics;		def int_riscv_crc32c_h : BitManipGPRIntrinsics;
def int_riscv_crc32c_w : BitManipGPRIntrinsics;		def int_riscv_crc32c_w : BitManipGPRIntrinsics;
def int_riscv_crc32c_d : BitManipGPRIntrinsics;		def int_riscv_crc32c_d : BitManipGPRIntrinsics;

// Zbt
def int_riscv_fsl : BitManipGPRGPRGRIntrinsics;
def int_riscv_fsr : BitManipGPRGPRGRIntrinsics;

// Zbkb		// Zbkb
def int_riscv_brev8 : BitManipGPRIntrinsics;		def int_riscv_brev8 : BitManipGPRIntrinsics;
def int_riscv_zip : BitManipGPRIntrinsics;		def int_riscv_zip : BitManipGPRIntrinsics;
def int_riscv_unzip : BitManipGPRIntrinsics;		def int_riscv_unzip : BitManipGPRIntrinsics;

// Zbkx		// Zbkx
def int_riscv_xperm4 : BitManipGPRGPRIntrinsics;		def int_riscv_xperm4 : BitManipGPRGPRIntrinsics;
def int_riscv_xperm8 : BitManipGPRGPRIntrinsics;		def int_riscv_xperm8 : BitManipGPRGPRIntrinsics;
▲ Show 20 Lines • Show All 1,476 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCV.td

	Show First 20 Lines • Show All 192 Lines • ▼ Show 20 Lines

	def FeatureStdExtZbs			def FeatureStdExtZbs
	: SubtargetFeature<"zbs", "HasStdExtZbs", "true",			: SubtargetFeature<"zbs", "HasStdExtZbs", "true",
	"'Zbs' (Single-Bit Instructions)">;			"'Zbs' (Single-Bit Instructions)">;
	def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,			def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
	AssemblerPredicate<(all_of FeatureStdExtZbs),			AssemblerPredicate<(all_of FeatureStdExtZbs),
	"'Zbs' (Single-Bit Instructions)">;			"'Zbs' (Single-Bit Instructions)">;

	def FeatureStdExtZbt
	: SubtargetFeature<"experimental-zbt", "HasStdExtZbt", "true",
	"'Zbt' (Ternary 'Zb' Instructions)">;
	def HasStdExtZbt : Predicate<"Subtarget->hasStdExtZbt()">,
	AssemblerPredicate<(all_of FeatureStdExtZbt),
	"'Zbt' (Ternary 'Zb' Instructions)">;

	// Some instructions belong to both the basic and the permutation			// Some instructions belong to both the basic and the permutation
	// subextensions. They should be enabled if either has been specified.			// subextensions. They should be enabled if either has been specified.
	def HasStdExtZbbOrZbp			def HasStdExtZbbOrZbp
	: Predicate<"Subtarget->hasStdExtZbb() \|\| Subtarget->hasStdExtZbp()">,			: Predicate<"Subtarget->hasStdExtZbb() \|\| Subtarget->hasStdExtZbp()">,
	AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbp),			AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbp),
	"'Zbb' (Basic Bit-Manipulation) or "			"'Zbb' (Basic Bit-Manipulation) or "
	"'Zbp' (Permutation 'Zb' Instructions)">;			"'Zbp' (Permutation 'Zb' Instructions)">;

	▲ Show 20 Lines • Show All 441 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelLowering.h

//===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------- C++ --===//		//===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------- C++ --===//
		Lint: Lint Inline Actions clang-format not found in user’s local PATH; not linting file. Lint: Lint: clang-format not found in user’s local PATH; not linting file.
//		//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.		// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.		// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception		// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//		//
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
//		//
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines	enum NodeType : unsigned {
// RV64IB rotates, directly matching the semantics of the named RISC-V		// RV64IB rotates, directly matching the semantics of the named RISC-V
// instructions.		// instructions.
ROLW,		ROLW,
RORW,		RORW,
// RV64IZbb bit counting instructions directly matching the semantics of the		// RV64IZbb bit counting instructions directly matching the semantics of the
// named RISC-V instructions.		// named RISC-V instructions.
CLZW,		CLZW,
CTZW,		CTZW,
// RV64IB/RV32IB funnel shifts, with the semantics of the named RISC-V
// instructions. Operand order is rs1, rs3, rs2/shamt.
FSR,
FSL,
// RV64IB funnel shifts, with the semantics of the named RISC-V instructions.
// Operand order is rs1, rs3, rs2/shamt.
FSRW,
FSLW,
// FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as		// FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as
// XLEN is the only legal integer width.		// XLEN is the only legal integer width.
//		//
// FMV_H_X matches the semantics of the FMV.H.X.		// FMV_H_X matches the semantics of the FMV.H.X.
// FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.		// FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.
// FMV_X_SIGNEXTH is similar to FMV.X.H and has a sign-extended result.		// FMV_X_SIGNEXTH is similar to FMV.X.H and has a sign-extended result.
// FMV_W_X_RV64 matches the semantics of the FMV.W.X.		// FMV_W_X_RV64 matches the semantics of the FMV.W.X.
// FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.		// FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
▲ Show 20 Lines • Show All 500 Lines • ▼ Show 20 Lines	public:
MVT getContainerForFixedLengthVector(MVT VT) const;		MVT getContainerForFixedLengthVector(MVT VT) const;

bool shouldRemoveExtendFromGSIndex(EVT IndexVT, EVT DataVT) const override;		bool shouldRemoveExtendFromGSIndex(EVT IndexVT, EVT DataVT) const override;

bool isLegalElementTypeForRVV(Type *ScalarTy) const;		bool isLegalElementTypeForRVV(Type *ScalarTy) const;

bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;		bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;

SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
SmallVectorImpl<SDNode *> &Created) const override;

unsigned getJumpTableEncoding() const override;		unsigned getJumpTableEncoding() const override;

const MCExpr LowerCustomJumpTableEntry(const MachineJumpTableInfo MJTI,		const MCExpr LowerCustomJumpTableEntry(const MachineJumpTableInfo MJTI,
const MachineBasicBlock *MBB,		const MachineBasicBlock *MBB,
unsigned uid,		unsigned uid,
MCContext &Ctx) const override;		MCContext &Ctx) const override;

bool isVScaleKnownToBeAPowerOfTwo() const override;		bool isVScaleKnownToBeAPowerOfTwo() const override;
▲ Show 20 Lines • Show All 155 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

//===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===//		//===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===//
		Lint: Lint Inline Actions clang-format not found in user’s local PATH; not linting file. Lint: Lint: clang-format not found in user’s local PATH; not linting file.
//		//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.		// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.		// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception		// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//		//
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
//		//
▲ Show 20 Lines • Show All 287 Lines • ▼ Show 20 Lines	if (Subtarget.is64Bit())
MVT::i32, Custom);		MVT::i32, Custom);
} else {		} else {
setOperationAction({ISD::CTTZ, ISD::CTLZ, ISD::CTPOP}, XLenVT, Expand);		setOperationAction({ISD::CTTZ, ISD::CTLZ, ISD::CTPOP}, XLenVT, Expand);

if (Subtarget.is64Bit())		if (Subtarget.is64Bit())
setOperationAction(ISD::ABS, MVT::i32, Custom);		setOperationAction(ISD::ABS, MVT::i32, Custom);
}		}

if (Subtarget.hasStdExtZbt()) {
setOperationAction({ISD::FSHL, ISD::FSHR}, XLenVT, Custom);
setOperationAction(ISD::SELECT, XLenVT, Legal);

if (Subtarget.is64Bit())
setOperationAction({ISD::FSHL, ISD::FSHR}, MVT::i32, Custom);
} else {
setOperationAction(ISD::SELECT, XLenVT, Custom);		setOperationAction(ISD::SELECT, XLenVT, Custom);
}

static const unsigned FPLegalNodeTypes[] = {		static const unsigned FPLegalNodeTypes[] = {
ISD::FMINNUM, ISD::FMAXNUM, ISD::LRINT,		ISD::FMINNUM, ISD::FMAXNUM, ISD::LRINT,
ISD::LLRINT, ISD::LROUND, ISD::LLROUND,		ISD::LLRINT, ISD::LROUND, ISD::LLROUND,
ISD::STRICT_LRINT, ISD::STRICT_LLRINT, ISD::STRICT_LROUND,		ISD::STRICT_LRINT, ISD::STRICT_LLRINT, ISD::STRICT_LROUND,
ISD::STRICT_LLROUND, ISD::STRICT_FMA, ISD::STRICT_FADD,		ISD::STRICT_LLROUND, ISD::STRICT_FMA, ISD::STRICT_FADD,
ISD::STRICT_FSUB, ISD::STRICT_FMUL, ISD::STRICT_FDIV,		ISD::STRICT_FSUB, ISD::STRICT_FMUL, ISD::STRICT_FDIV,
ISD::STRICT_FSQRT, ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS};		ISD::STRICT_FSQRT, ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS};
▲ Show 20 Lines • Show All 3,036 Lines • ▼ Show 20 Lines	case ISD::BITREVERSE: {
assert(Op.getOpcode() == ISD::BITREVERSE && "Unexpected opcode");		assert(Op.getOpcode() == ISD::BITREVERSE && "Unexpected opcode");
// Expand bitreverse to a bswap(rev8) followed by brev8.		// Expand bitreverse to a bswap(rev8) followed by brev8.
SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT, Op.getOperand(0));		SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT, Op.getOperand(0));
// We use the Zbp grevi encoding for rev.b/brev8 which will be recognized		// We use the Zbp grevi encoding for rev.b/brev8 which will be recognized
// as brev8 by an isel pattern.		// as brev8 by an isel pattern.
return DAG.getNode(RISCVISD::GREV, DL, VT, BSwap,		return DAG.getNode(RISCVISD::GREV, DL, VT, BSwap,
DAG.getConstant(7, DL, VT));		DAG.getConstant(7, DL, VT));
}		}
case ISD::FSHL:
case ISD::FSHR: {
MVT VT = Op.getSimpleValueType();
assert(VT == Subtarget.getXLenVT() && "Unexpected custom legalization");
SDLoc DL(Op);
// FSL/FSR take a log2(XLen)+1 bit shift amount but XLenVT FSHL/FSHR only
// use log(XLen) bits. Mask the shift amount accordingly to prevent
// accidentally setting the extra bit.
unsigned ShAmtWidth = Subtarget.getXLen() - 1;
SDValue ShAmt = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(2),
DAG.getConstant(ShAmtWidth, DL, VT));
// fshl and fshr concatenate their operands in the same order. fsr and fsl
// instruction use different orders. fshl will return its first operand for
// shift of zero, fshr will return its second operand. fsl and fsr both
// return rs1 so the ISD nodes need to have different operand orders.
// Shift amount is in rs2.
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
unsigned Opc = RISCVISD::FSL;
if (Op.getOpcode() == ISD::FSHR) {
std::swap(Op0, Op1);
Opc = RISCVISD::FSR;
}
return DAG.getNode(Opc, DL, VT, Op0, Op1, ShAmt);
}
case ISD::TRUNCATE:		case ISD::TRUNCATE:
// Only custom-lower vector truncates		// Only custom-lower vector truncates
if (!Op.getSimpleValueType().isVector())		if (!Op.getSimpleValueType().isVector())
return Op;		return Op;
return lowerVectorTruncLike(Op, DAG);		return lowerVectorTruncLike(Op, DAG);
case ISD::ANY_EXTEND:		case ISD::ANY_EXTEND:
case ISD::ZERO_EXTEND:		case ISD::ZERO_EXTEND:
if (Op.getOperand(0).getValueType().isVector() &&		if (Op.getOperand(0).getValueType().isVector() &&
▲ Show 20 Lines • Show All 1,717 Lines • ▼ Show 20 Lines	SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::riscv_bdecompress: {		case Intrinsic::riscv_bdecompress: {
unsigned Opc = IntNo == Intrinsic::riscv_bcompress ? RISCVISD::BCOMPRESS		unsigned Opc = IntNo == Intrinsic::riscv_bcompress ? RISCVISD::BCOMPRESS
: RISCVISD::BDECOMPRESS;		: RISCVISD::BDECOMPRESS;
return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1), Op.getOperand(2));		return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1), Op.getOperand(2));
}		}
case Intrinsic::riscv_bfp:		case Intrinsic::riscv_bfp:
return DAG.getNode(RISCVISD::BFP, DL, XLenVT, Op.getOperand(1),		return DAG.getNode(RISCVISD::BFP, DL, XLenVT, Op.getOperand(1),
Op.getOperand(2));		Op.getOperand(2));
case Intrinsic::riscv_fsl:
return DAG.getNode(RISCVISD::FSL, DL, XLenVT, Op.getOperand(1),
Op.getOperand(2), Op.getOperand(3));
case Intrinsic::riscv_fsr:
return DAG.getNode(RISCVISD::FSR, DL, XLenVT, Op.getOperand(1),
Op.getOperand(2), Op.getOperand(3));
case Intrinsic::riscv_vmv_x_s:		case Intrinsic::riscv_vmv_x_s:
assert(Op.getValueType() == XLenVT && "Unexpected VT!");		assert(Op.getValueType() == XLenVT && "Unexpected VT!");
return DAG.getNode(RISCVISD::VMV_X_S, DL, Op.getValueType(),		return DAG.getNode(RISCVISD::VMV_X_S, DL, Op.getValueType(),
Op.getOperand(1));		Op.getOperand(1));
case Intrinsic::riscv_vmv_v_x:		case Intrinsic::riscv_vmv_v_x:
return lowerScalarSplat(Op.getOperand(1), Op.getOperand(2),		return lowerScalarSplat(Op.getOperand(1), Op.getOperand(2),
Op.getOperand(3), Op.getSimpleValueType(), DL, DAG,		Op.getOperand(3), Op.getSimpleValueType(), DL, DAG,
Subtarget);		Subtarget);
▲ Show 20 Lines • Show All 1,943 Lines • ▼ Show 20 Lines	static RISCVISD::NodeType getRISCVWOpcodeByIntr(unsigned IntNo) {
default:		default:
llvm_unreachable("Unexpected Intrinsic");		llvm_unreachable("Unexpected Intrinsic");
case Intrinsic::riscv_bcompress:		case Intrinsic::riscv_bcompress:
return RISCVISD::BCOMPRESSW;		return RISCVISD::BCOMPRESSW;
case Intrinsic::riscv_bdecompress:		case Intrinsic::riscv_bdecompress:
return RISCVISD::BDECOMPRESSW;		return RISCVISD::BDECOMPRESSW;
case Intrinsic::riscv_bfp:		case Intrinsic::riscv_bfp:
return RISCVISD::BFPW;		return RISCVISD::BFPW;
case Intrinsic::riscv_fsl:
return RISCVISD::FSLW;
case Intrinsic::riscv_fsr:
return RISCVISD::FSRW;
}		}
}		}

// Converts the given intrinsic to a i64 operation with any extension.		// Converts the given intrinsic to a i64 operation with any extension.
static SDValue customLegalizeToWOpByIntr(SDNode *N, SelectionDAG &DAG,		static SDValue customLegalizeToWOpByIntr(SDNode *N, SelectionDAG &DAG,
unsigned IntNo) {		unsigned IntNo) {
SDLoc DL(N);		SDLoc DL(N);
RISCVISD::NodeType WOpcode = getRISCVWOpcodeByIntr(IntNo);		RISCVISD::NodeType WOpcode = getRISCVWOpcodeByIntr(IntNo);
▲ Show 20 Lines • Show All 419 Lines • ▼ Show 20 Lines	if (N->getOpcode() == ISD::BSWAP)
Imm &= ~0x7U;		Imm &= ~0x7U;
SDValue GREVI = DAG.getNode(RISCVISD::GREV, DL, XLenVT, NewOp0,		SDValue GREVI = DAG.getNode(RISCVISD::GREV, DL, XLenVT, NewOp0,
DAG.getConstant(Imm, DL, XLenVT));		DAG.getConstant(Imm, DL, XLenVT));
// ReplaceNodeResults requires we maintain the same type for the return		// ReplaceNodeResults requires we maintain the same type for the return
// value.		// value.
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, GREVI));		Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, GREVI));
break;		break;
}		}
case ISD::FSHL:
case ISD::FSHR: {
assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
Subtarget.hasStdExtZbt() && "Unexpected custom legalisation");
SDValue NewOp0 =
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0));
SDValue NewOp1 =
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
SDValue NewShAmt =
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));
// FSLW/FSRW take a 6 bit shift amount but i32 FSHL/FSHR only use 5 bits.
// Mask the shift amount to 5 bits to prevent accidentally setting bit 5.
NewShAmt = DAG.getNode(ISD::AND, DL, MVT::i64, NewShAmt,
DAG.getConstant(0x1f, DL, MVT::i64));
// fshl and fshr concatenate their operands in the same order. fsrw and fslw
// instruction use different orders. fshl will return its first operand for
// shift of zero, fshr will return its second operand. fsl and fsr both
// return rs1 so the ISD nodes need to have different operand orders.
// Shift amount is in rs2.
unsigned Opc = RISCVISD::FSLW;
if (N->getOpcode() == ISD::FSHR) {
std::swap(NewOp0, NewOp1);
Opc = RISCVISD::FSRW;
}
SDValue NewOp = DAG.getNode(Opc, DL, MVT::i64, NewOp0, NewOp1, NewShAmt);
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewOp));
break;
}
case ISD::EXTRACT_VECTOR_ELT: {		case ISD::EXTRACT_VECTOR_ELT: {
// Custom-legalize an EXTRACT_VECTOR_ELT where XLEN<SEW, as the SEW element		// Custom-legalize an EXTRACT_VECTOR_ELT where XLEN<SEW, as the SEW element
// type is illegal (currently only vXi64 RV32).		// type is illegal (currently only vXi64 RV32).
// With vmv.x.s, when SEW > XLEN, only the least-significant XLEN bits are		// With vmv.x.s, when SEW > XLEN, only the least-significant XLEN bits are
// transferred to the destination register. We issue two of these from the		// transferred to the destination register. We issue two of these from the
// upper- and lower- halves of the SEW-bit vector element, slid down to the		// upper- and lower- halves of the SEW-bit vector element, slid down to the
// first element.		// first element.
SDValue Vec = N->getOperand(0);		SDValue Vec = N->getOperand(0);
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines	case Intrinsic::riscv_gorc: {
Opc = IntNo == Intrinsic::riscv_grev ? RISCVISD::GREV : RISCVISD::GORC;		Opc = IntNo == Intrinsic::riscv_grev ? RISCVISD::GREV : RISCVISD::GORC;
}		}
SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp1, NewOp2);		SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp1, NewOp2);
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));		Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
break;		break;
}		}
case Intrinsic::riscv_bcompress:		case Intrinsic::riscv_bcompress:
case Intrinsic::riscv_bdecompress:		case Intrinsic::riscv_bdecompress:
case Intrinsic::riscv_bfp:		case Intrinsic::riscv_bfp: {
case Intrinsic::riscv_fsl:
case Intrinsic::riscv_fsr: {
assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&		assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
"Unexpected custom legalisation");		"Unexpected custom legalisation");
Results.push_back(customLegalizeToWOpByIntr(N, DAG, IntNo));		Results.push_back(customLegalizeToWOpByIntr(N, DAG, IntNo));
break;		break;
}		}
case Intrinsic::riscv_orc_b: {		case Intrinsic::riscv_orc_b: {
// Lower to the GORCI encoding for orc.b with the operand extended.		// Lower to the GORCI encoding for orc.b with the operand extended.
SDValue NewOp =		SDValue NewOp =
▲ Show 20 Lines • Show All 1,834 Lines • ▼ Show 20 Lines	SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
case RISCVISD::BDECOMPRESSW: {		case RISCVISD::BDECOMPRESSW: {
// Only the lower 32 bits of LHS and RHS are read.		// Only the lower 32 bits of LHS and RHS are read.
if (SimplifyDemandedLowBitsHelper(0, 32) \|\|		if (SimplifyDemandedLowBitsHelper(0, 32) \|\|
SimplifyDemandedLowBitsHelper(1, 32))		SimplifyDemandedLowBitsHelper(1, 32))
return SDValue(N, 0);		return SDValue(N, 0);

break;		break;
}		}
case RISCVISD::FSR:
case RISCVISD::FSL:
case RISCVISD::FSRW:
case RISCVISD::FSLW: {
bool IsWInstruction =
N->getOpcode() == RISCVISD::FSRW \|\| N->getOpcode() == RISCVISD::FSLW;
unsigned BitWidth =
IsWInstruction ? 32 : N->getSimpleValueType(0).getSizeInBits();
assert(isPowerOf2_32(BitWidth) && "Unexpected bit width");
// Only the lower log2(Bitwidth)+1 bits of the the shift amount are read.
if (SimplifyDemandedLowBitsHelper(1, Log2_32(BitWidth) + 1))
return SDValue(N, 0);

break;
}
case RISCVISD::FMV_X_ANYEXTH:		case RISCVISD::FMV_X_ANYEXTH:
case RISCVISD::FMV_X_ANYEXTW_RV64: {		case RISCVISD::FMV_X_ANYEXTW_RV64: {
SDLoc DL(N);		SDLoc DL(N);
SDValue Op0 = N->getOperand(0);		SDValue Op0 = N->getOperand(0);
MVT VT = N->getSimpleValueType(0);		MVT VT = N->getSimpleValueType(0);
// If the input to FMV_X_ANYEXTW_RV64 is just FMV_W_X_RV64 then the		// If the input to FMV_X_ANYEXTW_RV64 is just FMV_W_X_RV64 then the
// conversion is unnecessary and can be replaced with the FMV_W_X_RV64		// conversion is unnecessary and can be replaced with the FMV_W_X_RV64
// operand. Similar for FMV_X_ANYEXTH and FMV_H_X.		// operand. Similar for FMV_X_ANYEXTH and FMV_H_X.
▲ Show 20 Lines • Show All 679 Lines • ▼ Show 20 Lines	unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
case RISCVISD::SRLW:		case RISCVISD::SRLW:
case RISCVISD::DIVW:		case RISCVISD::DIVW:
case RISCVISD::DIVUW:		case RISCVISD::DIVUW:
case RISCVISD::REMUW:		case RISCVISD::REMUW:
case RISCVISD::ROLW:		case RISCVISD::ROLW:
case RISCVISD::RORW:		case RISCVISD::RORW:
case RISCVISD::GREVW:		case RISCVISD::GREVW:
case RISCVISD::GORCW:		case RISCVISD::GORCW:
case RISCVISD::FSLW:
case RISCVISD::FSRW:
case RISCVISD::SHFLW:		case RISCVISD::SHFLW:
case RISCVISD::UNSHFLW:		case RISCVISD::UNSHFLW:
case RISCVISD::BCOMPRESSW:		case RISCVISD::BCOMPRESSW:
case RISCVISD::BDECOMPRESSW:		case RISCVISD::BDECOMPRESSW:
case RISCVISD::BFPW:		case RISCVISD::BFPW:
case RISCVISD::FCVT_W_RV64:		case RISCVISD::FCVT_W_RV64:
case RISCVISD::FCVT_WU_RV64:		case RISCVISD::FCVT_WU_RV64:
case RISCVISD::STRICT_FCVT_W_RV64:		case RISCVISD::STRICT_FCVT_W_RV64:
▲ Show 20 Lines • Show All 2,043 Lines • ▼ Show 20 Lines	#define NODE_NAME_CASE(NODE) \
NODE_NAME_CASE(SRLW)		NODE_NAME_CASE(SRLW)
NODE_NAME_CASE(DIVW)		NODE_NAME_CASE(DIVW)
NODE_NAME_CASE(DIVUW)		NODE_NAME_CASE(DIVUW)
NODE_NAME_CASE(REMUW)		NODE_NAME_CASE(REMUW)
NODE_NAME_CASE(ROLW)		NODE_NAME_CASE(ROLW)
NODE_NAME_CASE(RORW)		NODE_NAME_CASE(RORW)
NODE_NAME_CASE(CLZW)		NODE_NAME_CASE(CLZW)
NODE_NAME_CASE(CTZW)		NODE_NAME_CASE(CTZW)
NODE_NAME_CASE(FSLW)
NODE_NAME_CASE(FSRW)
NODE_NAME_CASE(FSL)
NODE_NAME_CASE(FSR)
NODE_NAME_CASE(FMV_H_X)		NODE_NAME_CASE(FMV_H_X)
NODE_NAME_CASE(FMV_X_ANYEXTH)		NODE_NAME_CASE(FMV_X_ANYEXTH)
NODE_NAME_CASE(FMV_X_SIGNEXTH)		NODE_NAME_CASE(FMV_X_SIGNEXTH)
NODE_NAME_CASE(FMV_W_X_RV64)		NODE_NAME_CASE(FMV_W_X_RV64)
NODE_NAME_CASE(FMV_X_ANYEXTW_RV64)		NODE_NAME_CASE(FMV_X_ANYEXTW_RV64)
NODE_NAME_CASE(FCVT_X)		NODE_NAME_CASE(FCVT_X)
NODE_NAME_CASE(FCVT_XU)		NODE_NAME_CASE(FCVT_XU)
NODE_NAME_CASE(FCVT_W_RV64)		NODE_NAME_CASE(FCVT_W_RV64)
▲ Show 20 Lines • Show All 848 Lines • ▼ Show 20 Lines	if (PartVTBitSize % ValueVTBitSize == 0) {
Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,		Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
DAG.getVectorIdxConstant(0, DL));		DAG.getVectorIdxConstant(0, DL));
return Val;		return Val;
}		}
}		}
return SDValue();		return SDValue();
}		}

SDValue
RISCVTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
SelectionDAG &DAG,
SmallVectorImpl<SDNode *> &Created) const {
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
if (isIntDivCheap(N->getValueType(0), Attr))
return SDValue(N, 0); // Lower SDIV as SDIV

assert((Divisor.isPowerOf2() \|\| Divisor.isNegatedPowerOf2()) &&
"Unexpected divisor!");

// Conditional move is needed, so do the transformation iff Zbt is enabled.
if (!Subtarget.hasStdExtZbt())
return SDValue();

// When \|Divisor\| >= 2 ^ 12, it isn't profitable to do such transformation.
// Besides, more critical path instructions will be generated when dividing
// by 2. So we keep using the original DAGs for these cases.
unsigned Lg2 = Divisor.countTrailingZeros();
if (Lg2 == 1 \|\| Lg2 >= 12)
return SDValue();

// fold (sdiv X, pow2)
EVT VT = N->getValueType(0);
if (VT != MVT::i32 && !(Subtarget.is64Bit() && VT == MVT::i64))
return SDValue();

SDLoc DL(N);
SDValue N0 = N->getOperand(0);
SDValue Zero = DAG.getConstant(0, DL, VT);
SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT);

// Add (N0 < 0) ? Pow2 - 1 : 0;
SDValue Cmp = DAG.getSetCC(DL, VT, N0, Zero, ISD::SETLT);
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
SDValue Sel = DAG.getNode(ISD::SELECT, DL, VT, Cmp, Add, N0);

Created.push_back(Cmp.getNode());
Created.push_back(Add.getNode());
Created.push_back(Sel.getNode());

// Divide by pow2.
SDValue SRA =
DAG.getNode(ISD::SRA, DL, VT, Sel, DAG.getConstant(Lg2, DL, VT));

// If we're dividing by a positive value, we're done. Otherwise, we must
// negate the result.
if (Divisor.isNonNegative())
return SRA;

Created.push_back(SRA.getNode());
return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
}

bool RISCVTargetLowering::isIntDivCheap(EVT VT, AttributeList Attr) const {		bool RISCVTargetLowering::isIntDivCheap(EVT VT, AttributeList Attr) const {
// When aggressively optimizing for code size, we prefer to use a div		// When aggressively optimizing for code size, we prefer to use a div
// instruction, as it is usually smaller than the alternative sequence.		// instruction, as it is usually smaller than the alternative sequence.
// TODO: Add vector division?		// TODO: Add vector division?
bool OptSize = Attr.hasFnAttr(Attribute::MinSize);		bool OptSize = Attr.hasFnAttr(Attribute::MinSize);
return OptSize && !VT.isVector();		return OptSize && !VT.isVector();
}		}

Show All 25 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

Show All 11 Lines
// Zbb - 1.0		// Zbb - 1.0
// Zbc - 1.0		// Zbc - 1.0
// Zbs - 1.0		// Zbs - 1.0
// Zbe - 0.93 *experimental		// Zbe - 0.93 *experimental
// Zbf - 0.93 *experimental		// Zbf - 0.93 *experimental
// Zbm - 0.93 *experimental		// Zbm - 0.93 *experimental
// Zbp - 0.93 *experimental		// Zbp - 0.93 *experimental
// Zbr - 0.93 *experimental		// Zbr - 0.93 *experimental
// Zbt - 0.93 *experimental
//		//
// The experimental extensions appeared in an earlier draft of the Bitmanip		// The experimental extensions appeared in an earlier draft of the Bitmanip
// extensions. They are not ratified and subject to change.		// extensions. They are not ratified and subject to change.
//		//
// This file also describes RISC-V instructions from the Zbk* extensions in		// This file also describes RISC-V instructions from the Zbk* extensions in
// Cryptography Extensions Volume I: Scalar & Entropy Source Instructions,		// Cryptography Extensions Volume I: Scalar & Entropy Source Instructions,
// versions:		// versions:
// Zbkb - 1.0		// Zbkb - 1.0
// Zbkc - 1.0		// Zbkc - 1.0
// Zbkx - 1.0		// Zbkx - 1.0
//		//
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
// Operand and SDNode transformation definitions.		// Operand and SDNode transformation definitions.
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//

def riscv_clzw : SDNode<"RISCVISD::CLZW", SDT_RISCVIntUnaryOpW>;		def riscv_clzw : SDNode<"RISCVISD::CLZW", SDT_RISCVIntUnaryOpW>;
def riscv_ctzw : SDNode<"RISCVISD::CTZW", SDT_RISCVIntUnaryOpW>;		def riscv_ctzw : SDNode<"RISCVISD::CTZW", SDT_RISCVIntUnaryOpW>;
def riscv_rolw : SDNode<"RISCVISD::ROLW", SDT_RISCVIntBinOpW>;		def riscv_rolw : SDNode<"RISCVISD::ROLW", SDT_RISCVIntBinOpW>;
def riscv_rorw : SDNode<"RISCVISD::RORW", SDT_RISCVIntBinOpW>;		def riscv_rorw : SDNode<"RISCVISD::RORW", SDT_RISCVIntBinOpW>;
def riscv_fslw : SDNode<"RISCVISD::FSLW", SDT_RISCVIntShiftDOpW>;
def riscv_fsrw : SDNode<"RISCVISD::FSRW", SDT_RISCVIntShiftDOpW>;
def riscv_fsl : SDNode<"RISCVISD::FSL", SDTIntShiftDOp>;
def riscv_fsr : SDNode<"RISCVISD::FSR", SDTIntShiftDOp>;
def riscv_grev : SDNode<"RISCVISD::GREV", SDTIntBinOp>;		def riscv_grev : SDNode<"RISCVISD::GREV", SDTIntBinOp>;
def riscv_grevw : SDNode<"RISCVISD::GREVW", SDT_RISCVIntBinOpW>;		def riscv_grevw : SDNode<"RISCVISD::GREVW", SDT_RISCVIntBinOpW>;
def riscv_gorc : SDNode<"RISCVISD::GORC", SDTIntBinOp>;		def riscv_gorc : SDNode<"RISCVISD::GORC", SDTIntBinOp>;
def riscv_gorcw : SDNode<"RISCVISD::GORCW", SDT_RISCVIntBinOpW>;		def riscv_gorcw : SDNode<"RISCVISD::GORCW", SDT_RISCVIntBinOpW>;
def riscv_shfl : SDNode<"RISCVISD::SHFL", SDTIntBinOp>;		def riscv_shfl : SDNode<"RISCVISD::SHFL", SDTIntBinOp>;
def riscv_shflw : SDNode<"RISCVISD::SHFLW", SDT_RISCVIntBinOpW>;		def riscv_shflw : SDNode<"RISCVISD::SHFLW", SDT_RISCVIntBinOpW>;
def riscv_unshfl : SDNode<"RISCVISD::UNSHFL", SDTIntBinOp>;		def riscv_unshfl : SDNode<"RISCVISD::UNSHFL", SDTIntBinOp>;
def riscv_unshflw: SDNode<"RISCVISD::UNSHFLW",SDT_RISCVIntBinOpW>;		def riscv_unshflw: SDNode<"RISCVISD::UNSHFLW",SDT_RISCVIntBinOpW>;
▲ Show 20 Lines • Show All 256 Lines • ▼ Show 20 Lines	: RVInstIShiftW<imm11_5, funct3, opcode, (outs GPR:$rd),
"$rd, $rs1, $shamt">;		"$rd, $rs1, $shamt">;

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in		let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class RVBTernaryR<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode,		class RVBTernaryR<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode,
string opcodestr, string argstr>		string opcodestr, string argstr>
: RVInstR4<funct2, funct3, opcode, (outs GPR:$rd),		: RVInstR4<funct2, funct3, opcode, (outs GPR:$rd),
(ins GPR:$rs1, GPR:$rs2, GPR:$rs3), opcodestr, argstr>;		(ins GPR:$rs1, GPR:$rs2, GPR:$rs3), opcodestr, argstr>;

// Currently used by FSRI only
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class RVBTernaryImm6<bits<3> funct3, RISCVOpcode opcode,
string opcodestr, string argstr>
: RVInst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt),
opcodestr, argstr, [], InstFormatR4> {
bits<5> rs3;
bits<6> shamt;
bits<5> rs1;
bits<5> rd;

let Inst{31-27} = rs3;
let Inst{26} = 1;
let Inst{25-20} = shamt;
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
let Opcode = opcode.Value;
}

// Currently used by FSRIW only
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class RVBTernaryImm5<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode,
string opcodestr, string argstr>
: RVInst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs3, uimm5:$shamt),
opcodestr, argstr, [], InstFormatR4> {
bits<5> rs3;
bits<5> shamt;
bits<5> rs1;
bits<5> rd;

let Inst{31-27} = rs3;
let Inst{26-25} = funct2;
let Inst{24-20} = shamt;
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
let Opcode = opcode.Value;
}

//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
// Instructions		// Instructions
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//

let Predicates = [HasStdExtZbbOrZbpOrZbkb] in {		let Predicates = [HasStdExtZbbOrZbpOrZbkb] in {
def ANDN : ALU_rr<0b0100000, 0b111, "andn">,		def ANDN : ALU_rr<0b0100000, 0b111, "andn">,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;		Sched<[WriteIALU, ReadIALU, ReadIALU]>;
def ORN : ALU_rr<0b0100000, 0b110, "orn">,		def ORN : ALU_rr<0b0100000, 0b110, "orn">,
▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
// These instructions were named xperm.n and xperm.b in the last version of		// These instructions were named xperm.n and xperm.b in the last version of
// the draft bit manipulation specification they were included in. However, we		// the draft bit manipulation specification they were included in. However, we
// use the mnemonics given to them in the ratified Zbkx extension.		// use the mnemonics given to them in the ratified Zbkx extension.
let Predicates = [HasStdExtZbpOrZbkx] in {		let Predicates = [HasStdExtZbpOrZbkx] in {
def XPERM4 : ALU_rr<0b0010100, 0b010, "xperm4">, Sched<[]>;		def XPERM4 : ALU_rr<0b0010100, 0b010, "xperm4">, Sched<[]>;
def XPERM8 : ALU_rr<0b0010100, 0b100, "xperm8">, Sched<[]>;		def XPERM8 : ALU_rr<0b0010100, 0b100, "xperm8">, Sched<[]>;
} // Predicates = [HasStdExtZbpOrZbkx]		} // Predicates = [HasStdExtZbpOrZbkx]

let Predicates = [HasStdExtZbt] in {
def CMIX : RVBTernaryR<0b11, 0b001, OPC_OP, "cmix", "$rd, $rs2, $rs1, $rs3">,
Sched<[WriteCMix, ReadCMix, ReadCMix, ReadCMix]>;
def CMOV : RVBTernaryR<0b11, 0b101, OPC_OP, "cmov", "$rd, $rs2, $rs1, $rs3">,
Sched<[WriteCMov, ReadCMov, ReadCMov, ReadCMov]>;
def FSL : RVBTernaryR<0b10, 0b001, OPC_OP, "fsl", "$rd, $rs1, $rs3, $rs2">,
Sched<[WriteFSReg, ReadFSReg, ReadFSReg, ReadFSReg]>;
def FSR : RVBTernaryR<0b10, 0b101, OPC_OP, "fsr", "$rd, $rs1, $rs3, $rs2">,
Sched<[WriteFSReg, ReadFSReg, ReadFSReg, ReadFSReg]>;
def FSRI : RVBTernaryImm6<0b101, OPC_OP_IMM, "fsri",
"$rd, $rs1, $rs3, $shamt">,
Sched<[WriteFSRImm, ReadFSRImm, ReadFSRImm]>;
} // Predicates = [HasStdExtZbt]

let Predicates = [HasStdExtZbt, IsRV64] in {
def FSLW : RVBTernaryR<0b10, 0b001, OPC_OP_32,
"fslw", "$rd, $rs1, $rs3, $rs2">,
Sched<[WriteFSReg32, ReadFSReg32, ReadFSReg32, ReadFSReg32]>;
def FSRW : RVBTernaryR<0b10, 0b101, OPC_OP_32, "fsrw",
"$rd, $rs1, $rs3, $rs2">,
Sched<[WriteFSReg32, ReadFSReg32, ReadFSReg32, ReadFSReg32]>;
def FSRIW : RVBTernaryImm5<0b10, 0b101, OPC_OP_IMM_32,
"fsriw", "$rd, $rs1, $rs3, $shamt">,
Sched<[WriteFSRImm32, ReadFSRImm32, ReadFSRImm32]>;
} // Predicates = [HasStdExtZbt, IsRV64]

let Predicates = [HasStdExtZbb] in {		let Predicates = [HasStdExtZbb] in {
def CLZ : RVBUnary<0b0110000, 0b00000, 0b001, OPC_OP_IMM, "clz">,		def CLZ : RVBUnary<0b0110000, 0b00000, 0b001, OPC_OP_IMM, "clz">,
Sched<[WriteCLZ, ReadCLZ]>;		Sched<[WriteCLZ, ReadCLZ]>;
def CTZ : RVBUnary<0b0110000, 0b00001, 0b001, OPC_OP_IMM, "ctz">,		def CTZ : RVBUnary<0b0110000, 0b00001, 0b001, OPC_OP_IMM, "ctz">,
Sched<[WriteCTZ, ReadCTZ]>;		Sched<[WriteCTZ, ReadCTZ]>;
def CPOP : RVBUnary<0b0110000, 0b00010, 0b001, OPC_OP_IMM, "cpop">,		def CPOP : RVBUnary<0b0110000, 0b00010, 0b001, OPC_OP_IMM, "cpop">,
Sched<[WriteCPOP, ReadCPOP]>;		Sched<[WriteCPOP, ReadCPOP]>;
} // Predicates = [HasStdExtZbb]		} // Predicates = [HasStdExtZbb]
▲ Show 20 Lines • Show All 456 Lines • ▼ Show 20 Lines
def : Pat<(i32 (riscv_grev GPR:$rs1, 24)), (REV8_RV32 GPR:$rs1)>;		def : Pat<(i32 (riscv_grev GPR:$rs1, 24)), (REV8_RV32 GPR:$rs1)>;
} // Predicates = [HasStdExtZbp, IsRV32]		} // Predicates = [HasStdExtZbp, IsRV32]

let Predicates = [HasStdExtZbp, IsRV64] in {		let Predicates = [HasStdExtZbp, IsRV64] in {
// We treat rev8 as a separate instruction, so match it directly.		// We treat rev8 as a separate instruction, so match it directly.
def : Pat<(i64 (riscv_grev GPR:$rs1, 56)), (REV8_RV64 GPR:$rs1)>;		def : Pat<(i64 (riscv_grev GPR:$rs1, 56)), (REV8_RV64 GPR:$rs1)>;
} // Predicates = [HasStdExtZbp, IsRV64]		} // Predicates = [HasStdExtZbp, IsRV64]

let Predicates = [HasStdExtZbt] in {
def : Pat<(or (and (not GPR:$rs2), GPR:$rs3), (and GPR:$rs2, GPR:$rs1)),
(CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
def : Pat<(xor (and (xor GPR:$rs1, GPR:$rs3), GPR:$rs2), GPR:$rs3),
(CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>;

def : Pat<(select (XLenVT (setne GPR:$rs2, 0)), GPR:$rs1, GPR:$rs3),
(CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
def : Pat<(select (XLenVT (seteq GPR:$rs2, 0)), GPR:$rs3, GPR:$rs1),
(CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
def : Pat<(select (XLenVT (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1, GPR:$rs3),
(CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
def : Pat<(select (XLenVT (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs3, GPR:$rs1),
(CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
def : Pat<(select (XLenVT (setne GPR:$x, GPR:$y)), GPR:$rs1, GPR:$rs3),
(CMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
def : Pat<(select (XLenVT (seteq GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
(CMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;

def : Pat<(select GPR:$rs2, GPR:$rs1, GPR:$rs3),
(CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
} // Predicates = [HasStdExtZbt]

let Predicates = [HasStdExtZbt] in {
def : Pat<(riscv_fsl GPR:$rs1, GPR:$rs3, GPR:$rs2),
(FSL GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
def : Pat<(riscv_fsr GPR:$rs1, GPR:$rs3, GPR:$rs2),
(FSR GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
def : Pat<(riscv_fsr GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt),
(FSRI GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt)>;
// We can use FSRI for FSL by immediate if we subtract the immediate from
// XLen and swap the operands.
def : Pat<(riscv_fsl GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt),
(FSRI GPR:$rs1, GPR:$rs3, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
} // Predicates = [HasStdExtZbt]

let Predicates = [HasStdExtZbt, IsRV64] in {
def : Pat<(riscv_fslw GPR:$rs1, GPR:$rs3, GPR:$rs2),
(FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
def : Pat<(riscv_fsrw GPR:$rs1, GPR:$rs3, GPR:$rs2),
(FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
def : Pat<(riscv_fsrw GPR:$rs1, GPR:$rs3, uimm5:$shamt),
(FSRIW GPR:$rs1, GPR:$rs3, uimm5:$shamt)>;
// We can use FSRIW for FSLW by immediate if we subtract the immediate from
// 32 and swap the operands.
def : Pat<(riscv_fslw GPR:$rs3, GPR:$rs1, uimm5:$shamt),
(FSRIW GPR:$rs1, GPR:$rs3, (ImmSubFrom32 uimm5:$shamt))>;
} // Predicates = [HasStdExtZbt, IsRV64]

let Predicates = [HasStdExtZbb] in {		let Predicates = [HasStdExtZbb] in {
def : PatGpr<ctlz, CLZ>;		def : PatGpr<ctlz, CLZ>;
def : PatGpr<cttz, CTZ>;		def : PatGpr<cttz, CTZ>;
def : PatGpr<ctpop, CPOP>;		def : PatGpr<ctpop, CPOP>;
} // Predicates = [HasStdExtZbb]		} // Predicates = [HasStdExtZbb]

let Predicates = [HasStdExtZbb, IsRV64] in {		let Predicates = [HasStdExtZbb, IsRV64] in {
def : PatGpr<riscv_clzw, CLZW>;		def : PatGpr<riscv_clzw, CLZW>;
▲ Show 20 Lines • Show All 233 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVSchedRocket.td

	Show First 20 Lines • Show All 242 Lines • ▼ Show 20 Lines
	defm : UnsupportedSchedZbb;			defm : UnsupportedSchedZbb;
	defm : UnsupportedSchedZbc;			defm : UnsupportedSchedZbc;
	defm : UnsupportedSchedZbs;			defm : UnsupportedSchedZbs;
	defm : UnsupportedSchedZbe;			defm : UnsupportedSchedZbe;
	defm : UnsupportedSchedZbf;			defm : UnsupportedSchedZbf;
	defm : UnsupportedSchedZbm;			defm : UnsupportedSchedZbm;
	defm : UnsupportedSchedZbp;			defm : UnsupportedSchedZbp;
	defm : UnsupportedSchedZbr;			defm : UnsupportedSchedZbr;
	defm : UnsupportedSchedZbt;
	defm : UnsupportedSchedZfh;			defm : UnsupportedSchedZfh;
	}			}

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

	Show First 20 Lines • Show All 229 Lines • ▼ Show 20 Lines
	defm : UnsupportedSchedZbb;			defm : UnsupportedSchedZbb;
	defm : UnsupportedSchedZbc;			defm : UnsupportedSchedZbc;
	defm : UnsupportedSchedZbs;			defm : UnsupportedSchedZbs;
	defm : UnsupportedSchedZbe;			defm : UnsupportedSchedZbe;
	defm : UnsupportedSchedZbf;			defm : UnsupportedSchedZbf;
	defm : UnsupportedSchedZbm;			defm : UnsupportedSchedZbm;
	defm : UnsupportedSchedZbp;			defm : UnsupportedSchedZbp;
	defm : UnsupportedSchedZbr;			defm : UnsupportedSchedZbr;
	defm : UnsupportedSchedZbt;
	defm : UnsupportedSchedZfh;			defm : UnsupportedSchedZfh;
	}			}

llvm/lib/Target/RISCV/RISCVScheduleB.td

	Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
	def WriteCRCH : SchedWrite; // crc32.h			def WriteCRCH : SchedWrite; // crc32.h
	def WriteCRCW : SchedWrite; // crc32.w			def WriteCRCW : SchedWrite; // crc32.w
	def WriteCRCD : SchedWrite; // crc32.d			def WriteCRCD : SchedWrite; // crc32.d
	def WriteCRCCB : SchedWrite; // crc32c.b			def WriteCRCCB : SchedWrite; // crc32c.b
	def WriteCRCCH : SchedWrite; // crc32c.h			def WriteCRCCH : SchedWrite; // crc32c.h
	def WriteCRCCW : SchedWrite; // crc32c.w			def WriteCRCCW : SchedWrite; // crc32c.w
	def WriteCRCCD : SchedWrite; // crc32c.d			def WriteCRCCD : SchedWrite; // crc32c.d

	// Zbt extension
	def WriteCMix : SchedWrite; // cmix
	def WriteCMov : SchedWrite; // cmov
	def WriteFSReg : SchedWrite; // fsl/fsr
	def WriteFSRImm : SchedWrite; // fsri
	def WriteFSReg32 : SchedWrite; // fslw/fsrw
	def WriteFSRImm32 : SchedWrite; // fsriw

	/// Define scheduler resources associated with use operands.			/// Define scheduler resources associated with use operands.

	// Zba extension			// Zba extension
	def ReadSHXADD : SchedRead; // sh1add/sh2add/sh3add			def ReadSHXADD : SchedRead; // sh1add/sh2add/sh3add
	def ReadSHXADD32 : SchedRead; // sh1add.uw/sh2add.uw/sh3add.uw			def ReadSHXADD32 : SchedRead; // sh1add.uw/sh2add.uw/sh3add.uw

	// Zbb extension			// Zbb extension
	def ReadRotateImm : SchedRead;			def ReadRotateImm : SchedRead;
	▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
	def ReadCRCH : SchedRead; // crc32.h			def ReadCRCH : SchedRead; // crc32.h
	def ReadCRCW : SchedRead; // crc32.w			def ReadCRCW : SchedRead; // crc32.w
	def ReadCRCD : SchedRead; // crc32.d			def ReadCRCD : SchedRead; // crc32.d
	def ReadCRCCB : SchedRead; // crc32c.b			def ReadCRCCB : SchedRead; // crc32c.b
	def ReadCRCCH : SchedRead; // crc32c.h			def ReadCRCCH : SchedRead; // crc32c.h
	def ReadCRCCW : SchedRead; // crc32c.w			def ReadCRCCW : SchedRead; // crc32c.w
	def ReadCRCCD : SchedRead; // crc32c.d			def ReadCRCCD : SchedRead; // crc32c.d

	// Zbt extension
	def ReadCMix : SchedRead; // cmix
	def ReadCMov : SchedRead; // cmov
	def ReadFSReg : SchedRead; // fsl/fsr
	def ReadFSRImm : SchedRead; // fsri
	def ReadFSReg32 : SchedRead; // fslw/fsrw
	def ReadFSRImm32 : SchedRead; // fsriw

	/// Define default scheduler resources for B.			/// Define default scheduler resources for B.

	multiclass UnsupportedSchedZba {			multiclass UnsupportedSchedZba {
	let Unsupported = true in {			let Unsupported = true in {
	def : WriteRes<WriteSHXADD, []>;			def : WriteRes<WriteSHXADD, []>;
	def : WriteRes<WriteSHXADD32, []>;			def : WriteRes<WriteSHXADD32, []>;

	def : ReadAdvance<ReadSHXADD, 0>;			def : ReadAdvance<ReadSHXADD, 0>;
	▲ Show 20 Lines • Show All 143 Lines • ▼ Show 20 Lines
	def : ReadAdvance<ReadCRCW, 0>;			def : ReadAdvance<ReadCRCW, 0>;
	def : ReadAdvance<ReadCRCD, 0>;			def : ReadAdvance<ReadCRCD, 0>;
	def : ReadAdvance<ReadCRCCB, 0>;			def : ReadAdvance<ReadCRCCB, 0>;
	def : ReadAdvance<ReadCRCCH, 0>;			def : ReadAdvance<ReadCRCCH, 0>;
	def : ReadAdvance<ReadCRCCW, 0>;			def : ReadAdvance<ReadCRCCW, 0>;
	def : ReadAdvance<ReadCRCCD, 0>;			def : ReadAdvance<ReadCRCCD, 0>;
	}			}
	}			}

	multiclass UnsupportedSchedZbt {
	let Unsupported = true in {
	def : WriteRes<WriteCMix, []>;
	def : WriteRes<WriteCMov, []>;
	def : WriteRes<WriteFSReg, []>;
	def : WriteRes<WriteFSRImm, []>;
	def : WriteRes<WriteFSReg32, []>;
	def : WriteRes<WriteFSRImm32, []>;

	def : ReadAdvance<ReadCMix, 0>;
	def : ReadAdvance<ReadCMov, 0>;
	def : ReadAdvance<ReadFSReg, 0>;
	def : ReadAdvance<ReadFSRImm, 0>;
	def : ReadAdvance<ReadFSReg32, 0>;
	def : ReadAdvance<ReadFSRImm32, 0>;
	}
	}

llvm/lib/Target/RISCV/RISCVSubtarget.h

//===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------- C++ --===//		//===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------- C++ --===//
		Lint: Lint Inline Actions clang-format not found in user’s local PATH; not linting file. Lint: Lint: clang-format not found in user’s local PATH; not linting file.
//		//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.		// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.		// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception		// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//		//
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
//		//
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines	private:
bool HasStdExtZbb = false;		bool HasStdExtZbb = false;
bool HasStdExtZbc = false;		bool HasStdExtZbc = false;
bool HasStdExtZbe = false;		bool HasStdExtZbe = false;
bool HasStdExtZbf = false;		bool HasStdExtZbf = false;
bool HasStdExtZbm = false;		bool HasStdExtZbm = false;
bool HasStdExtZbp = false;		bool HasStdExtZbp = false;
bool HasStdExtZbr = false;		bool HasStdExtZbr = false;
bool HasStdExtZbs = false;		bool HasStdExtZbs = false;
bool HasStdExtZbt = false;
bool HasStdExtZca = false;		bool HasStdExtZca = false;
bool HasStdExtV = false;		bool HasStdExtV = false;
bool HasStdExtZve32x = false;		bool HasStdExtZve32x = false;
bool HasStdExtZve32f = false;		bool HasStdExtZve32f = false;
bool HasStdExtZve64x = false;		bool HasStdExtZve64x = false;
bool HasStdExtZve64f = false;		bool HasStdExtZve64f = false;
bool HasStdExtZve64d = false;		bool HasStdExtZve64d = false;
bool HasStdExtZvfh = false;		bool HasStdExtZvfh = false;
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines	public:
bool hasStdExtZbb() const { return HasStdExtZbb; }		bool hasStdExtZbb() const { return HasStdExtZbb; }
bool hasStdExtZbc() const { return HasStdExtZbc; }		bool hasStdExtZbc() const { return HasStdExtZbc; }
bool hasStdExtZbe() const { return HasStdExtZbe; }		bool hasStdExtZbe() const { return HasStdExtZbe; }
bool hasStdExtZbf() const { return HasStdExtZbf; }		bool hasStdExtZbf() const { return HasStdExtZbf; }
bool hasStdExtZbm() const { return HasStdExtZbm; }		bool hasStdExtZbm() const { return HasStdExtZbm; }
bool hasStdExtZbp() const { return HasStdExtZbp; }		bool hasStdExtZbp() const { return HasStdExtZbp; }
bool hasStdExtZbr() const { return HasStdExtZbr; }		bool hasStdExtZbr() const { return HasStdExtZbr; }
bool hasStdExtZbs() const { return HasStdExtZbs; }		bool hasStdExtZbs() const { return HasStdExtZbs; }
bool hasStdExtZbt() const { return HasStdExtZbt; }
bool hasStdExtZca() const { return HasStdExtZca; }		bool hasStdExtZca() const { return HasStdExtZca; }
bool hasStdExtZvl() const { return ZvlLen != 0; }		bool hasStdExtZvl() const { return ZvlLen != 0; }
bool hasStdExtZvfh() const { return HasStdExtZvfh; }		bool hasStdExtZvfh() const { return HasStdExtZvfh; }
bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }		bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
bool hasStdExtZfh() const { return HasStdExtZfh; }		bool hasStdExtZfh() const { return HasStdExtZfh; }
bool hasStdExtZfinx() const { return HasStdExtZfinx; }		bool hasStdExtZfinx() const { return HasStdExtZfinx; }
bool hasStdExtZdinx() const { return HasStdExtZdinx; }		bool hasStdExtZdinx() const { return HasStdExtZdinx; }
bool hasStdExtZhinxmin() const { return HasStdExtZhinxmin; }		bool hasStdExtZhinxmin() const { return HasStdExtZhinxmin; }
▲ Show 20 Lines • Show All 111 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/attributes.ll

	Show All 14 Lines
	; RUN: llc -mtriple=riscv32 -mattr=+zbb %s -o - \| FileCheck --check-prefix=RV32ZBB %s			; RUN: llc -mtriple=riscv32 -mattr=+zbb %s -o - \| FileCheck --check-prefix=RV32ZBB %s
	; RUN: llc -mtriple=riscv32 -mattr=+zbc %s -o - \| FileCheck --check-prefix=RV32ZBC %s			; RUN: llc -mtriple=riscv32 -mattr=+zbc %s -o - \| FileCheck --check-prefix=RV32ZBC %s
	; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe %s -o - \| FileCheck --check-prefix=RV32ZBE %s			; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe %s -o - \| FileCheck --check-prefix=RV32ZBE %s
	; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbf %s -o - \| FileCheck --check-prefix=RV32ZBF %s			; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbf %s -o - \| FileCheck --check-prefix=RV32ZBF %s
	; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbm %s -o - \| FileCheck --check-prefix=RV32ZBM %s			; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbm %s -o - \| FileCheck --check-prefix=RV32ZBM %s
	; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp %s -o - \| FileCheck --check-prefix=RV32ZBP %s			; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp %s -o - \| FileCheck --check-prefix=RV32ZBP %s
	; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - \| FileCheck --check-prefix=RV32ZBR %s			; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - \| FileCheck --check-prefix=RV32ZBR %s
	; RUN: llc -mtriple=riscv32 -mattr=+zbs %s -o - \| FileCheck --check-prefix=RV32ZBS %s			; RUN: llc -mtriple=riscv32 -mattr=+zbs %s -o - \| FileCheck --check-prefix=RV32ZBS %s
	; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - \| FileCheck --check-prefix=RV32ZBT %s
	; RUN: llc -mtriple=riscv32 -mattr=+v %s -o - \| FileCheck --check-prefix=RV32V %s			; RUN: llc -mtriple=riscv32 -mattr=+v %s -o - \| FileCheck --check-prefix=RV32V %s
	; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zfh,+v,+f %s -o - \| FileCheck --check-prefix=RV32COMBINED %s			; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zfh,+v,+f %s -o - \| FileCheck --check-prefix=RV32COMBINED %s
	; RUN: llc -mtriple=riscv32 -mattr=+zbkb %s -o - \| FileCheck --check-prefix=RV32ZBKB %s			; RUN: llc -mtriple=riscv32 -mattr=+zbkb %s -o - \| FileCheck --check-prefix=RV32ZBKB %s
	; RUN: llc -mtriple=riscv32 -mattr=+zbkc %s -o - \| FileCheck --check-prefix=RV32ZBKC %s			; RUN: llc -mtriple=riscv32 -mattr=+zbkc %s -o - \| FileCheck --check-prefix=RV32ZBKC %s
	; RUN: llc -mtriple=riscv32 -mattr=+zbkx %s -o - \| FileCheck --check-prefix=RV32ZBKX %s			; RUN: llc -mtriple=riscv32 -mattr=+zbkx %s -o - \| FileCheck --check-prefix=RV32ZBKX %s
	; RUN: llc -mtriple=riscv32 -mattr=+zknd %s -o - \| FileCheck --check-prefix=RV32ZKND %s			; RUN: llc -mtriple=riscv32 -mattr=+zknd %s -o - \| FileCheck --check-prefix=RV32ZKND %s
	; RUN: llc -mtriple=riscv32 -mattr=+zkne %s -o - \| FileCheck --check-prefix=RV32ZKNE %s			; RUN: llc -mtriple=riscv32 -mattr=+zkne %s -o - \| FileCheck --check-prefix=RV32ZKNE %s
	; RUN: llc -mtriple=riscv32 -mattr=+zknh %s -o - \| FileCheck --check-prefix=RV32ZKNH %s			; RUN: llc -mtriple=riscv32 -mattr=+zknh %s -o - \| FileCheck --check-prefix=RV32ZKNH %s
	Show All 25 Lines
	; RUN: llc -mtriple=riscv64 -mattr=+zbb %s -o - \| FileCheck --check-prefix=RV64ZBB %s			; RUN: llc -mtriple=riscv64 -mattr=+zbb %s -o - \| FileCheck --check-prefix=RV64ZBB %s
	; RUN: llc -mtriple=riscv64 -mattr=+zbc %s -o - \| FileCheck --check-prefix=RV64ZBC %s			; RUN: llc -mtriple=riscv64 -mattr=+zbc %s -o - \| FileCheck --check-prefix=RV64ZBC %s
	; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe %s -o - \| FileCheck --check-prefix=RV64ZBE %s			; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe %s -o - \| FileCheck --check-prefix=RV64ZBE %s
	; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbf %s -o - \| FileCheck --check-prefix=RV64ZBF %s			; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbf %s -o - \| FileCheck --check-prefix=RV64ZBF %s
	; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbm %s -o - \| FileCheck --check-prefix=RV64ZBM %s			; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbm %s -o - \| FileCheck --check-prefix=RV64ZBM %s
	; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp %s -o - \| FileCheck --check-prefix=RV64ZBP %s			; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp %s -o - \| FileCheck --check-prefix=RV64ZBP %s
	; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - \| FileCheck --check-prefix=RV64ZBR %s			; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - \| FileCheck --check-prefix=RV64ZBR %s
	; RUN: llc -mtriple=riscv64 -mattr=+zbs %s -o - \| FileCheck --check-prefix=RV64ZBS %s			; RUN: llc -mtriple=riscv64 -mattr=+zbs %s -o - \| FileCheck --check-prefix=RV64ZBS %s
	; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - \| FileCheck --check-prefix=RV64ZBT %s
	; RUN: llc -mtriple=riscv64 -mattr=+v %s -o - \| FileCheck --check-prefix=RV64V %s			; RUN: llc -mtriple=riscv64 -mattr=+v %s -o - \| FileCheck --check-prefix=RV64V %s
	; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zfh,+v,+f %s -o - \| FileCheck --check-prefix=RV64COMBINED %s			; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zfh,+v,+f %s -o - \| FileCheck --check-prefix=RV64COMBINED %s
	; RUN: llc -mtriple=riscv64 -mattr=+zbkb %s -o - \| FileCheck --check-prefix=RV64ZBKB %s			; RUN: llc -mtriple=riscv64 -mattr=+zbkb %s -o - \| FileCheck --check-prefix=RV64ZBKB %s
	; RUN: llc -mtriple=riscv64 -mattr=+zbkc %s -o - \| FileCheck --check-prefix=RV64ZBKC %s			; RUN: llc -mtriple=riscv64 -mattr=+zbkc %s -o - \| FileCheck --check-prefix=RV64ZBKC %s
	; RUN: llc -mtriple=riscv64 -mattr=+zbkx %s -o - \| FileCheck --check-prefix=RV64ZBKX %s			; RUN: llc -mtriple=riscv64 -mattr=+zbkx %s -o - \| FileCheck --check-prefix=RV64ZBKX %s
	; RUN: llc -mtriple=riscv64 -mattr=+zknd %s -o - \| FileCheck --check-prefix=RV64ZKND %s			; RUN: llc -mtriple=riscv64 -mattr=+zknd %s -o - \| FileCheck --check-prefix=RV64ZKND %s
	; RUN: llc -mtriple=riscv64 -mattr=+zkne %s -o - \| FileCheck --check-prefix=RV64ZKNE %s			; RUN: llc -mtriple=riscv64 -mattr=+zkne %s -o - \| FileCheck --check-prefix=RV64ZKNE %s
	; RUN: llc -mtriple=riscv64 -mattr=+zknh %s -o - \| FileCheck --check-prefix=RV64ZKNH %s			; RUN: llc -mtriple=riscv64 -mattr=+zknh %s -o - \| FileCheck --check-prefix=RV64ZKNH %s
	Show All 27 Lines
	; RV32ZBB: .attribute 5, "rv32i2p0_zbb1p0"			; RV32ZBB: .attribute 5, "rv32i2p0_zbb1p0"
	; RV32ZBC: .attribute 5, "rv32i2p0_zbc1p0"			; RV32ZBC: .attribute 5, "rv32i2p0_zbc1p0"
	; RV32ZBE: .attribute 5, "rv32i2p0_zbe0p93"			; RV32ZBE: .attribute 5, "rv32i2p0_zbe0p93"
	; RV32ZBF: .attribute 5, "rv32i2p0_zbf0p93"			; RV32ZBF: .attribute 5, "rv32i2p0_zbf0p93"
	; RV32ZBM: .attribute 5, "rv32i2p0_zbm0p93"			; RV32ZBM: .attribute 5, "rv32i2p0_zbm0p93"
	; RV32ZBP: .attribute 5, "rv32i2p0_zbp0p93"			; RV32ZBP: .attribute 5, "rv32i2p0_zbp0p93"
	; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"			; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
	; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0"			; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0"
	; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
	; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"			; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
	; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"			; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
	; RV32ZBKB: .attribute 5, "rv32i2p0_zbkb1p0"			; RV32ZBKB: .attribute 5, "rv32i2p0_zbkb1p0"
	; RV32ZBKC: .attribute 5, "rv32i2p0_zbkc1p0"			; RV32ZBKC: .attribute 5, "rv32i2p0_zbkc1p0"
	; RV32ZBKX: .attribute 5, "rv32i2p0_zbkx1p0"			; RV32ZBKX: .attribute 5, "rv32i2p0_zbkx1p0"
	; RV32ZKND: .attribute 5, "rv32i2p0_zknd1p0"			; RV32ZKND: .attribute 5, "rv32i2p0_zknd1p0"
	; RV32ZKNE: .attribute 5, "rv32i2p0_zkne1p0"			; RV32ZKNE: .attribute 5, "rv32i2p0_zkne1p0"
	; RV32ZKNH: .attribute 5, "rv32i2p0_zknh1p0"			; RV32ZKNH: .attribute 5, "rv32i2p0_zknh1p0"
	Show All 26 Lines
	; RV64ZBB: .attribute 5, "rv64i2p0_zbb1p0"			; RV64ZBB: .attribute 5, "rv64i2p0_zbb1p0"
	; RV64ZBC: .attribute 5, "rv64i2p0_zbc1p0"			; RV64ZBC: .attribute 5, "rv64i2p0_zbc1p0"
	; RV64ZBE: .attribute 5, "rv64i2p0_zbe0p93"			; RV64ZBE: .attribute 5, "rv64i2p0_zbe0p93"
	; RV64ZBF: .attribute 5, "rv64i2p0_zbf0p93"			; RV64ZBF: .attribute 5, "rv64i2p0_zbf0p93"
	; RV64ZBM: .attribute 5, "rv64i2p0_zbm0p93"			; RV64ZBM: .attribute 5, "rv64i2p0_zbm0p93"
	; RV64ZBP: .attribute 5, "rv64i2p0_zbp0p93"			; RV64ZBP: .attribute 5, "rv64i2p0_zbp0p93"
	; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"			; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
	; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0"			; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0"
	; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
	; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"			; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
	; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"			; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
	; RV64ZBKB: .attribute 5, "rv64i2p0_zbkb1p0"			; RV64ZBKB: .attribute 5, "rv64i2p0_zbkb1p0"
	; RV64ZBKC: .attribute 5, "rv64i2p0_zbkc1p0"			; RV64ZBKC: .attribute 5, "rv64i2p0_zbkc1p0"
	; RV64ZBKX: .attribute 5, "rv64i2p0_zbkx1p0"			; RV64ZBKX: .attribute 5, "rv64i2p0_zbkx1p0"
	; RV64ZKND: .attribute 5, "rv64i2p0_zknd1p0"			; RV64ZKND: .attribute 5, "rv64i2p0_zknd1p0"
	; RV64ZKNE: .attribute 5, "rv64i2p0_zkne1p0"			; RV64ZKNE: .attribute 5, "rv64i2p0_zkne1p0"
	; RV64ZKNH: .attribute 5, "rv64i2p0_zknh1p0"			; RV64ZKNH: .attribute 5, "rv64i2p0_zknh1p0"
	Show All 19 Lines

llvm/test/CodeGen/RISCV/div-pow2.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s -check-prefixes=RV32,RV32I			; RUN: \| FileCheck %s -check-prefixes=RV32I
	; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s -check-prefixes=RV32,RV32ZBT
	; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s -check-prefixes=RV64,RV64I			; RUN: \| FileCheck %s -check-prefixes=RV64I
	; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s -check-prefixes=RV64,RV64ZBT

	define i32 @sdiv32_pow2_2(i32 %a) {			define i32 @sdiv32_pow2_2(i32 %a) {
	; RV32-LABEL: sdiv32_pow2_2:			; RV32I-LABEL: sdiv32_pow2_2:
	; RV32: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	; RV32-NEXT: srli a1, a0, 31			; RV32I-NEXT: srli a1, a0, 31
	; RV32-NEXT: add a0, a0, a1			; RV32I-NEXT: add a0, a0, a1
	; RV32-NEXT: srai a0, a0, 1			; RV32I-NEXT: srai a0, a0, 1
	; RV32-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV64-LABEL: sdiv32_pow2_2:			; RV64I-LABEL: sdiv32_pow2_2:
	; RV64: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV64-NEXT: srliw a1, a0, 31			; RV64I-NEXT: srliw a1, a0, 31
	; RV64-NEXT: addw a0, a0, a1			; RV64I-NEXT: addw a0, a0, a1
	; RV64-NEXT: sraiw a0, a0, 1			; RV64I-NEXT: sraiw a0, a0, 1
	; RV64-NEXT: ret			; RV64I-NEXT: ret
	entry:			entry:
	%div = sdiv i32 %a, 2			%div = sdiv i32 %a, 2
	ret i32 %div			ret i32 %div
	}			}

	define i32 @sdiv32_pow2_negative_2(i32 %a) {			define i32 @sdiv32_pow2_negative_2(i32 %a) {
	; RV32-LABEL: sdiv32_pow2_negative_2:			; RV32I-LABEL: sdiv32_pow2_negative_2:
	; RV32: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	; RV32-NEXT: srli a1, a0, 31			; RV32I-NEXT: srli a1, a0, 31
	; RV32-NEXT: add a0, a0, a1			; RV32I-NEXT: add a0, a0, a1
	; RV32-NEXT: srai a0, a0, 1			; RV32I-NEXT: srai a0, a0, 1
	; RV32-NEXT: neg a0, a0			; RV32I-NEXT: neg a0, a0
	; RV32-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV64-LABEL: sdiv32_pow2_negative_2:			; RV64I-LABEL: sdiv32_pow2_negative_2:
	; RV64: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV64-NEXT: srliw a1, a0, 31			; RV64I-NEXT: srliw a1, a0, 31
	; RV64-NEXT: addw a0, a0, a1			; RV64I-NEXT: addw a0, a0, a1
	; RV64-NEXT: sraiw a0, a0, 1			; RV64I-NEXT: sraiw a0, a0, 1
	; RV64-NEXT: neg a0, a0			; RV64I-NEXT: neg a0, a0
	; RV64-NEXT: ret			; RV64I-NEXT: ret
	entry:			entry:
	%div = sdiv i32 %a, -2			%div = sdiv i32 %a, -2
	ret i32 %div			ret i32 %div
	}			}

	define i32 @sdiv32_pow2_2048(i32 %a) {			define i32 @sdiv32_pow2_2048(i32 %a) {
	; RV32I-LABEL: sdiv32_pow2_2048:			; RV32I-LABEL: sdiv32_pow2_2048:
	; RV32I: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	; RV32I-NEXT: srai a1, a0, 31			; RV32I-NEXT: srai a1, a0, 31
	; RV32I-NEXT: srli a1, a1, 21			; RV32I-NEXT: srli a1, a1, 21
	; RV32I-NEXT: add a0, a0, a1			; RV32I-NEXT: add a0, a0, a1
	; RV32I-NEXT: srai a0, a0, 11			; RV32I-NEXT: srai a0, a0, 11
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBT-LABEL: sdiv32_pow2_2048:
	; RV32ZBT: # %bb.0: # %entry
	; RV32ZBT-NEXT: slti a1, a0, 0
	; RV32ZBT-NEXT: addi a2, a0, 2047
	; RV32ZBT-NEXT: cmov a0, a1, a2, a0
	; RV32ZBT-NEXT: srai a0, a0, 11
	; RV32ZBT-NEXT: ret
	;
	; RV64I-LABEL: sdiv32_pow2_2048:			; RV64I-LABEL: sdiv32_pow2_2048:
	; RV64I: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV64I-NEXT: sraiw a1, a0, 31			; RV64I-NEXT: sraiw a1, a0, 31
	; RV64I-NEXT: srliw a1, a1, 21			; RV64I-NEXT: srliw a1, a1, 21
	; RV64I-NEXT: addw a0, a0, a1			; RV64I-NEXT: addw a0, a0, a1
	; RV64I-NEXT: sraiw a0, a0, 11			; RV64I-NEXT: sraiw a0, a0, 11
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: sdiv32_pow2_2048:
	; RV64ZBT: # %bb.0: # %entry
	; RV64ZBT-NEXT: sext.w a1, a0
	; RV64ZBT-NEXT: addi a2, a0, 2047
	; RV64ZBT-NEXT: slti a1, a1, 0
	; RV64ZBT-NEXT: cmov a0, a1, a2, a0
	; RV64ZBT-NEXT: sraiw a0, a0, 11
	; RV64ZBT-NEXT: ret
	entry:			entry:
	%div = sdiv i32 %a, 2048			%div = sdiv i32 %a, 2048
	ret i32 %div			ret i32 %div
	}			}

	define i32 @sdiv32_pow2_negative_2048(i32 %a) {			define i32 @sdiv32_pow2_negative_2048(i32 %a) {
	; RV32I-LABEL: sdiv32_pow2_negative_2048:			; RV32I-LABEL: sdiv32_pow2_negative_2048:
	; RV32I: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	; RV32I-NEXT: srai a1, a0, 31			; RV32I-NEXT: srai a1, a0, 31
	; RV32I-NEXT: srli a1, a1, 21			; RV32I-NEXT: srli a1, a1, 21
	; RV32I-NEXT: add a0, a0, a1			; RV32I-NEXT: add a0, a0, a1
	; RV32I-NEXT: srai a0, a0, 11			; RV32I-NEXT: srai a0, a0, 11
	; RV32I-NEXT: neg a0, a0			; RV32I-NEXT: neg a0, a0
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBT-LABEL: sdiv32_pow2_negative_2048:
	; RV32ZBT: # %bb.0: # %entry
	; RV32ZBT-NEXT: slti a1, a0, 0
	; RV32ZBT-NEXT: addi a2, a0, 2047
	; RV32ZBT-NEXT: cmov a0, a1, a2, a0
	; RV32ZBT-NEXT: srai a0, a0, 11
	; RV32ZBT-NEXT: neg a0, a0
	; RV32ZBT-NEXT: ret
	;
	; RV64I-LABEL: sdiv32_pow2_negative_2048:			; RV64I-LABEL: sdiv32_pow2_negative_2048:
	; RV64I: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV64I-NEXT: sraiw a1, a0, 31			; RV64I-NEXT: sraiw a1, a0, 31
	; RV64I-NEXT: srliw a1, a1, 21			; RV64I-NEXT: srliw a1, a1, 21
	; RV64I-NEXT: addw a0, a0, a1			; RV64I-NEXT: addw a0, a0, a1
	; RV64I-NEXT: sraiw a0, a0, 11			; RV64I-NEXT: sraiw a0, a0, 11
	; RV64I-NEXT: neg a0, a0			; RV64I-NEXT: neg a0, a0
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: sdiv32_pow2_negative_2048:
	; RV64ZBT: # %bb.0: # %entry
	; RV64ZBT-NEXT: sext.w a1, a0
	; RV64ZBT-NEXT: addi a2, a0, 2047
	; RV64ZBT-NEXT: slti a1, a1, 0
	; RV64ZBT-NEXT: cmov a0, a1, a2, a0
	; RV64ZBT-NEXT: sraiw a0, a0, 11
	; RV64ZBT-NEXT: neg a0, a0
	; RV64ZBT-NEXT: ret
	entry:			entry:
	%div = sdiv i32 %a, -2048			%div = sdiv i32 %a, -2048
	ret i32 %div			ret i32 %div
	}			}

	define i32 @sdiv32_pow2_4096(i32 %a) {			define i32 @sdiv32_pow2_4096(i32 %a) {
	; RV32-LABEL: sdiv32_pow2_4096:			; RV32I-LABEL: sdiv32_pow2_4096:
	; RV32: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	; RV32-NEXT: srai a1, a0, 31			; RV32I-NEXT: srai a1, a0, 31
	; RV32-NEXT: srli a1, a1, 20			; RV32I-NEXT: srli a1, a1, 20
	; RV32-NEXT: add a0, a0, a1			; RV32I-NEXT: add a0, a0, a1
	; RV32-NEXT: srai a0, a0, 12			; RV32I-NEXT: srai a0, a0, 12
	; RV32-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV64-LABEL: sdiv32_pow2_4096:			; RV64I-LABEL: sdiv32_pow2_4096:
	; RV64: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV64-NEXT: sraiw a1, a0, 31			; RV64I-NEXT: sraiw a1, a0, 31
	; RV64-NEXT: srliw a1, a1, 20			; RV64I-NEXT: srliw a1, a1, 20
	; RV64-NEXT: addw a0, a0, a1			; RV64I-NEXT: addw a0, a0, a1
	; RV64-NEXT: sraiw a0, a0, 12			; RV64I-NEXT: sraiw a0, a0, 12
	; RV64-NEXT: ret			; RV64I-NEXT: ret
	entry:			entry:
	%div = sdiv i32 %a, 4096			%div = sdiv i32 %a, 4096
	ret i32 %div			ret i32 %div
	}			}

	define i32 @sdiv32_pow2_negative_4096(i32 %a) {			define i32 @sdiv32_pow2_negative_4096(i32 %a) {
	; RV32-LABEL: sdiv32_pow2_negative_4096:			; RV32I-LABEL: sdiv32_pow2_negative_4096:
	; RV32: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	; RV32-NEXT: srai a1, a0, 31			; RV32I-NEXT: srai a1, a0, 31
	; RV32-NEXT: srli a1, a1, 20			; RV32I-NEXT: srli a1, a1, 20
	; RV32-NEXT: add a0, a0, a1			; RV32I-NEXT: add a0, a0, a1
	; RV32-NEXT: srai a0, a0, 12			; RV32I-NEXT: srai a0, a0, 12
	; RV32-NEXT: neg a0, a0			; RV32I-NEXT: neg a0, a0
	; RV32-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV64-LABEL: sdiv32_pow2_negative_4096:			; RV64I-LABEL: sdiv32_pow2_negative_4096:
	; RV64: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV64-NEXT: sraiw a1, a0, 31			; RV64I-NEXT: sraiw a1, a0, 31
	; RV64-NEXT: srliw a1, a1, 20			; RV64I-NEXT: srliw a1, a1, 20
	; RV64-NEXT: addw a0, a0, a1			; RV64I-NEXT: addw a0, a0, a1
	; RV64-NEXT: sraiw a0, a0, 12			; RV64I-NEXT: sraiw a0, a0, 12
	; RV64-NEXT: neg a0, a0			; RV64I-NEXT: neg a0, a0
	; RV64-NEXT: ret			; RV64I-NEXT: ret
	entry:			entry:
	%div = sdiv i32 %a, -4096			%div = sdiv i32 %a, -4096
	ret i32 %div			ret i32 %div
	}			}

	define i32 @sdiv32_pow2_65536(i32 %a) {			define i32 @sdiv32_pow2_65536(i32 %a) {
	; RV32-LABEL: sdiv32_pow2_65536:			; RV32I-LABEL: sdiv32_pow2_65536:
	; RV32: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	; RV32-NEXT: srai a1, a0, 31			; RV32I-NEXT: srai a1, a0, 31
	; RV32-NEXT: srli a1, a1, 16			; RV32I-NEXT: srli a1, a1, 16
	; RV32-NEXT: add a0, a0, a1			; RV32I-NEXT: add a0, a0, a1
	; RV32-NEXT: srai a0, a0, 16			; RV32I-NEXT: srai a0, a0, 16
	; RV32-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV64-LABEL: sdiv32_pow2_65536:			; RV64I-LABEL: sdiv32_pow2_65536:
	; RV64: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV64-NEXT: sraiw a1, a0, 31			; RV64I-NEXT: sraiw a1, a0, 31
	; RV64-NEXT: srliw a1, a1, 16			; RV64I-NEXT: srliw a1, a1, 16
	; RV64-NEXT: addw a0, a0, a1			; RV64I-NEXT: addw a0, a0, a1
	; RV64-NEXT: sraiw a0, a0, 16			; RV64I-NEXT: sraiw a0, a0, 16
	; RV64-NEXT: ret			; RV64I-NEXT: ret
	entry:			entry:
	%div = sdiv i32 %a, 65536			%div = sdiv i32 %a, 65536
	ret i32 %div			ret i32 %div
	}			}

	define i32 @sdiv32_pow2_negative_65536(i32 %a) {			define i32 @sdiv32_pow2_negative_65536(i32 %a) {
	; RV32-LABEL: sdiv32_pow2_negative_65536:			; RV32I-LABEL: sdiv32_pow2_negative_65536:
	; RV32: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	; RV32-NEXT: srai a1, a0, 31			; RV32I-NEXT: srai a1, a0, 31
	; RV32-NEXT: srli a1, a1, 16			; RV32I-NEXT: srli a1, a1, 16
	; RV32-NEXT: add a0, a0, a1			; RV32I-NEXT: add a0, a0, a1
	; RV32-NEXT: srai a0, a0, 16			; RV32I-NEXT: srai a0, a0, 16
	; RV32-NEXT: neg a0, a0			; RV32I-NEXT: neg a0, a0
	; RV32-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV64-LABEL: sdiv32_pow2_negative_65536:			; RV64I-LABEL: sdiv32_pow2_negative_65536:
	; RV64: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV64-NEXT: sraiw a1, a0, 31			; RV64I-NEXT: sraiw a1, a0, 31
	; RV64-NEXT: srliw a1, a1, 16			; RV64I-NEXT: srliw a1, a1, 16
	; RV64-NEXT: addw a0, a0, a1			; RV64I-NEXT: addw a0, a0, a1
	; RV64-NEXT: sraiw a0, a0, 16			; RV64I-NEXT: sraiw a0, a0, 16
	; RV64-NEXT: neg a0, a0			; RV64I-NEXT: neg a0, a0
	; RV64-NEXT: ret			; RV64I-NEXT: ret
	entry:			entry:
	%div = sdiv i32 %a, -65536			%div = sdiv i32 %a, -65536
	ret i32 %div			ret i32 %div
	}			}

	define i64 @sdiv64_pow2_2(i64 %a) {			define i64 @sdiv64_pow2_2(i64 %a) {
	; RV32I-LABEL: sdiv64_pow2_2:			; RV32I-LABEL: sdiv64_pow2_2:
	; RV32I: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	; RV32I-NEXT: srli a2, a1, 31			; RV32I-NEXT: srli a2, a1, 31
	; RV32I-NEXT: add a2, a0, a2			; RV32I-NEXT: add a2, a0, a2
	; RV32I-NEXT: srli a3, a2, 1			; RV32I-NEXT: srli a3, a2, 1
	; RV32I-NEXT: sltu a0, a2, a0			; RV32I-NEXT: sltu a0, a2, a0
	; RV32I-NEXT: add a1, a1, a0			; RV32I-NEXT: add a1, a1, a0
	; RV32I-NEXT: slli a0, a1, 31			; RV32I-NEXT: slli a0, a1, 31
	; RV32I-NEXT: or a0, a3, a0			; RV32I-NEXT: or a0, a3, a0
	; RV32I-NEXT: srai a1, a1, 1			; RV32I-NEXT: srai a1, a1, 1
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBT-LABEL: sdiv64_pow2_2:			; RV64I-LABEL: sdiv64_pow2_2:
	; RV32ZBT: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV32ZBT-NEXT: srli a2, a1, 31			; RV64I-NEXT: srli a1, a0, 63
	; RV32ZBT-NEXT: add a2, a0, a2			; RV64I-NEXT: add a0, a0, a1
	; RV32ZBT-NEXT: sltu a0, a2, a0			; RV64I-NEXT: srai a0, a0, 1
	; RV32ZBT-NEXT: add a1, a1, a0			; RV64I-NEXT: ret
	; RV32ZBT-NEXT: fsri a0, a2, a1, 1
	; RV32ZBT-NEXT: srai a1, a1, 1
	; RV32ZBT-NEXT: ret
	;
	; RV64-LABEL: sdiv64_pow2_2:
	; RV64: # %bb.0: # %entry
	; RV64-NEXT: srli a1, a0, 63
	; RV64-NEXT: add a0, a0, a1
	; RV64-NEXT: srai a0, a0, 1
	; RV64-NEXT: ret
	entry:			entry:
	%div = sdiv i64 %a, 2			%div = sdiv i64 %a, 2
	ret i64 %div			ret i64 %div
	}			}

	define i64 @sdiv64_pow2_negative_2(i64 %a) {			define i64 @sdiv64_pow2_negative_2(i64 %a) {
	; RV32I-LABEL: sdiv64_pow2_negative_2:			; RV32I-LABEL: sdiv64_pow2_negative_2:
	; RV32I: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	; RV32I-NEXT: srli a2, a1, 31			; RV32I-NEXT: srli a2, a1, 31
	; RV32I-NEXT: add a2, a0, a2			; RV32I-NEXT: add a2, a0, a2
	; RV32I-NEXT: srli a3, a2, 1			; RV32I-NEXT: srli a3, a2, 1
	; RV32I-NEXT: sltu a0, a2, a0			; RV32I-NEXT: sltu a0, a2, a0
	; RV32I-NEXT: add a1, a1, a0			; RV32I-NEXT: add a1, a1, a0
	; RV32I-NEXT: slli a0, a1, 31			; RV32I-NEXT: slli a0, a1, 31
	; RV32I-NEXT: or a2, a3, a0			; RV32I-NEXT: or a2, a3, a0
	; RV32I-NEXT: neg a0, a2			; RV32I-NEXT: neg a0, a2
	; RV32I-NEXT: snez a2, a2			; RV32I-NEXT: snez a2, a2
	; RV32I-NEXT: srai a1, a1, 1			; RV32I-NEXT: srai a1, a1, 1
	; RV32I-NEXT: add a1, a1, a2			; RV32I-NEXT: add a1, a1, a2
	; RV32I-NEXT: neg a1, a1			; RV32I-NEXT: neg a1, a1
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBT-LABEL: sdiv64_pow2_negative_2:			; RV64I-LABEL: sdiv64_pow2_negative_2:
	; RV32ZBT: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV32ZBT-NEXT: srli a2, a1, 31			; RV64I-NEXT: srli a1, a0, 63
	; RV32ZBT-NEXT: add a2, a0, a2			; RV64I-NEXT: add a0, a0, a1
	; RV32ZBT-NEXT: sltu a0, a2, a0			; RV64I-NEXT: srai a0, a0, 1
	; RV32ZBT-NEXT: add a1, a1, a0			; RV64I-NEXT: neg a0, a0
	; RV32ZBT-NEXT: fsri a2, a2, a1, 1			; RV64I-NEXT: ret
	; RV32ZBT-NEXT: neg a0, a2
	; RV32ZBT-NEXT: snez a2, a2
	; RV32ZBT-NEXT: srai a1, a1, 1
	; RV32ZBT-NEXT: add a1, a1, a2
	; RV32ZBT-NEXT: neg a1, a1
	; RV32ZBT-NEXT: ret
	;
	; RV64-LABEL: sdiv64_pow2_negative_2:
	; RV64: # %bb.0: # %entry
	; RV64-NEXT: srli a1, a0, 63
	; RV64-NEXT: add a0, a0, a1
	; RV64-NEXT: srai a0, a0, 1
	; RV64-NEXT: neg a0, a0
	; RV64-NEXT: ret
	entry:			entry:
	%div = sdiv i64 %a, -2			%div = sdiv i64 %a, -2
	ret i64 %div			ret i64 %div
	}			}

	define i64 @sdiv64_pow2_2048(i64 %a) {			define i64 @sdiv64_pow2_2048(i64 %a) {
	; RV32I-LABEL: sdiv64_pow2_2048:			; RV32I-LABEL: sdiv64_pow2_2048:
	; RV32I: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	; RV32I-NEXT: srai a2, a1, 31			; RV32I-NEXT: srai a2, a1, 31
	; RV32I-NEXT: srli a2, a2, 21			; RV32I-NEXT: srli a2, a2, 21
	; RV32I-NEXT: add a2, a0, a2			; RV32I-NEXT: add a2, a0, a2
	; RV32I-NEXT: srli a3, a2, 11			; RV32I-NEXT: srli a3, a2, 11
	; RV32I-NEXT: sltu a0, a2, a0			; RV32I-NEXT: sltu a0, a2, a0
	; RV32I-NEXT: add a1, a1, a0			; RV32I-NEXT: add a1, a1, a0
	; RV32I-NEXT: slli a0, a1, 21			; RV32I-NEXT: slli a0, a1, 21
	; RV32I-NEXT: or a0, a3, a0			; RV32I-NEXT: or a0, a3, a0
	; RV32I-NEXT: srai a1, a1, 11			; RV32I-NEXT: srai a1, a1, 11
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBT-LABEL: sdiv64_pow2_2048:
	; RV32ZBT: # %bb.0: # %entry
	; RV32ZBT-NEXT: srai a2, a1, 31
	; RV32ZBT-NEXT: srli a2, a2, 21
	; RV32ZBT-NEXT: add a2, a0, a2
	; RV32ZBT-NEXT: sltu a0, a2, a0
	; RV32ZBT-NEXT: add a1, a1, a0
	; RV32ZBT-NEXT: fsri a0, a2, a1, 11
	; RV32ZBT-NEXT: srai a1, a1, 11
	; RV32ZBT-NEXT: ret
	;
	; RV64I-LABEL: sdiv64_pow2_2048:			; RV64I-LABEL: sdiv64_pow2_2048:
	; RV64I: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV64I-NEXT: srai a1, a0, 63			; RV64I-NEXT: srai a1, a0, 63
	; RV64I-NEXT: srli a1, a1, 53			; RV64I-NEXT: srli a1, a1, 53
	; RV64I-NEXT: add a0, a0, a1			; RV64I-NEXT: add a0, a0, a1
	; RV64I-NEXT: srai a0, a0, 11			; RV64I-NEXT: srai a0, a0, 11
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: sdiv64_pow2_2048:
	; RV64ZBT: # %bb.0: # %entry
	; RV64ZBT-NEXT: slti a1, a0, 0
	; RV64ZBT-NEXT: addi a2, a0, 2047
	; RV64ZBT-NEXT: cmov a0, a1, a2, a0
	; RV64ZBT-NEXT: srai a0, a0, 11
	; RV64ZBT-NEXT: ret
	entry:			entry:
	%div = sdiv i64 %a, 2048			%div = sdiv i64 %a, 2048
	ret i64 %div			ret i64 %div
	}			}

	define i64 @sdiv64_pow2_negative_2048(i64 %a) {			define i64 @sdiv64_pow2_negative_2048(i64 %a) {
	; RV32I-LABEL: sdiv64_pow2_negative_2048:			; RV32I-LABEL: sdiv64_pow2_negative_2048:
	; RV32I: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	; RV32I-NEXT: srai a2, a1, 31			; RV32I-NEXT: srai a2, a1, 31
	; RV32I-NEXT: srli a2, a2, 21			; RV32I-NEXT: srli a2, a2, 21
	; RV32I-NEXT: add a2, a0, a2			; RV32I-NEXT: add a2, a0, a2
	; RV32I-NEXT: srli a3, a2, 11			; RV32I-NEXT: srli a3, a2, 11
	; RV32I-NEXT: sltu a0, a2, a0			; RV32I-NEXT: sltu a0, a2, a0
	; RV32I-NEXT: add a1, a1, a0			; RV32I-NEXT: add a1, a1, a0
	; RV32I-NEXT: slli a0, a1, 21			; RV32I-NEXT: slli a0, a1, 21
	; RV32I-NEXT: or a2, a3, a0			; RV32I-NEXT: or a2, a3, a0
	; RV32I-NEXT: neg a0, a2			; RV32I-NEXT: neg a0, a2
	; RV32I-NEXT: snez a2, a2			; RV32I-NEXT: snez a2, a2
	; RV32I-NEXT: srai a1, a1, 11			; RV32I-NEXT: srai a1, a1, 11
	; RV32I-NEXT: add a1, a1, a2			; RV32I-NEXT: add a1, a1, a2
	; RV32I-NEXT: neg a1, a1			; RV32I-NEXT: neg a1, a1
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBT-LABEL: sdiv64_pow2_negative_2048:
	; RV32ZBT: # %bb.0: # %entry
	; RV32ZBT-NEXT: srai a2, a1, 31
	; RV32ZBT-NEXT: srli a2, a2, 21
	; RV32ZBT-NEXT: add a2, a0, a2
	; RV32ZBT-NEXT: sltu a0, a2, a0
	; RV32ZBT-NEXT: add a1, a1, a0
	; RV32ZBT-NEXT: fsri a2, a2, a1, 11
	; RV32ZBT-NEXT: neg a0, a2
	; RV32ZBT-NEXT: snez a2, a2
	; RV32ZBT-NEXT: srai a1, a1, 11
	; RV32ZBT-NEXT: add a1, a1, a2
	; RV32ZBT-NEXT: neg a1, a1
	; RV32ZBT-NEXT: ret
	;
	; RV64I-LABEL: sdiv64_pow2_negative_2048:			; RV64I-LABEL: sdiv64_pow2_negative_2048:
	; RV64I: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV64I-NEXT: srai a1, a0, 63			; RV64I-NEXT: srai a1, a0, 63
	; RV64I-NEXT: srli a1, a1, 53			; RV64I-NEXT: srli a1, a1, 53
	; RV64I-NEXT: add a0, a0, a1			; RV64I-NEXT: add a0, a0, a1
	; RV64I-NEXT: srai a0, a0, 11			; RV64I-NEXT: srai a0, a0, 11
	; RV64I-NEXT: neg a0, a0			; RV64I-NEXT: neg a0, a0
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: sdiv64_pow2_negative_2048:
	; RV64ZBT: # %bb.0: # %entry
	; RV64ZBT-NEXT: slti a1, a0, 0
	; RV64ZBT-NEXT: addi a2, a0, 2047
	; RV64ZBT-NEXT: cmov a0, a1, a2, a0
	; RV64ZBT-NEXT: srai a0, a0, 11
	; RV64ZBT-NEXT: neg a0, a0
	; RV64ZBT-NEXT: ret
	entry:			entry:
	%div = sdiv i64 %a, -2048			%div = sdiv i64 %a, -2048
	ret i64 %div			ret i64 %div
	}			}

	define i64 @sdiv64_pow2_4096(i64 %a) {			define i64 @sdiv64_pow2_4096(i64 %a) {
	; RV32I-LABEL: sdiv64_pow2_4096:			; RV32I-LABEL: sdiv64_pow2_4096:
	; RV32I: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	; RV32I-NEXT: srai a2, a1, 31			; RV32I-NEXT: srai a2, a1, 31
	; RV32I-NEXT: srli a2, a2, 20			; RV32I-NEXT: srli a2, a2, 20
	; RV32I-NEXT: add a2, a0, a2			; RV32I-NEXT: add a2, a0, a2
	; RV32I-NEXT: srli a3, a2, 12			; RV32I-NEXT: srli a3, a2, 12
	; RV32I-NEXT: sltu a0, a2, a0			; RV32I-NEXT: sltu a0, a2, a0
	; RV32I-NEXT: add a1, a1, a0			; RV32I-NEXT: add a1, a1, a0
	; RV32I-NEXT: slli a0, a1, 20			; RV32I-NEXT: slli a0, a1, 20
	; RV32I-NEXT: or a0, a3, a0			; RV32I-NEXT: or a0, a3, a0
	; RV32I-NEXT: srai a1, a1, 12			; RV32I-NEXT: srai a1, a1, 12
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBT-LABEL: sdiv64_pow2_4096:			; RV64I-LABEL: sdiv64_pow2_4096:
	; RV32ZBT: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV32ZBT-NEXT: srai a2, a1, 31			; RV64I-NEXT: srai a1, a0, 63
	; RV32ZBT-NEXT: srli a2, a2, 20			; RV64I-NEXT: srli a1, a1, 52
	; RV32ZBT-NEXT: add a2, a0, a2			; RV64I-NEXT: add a0, a0, a1
	; RV32ZBT-NEXT: sltu a0, a2, a0			; RV64I-NEXT: srai a0, a0, 12
	; RV32ZBT-NEXT: add a1, a1, a0			; RV64I-NEXT: ret
	; RV32ZBT-NEXT: fsri a0, a2, a1, 12
	; RV32ZBT-NEXT: srai a1, a1, 12
	; RV32ZBT-NEXT: ret
	;
	; RV64-LABEL: sdiv64_pow2_4096:
	; RV64: # %bb.0: # %entry
	; RV64-NEXT: srai a1, a0, 63
	; RV64-NEXT: srli a1, a1, 52
	; RV64-NEXT: add a0, a0, a1
	; RV64-NEXT: srai a0, a0, 12
	; RV64-NEXT: ret
	entry:			entry:
	%div = sdiv i64 %a, 4096			%div = sdiv i64 %a, 4096
	ret i64 %div			ret i64 %div
	}			}

	define i64 @sdiv64_pow2_negative_4096(i64 %a) {			define i64 @sdiv64_pow2_negative_4096(i64 %a) {
	; RV32I-LABEL: sdiv64_pow2_negative_4096:			; RV32I-LABEL: sdiv64_pow2_negative_4096:
	; RV32I: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	; RV32I-NEXT: srai a2, a1, 31			; RV32I-NEXT: srai a2, a1, 31
	; RV32I-NEXT: srli a2, a2, 20			; RV32I-NEXT: srli a2, a2, 20
	; RV32I-NEXT: add a2, a0, a2			; RV32I-NEXT: add a2, a0, a2
	; RV32I-NEXT: srli a3, a2, 12			; RV32I-NEXT: srli a3, a2, 12
	; RV32I-NEXT: sltu a0, a2, a0			; RV32I-NEXT: sltu a0, a2, a0
	; RV32I-NEXT: add a1, a1, a0			; RV32I-NEXT: add a1, a1, a0
	; RV32I-NEXT: slli a0, a1, 20			; RV32I-NEXT: slli a0, a1, 20
	; RV32I-NEXT: or a2, a3, a0			; RV32I-NEXT: or a2, a3, a0
	; RV32I-NEXT: neg a0, a2			; RV32I-NEXT: neg a0, a2
	; RV32I-NEXT: snez a2, a2			; RV32I-NEXT: snez a2, a2
	; RV32I-NEXT: srai a1, a1, 12			; RV32I-NEXT: srai a1, a1, 12
	; RV32I-NEXT: add a1, a1, a2			; RV32I-NEXT: add a1, a1, a2
	; RV32I-NEXT: neg a1, a1			; RV32I-NEXT: neg a1, a1
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBT-LABEL: sdiv64_pow2_negative_4096:			; RV64I-LABEL: sdiv64_pow2_negative_4096:
	; RV32ZBT: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV32ZBT-NEXT: srai a2, a1, 31			; RV64I-NEXT: srai a1, a0, 63
	; RV32ZBT-NEXT: srli a2, a2, 20			; RV64I-NEXT: srli a1, a1, 52
	; RV32ZBT-NEXT: add a2, a0, a2			; RV64I-NEXT: add a0, a0, a1
	; RV32ZBT-NEXT: sltu a0, a2, a0			; RV64I-NEXT: srai a0, a0, 12
	; RV32ZBT-NEXT: add a1, a1, a0			; RV64I-NEXT: neg a0, a0
	; RV32ZBT-NEXT: fsri a2, a2, a1, 12			; RV64I-NEXT: ret
	; RV32ZBT-NEXT: neg a0, a2
	; RV32ZBT-NEXT: snez a2, a2
	; RV32ZBT-NEXT: srai a1, a1, 12
	; RV32ZBT-NEXT: add a1, a1, a2
	; RV32ZBT-NEXT: neg a1, a1
	; RV32ZBT-NEXT: ret
	;
	; RV64-LABEL: sdiv64_pow2_negative_4096:
	; RV64: # %bb.0: # %entry
	; RV64-NEXT: srai a1, a0, 63
	; RV64-NEXT: srli a1, a1, 52
	; RV64-NEXT: add a0, a0, a1
	; RV64-NEXT: srai a0, a0, 12
	; RV64-NEXT: neg a0, a0
	; RV64-NEXT: ret
	entry:			entry:
	%div = sdiv i64 %a, -4096			%div = sdiv i64 %a, -4096
	ret i64 %div			ret i64 %div
	}			}

	define i64 @sdiv64_pow2_65536(i64 %a) {			define i64 @sdiv64_pow2_65536(i64 %a) {
	; RV32I-LABEL: sdiv64_pow2_65536:			; RV32I-LABEL: sdiv64_pow2_65536:
	; RV32I: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	; RV32I-NEXT: srai a2, a1, 31			; RV32I-NEXT: srai a2, a1, 31
	; RV32I-NEXT: srli a2, a2, 16			; RV32I-NEXT: srli a2, a2, 16
	; RV32I-NEXT: add a2, a0, a2			; RV32I-NEXT: add a2, a0, a2
	; RV32I-NEXT: srli a3, a2, 16			; RV32I-NEXT: srli a3, a2, 16
	; RV32I-NEXT: sltu a0, a2, a0			; RV32I-NEXT: sltu a0, a2, a0
	; RV32I-NEXT: add a1, a1, a0			; RV32I-NEXT: add a1, a1, a0
	; RV32I-NEXT: slli a0, a1, 16			; RV32I-NEXT: slli a0, a1, 16
	; RV32I-NEXT: or a0, a3, a0			; RV32I-NEXT: or a0, a3, a0
	; RV32I-NEXT: srai a1, a1, 16			; RV32I-NEXT: srai a1, a1, 16
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBT-LABEL: sdiv64_pow2_65536:			; RV64I-LABEL: sdiv64_pow2_65536:
	; RV32ZBT: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV32ZBT-NEXT: srai a2, a1, 31			; RV64I-NEXT: srai a1, a0, 63
	; RV32ZBT-NEXT: srli a2, a2, 16			; RV64I-NEXT: srli a1, a1, 48
	; RV32ZBT-NEXT: add a2, a0, a2			; RV64I-NEXT: add a0, a0, a1
	; RV32ZBT-NEXT: sltu a0, a2, a0			; RV64I-NEXT: srai a0, a0, 16
	; RV32ZBT-NEXT: add a1, a1, a0			; RV64I-NEXT: ret
	; RV32ZBT-NEXT: fsri a0, a2, a1, 16
	; RV32ZBT-NEXT: srai a1, a1, 16
	; RV32ZBT-NEXT: ret
	;
	; RV64-LABEL: sdiv64_pow2_65536:
	; RV64: # %bb.0: # %entry
	; RV64-NEXT: srai a1, a0, 63
	; RV64-NEXT: srli a1, a1, 48
	; RV64-NEXT: add a0, a0, a1
	; RV64-NEXT: srai a0, a0, 16
	; RV64-NEXT: ret
	entry:			entry:
	%div = sdiv i64 %a, 65536			%div = sdiv i64 %a, 65536
	ret i64 %div			ret i64 %div
	}			}

	define i64 @sdiv64_pow2_negative_65536(i64 %a) {			define i64 @sdiv64_pow2_negative_65536(i64 %a) {
	; RV32I-LABEL: sdiv64_pow2_negative_65536:			; RV32I-LABEL: sdiv64_pow2_negative_65536:
	; RV32I: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	; RV32I-NEXT: srai a2, a1, 31			; RV32I-NEXT: srai a2, a1, 31
	; RV32I-NEXT: srli a2, a2, 16			; RV32I-NEXT: srli a2, a2, 16
	; RV32I-NEXT: add a2, a0, a2			; RV32I-NEXT: add a2, a0, a2
	; RV32I-NEXT: srli a3, a2, 16			; RV32I-NEXT: srli a3, a2, 16
	; RV32I-NEXT: sltu a0, a2, a0			; RV32I-NEXT: sltu a0, a2, a0
	; RV32I-NEXT: add a1, a1, a0			; RV32I-NEXT: add a1, a1, a0
	; RV32I-NEXT: slli a0, a1, 16			; RV32I-NEXT: slli a0, a1, 16
	; RV32I-NEXT: or a2, a3, a0			; RV32I-NEXT: or a2, a3, a0
	; RV32I-NEXT: neg a0, a2			; RV32I-NEXT: neg a0, a2
	; RV32I-NEXT: snez a2, a2			; RV32I-NEXT: snez a2, a2
	; RV32I-NEXT: srai a1, a1, 16			; RV32I-NEXT: srai a1, a1, 16
	; RV32I-NEXT: add a1, a1, a2			; RV32I-NEXT: add a1, a1, a2
	; RV32I-NEXT: neg a1, a1			; RV32I-NEXT: neg a1, a1
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBT-LABEL: sdiv64_pow2_negative_65536:			; RV64I-LABEL: sdiv64_pow2_negative_65536:
	; RV32ZBT: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV32ZBT-NEXT: srai a2, a1, 31			; RV64I-NEXT: srai a1, a0, 63
	; RV32ZBT-NEXT: srli a2, a2, 16			; RV64I-NEXT: srli a1, a1, 48
	; RV32ZBT-NEXT: add a2, a0, a2			; RV64I-NEXT: add a0, a0, a1
	; RV32ZBT-NEXT: sltu a0, a2, a0			; RV64I-NEXT: srai a0, a0, 16
	; RV32ZBT-NEXT: add a1, a1, a0			; RV64I-NEXT: neg a0, a0
	; RV32ZBT-NEXT: fsri a2, a2, a1, 16			; RV64I-NEXT: ret
	; RV32ZBT-NEXT: neg a0, a2
	; RV32ZBT-NEXT: snez a2, a2
	; RV32ZBT-NEXT: srai a1, a1, 16
	; RV32ZBT-NEXT: add a1, a1, a2
	; RV32ZBT-NEXT: neg a1, a1
	; RV32ZBT-NEXT: ret
	;
	; RV64-LABEL: sdiv64_pow2_negative_65536:
	; RV64: # %bb.0: # %entry
	; RV64-NEXT: srai a1, a0, 63
	; RV64-NEXT: srli a1, a1, 48
	; RV64-NEXT: add a0, a0, a1
	; RV64-NEXT: srai a0, a0, 16
	; RV64-NEXT: neg a0, a0
	; RV64-NEXT: ret
	entry:			entry:
	%div = sdiv i64 %a, -65536			%div = sdiv i64 %a, -65536
	ret i64 %div			ret i64 %div
	}			}

	define i64 @sdiv64_pow2_8589934592(i64 %a) {			define i64 @sdiv64_pow2_8589934592(i64 %a) {
	; RV32I-LABEL: sdiv64_pow2_8589934592:			; RV32I-LABEL: sdiv64_pow2_8589934592:
	; RV32I: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	; RV32I-NEXT: srli a2, a1, 31			; RV32I-NEXT: srli a2, a1, 31
	; RV32I-NEXT: add a2, a1, a2			; RV32I-NEXT: add a2, a1, a2
	; RV32I-NEXT: srai a1, a1, 31			; RV32I-NEXT: srai a1, a1, 31
	; RV32I-NEXT: add a1, a0, a1			; RV32I-NEXT: add a1, a0, a1
	; RV32I-NEXT: sltu a0, a1, a0			; RV32I-NEXT: sltu a0, a1, a0
	; RV32I-NEXT: add a1, a2, a0			; RV32I-NEXT: add a1, a2, a0
	; RV32I-NEXT: srai a0, a1, 1			; RV32I-NEXT: srai a0, a1, 1
	; RV32I-NEXT: srai a1, a1, 31			; RV32I-NEXT: srai a1, a1, 31
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBT-LABEL: sdiv64_pow2_8589934592:			; RV64I-LABEL: sdiv64_pow2_8589934592:
	; RV32ZBT: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV32ZBT-NEXT: srli a2, a1, 31			; RV64I-NEXT: srai a1, a0, 63
	; RV32ZBT-NEXT: add a2, a1, a2			; RV64I-NEXT: srli a1, a1, 31
	; RV32ZBT-NEXT: srai a1, a1, 31			; RV64I-NEXT: add a0, a0, a1
	; RV32ZBT-NEXT: fsri a1, a1, a1, 31			; RV64I-NEXT: srai a0, a0, 33
	; RV32ZBT-NEXT: add a1, a0, a1			; RV64I-NEXT: ret
	; RV32ZBT-NEXT: sltu a0, a1, a0
	; RV32ZBT-NEXT: add a1, a2, a0
	; RV32ZBT-NEXT: srai a0, a1, 1
	; RV32ZBT-NEXT: srai a1, a1, 31
	; RV32ZBT-NEXT: ret
	;
	; RV64-LABEL: sdiv64_pow2_8589934592:
	; RV64: # %bb.0: # %entry
	; RV64-NEXT: srai a1, a0, 63
	; RV64-NEXT: srli a1, a1, 31
	; RV64-NEXT: add a0, a0, a1
	; RV64-NEXT: srai a0, a0, 33
	; RV64-NEXT: ret
	entry:			entry:
	%div = sdiv i64 %a, 8589934592 ; 2^33			%div = sdiv i64 %a, 8589934592 ; 2^33
	ret i64 %div			ret i64 %div
	}			}

	define i64 @sdiv64_pow2_negative_8589934592(i64 %a) {			define i64 @sdiv64_pow2_negative_8589934592(i64 %a) {
	; RV32I-LABEL: sdiv64_pow2_negative_8589934592:			; RV32I-LABEL: sdiv64_pow2_negative_8589934592:
	; RV32I: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	; RV32I-NEXT: srli a2, a1, 31			; RV32I-NEXT: srli a2, a1, 31
	; RV32I-NEXT: add a2, a1, a2			; RV32I-NEXT: add a2, a1, a2
	; RV32I-NEXT: srai a1, a1, 31			; RV32I-NEXT: srai a1, a1, 31
	; RV32I-NEXT: add a1, a0, a1			; RV32I-NEXT: add a1, a0, a1
	; RV32I-NEXT: sltu a0, a1, a0			; RV32I-NEXT: sltu a0, a1, a0
	; RV32I-NEXT: add a0, a2, a0			; RV32I-NEXT: add a0, a2, a0
	; RV32I-NEXT: srai a1, a0, 31			; RV32I-NEXT: srai a1, a0, 31
	; RV32I-NEXT: srai a0, a0, 1			; RV32I-NEXT: srai a0, a0, 1
	; RV32I-NEXT: snez a2, a0			; RV32I-NEXT: snez a2, a0
	; RV32I-NEXT: add a1, a1, a2			; RV32I-NEXT: add a1, a1, a2
	; RV32I-NEXT: neg a1, a1			; RV32I-NEXT: neg a1, a1
	; RV32I-NEXT: neg a0, a0			; RV32I-NEXT: neg a0, a0
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBT-LABEL: sdiv64_pow2_negative_8589934592:			; RV64I-LABEL: sdiv64_pow2_negative_8589934592:
	; RV32ZBT: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV32ZBT-NEXT: srli a2, a1, 31			; RV64I-NEXT: srai a1, a0, 63
	; RV32ZBT-NEXT: add a2, a1, a2			; RV64I-NEXT: srli a1, a1, 31
	; RV32ZBT-NEXT: srai a1, a1, 31			; RV64I-NEXT: add a0, a0, a1
	; RV32ZBT-NEXT: fsri a1, a1, a1, 31			; RV64I-NEXT: srai a0, a0, 33
	; RV32ZBT-NEXT: add a1, a0, a1			; RV64I-NEXT: neg a0, a0
	; RV32ZBT-NEXT: sltu a0, a1, a0			; RV64I-NEXT: ret
	; RV32ZBT-NEXT: add a0, a2, a0
	; RV32ZBT-NEXT: srai a1, a0, 31
	; RV32ZBT-NEXT: srai a0, a0, 1
	; RV32ZBT-NEXT: snez a2, a0
	; RV32ZBT-NEXT: add a1, a1, a2
	; RV32ZBT-NEXT: neg a1, a1
	; RV32ZBT-NEXT: neg a0, a0
	; RV32ZBT-NEXT: ret
	;
	; RV64-LABEL: sdiv64_pow2_negative_8589934592:
	; RV64: # %bb.0: # %entry
	; RV64-NEXT: srai a1, a0, 63
	; RV64-NEXT: srli a1, a1, 31
	; RV64-NEXT: add a0, a0, a1
	; RV64-NEXT: srai a0, a0, 33
	; RV64-NEXT: neg a0, a0
	; RV64-NEXT: ret
	entry:			entry:
	%div = sdiv i64 %a, -8589934592 ; -2^33			%div = sdiv i64 %a, -8589934592 ; -2^33
	ret i64 %div			ret i64 %div
	}			}

llvm/test/CodeGen/RISCV/iabs.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s --check-prefix=RV32I			; RUN: \| FileCheck %s --check-prefix=RV32I
	; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s --check-prefix=RV32ZBB			; RUN: \| FileCheck %s --check-prefix=RV32ZBB
	; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s --check-prefix=RV32ZBT
	; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s --check-prefix=RV64I			; RUN: \| FileCheck %s --check-prefix=RV64I
	; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s --check-prefix=RV64ZBB			; RUN: \| FileCheck %s --check-prefix=RV64ZBB
	; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s --check-prefix=RV64ZBT

	declare i8 @llvm.abs.i8(i8, i1 immarg)			declare i8 @llvm.abs.i8(i8, i1 immarg)
	declare i16 @llvm.abs.i16(i16, i1 immarg)			declare i16 @llvm.abs.i16(i16, i1 immarg)
	declare i32 @llvm.abs.i32(i32, i1 immarg)			declare i32 @llvm.abs.i32(i32, i1 immarg)
	declare i64 @llvm.abs.i64(i64, i1 immarg)			declare i64 @llvm.abs.i64(i64, i1 immarg)
	declare i128 @llvm.abs.i128(i128, i1 immarg)			declare i128 @llvm.abs.i128(i128, i1 immarg)

	define i8 @abs8(i8 %x) {			define i8 @abs8(i8 %x) {
	; RV32I-LABEL: abs8:			; RV32I-LABEL: abs8:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	; RV32I-NEXT: slli a1, a0, 24			; RV32I-NEXT: slli a1, a0, 24
	; RV32I-NEXT: srai a1, a1, 31			; RV32I-NEXT: srai a1, a1, 31
	; RV32I-NEXT: xor a0, a0, a1			; RV32I-NEXT: xor a0, a0, a1
	; RV32I-NEXT: sub a0, a0, a1			; RV32I-NEXT: sub a0, a0, a1
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBB-LABEL: abs8:			; RV32ZBB-LABEL: abs8:
	; RV32ZBB: # %bb.0:			; RV32ZBB: # %bb.0:
	; RV32ZBB-NEXT: sext.b a0, a0			; RV32ZBB-NEXT: sext.b a0, a0
	; RV32ZBB-NEXT: neg a1, a0			; RV32ZBB-NEXT: neg a1, a0
	; RV32ZBB-NEXT: max a0, a0, a1			; RV32ZBB-NEXT: max a0, a0, a1
	; RV32ZBB-NEXT: ret			; RV32ZBB-NEXT: ret
	;			;
	; RV32ZBT-LABEL: abs8:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: slli a1, a0, 24
	; RV32ZBT-NEXT: srai a1, a1, 31
	; RV32ZBT-NEXT: xor a0, a0, a1
	; RV32ZBT-NEXT: sub a0, a0, a1
	; RV32ZBT-NEXT: ret
	;
	; RV64I-LABEL: abs8:			; RV64I-LABEL: abs8:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: slli a1, a0, 56			; RV64I-NEXT: slli a1, a0, 56
	; RV64I-NEXT: srai a1, a1, 63			; RV64I-NEXT: srai a1, a1, 63
	; RV64I-NEXT: xor a0, a0, a1			; RV64I-NEXT: xor a0, a0, a1
	; RV64I-NEXT: sub a0, a0, a1			; RV64I-NEXT: sub a0, a0, a1
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;			;
	; RV64ZBB-LABEL: abs8:			; RV64ZBB-LABEL: abs8:
	; RV64ZBB: # %bb.0:			; RV64ZBB: # %bb.0:
	; RV64ZBB-NEXT: sext.b a0, a0			; RV64ZBB-NEXT: sext.b a0, a0
	; RV64ZBB-NEXT: neg a1, a0			; RV64ZBB-NEXT: neg a1, a0
	; RV64ZBB-NEXT: max a0, a0, a1			; RV64ZBB-NEXT: max a0, a0, a1
	; RV64ZBB-NEXT: ret			; RV64ZBB-NEXT: ret
	;
	; RV64ZBT-LABEL: abs8:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: slli a1, a0, 56
	; RV64ZBT-NEXT: srai a1, a1, 63
	; RV64ZBT-NEXT: xor a0, a0, a1
	; RV64ZBT-NEXT: sub a0, a0, a1
	; RV64ZBT-NEXT: ret
	%abs = tail call i8 @llvm.abs.i8(i8 %x, i1 true)			%abs = tail call i8 @llvm.abs.i8(i8 %x, i1 true)
	ret i8 %abs			ret i8 %abs
	}			}

	define i8 @select_abs8(i8 %x) {			define i8 @select_abs8(i8 %x) {
	; RV32I-LABEL: select_abs8:			; RV32I-LABEL: select_abs8:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	; RV32I-NEXT: slli a1, a0, 24			; RV32I-NEXT: slli a1, a0, 24
	; RV32I-NEXT: srai a1, a1, 31			; RV32I-NEXT: srai a1, a1, 31
	; RV32I-NEXT: xor a0, a0, a1			; RV32I-NEXT: xor a0, a0, a1
	; RV32I-NEXT: sub a0, a0, a1			; RV32I-NEXT: sub a0, a0, a1
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBB-LABEL: select_abs8:			; RV32ZBB-LABEL: select_abs8:
	; RV32ZBB: # %bb.0:			; RV32ZBB: # %bb.0:
	; RV32ZBB-NEXT: sext.b a0, a0			; RV32ZBB-NEXT: sext.b a0, a0
	; RV32ZBB-NEXT: neg a1, a0			; RV32ZBB-NEXT: neg a1, a0
	; RV32ZBB-NEXT: max a0, a0, a1			; RV32ZBB-NEXT: max a0, a0, a1
	; RV32ZBB-NEXT: ret			; RV32ZBB-NEXT: ret
	;			;
	; RV32ZBT-LABEL: select_abs8:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: slli a1, a0, 24
	; RV32ZBT-NEXT: srai a1, a1, 31
	; RV32ZBT-NEXT: xor a0, a0, a1
	; RV32ZBT-NEXT: sub a0, a0, a1
	; RV32ZBT-NEXT: ret
	;
	; RV64I-LABEL: select_abs8:			; RV64I-LABEL: select_abs8:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: slli a1, a0, 56			; RV64I-NEXT: slli a1, a0, 56
	; RV64I-NEXT: srai a1, a1, 63			; RV64I-NEXT: srai a1, a1, 63
	; RV64I-NEXT: xor a0, a0, a1			; RV64I-NEXT: xor a0, a0, a1
	; RV64I-NEXT: sub a0, a0, a1			; RV64I-NEXT: sub a0, a0, a1
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;			;
	; RV64ZBB-LABEL: select_abs8:			; RV64ZBB-LABEL: select_abs8:
	; RV64ZBB: # %bb.0:			; RV64ZBB: # %bb.0:
	; RV64ZBB-NEXT: sext.b a0, a0			; RV64ZBB-NEXT: sext.b a0, a0
	; RV64ZBB-NEXT: neg a1, a0			; RV64ZBB-NEXT: neg a1, a0
	; RV64ZBB-NEXT: max a0, a0, a1			; RV64ZBB-NEXT: max a0, a0, a1
	; RV64ZBB-NEXT: ret			; RV64ZBB-NEXT: ret
	;
	; RV64ZBT-LABEL: select_abs8:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: slli a1, a0, 56
	; RV64ZBT-NEXT: srai a1, a1, 63
	; RV64ZBT-NEXT: xor a0, a0, a1
	; RV64ZBT-NEXT: sub a0, a0, a1
	; RV64ZBT-NEXT: ret
	%1 = icmp slt i8 %x, 0			%1 = icmp slt i8 %x, 0
	%2 = sub nsw i8 0, %x			%2 = sub nsw i8 0, %x
	%3 = select i1 %1, i8 %2, i8 %x			%3 = select i1 %1, i8 %2, i8 %x
	ret i8 %3			ret i8 %3
	}			}

	define i16 @abs16(i16 %x) {			define i16 @abs16(i16 %x) {
	; RV32I-LABEL: abs16:			; RV32I-LABEL: abs16:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	; RV32I-NEXT: slli a1, a0, 16			; RV32I-NEXT: slli a1, a0, 16
	; RV32I-NEXT: srai a1, a1, 31			; RV32I-NEXT: srai a1, a1, 31
	; RV32I-NEXT: xor a0, a0, a1			; RV32I-NEXT: xor a0, a0, a1
	; RV32I-NEXT: sub a0, a0, a1			; RV32I-NEXT: sub a0, a0, a1
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBB-LABEL: abs16:			; RV32ZBB-LABEL: abs16:
	; RV32ZBB: # %bb.0:			; RV32ZBB: # %bb.0:
	; RV32ZBB-NEXT: sext.h a0, a0			; RV32ZBB-NEXT: sext.h a0, a0
	; RV32ZBB-NEXT: neg a1, a0			; RV32ZBB-NEXT: neg a1, a0
	; RV32ZBB-NEXT: max a0, a0, a1			; RV32ZBB-NEXT: max a0, a0, a1
	; RV32ZBB-NEXT: ret			; RV32ZBB-NEXT: ret
	;			;
	; RV32ZBT-LABEL: abs16:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: slli a1, a0, 16
	; RV32ZBT-NEXT: srai a1, a1, 31
	; RV32ZBT-NEXT: xor a0, a0, a1
	; RV32ZBT-NEXT: sub a0, a0, a1
	; RV32ZBT-NEXT: ret
	;
	; RV64I-LABEL: abs16:			; RV64I-LABEL: abs16:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: slli a1, a0, 48			; RV64I-NEXT: slli a1, a0, 48
	; RV64I-NEXT: srai a1, a1, 63			; RV64I-NEXT: srai a1, a1, 63
	; RV64I-NEXT: xor a0, a0, a1			; RV64I-NEXT: xor a0, a0, a1
	; RV64I-NEXT: sub a0, a0, a1			; RV64I-NEXT: sub a0, a0, a1
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;			;
	; RV64ZBB-LABEL: abs16:			; RV64ZBB-LABEL: abs16:
	; RV64ZBB: # %bb.0:			; RV64ZBB: # %bb.0:
	; RV64ZBB-NEXT: sext.h a0, a0			; RV64ZBB-NEXT: sext.h a0, a0
	; RV64ZBB-NEXT: neg a1, a0			; RV64ZBB-NEXT: neg a1, a0
	; RV64ZBB-NEXT: max a0, a0, a1			; RV64ZBB-NEXT: max a0, a0, a1
	; RV64ZBB-NEXT: ret			; RV64ZBB-NEXT: ret
	;
	; RV64ZBT-LABEL: abs16:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: slli a1, a0, 48
	; RV64ZBT-NEXT: srai a1, a1, 63
	; RV64ZBT-NEXT: xor a0, a0, a1
	; RV64ZBT-NEXT: sub a0, a0, a1
	; RV64ZBT-NEXT: ret
	%abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true)			%abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true)
	ret i16 %abs			ret i16 %abs
	}			}

	define i16 @select_abs16(i16 %x) {			define i16 @select_abs16(i16 %x) {
	; RV32I-LABEL: select_abs16:			; RV32I-LABEL: select_abs16:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	; RV32I-NEXT: slli a1, a0, 16			; RV32I-NEXT: slli a1, a0, 16
	; RV32I-NEXT: srai a1, a1, 31			; RV32I-NEXT: srai a1, a1, 31
	; RV32I-NEXT: xor a0, a0, a1			; RV32I-NEXT: xor a0, a0, a1
	; RV32I-NEXT: sub a0, a0, a1			; RV32I-NEXT: sub a0, a0, a1
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBB-LABEL: select_abs16:			; RV32ZBB-LABEL: select_abs16:
	; RV32ZBB: # %bb.0:			; RV32ZBB: # %bb.0:
	; RV32ZBB-NEXT: sext.h a0, a0			; RV32ZBB-NEXT: sext.h a0, a0
	; RV32ZBB-NEXT: neg a1, a0			; RV32ZBB-NEXT: neg a1, a0
	; RV32ZBB-NEXT: max a0, a0, a1			; RV32ZBB-NEXT: max a0, a0, a1
	; RV32ZBB-NEXT: ret			; RV32ZBB-NEXT: ret
	;			;
	; RV32ZBT-LABEL: select_abs16:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: slli a1, a0, 16
	; RV32ZBT-NEXT: srai a1, a1, 31
	; RV32ZBT-NEXT: xor a0, a0, a1
	; RV32ZBT-NEXT: sub a0, a0, a1
	; RV32ZBT-NEXT: ret
	;
	; RV64I-LABEL: select_abs16:			; RV64I-LABEL: select_abs16:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: slli a1, a0, 48			; RV64I-NEXT: slli a1, a0, 48
	; RV64I-NEXT: srai a1, a1, 63			; RV64I-NEXT: srai a1, a1, 63
	; RV64I-NEXT: xor a0, a0, a1			; RV64I-NEXT: xor a0, a0, a1
	; RV64I-NEXT: sub a0, a0, a1			; RV64I-NEXT: sub a0, a0, a1
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;			;
	; RV64ZBB-LABEL: select_abs16:			; RV64ZBB-LABEL: select_abs16:
	; RV64ZBB: # %bb.0:			; RV64ZBB: # %bb.0:
	; RV64ZBB-NEXT: sext.h a0, a0			; RV64ZBB-NEXT: sext.h a0, a0
	; RV64ZBB-NEXT: neg a1, a0			; RV64ZBB-NEXT: neg a1, a0
	; RV64ZBB-NEXT: max a0, a0, a1			; RV64ZBB-NEXT: max a0, a0, a1
	; RV64ZBB-NEXT: ret			; RV64ZBB-NEXT: ret
	;
	; RV64ZBT-LABEL: select_abs16:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: slli a1, a0, 48
	; RV64ZBT-NEXT: srai a1, a1, 63
	; RV64ZBT-NEXT: xor a0, a0, a1
	; RV64ZBT-NEXT: sub a0, a0, a1
	; RV64ZBT-NEXT: ret
	%1 = icmp slt i16 %x, 0			%1 = icmp slt i16 %x, 0
	%2 = sub nsw i16 0, %x			%2 = sub nsw i16 0, %x
	%3 = select i1 %1, i16 %2, i16 %x			%3 = select i1 %1, i16 %2, i16 %x
	ret i16 %3			ret i16 %3
	}			}

	define i32 @abs32(i32 %x) {			define i32 @abs32(i32 %x) {
	; RV32I-LABEL: abs32:			; RV32I-LABEL: abs32:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	; RV32I-NEXT: srai a1, a0, 31			; RV32I-NEXT: srai a1, a0, 31
	; RV32I-NEXT: xor a0, a0, a1			; RV32I-NEXT: xor a0, a0, a1
	; RV32I-NEXT: sub a0, a0, a1			; RV32I-NEXT: sub a0, a0, a1
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBB-LABEL: abs32:			; RV32ZBB-LABEL: abs32:
	; RV32ZBB: # %bb.0:			; RV32ZBB: # %bb.0:
	; RV32ZBB-NEXT: neg a1, a0			; RV32ZBB-NEXT: neg a1, a0
	; RV32ZBB-NEXT: max a0, a0, a1			; RV32ZBB-NEXT: max a0, a0, a1
	; RV32ZBB-NEXT: ret			; RV32ZBB-NEXT: ret
	;			;
	; RV32ZBT-LABEL: abs32:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: srai a1, a0, 31
	; RV32ZBT-NEXT: xor a0, a0, a1
	; RV32ZBT-NEXT: sub a0, a0, a1
	; RV32ZBT-NEXT: ret
	;
	; RV64I-LABEL: abs32:			; RV64I-LABEL: abs32:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: sraiw a1, a0, 31			; RV64I-NEXT: sraiw a1, a0, 31
	; RV64I-NEXT: xor a0, a0, a1			; RV64I-NEXT: xor a0, a0, a1
	; RV64I-NEXT: subw a0, a0, a1			; RV64I-NEXT: subw a0, a0, a1
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;			;
	; RV64ZBB-LABEL: abs32:			; RV64ZBB-LABEL: abs32:
	; RV64ZBB: # %bb.0:			; RV64ZBB: # %bb.0:
	; RV64ZBB-NEXT: sext.w a0, a0			; RV64ZBB-NEXT: sext.w a0, a0
	; RV64ZBB-NEXT: neg a1, a0			; RV64ZBB-NEXT: neg a1, a0
	; RV64ZBB-NEXT: max a0, a0, a1			; RV64ZBB-NEXT: max a0, a0, a1
	; RV64ZBB-NEXT: ret			; RV64ZBB-NEXT: ret
	;
	; RV64ZBT-LABEL: abs32:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: sraiw a1, a0, 31
	; RV64ZBT-NEXT: xor a0, a0, a1
	; RV64ZBT-NEXT: subw a0, a0, a1
	; RV64ZBT-NEXT: ret
	%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)			%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
	ret i32 %abs			ret i32 %abs
	}			}

	define i32 @select_abs32(i32 %x) {			define i32 @select_abs32(i32 %x) {
	; RV32I-LABEL: select_abs32:			; RV32I-LABEL: select_abs32:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	; RV32I-NEXT: srai a1, a0, 31			; RV32I-NEXT: srai a1, a0, 31
	; RV32I-NEXT: xor a0, a0, a1			; RV32I-NEXT: xor a0, a0, a1
	; RV32I-NEXT: sub a0, a0, a1			; RV32I-NEXT: sub a0, a0, a1
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBB-LABEL: select_abs32:			; RV32ZBB-LABEL: select_abs32:
	; RV32ZBB: # %bb.0:			; RV32ZBB: # %bb.0:
	; RV32ZBB-NEXT: neg a1, a0			; RV32ZBB-NEXT: neg a1, a0
	; RV32ZBB-NEXT: max a0, a0, a1			; RV32ZBB-NEXT: max a0, a0, a1
	; RV32ZBB-NEXT: ret			; RV32ZBB-NEXT: ret
	;			;
	; RV32ZBT-LABEL: select_abs32:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: srai a1, a0, 31
	; RV32ZBT-NEXT: xor a0, a0, a1
	; RV32ZBT-NEXT: sub a0, a0, a1
	; RV32ZBT-NEXT: ret
	;
	; RV64I-LABEL: select_abs32:			; RV64I-LABEL: select_abs32:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: sraiw a1, a0, 31			; RV64I-NEXT: sraiw a1, a0, 31
	; RV64I-NEXT: xor a0, a0, a1			; RV64I-NEXT: xor a0, a0, a1
	; RV64I-NEXT: subw a0, a0, a1			; RV64I-NEXT: subw a0, a0, a1
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;			;
	; RV64ZBB-LABEL: select_abs32:			; RV64ZBB-LABEL: select_abs32:
	; RV64ZBB: # %bb.0:			; RV64ZBB: # %bb.0:
	; RV64ZBB-NEXT: sext.w a0, a0			; RV64ZBB-NEXT: sext.w a0, a0
	; RV64ZBB-NEXT: neg a1, a0			; RV64ZBB-NEXT: neg a1, a0
	; RV64ZBB-NEXT: max a0, a0, a1			; RV64ZBB-NEXT: max a0, a0, a1
	; RV64ZBB-NEXT: ret			; RV64ZBB-NEXT: ret
	;
	; RV64ZBT-LABEL: select_abs32:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: sraiw a1, a0, 31
	; RV64ZBT-NEXT: xor a0, a0, a1
	; RV64ZBT-NEXT: subw a0, a0, a1
	; RV64ZBT-NEXT: ret
	%1 = icmp slt i32 %x, 0			%1 = icmp slt i32 %x, 0
	%2 = sub nsw i32 0, %x			%2 = sub nsw i32 0, %x
	%3 = select i1 %1, i32 %2, i32 %x			%3 = select i1 %1, i32 %2, i32 %x
	ret i32 %3			ret i32 %3
	}			}

	define i64 @abs64(i64 %x) {			define i64 @abs64(i64 %x) {
	; RV32I-LABEL: abs64:			; RV32I-LABEL: abs64:
	Show All 13 Lines
	; RV32ZBB-NEXT: # %bb.1:			; RV32ZBB-NEXT: # %bb.1:
	; RV32ZBB-NEXT: snez a2, a0			; RV32ZBB-NEXT: snez a2, a0
	; RV32ZBB-NEXT: neg a0, a0			; RV32ZBB-NEXT: neg a0, a0
	; RV32ZBB-NEXT: add a1, a1, a2			; RV32ZBB-NEXT: add a1, a1, a2
	; RV32ZBB-NEXT: neg a1, a1			; RV32ZBB-NEXT: neg a1, a1
	; RV32ZBB-NEXT: .LBB6_2:			; RV32ZBB-NEXT: .LBB6_2:
	; RV32ZBB-NEXT: ret			; RV32ZBB-NEXT: ret
	;			;
	; RV32ZBT-LABEL: abs64:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: neg a2, a0
	; RV32ZBT-NEXT: slti a3, a1, 0
	; RV32ZBT-NEXT: cmov a2, a3, a2, a0
	; RV32ZBT-NEXT: snez a0, a0
	; RV32ZBT-NEXT: add a0, a1, a0
	; RV32ZBT-NEXT: neg a0, a0
	; RV32ZBT-NEXT: cmov a1, a3, a0, a1
	; RV32ZBT-NEXT: mv a0, a2
	; RV32ZBT-NEXT: ret
	;
	; RV64I-LABEL: abs64:			; RV64I-LABEL: abs64:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: srai a1, a0, 63			; RV64I-NEXT: srai a1, a0, 63
	; RV64I-NEXT: xor a0, a0, a1			; RV64I-NEXT: xor a0, a0, a1
	; RV64I-NEXT: sub a0, a0, a1			; RV64I-NEXT: sub a0, a0, a1
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;			;
	; RV64ZBB-LABEL: abs64:			; RV64ZBB-LABEL: abs64:
	; RV64ZBB: # %bb.0:			; RV64ZBB: # %bb.0:
	; RV64ZBB-NEXT: neg a1, a0			; RV64ZBB-NEXT: neg a1, a0
	; RV64ZBB-NEXT: max a0, a0, a1			; RV64ZBB-NEXT: max a0, a0, a1
	; RV64ZBB-NEXT: ret			; RV64ZBB-NEXT: ret
	;
	; RV64ZBT-LABEL: abs64:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: srai a1, a0, 63
	; RV64ZBT-NEXT: xor a0, a0, a1
	; RV64ZBT-NEXT: sub a0, a0, a1
	; RV64ZBT-NEXT: ret
	%abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)			%abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
	ret i64 %abs			ret i64 %abs
	}			}

	define i64 @select_abs64(i64 %x) {			define i64 @select_abs64(i64 %x) {
	; RV32I-LABEL: select_abs64:			; RV32I-LABEL: select_abs64:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	; RV32I-NEXT: bgez a1, .LBB7_2			; RV32I-NEXT: bgez a1, .LBB7_2
	Show All 11 Lines
	; RV32ZBB-NEXT: # %bb.1:			; RV32ZBB-NEXT: # %bb.1:
	; RV32ZBB-NEXT: snez a2, a0			; RV32ZBB-NEXT: snez a2, a0
	; RV32ZBB-NEXT: neg a0, a0			; RV32ZBB-NEXT: neg a0, a0
	; RV32ZBB-NEXT: add a1, a1, a2			; RV32ZBB-NEXT: add a1, a1, a2
	; RV32ZBB-NEXT: neg a1, a1			; RV32ZBB-NEXT: neg a1, a1
	; RV32ZBB-NEXT: .LBB7_2:			; RV32ZBB-NEXT: .LBB7_2:
	; RV32ZBB-NEXT: ret			; RV32ZBB-NEXT: ret
	;			;
	; RV32ZBT-LABEL: select_abs64:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: neg a2, a0
	; RV32ZBT-NEXT: slti a3, a1, 0
	; RV32ZBT-NEXT: cmov a2, a3, a2, a0
	; RV32ZBT-NEXT: snez a0, a0
	; RV32ZBT-NEXT: add a0, a1, a0
	; RV32ZBT-NEXT: neg a0, a0
	; RV32ZBT-NEXT: cmov a1, a3, a0, a1
	; RV32ZBT-NEXT: mv a0, a2
	; RV32ZBT-NEXT: ret
	;
	; RV64I-LABEL: select_abs64:			; RV64I-LABEL: select_abs64:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: srai a1, a0, 63			; RV64I-NEXT: srai a1, a0, 63
	; RV64I-NEXT: xor a0, a0, a1			; RV64I-NEXT: xor a0, a0, a1
	; RV64I-NEXT: sub a0, a0, a1			; RV64I-NEXT: sub a0, a0, a1
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;			;
	; RV64ZBB-LABEL: select_abs64:			; RV64ZBB-LABEL: select_abs64:
	; RV64ZBB: # %bb.0:			; RV64ZBB: # %bb.0:
	; RV64ZBB-NEXT: neg a1, a0			; RV64ZBB-NEXT: neg a1, a0
	; RV64ZBB-NEXT: max a0, a0, a1			; RV64ZBB-NEXT: max a0, a0, a1
	; RV64ZBB-NEXT: ret			; RV64ZBB-NEXT: ret
	;
	; RV64ZBT-LABEL: select_abs64:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: srai a1, a0, 63
	; RV64ZBT-NEXT: xor a0, a0, a1
	; RV64ZBT-NEXT: sub a0, a0, a1
	; RV64ZBT-NEXT: ret
	%1 = icmp slt i64 %x, 0			%1 = icmp slt i64 %x, 0
	%2 = sub nsw i64 0, %x			%2 = sub nsw i64 0, %x
	%3 = select i1 %1, i64 %2, i64 %x			%3 = select i1 %1, i64 %2, i64 %x
	ret i64 %3			ret i64 %3
	}			}

	define i128 @abs128(i128 %x) {			define i128 @abs128(i128 %x) {
	; RV32I-LABEL: abs128:			; RV32I-LABEL: abs128:
	▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
	; RV32ZBB-NEXT: neg a3, a3			; RV32ZBB-NEXT: neg a3, a3
	; RV32ZBB-NEXT: .LBB8_4:			; RV32ZBB-NEXT: .LBB8_4:
	; RV32ZBB-NEXT: sw a3, 0(a0)			; RV32ZBB-NEXT: sw a3, 0(a0)
	; RV32ZBB-NEXT: sw a1, 8(a0)			; RV32ZBB-NEXT: sw a1, 8(a0)
	; RV32ZBB-NEXT: sw a2, 4(a0)			; RV32ZBB-NEXT: sw a2, 4(a0)
	; RV32ZBB-NEXT: sw a4, 12(a0)			; RV32ZBB-NEXT: sw a4, 12(a0)
	; RV32ZBB-NEXT: ret			; RV32ZBB-NEXT: ret
	;			;
	; RV32ZBT-LABEL: abs128:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: lw a2, 0(a1)
	; RV32ZBT-NEXT: lw a3, 4(a1)
	; RV32ZBT-NEXT: lw a4, 12(a1)
	; RV32ZBT-NEXT: lw a1, 8(a1)
	; RV32ZBT-NEXT: snez a5, a2
	; RV32ZBT-NEXT: snez a6, a3
	; RV32ZBT-NEXT: cmov a6, a3, a6, a5
	; RV32ZBT-NEXT: neg a7, a1
	; RV32ZBT-NEXT: sltu t0, a7, a6
	; RV32ZBT-NEXT: snez t1, a1
	; RV32ZBT-NEXT: add t1, a4, t1
	; RV32ZBT-NEXT: add t0, t1, t0
	; RV32ZBT-NEXT: neg t0, t0
	; RV32ZBT-NEXT: slti t1, a4, 0
	; RV32ZBT-NEXT: cmov a4, t1, t0, a4
	; RV32ZBT-NEXT: sub a6, a7, a6
	; RV32ZBT-NEXT: cmov a1, t1, a6, a1
	; RV32ZBT-NEXT: add a5, a3, a5
	; RV32ZBT-NEXT: neg a5, a5
	; RV32ZBT-NEXT: cmov a3, t1, a5, a3
	; RV32ZBT-NEXT: neg a5, a2
	; RV32ZBT-NEXT: cmov a2, t1, a5, a2
	; RV32ZBT-NEXT: sw a2, 0(a0)
	; RV32ZBT-NEXT: sw a1, 8(a0)
	; RV32ZBT-NEXT: sw a3, 4(a0)
	; RV32ZBT-NEXT: sw a4, 12(a0)
	; RV32ZBT-NEXT: ret
	;
	; RV64I-LABEL: abs128:			; RV64I-LABEL: abs128:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: bgez a1, .LBB8_2			; RV64I-NEXT: bgez a1, .LBB8_2
	; RV64I-NEXT: # %bb.1:			; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: snez a2, a0			; RV64I-NEXT: snez a2, a0
	; RV64I-NEXT: neg a0, a0			; RV64I-NEXT: neg a0, a0
	; RV64I-NEXT: add a1, a1, a2			; RV64I-NEXT: add a1, a1, a2
	; RV64I-NEXT: neg a1, a1			; RV64I-NEXT: neg a1, a1
	; RV64I-NEXT: .LBB8_2:			; RV64I-NEXT: .LBB8_2:
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;			;
	; RV64ZBB-LABEL: abs128:			; RV64ZBB-LABEL: abs128:
	; RV64ZBB: # %bb.0:			; RV64ZBB: # %bb.0:
	; RV64ZBB-NEXT: bgez a1, .LBB8_2			; RV64ZBB-NEXT: bgez a1, .LBB8_2
	; RV64ZBB-NEXT: # %bb.1:			; RV64ZBB-NEXT: # %bb.1:
	; RV64ZBB-NEXT: snez a2, a0			; RV64ZBB-NEXT: snez a2, a0
	; RV64ZBB-NEXT: neg a0, a0			; RV64ZBB-NEXT: neg a0, a0
	; RV64ZBB-NEXT: add a1, a1, a2			; RV64ZBB-NEXT: add a1, a1, a2
	; RV64ZBB-NEXT: neg a1, a1			; RV64ZBB-NEXT: neg a1, a1
	; RV64ZBB-NEXT: .LBB8_2:			; RV64ZBB-NEXT: .LBB8_2:
	; RV64ZBB-NEXT: ret			; RV64ZBB-NEXT: ret
	;
	; RV64ZBT-LABEL: abs128:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: neg a2, a0
	; RV64ZBT-NEXT: slti a3, a1, 0
	; RV64ZBT-NEXT: cmov a2, a3, a2, a0
	; RV64ZBT-NEXT: snez a0, a0
	; RV64ZBT-NEXT: add a0, a1, a0
	; RV64ZBT-NEXT: neg a0, a0
	; RV64ZBT-NEXT: cmov a1, a3, a0, a1
	; RV64ZBT-NEXT: mv a0, a2
	; RV64ZBT-NEXT: ret
	%abs = tail call i128 @llvm.abs.i128(i128 %x, i1 true)			%abs = tail call i128 @llvm.abs.i128(i128 %x, i1 true)
	ret i128 %abs			ret i128 %abs
	}			}

	define i128 @select_abs128(i128 %x) {			define i128 @select_abs128(i128 %x) {
	; RV32I-LABEL: select_abs128:			; RV32I-LABEL: select_abs128:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	; RV32I-NEXT: lw a3, 0(a1)			; RV32I-NEXT: lw a3, 0(a1)
	▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
	; RV32ZBB-NEXT: neg a3, a3			; RV32ZBB-NEXT: neg a3, a3
	; RV32ZBB-NEXT: .LBB9_4:			; RV32ZBB-NEXT: .LBB9_4:
	; RV32ZBB-NEXT: sw a3, 0(a0)			; RV32ZBB-NEXT: sw a3, 0(a0)
	; RV32ZBB-NEXT: sw a1, 8(a0)			; RV32ZBB-NEXT: sw a1, 8(a0)
	; RV32ZBB-NEXT: sw a2, 4(a0)			; RV32ZBB-NEXT: sw a2, 4(a0)
	; RV32ZBB-NEXT: sw a4, 12(a0)			; RV32ZBB-NEXT: sw a4, 12(a0)
	; RV32ZBB-NEXT: ret			; RV32ZBB-NEXT: ret
	;			;
	; RV32ZBT-LABEL: select_abs128:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: lw a2, 0(a1)
	; RV32ZBT-NEXT: lw a3, 4(a1)
	; RV32ZBT-NEXT: lw a4, 12(a1)
	; RV32ZBT-NEXT: lw a1, 8(a1)
	; RV32ZBT-NEXT: snez a5, a2
	; RV32ZBT-NEXT: snez a6, a3
	; RV32ZBT-NEXT: cmov a6, a3, a6, a5
	; RV32ZBT-NEXT: neg a7, a1
	; RV32ZBT-NEXT: sltu t0, a7, a6
	; RV32ZBT-NEXT: snez t1, a1
	; RV32ZBT-NEXT: add t1, a4, t1
	; RV32ZBT-NEXT: add t0, t1, t0
	; RV32ZBT-NEXT: neg t0, t0
	; RV32ZBT-NEXT: slti t1, a4, 0
	; RV32ZBT-NEXT: cmov a4, t1, t0, a4
	; RV32ZBT-NEXT: sub a6, a7, a6
	; RV32ZBT-NEXT: cmov a1, t1, a6, a1
	; RV32ZBT-NEXT: add a5, a3, a5
	; RV32ZBT-NEXT: neg a5, a5
	; RV32ZBT-NEXT: cmov a3, t1, a5, a3
	; RV32ZBT-NEXT: neg a5, a2
	; RV32ZBT-NEXT: cmov a2, t1, a5, a2
	; RV32ZBT-NEXT: sw a2, 0(a0)
	; RV32ZBT-NEXT: sw a1, 8(a0)
	; RV32ZBT-NEXT: sw a3, 4(a0)
	; RV32ZBT-NEXT: sw a4, 12(a0)
	; RV32ZBT-NEXT: ret
	;
	; RV64I-LABEL: select_abs128:			; RV64I-LABEL: select_abs128:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: bgez a1, .LBB9_2			; RV64I-NEXT: bgez a1, .LBB9_2
	; RV64I-NEXT: # %bb.1:			; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: snez a2, a0			; RV64I-NEXT: snez a2, a0
	; RV64I-NEXT: neg a0, a0			; RV64I-NEXT: neg a0, a0
	; RV64I-NEXT: add a1, a1, a2			; RV64I-NEXT: add a1, a1, a2
	; RV64I-NEXT: neg a1, a1			; RV64I-NEXT: neg a1, a1
	; RV64I-NEXT: .LBB9_2:			; RV64I-NEXT: .LBB9_2:
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;			;
	; RV64ZBB-LABEL: select_abs128:			; RV64ZBB-LABEL: select_abs128:
	; RV64ZBB: # %bb.0:			; RV64ZBB: # %bb.0:
	; RV64ZBB-NEXT: bgez a1, .LBB9_2			; RV64ZBB-NEXT: bgez a1, .LBB9_2
	; RV64ZBB-NEXT: # %bb.1:			; RV64ZBB-NEXT: # %bb.1:
	; RV64ZBB-NEXT: snez a2, a0			; RV64ZBB-NEXT: snez a2, a0
	; RV64ZBB-NEXT: neg a0, a0			; RV64ZBB-NEXT: neg a0, a0
	; RV64ZBB-NEXT: add a1, a1, a2			; RV64ZBB-NEXT: add a1, a1, a2
	; RV64ZBB-NEXT: neg a1, a1			; RV64ZBB-NEXT: neg a1, a1
	; RV64ZBB-NEXT: .LBB9_2:			; RV64ZBB-NEXT: .LBB9_2:
	; RV64ZBB-NEXT: ret			; RV64ZBB-NEXT: ret
	;
	; RV64ZBT-LABEL: select_abs128:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: neg a2, a0
	; RV64ZBT-NEXT: slti a3, a1, 0
	; RV64ZBT-NEXT: cmov a2, a3, a2, a0
	; RV64ZBT-NEXT: snez a0, a0
	; RV64ZBT-NEXT: add a0, a1, a0
	; RV64ZBT-NEXT: neg a0, a0
	; RV64ZBT-NEXT: cmov a1, a3, a0, a1
	; RV64ZBT-NEXT: mv a0, a2
	; RV64ZBT-NEXT: ret
	%1 = icmp slt i128 %x, 0			%1 = icmp slt i128 %x, 0
	%2 = sub nsw i128 0, %x			%2 = sub nsw i128 0, %x
	%3 = select i1 %1, i128 %2, i128 %x			%3 = select i1 %1, i128 %2, i128 %x
	ret i128 %3			ret i128 %3
	}			}

	define i64 @zext_abs32(i32 %x) {			define i64 @zext_abs32(i32 %x) {
	; RV32I-LABEL: zext_abs32:			; RV32I-LABEL: zext_abs32:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	; RV32I-NEXT: srai a1, a0, 31			; RV32I-NEXT: srai a1, a0, 31
	; RV32I-NEXT: xor a0, a0, a1			; RV32I-NEXT: xor a0, a0, a1
	; RV32I-NEXT: sub a0, a0, a1			; RV32I-NEXT: sub a0, a0, a1
	; RV32I-NEXT: li a1, 0			; RV32I-NEXT: li a1, 0
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBB-LABEL: zext_abs32:			; RV32ZBB-LABEL: zext_abs32:
	; RV32ZBB: # %bb.0:			; RV32ZBB: # %bb.0:
	; RV32ZBB-NEXT: neg a1, a0			; RV32ZBB-NEXT: neg a1, a0
	; RV32ZBB-NEXT: max a0, a0, a1			; RV32ZBB-NEXT: max a0, a0, a1
	; RV32ZBB-NEXT: li a1, 0			; RV32ZBB-NEXT: li a1, 0
	; RV32ZBB-NEXT: ret			; RV32ZBB-NEXT: ret
	;			;
	; RV32ZBT-LABEL: zext_abs32:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: srai a1, a0, 31
	; RV32ZBT-NEXT: xor a0, a0, a1
	; RV32ZBT-NEXT: sub a0, a0, a1
	; RV32ZBT-NEXT: li a1, 0
	; RV32ZBT-NEXT: ret
	;
	; RV64I-LABEL: zext_abs32:			; RV64I-LABEL: zext_abs32:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: sraiw a1, a0, 31			; RV64I-NEXT: sraiw a1, a0, 31
	; RV64I-NEXT: xor a0, a0, a1			; RV64I-NEXT: xor a0, a0, a1
	; RV64I-NEXT: subw a0, a0, a1			; RV64I-NEXT: subw a0, a0, a1
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;			;
	; RV64ZBB-LABEL: zext_abs32:			; RV64ZBB-LABEL: zext_abs32:
	; RV64ZBB: # %bb.0:			; RV64ZBB: # %bb.0:
	; RV64ZBB-NEXT: sext.w a1, a0			; RV64ZBB-NEXT: sext.w a1, a0
	; RV64ZBB-NEXT: negw a0, a0			; RV64ZBB-NEXT: negw a0, a0
	; RV64ZBB-NEXT: max a0, a1, a0			; RV64ZBB-NEXT: max a0, a1, a0
	; RV64ZBB-NEXT: ret			; RV64ZBB-NEXT: ret
	;
	; RV64ZBT-LABEL: zext_abs32:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: sraiw a1, a0, 31
	; RV64ZBT-NEXT: xor a0, a0, a1
	; RV64ZBT-NEXT: subw a0, a0, a1
	; RV64ZBT-NEXT: ret
	%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)			%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
	%zext = zext i32 %abs to i64			%zext = zext i32 %abs to i64
	ret i64 %zext			ret i64 %zext
	}			}

llvm/test/CodeGen/RISCV/neg-abs.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s --check-prefix=RV32I			; RUN: \| FileCheck %s --check-prefix=RV32I
	; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s --check-prefix=RV32ZBB			; RUN: \| FileCheck %s --check-prefix=RV32ZBB
	; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s --check-prefix=RV32IBT
	; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s --check-prefix=RV64I			; RUN: \| FileCheck %s --check-prefix=RV64I
	; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s --check-prefix=RV64ZBB			; RUN: \| FileCheck %s --check-prefix=RV64ZBB
	; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s --check-prefix=RV64IBT

	declare i32 @llvm.abs.i32(i32, i1 immarg)			declare i32 @llvm.abs.i32(i32, i1 immarg)
	declare i64 @llvm.abs.i64(i64, i1 immarg)			declare i64 @llvm.abs.i64(i64, i1 immarg)

	define i32 @neg_abs32(i32 %x) {			define i32 @neg_abs32(i32 %x) {
	; RV32I-LABEL: neg_abs32:			; RV32I-LABEL: neg_abs32:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	; RV32I-NEXT: srai a1, a0, 31			; RV32I-NEXT: srai a1, a0, 31
	; RV32I-NEXT: xor a0, a0, a1			; RV32I-NEXT: xor a0, a0, a1
	; RV32I-NEXT: sub a0, a1, a0			; RV32I-NEXT: sub a0, a1, a0
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBB-LABEL: neg_abs32:			; RV32ZBB-LABEL: neg_abs32:
	; RV32ZBB: # %bb.0:			; RV32ZBB: # %bb.0:
	; RV32ZBB-NEXT: neg a1, a0			; RV32ZBB-NEXT: neg a1, a0
	; RV32ZBB-NEXT: min a0, a0, a1			; RV32ZBB-NEXT: min a0, a0, a1
	; RV32ZBB-NEXT: ret			; RV32ZBB-NEXT: ret
	;			;
	; RV32IBT-LABEL: neg_abs32:
	; RV32IBT: # %bb.0:
	; RV32IBT-NEXT: srai a1, a0, 31
	; RV32IBT-NEXT: xor a0, a0, a1
	; RV32IBT-NEXT: sub a0, a1, a0
	; RV32IBT-NEXT: ret
	;
	; RV64I-LABEL: neg_abs32:			; RV64I-LABEL: neg_abs32:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: sraiw a1, a0, 31			; RV64I-NEXT: sraiw a1, a0, 31
	; RV64I-NEXT: xor a0, a0, a1			; RV64I-NEXT: xor a0, a0, a1
	; RV64I-NEXT: subw a0, a1, a0			; RV64I-NEXT: subw a0, a1, a0
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;			;
	; RV64ZBB-LABEL: neg_abs32:			; RV64ZBB-LABEL: neg_abs32:
	; RV64ZBB: # %bb.0:			; RV64ZBB: # %bb.0:
	; RV64ZBB-NEXT: sraiw a1, a0, 31			; RV64ZBB-NEXT: sraiw a1, a0, 31
	; RV64ZBB-NEXT: xor a0, a0, a1			; RV64ZBB-NEXT: xor a0, a0, a1
	; RV64ZBB-NEXT: subw a0, a1, a0			; RV64ZBB-NEXT: subw a0, a1, a0
	; RV64ZBB-NEXT: ret			; RV64ZBB-NEXT: ret
	;
	; RV64IBT-LABEL: neg_abs32:
	; RV64IBT: # %bb.0:
	; RV64IBT-NEXT: sraiw a1, a0, 31
	; RV64IBT-NEXT: xor a0, a0, a1
	; RV64IBT-NEXT: subw a0, a1, a0
	; RV64IBT-NEXT: ret
	%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)			%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
	%neg = sub nsw i32 0, %abs			%neg = sub nsw i32 0, %abs
	ret i32 %neg			ret i32 %neg
	}			}

	define i32 @select_neg_abs32(i32 %x) {			define i32 @select_neg_abs32(i32 %x) {
	; RV32I-LABEL: select_neg_abs32:			; RV32I-LABEL: select_neg_abs32:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	; RV32I-NEXT: srai a1, a0, 31			; RV32I-NEXT: srai a1, a0, 31
	; RV32I-NEXT: xor a0, a0, a1			; RV32I-NEXT: xor a0, a0, a1
	; RV32I-NEXT: sub a0, a1, a0			; RV32I-NEXT: sub a0, a1, a0
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBB-LABEL: select_neg_abs32:			; RV32ZBB-LABEL: select_neg_abs32:
	; RV32ZBB: # %bb.0:			; RV32ZBB: # %bb.0:
	; RV32ZBB-NEXT: neg a1, a0			; RV32ZBB-NEXT: neg a1, a0
	; RV32ZBB-NEXT: min a0, a0, a1			; RV32ZBB-NEXT: min a0, a0, a1
	; RV32ZBB-NEXT: ret			; RV32ZBB-NEXT: ret
	;			;
	; RV32IBT-LABEL: select_neg_abs32:
	; RV32IBT: # %bb.0:
	; RV32IBT-NEXT: srai a1, a0, 31
	; RV32IBT-NEXT: xor a0, a0, a1
	; RV32IBT-NEXT: sub a0, a1, a0
	; RV32IBT-NEXT: ret
	;
	; RV64I-LABEL: select_neg_abs32:			; RV64I-LABEL: select_neg_abs32:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: sraiw a1, a0, 31			; RV64I-NEXT: sraiw a1, a0, 31
	; RV64I-NEXT: xor a0, a0, a1			; RV64I-NEXT: xor a0, a0, a1
	; RV64I-NEXT: subw a0, a1, a0			; RV64I-NEXT: subw a0, a1, a0
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;			;
	; RV64ZBB-LABEL: select_neg_abs32:			; RV64ZBB-LABEL: select_neg_abs32:
	; RV64ZBB: # %bb.0:			; RV64ZBB: # %bb.0:
	; RV64ZBB-NEXT: sraiw a1, a0, 31			; RV64ZBB-NEXT: sraiw a1, a0, 31
	; RV64ZBB-NEXT: xor a0, a0, a1			; RV64ZBB-NEXT: xor a0, a0, a1
	; RV64ZBB-NEXT: subw a0, a1, a0			; RV64ZBB-NEXT: subw a0, a1, a0
	; RV64ZBB-NEXT: ret			; RV64ZBB-NEXT: ret
	;
	; RV64IBT-LABEL: select_neg_abs32:
	; RV64IBT: # %bb.0:
	; RV64IBT-NEXT: sraiw a1, a0, 31
	; RV64IBT-NEXT: xor a0, a0, a1
	; RV64IBT-NEXT: subw a0, a1, a0
	; RV64IBT-NEXT: ret
	%1 = icmp slt i32 %x, 0			%1 = icmp slt i32 %x, 0
	%2 = sub nsw i32 0, %x			%2 = sub nsw i32 0, %x
	%3 = select i1 %1, i32 %x, i32 %2			%3 = select i1 %1, i32 %x, i32 %2
	ret i32 %3			ret i32 %3
	}			}

	define i64 @neg_abs64(i64 %x) {			define i64 @neg_abs64(i64 %x) {
	; RV32I-LABEL: neg_abs64:			; RV32I-LABEL: neg_abs64:
	Show All 13 Lines
	; RV32ZBB-NEXT: xor a0, a0, a2			; RV32ZBB-NEXT: xor a0, a0, a2
	; RV32ZBB-NEXT: sltu a3, a2, a0			; RV32ZBB-NEXT: sltu a3, a2, a0
	; RV32ZBB-NEXT: xor a1, a1, a2			; RV32ZBB-NEXT: xor a1, a1, a2
	; RV32ZBB-NEXT: sub a1, a2, a1			; RV32ZBB-NEXT: sub a1, a2, a1
	; RV32ZBB-NEXT: sub a1, a1, a3			; RV32ZBB-NEXT: sub a1, a1, a3
	; RV32ZBB-NEXT: sub a0, a2, a0			; RV32ZBB-NEXT: sub a0, a2, a0
	; RV32ZBB-NEXT: ret			; RV32ZBB-NEXT: ret
	;			;
	; RV32IBT-LABEL: neg_abs64:
	; RV32IBT: # %bb.0:
	; RV32IBT-NEXT: srai a2, a1, 31
	; RV32IBT-NEXT: xor a0, a0, a2
	; RV32IBT-NEXT: sltu a3, a2, a0
	; RV32IBT-NEXT: xor a1, a1, a2
	; RV32IBT-NEXT: sub a1, a2, a1
	; RV32IBT-NEXT: sub a1, a1, a3
	; RV32IBT-NEXT: sub a0, a2, a0
	; RV32IBT-NEXT: ret
	;
	; RV64I-LABEL: neg_abs64:			; RV64I-LABEL: neg_abs64:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: srai a1, a0, 63			; RV64I-NEXT: srai a1, a0, 63
	; RV64I-NEXT: xor a0, a0, a1			; RV64I-NEXT: xor a0, a0, a1
	; RV64I-NEXT: sub a0, a1, a0			; RV64I-NEXT: sub a0, a1, a0
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;			;
	; RV64ZBB-LABEL: neg_abs64:			; RV64ZBB-LABEL: neg_abs64:
	; RV64ZBB: # %bb.0:			; RV64ZBB: # %bb.0:
	; RV64ZBB-NEXT: neg a1, a0			; RV64ZBB-NEXT: neg a1, a0
	; RV64ZBB-NEXT: min a0, a0, a1			; RV64ZBB-NEXT: min a0, a0, a1
	; RV64ZBB-NEXT: ret			; RV64ZBB-NEXT: ret
	;
	; RV64IBT-LABEL: neg_abs64:
	; RV64IBT: # %bb.0:
	; RV64IBT-NEXT: srai a1, a0, 63
	; RV64IBT-NEXT: xor a0, a0, a1
	; RV64IBT-NEXT: sub a0, a1, a0
	; RV64IBT-NEXT: ret
	%abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)			%abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
	%neg = sub nsw i64 0, %abs			%neg = sub nsw i64 0, %abs
	ret i64 %neg			ret i64 %neg
	}			}

	define i64 @select_neg_abs64(i64 %x) {			define i64 @select_neg_abs64(i64 %x) {
	; RV32I-LABEL: select_neg_abs64:			; RV32I-LABEL: select_neg_abs64:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	Show All 12 Lines
	; RV32ZBB-NEXT: xor a0, a0, a2			; RV32ZBB-NEXT: xor a0, a0, a2
	; RV32ZBB-NEXT: sltu a3, a2, a0			; RV32ZBB-NEXT: sltu a3, a2, a0
	; RV32ZBB-NEXT: xor a1, a1, a2			; RV32ZBB-NEXT: xor a1, a1, a2
	; RV32ZBB-NEXT: sub a1, a2, a1			; RV32ZBB-NEXT: sub a1, a2, a1
	; RV32ZBB-NEXT: sub a1, a1, a3			; RV32ZBB-NEXT: sub a1, a1, a3
	; RV32ZBB-NEXT: sub a0, a2, a0			; RV32ZBB-NEXT: sub a0, a2, a0
	; RV32ZBB-NEXT: ret			; RV32ZBB-NEXT: ret
	;			;
	; RV32IBT-LABEL: select_neg_abs64:
	; RV32IBT: # %bb.0:
	; RV32IBT-NEXT: srai a2, a1, 31
	; RV32IBT-NEXT: xor a0, a0, a2
	; RV32IBT-NEXT: sltu a3, a2, a0
	; RV32IBT-NEXT: xor a1, a1, a2
	; RV32IBT-NEXT: sub a1, a2, a1
	; RV32IBT-NEXT: sub a1, a1, a3
	; RV32IBT-NEXT: sub a0, a2, a0
	; RV32IBT-NEXT: ret
	;
	; RV64I-LABEL: select_neg_abs64:			; RV64I-LABEL: select_neg_abs64:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: srai a1, a0, 63			; RV64I-NEXT: srai a1, a0, 63
	; RV64I-NEXT: xor a0, a0, a1			; RV64I-NEXT: xor a0, a0, a1
	; RV64I-NEXT: sub a0, a1, a0			; RV64I-NEXT: sub a0, a1, a0
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;			;
	; RV64ZBB-LABEL: select_neg_abs64:			; RV64ZBB-LABEL: select_neg_abs64:
	; RV64ZBB: # %bb.0:			; RV64ZBB: # %bb.0:
	; RV64ZBB-NEXT: neg a1, a0			; RV64ZBB-NEXT: neg a1, a0
	; RV64ZBB-NEXT: min a0, a0, a1			; RV64ZBB-NEXT: min a0, a0, a1
	; RV64ZBB-NEXT: ret			; RV64ZBB-NEXT: ret
	;
	; RV64IBT-LABEL: select_neg_abs64:
	; RV64IBT: # %bb.0:
	; RV64IBT-NEXT: srai a1, a0, 63
	; RV64IBT-NEXT: xor a0, a0, a1
	; RV64IBT-NEXT: sub a0, a1, a0
	; RV64IBT-NEXT: ret
	%1 = icmp slt i64 %x, 0			%1 = icmp slt i64 %x, 0
	%2 = sub nsw i64 0, %x			%2 = sub nsw i64 0, %x
	%3 = select i1 %1, i64 %x, i64 %2			%3 = select i1 %1, i64 %x, i64 %2
	ret i64 %3			ret i64 %3
	}			}

	define i32 @neg_abs32_multiuse(i32 %x, i32* %y) {			define i32 @neg_abs32_multiuse(i32 %x, i32* %y) {
	; RV32I-LABEL: neg_abs32_multiuse:			; RV32I-LABEL: neg_abs32_multiuse:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	; RV32I-NEXT: srai a2, a0, 31			; RV32I-NEXT: srai a2, a0, 31
	; RV32I-NEXT: xor a0, a0, a2			; RV32I-NEXT: xor a0, a0, a2
	; RV32I-NEXT: sub a2, a0, a2			; RV32I-NEXT: sub a2, a0, a2
	; RV32I-NEXT: neg a0, a2			; RV32I-NEXT: neg a0, a2
	; RV32I-NEXT: sw a2, 0(a1)			; RV32I-NEXT: sw a2, 0(a1)
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBB-LABEL: neg_abs32_multiuse:			; RV32ZBB-LABEL: neg_abs32_multiuse:
	; RV32ZBB: # %bb.0:			; RV32ZBB: # %bb.0:
	; RV32ZBB-NEXT: neg a2, a0			; RV32ZBB-NEXT: neg a2, a0
	; RV32ZBB-NEXT: max a2, a0, a2			; RV32ZBB-NEXT: max a2, a0, a2
	; RV32ZBB-NEXT: neg a0, a2			; RV32ZBB-NEXT: neg a0, a2
	; RV32ZBB-NEXT: sw a2, 0(a1)			; RV32ZBB-NEXT: sw a2, 0(a1)
	; RV32ZBB-NEXT: ret			; RV32ZBB-NEXT: ret
	;			;
	; RV32IBT-LABEL: neg_abs32_multiuse:
	; RV32IBT: # %bb.0:
	; RV32IBT-NEXT: srai a2, a0, 31
	; RV32IBT-NEXT: xor a0, a0, a2
	; RV32IBT-NEXT: sub a2, a0, a2
	; RV32IBT-NEXT: neg a0, a2
	; RV32IBT-NEXT: sw a2, 0(a1)
	; RV32IBT-NEXT: ret
	;
	; RV64I-LABEL: neg_abs32_multiuse:			; RV64I-LABEL: neg_abs32_multiuse:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: sraiw a2, a0, 31			; RV64I-NEXT: sraiw a2, a0, 31
	; RV64I-NEXT: xor a0, a0, a2			; RV64I-NEXT: xor a0, a0, a2
	; RV64I-NEXT: subw a2, a0, a2			; RV64I-NEXT: subw a2, a0, a2
	; RV64I-NEXT: negw a0, a2			; RV64I-NEXT: negw a0, a2
	; RV64I-NEXT: sw a2, 0(a1)			; RV64I-NEXT: sw a2, 0(a1)
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;			;
	; RV64ZBB-LABEL: neg_abs32_multiuse:			; RV64ZBB-LABEL: neg_abs32_multiuse:
	; RV64ZBB: # %bb.0:			; RV64ZBB: # %bb.0:
	; RV64ZBB-NEXT: sext.w a0, a0			; RV64ZBB-NEXT: sext.w a0, a0
	; RV64ZBB-NEXT: neg a2, a0			; RV64ZBB-NEXT: neg a2, a0
	; RV64ZBB-NEXT: max a2, a0, a2			; RV64ZBB-NEXT: max a2, a0, a2
	; RV64ZBB-NEXT: negw a0, a2			; RV64ZBB-NEXT: negw a0, a2
	; RV64ZBB-NEXT: sw a2, 0(a1)			; RV64ZBB-NEXT: sw a2, 0(a1)
	; RV64ZBB-NEXT: ret			; RV64ZBB-NEXT: ret
	;
	; RV64IBT-LABEL: neg_abs32_multiuse:
	; RV64IBT: # %bb.0:
	; RV64IBT-NEXT: sraiw a2, a0, 31
	; RV64IBT-NEXT: xor a0, a0, a2
	; RV64IBT-NEXT: subw a2, a0, a2
	; RV64IBT-NEXT: negw a0, a2
	; RV64IBT-NEXT: sw a2, 0(a1)
	; RV64IBT-NEXT: ret
	%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)			%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
	store i32 %abs, i32* %y			store i32 %abs, i32* %y
	%neg = sub nsw i32 0, %abs			%neg = sub nsw i32 0, %abs
	ret i32 %neg			ret i32 %neg
	}			}

	define i64 @neg_abs64_multiuse(i64 %x, i64* %y) {			define i64 @neg_abs64_multiuse(i64 %x, i64* %y) {
	; RV32I-LABEL: neg_abs64_multiuse:			; RV32I-LABEL: neg_abs64_multiuse:
	Show All 27 Lines
	; RV32ZBB-NEXT: snez a3, a0			; RV32ZBB-NEXT: snez a3, a0
	; RV32ZBB-NEXT: add a3, a1, a3			; RV32ZBB-NEXT: add a3, a1, a3
	; RV32ZBB-NEXT: neg a3, a3			; RV32ZBB-NEXT: neg a3, a3
	; RV32ZBB-NEXT: neg a0, a0			; RV32ZBB-NEXT: neg a0, a0
	; RV32ZBB-NEXT: sw a1, 4(a2)			; RV32ZBB-NEXT: sw a1, 4(a2)
	; RV32ZBB-NEXT: mv a1, a3			; RV32ZBB-NEXT: mv a1, a3
	; RV32ZBB-NEXT: ret			; RV32ZBB-NEXT: ret
	;			;
	; RV32IBT-LABEL: neg_abs64_multiuse:
	; RV32IBT: # %bb.0:
	; RV32IBT-NEXT: snez a3, a0
	; RV32IBT-NEXT: add a3, a1, a3
	; RV32IBT-NEXT: neg a3, a3
	; RV32IBT-NEXT: slti a4, a1, 0
	; RV32IBT-NEXT: cmov a3, a4, a3, a1
	; RV32IBT-NEXT: neg a1, a0
	; RV32IBT-NEXT: cmov a0, a4, a1, a0
	; RV32IBT-NEXT: sw a0, 0(a2)
	; RV32IBT-NEXT: snez a1, a0
	; RV32IBT-NEXT: add a1, a3, a1
	; RV32IBT-NEXT: neg a1, a1
	; RV32IBT-NEXT: neg a0, a0
	; RV32IBT-NEXT: sw a3, 4(a2)
	; RV32IBT-NEXT: ret
	;
	; RV64I-LABEL: neg_abs64_multiuse:			; RV64I-LABEL: neg_abs64_multiuse:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: srai a2, a0, 63			; RV64I-NEXT: srai a2, a0, 63
	; RV64I-NEXT: xor a0, a0, a2			; RV64I-NEXT: xor a0, a0, a2
	; RV64I-NEXT: sub a2, a0, a2			; RV64I-NEXT: sub a2, a0, a2
	; RV64I-NEXT: neg a0, a2			; RV64I-NEXT: neg a0, a2
	; RV64I-NEXT: sd a2, 0(a1)			; RV64I-NEXT: sd a2, 0(a1)
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;			;
	; RV64ZBB-LABEL: neg_abs64_multiuse:			; RV64ZBB-LABEL: neg_abs64_multiuse:
	; RV64ZBB: # %bb.0:			; RV64ZBB: # %bb.0:
	; RV64ZBB-NEXT: neg a2, a0			; RV64ZBB-NEXT: neg a2, a0
	; RV64ZBB-NEXT: max a2, a0, a2			; RV64ZBB-NEXT: max a2, a0, a2
	; RV64ZBB-NEXT: neg a0, a2			; RV64ZBB-NEXT: neg a0, a2
	; RV64ZBB-NEXT: sd a2, 0(a1)			; RV64ZBB-NEXT: sd a2, 0(a1)
	; RV64ZBB-NEXT: ret			; RV64ZBB-NEXT: ret
	;
	; RV64IBT-LABEL: neg_abs64_multiuse:
	; RV64IBT: # %bb.0:
	; RV64IBT-NEXT: srai a2, a0, 63
	; RV64IBT-NEXT: xor a0, a0, a2
	; RV64IBT-NEXT: sub a2, a0, a2
	; RV64IBT-NEXT: neg a0, a2
	; RV64IBT-NEXT: sd a2, 0(a1)
	; RV64IBT-NEXT: ret
	%abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)			%abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
	store i64 %abs, i64* %y			store i64 %abs, i64* %y
	%neg = sub nsw i64 0, %abs			%neg = sub nsw i64 0, %abs
	ret i64 %neg			ret i64 %neg
	}			}

llvm/test/CodeGen/RISCV/rv32zbt-intrinsic.ll

This file was deleted.

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s -check-prefix=RV32ZBT

	declare i32 @llvm.riscv.fsl.i32(i32, i32, i32)

	define i32 @fsl_i32(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32ZBT-LABEL: fsl_i32:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: fsl a0, a0, a1, a2
	; RV32ZBT-NEXT: ret
	%1 = call i32 @llvm.riscv.fsl.i32(i32 %a, i32 %b, i32 %c)
	ret i32 %1
	}

	define i32 @fsl_i32_demandedbits(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32ZBT-LABEL: fsl_i32_demandedbits:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: andi a1, a1, 31
	; RV32ZBT-NEXT: fsl a0, a0, a1, a2
	; RV32ZBT-NEXT: ret
	%bmask = and i32 %b, 95
	%1 = call i32 @llvm.riscv.fsl.i32(i32 %a, i32 %bmask, i32 %c)
	ret i32 %1
	}

	declare i32 @llvm.riscv.fsr.i32(i32, i32, i32)

	define i32 @fsr_i32(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32ZBT-LABEL: fsr_i32:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: fsr a0, a0, a1, a2
	; RV32ZBT-NEXT: ret
	%1 = call i32 @llvm.riscv.fsr.i32(i32 %a, i32 %b, i32 %c)
	ret i32 %1
	}

	define i32 @fsr_i32_demandedbits(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32ZBT-LABEL: fsr_i32_demandedbits:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: andi a1, a1, 31
	; RV32ZBT-NEXT: fsr a0, a0, a1, a2
	; RV32ZBT-NEXT: ret
	%bmask = and i32 %b, 95
	%1 = call i32 @llvm.riscv.fsr.i32(i32 %a, i32 %bmask, i32 %c)
	ret i32 %1
	}

	define i32 @fsli_i32(i32 %a, i32 %b) nounwind {
	; RV32ZBT-LABEL: fsli_i32:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: fsri a0, a1, a0, 27
	; RV32ZBT-NEXT: ret
	%1 = call i32 @llvm.riscv.fsl.i32(i32 %a, i32 %b, i32 5)
	ret i32 %1
	}

	define i32 @fsri_i32(i32 %a, i32 %b) nounwind {
	; RV32ZBT-LABEL: fsri_i32:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: fsri a0, a0, a1, 15
	; RV32ZBT-NEXT: ret
	%1 = call i32 @llvm.riscv.fsr.i32(i32 %a, i32 %b, i32 15)
	ret i32 %1
	}

llvm/test/CodeGen/RISCV/rv32zbt.ll

This file was deleted.

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s -check-prefix=RV32I
	; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s -check-prefix=RV32ZBT

	define i32 @cmix_i32(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: cmix_i32:
	; RV32I: # %bb.0:
	; RV32I-NEXT: and a0, a1, a0
	; RV32I-NEXT: not a1, a1
	; RV32I-NEXT: and a1, a1, a2
	; RV32I-NEXT: or a0, a1, a0
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmix_i32:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: cmix a0, a1, a0, a2
	; RV32ZBT-NEXT: ret
	%and = and i32 %b, %a
	%neg = xor i32 %b, -1
	%and1 = and i32 %neg, %c
	%or = or i32 %and1, %and
	ret i32 %or
	}

	define i32 @cmix_i32_2(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: cmix_i32_2:
	; RV32I: # %bb.0:
	; RV32I-NEXT: xor a0, a0, a2
	; RV32I-NEXT: and a0, a0, a1
	; RV32I-NEXT: xor a0, a0, a2
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmix_i32_2:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: cmix a0, a1, a0, a2
	; RV32ZBT-NEXT: ret
	%xor = xor i32 %a, %c
	%and = and i32 %xor, %b
	%xor1 = xor i32 %and, %c
	ret i32 %xor1
	}

	define i64 @cmix_i64(i64 %a, i64 %b, i64 %c) nounwind {
	; RV32I-LABEL: cmix_i64:
	; RV32I: # %bb.0:
	; RV32I-NEXT: and a1, a3, a1
	; RV32I-NEXT: and a0, a2, a0
	; RV32I-NEXT: not a2, a2
	; RV32I-NEXT: not a3, a3
	; RV32I-NEXT: and a3, a3, a5
	; RV32I-NEXT: and a2, a2, a4
	; RV32I-NEXT: or a0, a2, a0
	; RV32I-NEXT: or a1, a3, a1
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmix_i64:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: cmix a0, a2, a0, a4
	; RV32ZBT-NEXT: cmix a1, a3, a1, a5
	; RV32ZBT-NEXT: ret
	%and = and i64 %b, %a
	%neg = xor i64 %b, -1
	%and1 = and i64 %neg, %c
	%or = or i64 %and1, %and
	ret i64 %or
	}

	define i64 @cmix_i64_2(i64 %a, i64 %b, i64 %c) nounwind {
	; RV32I-LABEL: cmix_i64_2:
	; RV32I: # %bb.0:
	; RV32I-NEXT: xor a0, a0, a4
	; RV32I-NEXT: xor a1, a1, a5
	; RV32I-NEXT: and a1, a1, a3
	; RV32I-NEXT: and a0, a0, a2
	; RV32I-NEXT: xor a0, a0, a4
	; RV32I-NEXT: xor a1, a1, a5
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmix_i64_2:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: cmix a0, a2, a0, a4
	; RV32ZBT-NEXT: cmix a1, a3, a1, a5
	; RV32ZBT-NEXT: ret
	%xor = xor i64 %a, %c
	%and = and i64 %xor, %b
	%xor1 = xor i64 %and, %c
	ret i64 %xor1
	}

	define i32 @cmov_eq_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
	; RV32I-LABEL: cmov_eq_i32:
	; RV32I: # %bb.0:
	; RV32I-NEXT: beq a1, a2, .LBB4_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a3
	; RV32I-NEXT: .LBB4_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_eq_i32:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: xor a1, a1, a2
	; RV32ZBT-NEXT: cmov a0, a1, a3, a0
	; RV32ZBT-NEXT: ret
	%tobool.not = icmp eq i32 %b, %c
	%cond = select i1 %tobool.not, i32 %a, i32 %d
	ret i32 %cond
	}

	define i32 @cmov_eq_i32_constant_zero(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: cmov_eq_i32_constant_zero:
	; RV32I: # %bb.0:
	; RV32I-NEXT: beqz a1, .LBB5_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: .LBB5_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_eq_i32_constant_zero:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: cmov a0, a1, a2, a0
	; RV32ZBT-NEXT: ret
	%tobool.not = icmp eq i32 %b, 0
	%cond = select i1 %tobool.not, i32 %a, i32 %c
	ret i32 %cond
	}

	define i32 @cmov_eq_i32_constant_2048(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: cmov_eq_i32_constant_2048:
	; RV32I: # %bb.0:
	; RV32I-NEXT: lui a3, 1
	; RV32I-NEXT: addi a3, a3, -2048
	; RV32I-NEXT: beq a1, a3, .LBB6_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: .LBB6_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_eq_i32_constant_2048:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: addi a1, a1, -2048
	; RV32ZBT-NEXT: cmov a0, a1, a2, a0
	; RV32ZBT-NEXT: ret
	%tobool.not = icmp eq i32 %b, 2048
	%cond = select i1 %tobool.not, i32 %a, i32 %c
	ret i32 %cond
	}

	define i32 @cmov_eq_i32_constant_neg_2047(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: cmov_eq_i32_constant_neg_2047:
	; RV32I: # %bb.0:
	; RV32I-NEXT: li a3, -2047
	; RV32I-NEXT: beq a1, a3, .LBB7_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: .LBB7_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_eq_i32_constant_neg_2047:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: addi a1, a1, 2047
	; RV32ZBT-NEXT: cmov a0, a1, a2, a0
	; RV32ZBT-NEXT: ret
	%tobool.not = icmp eq i32 %b, -2047
	%cond = select i1 %tobool.not, i32 %a, i32 %c
	ret i32 %cond
	}

	define i32 @cmov_ne_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
	; RV32I-LABEL: cmov_ne_i32:
	; RV32I: # %bb.0:
	; RV32I-NEXT: bne a1, a2, .LBB8_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a3
	; RV32I-NEXT: .LBB8_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_ne_i32:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: xor a1, a1, a2
	; RV32ZBT-NEXT: cmov a0, a1, a0, a3
	; RV32ZBT-NEXT: ret
	%tobool.not = icmp ne i32 %b, %c
	%cond = select i1 %tobool.not, i32 %a, i32 %d
	ret i32 %cond
	}

	define i32 @cmov_ne_i32_constant_zero(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: cmov_ne_i32_constant_zero:
	; RV32I: # %bb.0:
	; RV32I-NEXT: bnez a1, .LBB9_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: .LBB9_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_ne_i32_constant_zero:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: cmov a0, a1, a0, a2
	; RV32ZBT-NEXT: ret
	%tobool.not = icmp ne i32 %b, 0
	%cond = select i1 %tobool.not, i32 %a, i32 %c
	ret i32 %cond
	}

	define i32 @cmov_ne_i32_constant_2048(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: cmov_ne_i32_constant_2048:
	; RV32I: # %bb.0:
	; RV32I-NEXT: lui a3, 1
	; RV32I-NEXT: addi a3, a3, -2048
	; RV32I-NEXT: bne a1, a3, .LBB10_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: .LBB10_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_ne_i32_constant_2048:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: addi a1, a1, -2048
	; RV32ZBT-NEXT: cmov a0, a1, a0, a2
	; RV32ZBT-NEXT: ret
	%tobool.not = icmp ne i32 %b, 2048
	%cond = select i1 %tobool.not, i32 %a, i32 %c
	ret i32 %cond
	}

	define i32 @cmov_ne_i32_constant_neg_2047(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: cmov_ne_i32_constant_neg_2047:
	; RV32I: # %bb.0:
	; RV32I-NEXT: li a3, -2047
	; RV32I-NEXT: bne a1, a3, .LBB11_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: .LBB11_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_ne_i32_constant_neg_2047:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: addi a1, a1, 2047
	; RV32ZBT-NEXT: cmov a0, a1, a0, a2
	; RV32ZBT-NEXT: ret
	%tobool.not = icmp ne i32 %b, -2047
	%cond = select i1 %tobool.not, i32 %a, i32 %c
	ret i32 %cond
	}

	define i32 @cmov_sle_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
	; RV32I-LABEL: cmov_sle_i32:
	; RV32I: # %bb.0:
	; RV32I-NEXT: bge a2, a1, .LBB12_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a3
	; RV32I-NEXT: .LBB12_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_sle_i32:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: slt a1, a2, a1
	; RV32ZBT-NEXT: cmov a0, a1, a3, a0
	; RV32ZBT-NEXT: ret
	%tobool = icmp sle i32 %b, %c
	%cond = select i1 %tobool, i32 %a, i32 %d
	ret i32 %cond
	}

	define i32 @cmov_sle_i32_constant_2046(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: cmov_sle_i32_constant_2046:
	; RV32I: # %bb.0:
	; RV32I-NEXT: li a3, 2047
	; RV32I-NEXT: blt a1, a3, .LBB13_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: .LBB13_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_sle_i32_constant_2046:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: slti a1, a1, 2047
	; RV32ZBT-NEXT: cmov a0, a1, a0, a2
	; RV32ZBT-NEXT: ret
	%tobool = icmp sle i32 %b, 2046
	%cond = select i1 %tobool, i32 %a, i32 %c
	ret i32 %cond
	}

	define i32 @cmov_sle_i32_constant_neg_2049(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: cmov_sle_i32_constant_neg_2049:
	; RV32I: # %bb.0:
	; RV32I-NEXT: li a3, -2048
	; RV32I-NEXT: blt a1, a3, .LBB14_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: .LBB14_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_sle_i32_constant_neg_2049:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: slti a1, a1, -2048
	; RV32ZBT-NEXT: cmov a0, a1, a0, a2
	; RV32ZBT-NEXT: ret
	%tobool = icmp sle i32 %b, -2049
	%cond = select i1 %tobool, i32 %a, i32 %c
	ret i32 %cond
	}

	define i32 @cmov_sgt_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
	; RV32I-LABEL: cmov_sgt_i32:
	; RV32I: # %bb.0:
	; RV32I-NEXT: blt a2, a1, .LBB15_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a3
	; RV32I-NEXT: .LBB15_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_sgt_i32:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: slt a1, a2, a1
	; RV32ZBT-NEXT: cmov a0, a1, a0, a3
	; RV32ZBT-NEXT: ret
	%tobool = icmp sgt i32 %b, %c
	%cond = select i1 %tobool, i32 %a, i32 %d
	ret i32 %cond
	}

	define i32 @cmov_sgt_i32_constant_2046(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: cmov_sgt_i32_constant_2046:
	; RV32I: # %bb.0:
	; RV32I-NEXT: li a3, 2046
	; RV32I-NEXT: blt a3, a1, .LBB16_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: .LBB16_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_sgt_i32_constant_2046:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: slti a1, a1, 2047
	; RV32ZBT-NEXT: cmov a0, a1, a2, a0
	; RV32ZBT-NEXT: ret
	%tobool = icmp sgt i32 %b, 2046
	%cond = select i1 %tobool, i32 %a, i32 %c
	ret i32 %cond
	}

	define i32 @cmov_sgt_i32_constant_neg_2049(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: cmov_sgt_i32_constant_neg_2049:
	; RV32I: # %bb.0:
	; RV32I-NEXT: lui a3, 1048575
	; RV32I-NEXT: addi a3, a3, 2047
	; RV32I-NEXT: blt a3, a1, .LBB17_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: .LBB17_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_sgt_i32_constant_neg_2049:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: slti a1, a1, -2048
	; RV32ZBT-NEXT: cmov a0, a1, a2, a0
	; RV32ZBT-NEXT: ret
	%tobool = icmp sgt i32 %b, -2049
	%cond = select i1 %tobool, i32 %a, i32 %c
	ret i32 %cond
	}

	define i32 @cmov_sge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
	; RV32I-LABEL: cmov_sge_i32:
	; RV32I: # %bb.0:
	; RV32I-NEXT: bge a1, a2, .LBB18_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a3
	; RV32I-NEXT: .LBB18_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_sge_i32:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: slt a1, a1, a2
	; RV32ZBT-NEXT: cmov a0, a1, a3, a0
	; RV32ZBT-NEXT: ret
	%tobool = icmp sge i32 %b, %c
	%cond = select i1 %tobool, i32 %a, i32 %d
	ret i32 %cond
	}

	define i32 @cmov_sge_i32_constant_2047(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: cmov_sge_i32_constant_2047:
	; RV32I: # %bb.0:
	; RV32I-NEXT: li a3, 2046
	; RV32I-NEXT: blt a3, a1, .LBB19_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: .LBB19_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_sge_i32_constant_2047:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: slti a1, a1, 2047
	; RV32ZBT-NEXT: cmov a0, a1, a2, a0
	; RV32ZBT-NEXT: ret
	%tobool = icmp sge i32 %b, 2047
	%cond = select i1 %tobool, i32 %a, i32 %c
	ret i32 %cond
	}

	define i32 @cmov_sge_i32_constant_neg_2048(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: cmov_sge_i32_constant_neg_2048:
	; RV32I: # %bb.0:
	; RV32I-NEXT: lui a3, 1048575
	; RV32I-NEXT: addi a3, a3, 2047
	; RV32I-NEXT: blt a3, a1, .LBB20_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: .LBB20_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_sge_i32_constant_neg_2048:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: slti a1, a1, -2048
	; RV32ZBT-NEXT: cmov a0, a1, a2, a0
	; RV32ZBT-NEXT: ret
	%tobool = icmp sge i32 %b, -2048
	%cond = select i1 %tobool, i32 %a, i32 %c
	ret i32 %cond
	}

	define i32 @cmov_ule_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
	; RV32I-LABEL: cmov_ule_i32:
	; RV32I: # %bb.0:
	; RV32I-NEXT: bgeu a2, a1, .LBB21_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a3
	; RV32I-NEXT: .LBB21_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_ule_i32:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: sltu a1, a2, a1
	; RV32ZBT-NEXT: cmov a0, a1, a3, a0
	; RV32ZBT-NEXT: ret
	%tobool = icmp ule i32 %b, %c
	%cond = select i1 %tobool, i32 %a, i32 %d
	ret i32 %cond
	}

	define i32 @cmov_ule_i32_constant_2047(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: cmov_ule_i32_constant_2047:
	; RV32I: # %bb.0:
	; RV32I-NEXT: srli a1, a1, 11
	; RV32I-NEXT: beqz a1, .LBB22_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: .LBB22_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_ule_i32_constant_2047:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: srli a1, a1, 11
	; RV32ZBT-NEXT: cmov a0, a1, a2, a0
	; RV32ZBT-NEXT: ret
	%tobool = icmp ule i32 %b, 2047
	%cond = select i1 %tobool, i32 %a, i32 %c
	ret i32 %cond
	}

	define i32 @cmov_ule_i32_constant_neg_2049(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: cmov_ule_i32_constant_neg_2049:
	; RV32I: # %bb.0:
	; RV32I-NEXT: li a3, -2048
	; RV32I-NEXT: bltu a1, a3, .LBB23_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: .LBB23_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_ule_i32_constant_neg_2049:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: sltiu a1, a1, -2048
	; RV32ZBT-NEXT: cmov a0, a1, a0, a2
	; RV32ZBT-NEXT: ret
	%tobool = icmp ule i32 %b, 4294965247
	%cond = select i1 %tobool, i32 %a, i32 %c
	ret i32 %cond
	}

	define i32 @cmov_ugt_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
	; RV32I-LABEL: cmov_ugt_i32:
	; RV32I: # %bb.0:
	; RV32I-NEXT: bltu a2, a1, .LBB24_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a3
	; RV32I-NEXT: .LBB24_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_ugt_i32:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: sltu a1, a2, a1
	; RV32ZBT-NEXT: cmov a0, a1, a0, a3
	; RV32ZBT-NEXT: ret
	%tobool = icmp ugt i32 %b, %c
	%cond = select i1 %tobool, i32 %a, i32 %d
	ret i32 %cond
	}

	define i32 @cmov_ugt_i32_constant_2046(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: cmov_ugt_i32_constant_2046:
	; RV32I: # %bb.0:
	; RV32I-NEXT: li a3, 2046
	; RV32I-NEXT: bltu a3, a1, .LBB25_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: .LBB25_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_ugt_i32_constant_2046:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: sltiu a1, a1, 2047
	; RV32ZBT-NEXT: cmov a0, a1, a2, a0
	; RV32ZBT-NEXT: ret
	%tobool = icmp ugt i32 %b, 2046
	%cond = select i1 %tobool, i32 %a, i32 %c
	ret i32 %cond
	}

	define i32 @cmov_ugt_i32_constant_neg_2049(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: cmov_ugt_i32_constant_neg_2049:
	; RV32I: # %bb.0:
	; RV32I-NEXT: lui a3, 1048575
	; RV32I-NEXT: addi a3, a3, 2047
	; RV32I-NEXT: bltu a3, a1, .LBB26_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: .LBB26_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_ugt_i32_constant_neg_2049:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: sltiu a1, a1, -2048
	; RV32ZBT-NEXT: cmov a0, a1, a2, a0
	; RV32ZBT-NEXT: ret
	%tobool = icmp ugt i32 %b, 4294965247
	%cond = select i1 %tobool, i32 %a, i32 %c
	ret i32 %cond
	}

	define i32 @cmov_uge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
	; RV32I-LABEL: cmov_uge_i32:
	; RV32I: # %bb.0:
	; RV32I-NEXT: bgeu a1, a2, .LBB27_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a3
	; RV32I-NEXT: .LBB27_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_uge_i32:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: sltu a1, a1, a2
	; RV32ZBT-NEXT: cmov a0, a1, a3, a0
	; RV32ZBT-NEXT: ret
	%tobool = icmp uge i32 %b, %c
	%cond = select i1 %tobool, i32 %a, i32 %d
	ret i32 %cond
	}

	define i32 @cmov_uge_i32_constant_2047(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: cmov_uge_i32_constant_2047:
	; RV32I: # %bb.0:
	; RV32I-NEXT: li a3, 2046
	; RV32I-NEXT: bltu a3, a1, .LBB28_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: .LBB28_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_uge_i32_constant_2047:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: sltiu a1, a1, 2047
	; RV32ZBT-NEXT: cmov a0, a1, a2, a0
	; RV32ZBT-NEXT: ret
	%tobool = icmp uge i32 %b, 2047
	%cond = select i1 %tobool, i32 %a, i32 %c
	ret i32 %cond
	}

	define i32 @cmov_uge_i32_constant_neg_2048(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: cmov_uge_i32_constant_neg_2048:
	; RV32I: # %bb.0:
	; RV32I-NEXT: lui a3, 1048575
	; RV32I-NEXT: addi a3, a3, 2047
	; RV32I-NEXT: bltu a3, a1, .LBB29_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: .LBB29_2:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_uge_i32_constant_neg_2048:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: sltiu a1, a1, -2048
	; RV32ZBT-NEXT: cmov a0, a1, a2, a0
	; RV32ZBT-NEXT: ret
	%tobool = icmp uge i32 %b, 4294965248
	%cond = select i1 %tobool, i32 %a, i32 %c
	ret i32 %cond
	}

	define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind {
	; RV32I-LABEL: cmov_i64:
	; RV32I: # %bb.0:
	; RV32I-NEXT: or a2, a2, a3
	; RV32I-NEXT: beqz a2, .LBB30_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a4, a0
	; RV32I-NEXT: mv a5, a1
	; RV32I-NEXT: .LBB30_2:
	; RV32I-NEXT: mv a0, a4
	; RV32I-NEXT: mv a1, a5
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_i64:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: or a2, a2, a3
	; RV32ZBT-NEXT: cmov a0, a2, a0, a4
	; RV32ZBT-NEXT: cmov a1, a2, a1, a5
	; RV32ZBT-NEXT: ret
	%tobool.not = icmp eq i64 %b, 0
	%cond = select i1 %tobool.not, i64 %c, i64 %a
	ret i64 %cond
	}

	define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
	; RV32I-LABEL: cmov_sle_i64:
	; RV32I: # %bb.0:
	; RV32I-NEXT: beq a3, a5, .LBB31_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: slt a2, a5, a3
	; RV32I-NEXT: xori a2, a2, 1
	; RV32I-NEXT: beqz a2, .LBB31_3
	; RV32I-NEXT: j .LBB31_4
	; RV32I-NEXT: .LBB31_2:
	; RV32I-NEXT: sltu a2, a4, a2
	; RV32I-NEXT: xori a2, a2, 1
	; RV32I-NEXT: bnez a2, .LBB31_4
	; RV32I-NEXT: .LBB31_3:
	; RV32I-NEXT: mv a0, a6
	; RV32I-NEXT: mv a1, a7
	; RV32I-NEXT: .LBB31_4:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_sle_i64:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: sltu a2, a4, a2
	; RV32ZBT-NEXT: xor a4, a3, a5
	; RV32ZBT-NEXT: slt a3, a5, a3
	; RV32ZBT-NEXT: cmov a2, a4, a3, a2
	; RV32ZBT-NEXT: cmov a0, a2, a6, a0
	; RV32ZBT-NEXT: cmov a1, a2, a7, a1
	; RV32ZBT-NEXT: ret
	%tobool = icmp sle i64 %b, %c
	%cond = select i1 %tobool, i64 %a, i64 %d
	ret i64 %cond
	}

	define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
	; RV32I-LABEL: cmov_sge_i64:
	; RV32I: # %bb.0:
	; RV32I-NEXT: beq a3, a5, .LBB32_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: slt a2, a3, a5
	; RV32I-NEXT: xori a2, a2, 1
	; RV32I-NEXT: beqz a2, .LBB32_3
	; RV32I-NEXT: j .LBB32_4
	; RV32I-NEXT: .LBB32_2:
	; RV32I-NEXT: sltu a2, a2, a4
	; RV32I-NEXT: xori a2, a2, 1
	; RV32I-NEXT: bnez a2, .LBB32_4
	; RV32I-NEXT: .LBB32_3:
	; RV32I-NEXT: mv a0, a6
	; RV32I-NEXT: mv a1, a7
	; RV32I-NEXT: .LBB32_4:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_sge_i64:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: sltu a2, a2, a4
	; RV32ZBT-NEXT: xor a4, a3, a5
	; RV32ZBT-NEXT: slt a3, a3, a5
	; RV32ZBT-NEXT: cmov a2, a4, a3, a2
	; RV32ZBT-NEXT: cmov a0, a2, a6, a0
	; RV32ZBT-NEXT: cmov a1, a2, a7, a1
	; RV32ZBT-NEXT: ret
	%tobool = icmp sge i64 %b, %c
	%cond = select i1 %tobool, i64 %a, i64 %d
	ret i64 %cond
	}

	define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
	; RV32I-LABEL: cmov_ule_i64:
	; RV32I: # %bb.0:
	; RV32I-NEXT: beq a3, a5, .LBB33_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: sltu a2, a5, a3
	; RV32I-NEXT: xori a2, a2, 1
	; RV32I-NEXT: beqz a2, .LBB33_3
	; RV32I-NEXT: j .LBB33_4
	; RV32I-NEXT: .LBB33_2:
	; RV32I-NEXT: sltu a2, a4, a2
	; RV32I-NEXT: xori a2, a2, 1
	; RV32I-NEXT: bnez a2, .LBB33_4
	; RV32I-NEXT: .LBB33_3:
	; RV32I-NEXT: mv a0, a6
	; RV32I-NEXT: mv a1, a7
	; RV32I-NEXT: .LBB33_4:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_ule_i64:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: sltu a2, a4, a2
	; RV32ZBT-NEXT: xor a4, a3, a5
	; RV32ZBT-NEXT: sltu a3, a5, a3
	; RV32ZBT-NEXT: cmov a2, a4, a3, a2
	; RV32ZBT-NEXT: cmov a0, a2, a6, a0
	; RV32ZBT-NEXT: cmov a1, a2, a7, a1
	; RV32ZBT-NEXT: ret
	%tobool = icmp ule i64 %b, %c
	%cond = select i1 %tobool, i64 %a, i64 %d
	ret i64 %cond
	}

	define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
	; RV32I-LABEL: cmov_uge_i64:
	; RV32I: # %bb.0:
	; RV32I-NEXT: beq a3, a5, .LBB34_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: sltu a2, a3, a5
	; RV32I-NEXT: xori a2, a2, 1
	; RV32I-NEXT: beqz a2, .LBB34_3
	; RV32I-NEXT: j .LBB34_4
	; RV32I-NEXT: .LBB34_2:
	; RV32I-NEXT: sltu a2, a2, a4
	; RV32I-NEXT: xori a2, a2, 1
	; RV32I-NEXT: bnez a2, .LBB34_4
	; RV32I-NEXT: .LBB34_3:
	; RV32I-NEXT: mv a0, a6
	; RV32I-NEXT: mv a1, a7
	; RV32I-NEXT: .LBB34_4:
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: cmov_uge_i64:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: sltu a2, a2, a4
	; RV32ZBT-NEXT: xor a4, a3, a5
	; RV32ZBT-NEXT: sltu a3, a3, a5
	; RV32ZBT-NEXT: cmov a2, a4, a3, a2
	; RV32ZBT-NEXT: cmov a0, a2, a6, a0
	; RV32ZBT-NEXT: cmov a1, a2, a7, a1
	; RV32ZBT-NEXT: ret
	%tobool = icmp uge i64 %b, %c
	%cond = select i1 %tobool, i64 %a, i64 %d
	ret i64 %cond
	}

	declare i32 @llvm.fshl.i32(i32, i32, i32)

	define i32 @fshl_i32(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: fshl_i32:
	; RV32I: # %bb.0:
	; RV32I-NEXT: sll a0, a0, a2
	; RV32I-NEXT: not a2, a2
	; RV32I-NEXT: srli a1, a1, 1
	; RV32I-NEXT: srl a1, a1, a2
	; RV32I-NEXT: or a0, a0, a1
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: fshl_i32:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: andi a2, a2, 31
	; RV32ZBT-NEXT: fsl a0, a0, a1, a2
	; RV32ZBT-NEXT: ret
	%1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c)
	ret i32 %1
	}

	; As we are not matching directly i64 code patterns on RV32 some i64 patterns
	; don't have yet an efficient pattern-matching with bit manipulation
	; instructions on RV32.
	; This test is presented here in case future expansions of the Bitmanip
	; extensions introduce instructions that can match more efficiently this pattern.

	declare i64 @llvm.fshl.i64(i64, i64, i64)

	define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
	; RV32I-LABEL: fshl_i64:
	; RV32I: # %bb.0:
	; RV32I-NEXT: slli a5, a4, 26
	; RV32I-NEXT: srli a6, a5, 31
	; RV32I-NEXT: mv a5, a3
	; RV32I-NEXT: bnez a6, .LBB36_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a5, a0
	; RV32I-NEXT: .LBB36_2:
	; RV32I-NEXT: sll a7, a5, a4
	; RV32I-NEXT: bnez a6, .LBB36_4
	; RV32I-NEXT: # %bb.3:
	; RV32I-NEXT: mv a2, a3
	; RV32I-NEXT: .LBB36_4:
	; RV32I-NEXT: srli a2, a2, 1
	; RV32I-NEXT: not a3, a4
	; RV32I-NEXT: srl a2, a2, a3
	; RV32I-NEXT: or a2, a7, a2
	; RV32I-NEXT: bnez a6, .LBB36_6
	; RV32I-NEXT: # %bb.5:
	; RV32I-NEXT: mv a0, a1
	; RV32I-NEXT: .LBB36_6:
	; RV32I-NEXT: sll a0, a0, a4
	; RV32I-NEXT: srli a1, a5, 1
	; RV32I-NEXT: srl a1, a1, a3
	; RV32I-NEXT: or a1, a0, a1
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: fshl_i64:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: slli a5, a4, 26
	; RV32ZBT-NEXT: srli a5, a5, 31
	; RV32ZBT-NEXT: cmov a2, a5, a2, a3
	; RV32ZBT-NEXT: cmov a3, a5, a3, a0
	; RV32ZBT-NEXT: andi a4, a4, 31
	; RV32ZBT-NEXT: fsl a2, a3, a2, a4
	; RV32ZBT-NEXT: cmov a0, a5, a0, a1
	; RV32ZBT-NEXT: fsl a1, a0, a3, a4
	; RV32ZBT-NEXT: mv a0, a2
	; RV32ZBT-NEXT: ret
	%1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 %c)
	ret i64 %1
	}

	declare i32 @llvm.fshr.i32(i32, i32, i32)

	define i32 @fshr_i32(i32 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: fshr_i32:
	; RV32I: # %bb.0:
	; RV32I-NEXT: srl a1, a1, a2
	; RV32I-NEXT: not a2, a2
	; RV32I-NEXT: slli a0, a0, 1
	; RV32I-NEXT: sll a0, a0, a2
	; RV32I-NEXT: or a0, a0, a1
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: fshr_i32:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: andi a2, a2, 31
	; RV32ZBT-NEXT: fsr a0, a1, a0, a2
	; RV32ZBT-NEXT: ret
	%1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)
	ret i32 %1
	}

	; As we are not matching directly i64 code patterns on RV32 some i64 patterns
	; don't have yet an efficient pattern-matching with bit manipulation
	; instructions on RV32.
	; This test is presented here in case future expansions of the Bitmanip
	; extensions introduce instructions that can match more efficiently this pattern.

	declare i64 @llvm.fshr.i64(i64, i64, i64)

	define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind {
	; RV32I-LABEL: fshr_i64:
	; RV32I: # %bb.0:
	; RV32I-NEXT: andi a5, a4, 32
	; RV32I-NEXT: beqz a5, .LBB38_2
	; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a2, a3
	; RV32I-NEXT: .LBB38_2:
	; RV32I-NEXT: srl a2, a2, a4
	; RV32I-NEXT: beqz a5, .LBB38_4
	; RV32I-NEXT: # %bb.3:
	; RV32I-NEXT: mv a3, a0
	; RV32I-NEXT: .LBB38_4:
	; RV32I-NEXT: slli a7, a3, 1
	; RV32I-NEXT: not a6, a4
	; RV32I-NEXT: sll a7, a7, a6
	; RV32I-NEXT: or a2, a7, a2
	; RV32I-NEXT: srl a3, a3, a4
	; RV32I-NEXT: beqz a5, .LBB38_6
	; RV32I-NEXT: # %bb.5:
	; RV32I-NEXT: mv a0, a1
	; RV32I-NEXT: .LBB38_6:
	; RV32I-NEXT: slli a0, a0, 1
	; RV32I-NEXT: sll a0, a0, a6
	; RV32I-NEXT: or a1, a0, a3
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: fshr_i64:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: andi a5, a4, 32
	; RV32ZBT-NEXT: cmov a6, a5, a0, a3
	; RV32ZBT-NEXT: cmov a2, a5, a3, a2
	; RV32ZBT-NEXT: andi a3, a4, 31
	; RV32ZBT-NEXT: fsr a2, a2, a6, a3
	; RV32ZBT-NEXT: cmov a0, a5, a1, a0
	; RV32ZBT-NEXT: fsr a1, a6, a0, a3
	; RV32ZBT-NEXT: mv a0, a2
	; RV32ZBT-NEXT: ret
	%1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 %c)
	ret i64 %1
	}

	define i32 @fshri_i32(i32 %a, i32 %b) nounwind {
	; RV32I-LABEL: fshri_i32:
	; RV32I: # %bb.0:
	; RV32I-NEXT: srli a1, a1, 5
	; RV32I-NEXT: slli a0, a0, 27
	; RV32I-NEXT: or a0, a0, a1
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: fshri_i32:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: fsri a0, a1, a0, 5
	; RV32ZBT-NEXT: ret
	%1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 5)
	ret i32 %1
	}

	define i64 @fshri_i64(i64 %a, i64 %b) nounwind {
	; RV32I-LABEL: fshri_i64:
	; RV32I: # %bb.0:
	; RV32I-NEXT: srli a1, a2, 5
	; RV32I-NEXT: slli a2, a3, 27
	; RV32I-NEXT: or a2, a2, a1
	; RV32I-NEXT: srli a1, a3, 5
	; RV32I-NEXT: slli a0, a0, 27
	; RV32I-NEXT: or a1, a0, a1
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: fshri_i64:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: fsri a2, a2, a3, 5
	; RV32ZBT-NEXT: fsri a1, a3, a0, 5
	; RV32ZBT-NEXT: mv a0, a2
	; RV32ZBT-NEXT: ret
	%1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 5)
	ret i64 %1
	}

	define i32 @fshli_i32(i32 %a, i32 %b) nounwind {
	; RV32I-LABEL: fshli_i32:
	; RV32I: # %bb.0:
	; RV32I-NEXT: srli a1, a1, 27
	; RV32I-NEXT: slli a0, a0, 5
	; RV32I-NEXT: or a0, a0, a1
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: fshli_i32:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: fsri a0, a1, a0, 27
	; RV32ZBT-NEXT: ret
	%1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 5)
	ret i32 %1
	}

	define i64 @fshli_i64(i64 %a, i64 %b) nounwind {
	; RV32I-LABEL: fshli_i64:
	; RV32I: # %bb.0:
	; RV32I-NEXT: srli a2, a3, 27
	; RV32I-NEXT: slli a3, a0, 5
	; RV32I-NEXT: or a2, a3, a2
	; RV32I-NEXT: srli a0, a0, 27
	; RV32I-NEXT: slli a1, a1, 5
	; RV32I-NEXT: or a1, a1, a0
	; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: ret
	;
	; RV32ZBT-LABEL: fshli_i64:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: fsri a2, a3, a0, 27
	; RV32ZBT-NEXT: fsri a1, a0, a1, 27
	; RV32ZBT-NEXT: mv a0, a2
	; RV32ZBT-NEXT: ret
	%1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 5)
	ret i64 %1
	}

llvm/test/CodeGen/RISCV/rv64zbt-intrinsic.ll

This file was deleted.

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s -check-prefix=RV64ZBT

	declare i32 @llvm.riscv.fsl.i32(i32, i32, i32)

	define i32 @fsl_i32(i32 %a, i32 %b, i32 %c) nounwind {
	; RV64ZBT-LABEL: fsl_i32:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: fslw a0, a0, a1, a2
	; RV64ZBT-NEXT: ret
	%1 = call i32 @llvm.riscv.fsl.i32(i32 %a, i32 %b, i32 %c)
	ret i32 %1
	}

	define i32 @fsl_i32_demandedbits(i32 %a, i32 %b, i32 %c) nounwind {
	; RV64ZBT-LABEL: fsl_i32_demandedbits:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: andi a1, a1, 31
	; RV64ZBT-NEXT: fslw a0, a0, a1, a2
	; RV64ZBT-NEXT: ret
	%bmask = and i32 %b, 95
	%1 = call i32 @llvm.riscv.fsl.i32(i32 %a, i32 %bmask, i32 %c)
	ret i32 %1
	}

	declare i32 @llvm.riscv.fsr.i32(i32, i32, i32)

	define i32 @fsr_i32(i32 %a, i32 %b, i32 %c) nounwind {
	; RV64ZBT-LABEL: fsr_i32:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: fsrw a0, a0, a1, a2
	; RV64ZBT-NEXT: ret
	%1 = call i32 @llvm.riscv.fsr.i32(i32 %a, i32 %b, i32 %c)
	ret i32 %1
	}

	define i32 @fsr_i32_demandedbits(i32 %a, i32 %b, i32 %c) nounwind {
	; RV64ZBT-LABEL: fsr_i32_demandedbits:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: andi a1, a1, 31
	; RV64ZBT-NEXT: fsrw a0, a0, a1, a2
	; RV64ZBT-NEXT: ret
	%bmask = and i32 %b, 95
	%1 = call i32 @llvm.riscv.fsr.i32(i32 %a, i32 %bmask, i32 %c)
	ret i32 %1
	}

	define i32 @fsli_i32(i32 %a, i32 %b) nounwind {
	; RV64ZBT-LABEL: fsli_i32:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: fsriw a0, a1, a0, 27
	; RV64ZBT-NEXT: ret
	%1 = call i32 @llvm.riscv.fsl.i32(i32 %a, i32 %b, i32 5)
	ret i32 %1
	}

	define i32 @fsri_i32(i32 %a, i32 %b) nounwind {
	; RV64ZBT-LABEL: fsri_i32:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: fsriw a0, a0, a1, 15
	; RV64ZBT-NEXT: ret
	%1 = call i32 @llvm.riscv.fsr.i32(i32 %a, i32 %b, i32 15)
	ret i32 %1
	}

	declare i64 @llvm.riscv.fsl.i64(i64, i64, i64)

	define i64 @fsl_i64(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64ZBT-LABEL: fsl_i64:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: fsl a0, a0, a1, a2
	; RV64ZBT-NEXT: ret
	%1 = call i64 @llvm.riscv.fsl.i64(i64 %a, i64 %b, i64 %c)
	ret i64 %1
	}

	define i64 @fsl_i64_demandedbits(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64ZBT-LABEL: fsl_i64_demandedbits:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: andi a1, a1, 63
	; RV64ZBT-NEXT: fsl a0, a0, a1, a2
	; RV64ZBT-NEXT: ret
	%bmask = and i64 %b, 191
	%1 = call i64 @llvm.riscv.fsl.i64(i64 %a, i64 %bmask, i64 %c)
	ret i64 %1
	}

	declare i64 @llvm.riscv.fsr.i64(i64, i64, i64)

	define i64 @fsr_i64(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64ZBT-LABEL: fsr_i64:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: fsr a0, a0, a1, a2
	; RV64ZBT-NEXT: ret
	%1 = call i64 @llvm.riscv.fsr.i64(i64 %a, i64 %b, i64 %c)
	ret i64 %1
	}

	define i64 @fsr_i64_demandedbits(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64ZBT-LABEL: fsr_i64_demandedbits:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: andi a1, a1, 63
	; RV64ZBT-NEXT: fsr a0, a0, a1, a2
	; RV64ZBT-NEXT: ret
	%bmask = and i64 %b, 191
	%1 = call i64 @llvm.riscv.fsr.i64(i64 %a, i64 %bmask, i64 %c)
	ret i64 %1
	}

	define i64 @fsli_i64(i64 %a, i64 %b) nounwind {
	; RV64ZBT-LABEL: fsli_i64:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: fsri a0, a1, a0, 49
	; RV64ZBT-NEXT: ret
	%1 = call i64 @llvm.riscv.fsl.i64(i64 %a, i64 %b, i64 15)
	ret i64 %1
	}

	define i64 @fsri_i64(i64 %a, i64 %b) nounwind {
	; RV64ZBT-LABEL: fsri_i64:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: fsri a0, a0, a1, 5
	; RV64ZBT-NEXT: ret
	%1 = call i64 @llvm.riscv.fsr.i64(i64 %a, i64 %b, i64 5)
	ret i64 %1
	}

llvm/test/CodeGen/RISCV/rv64zbt.ll

This file was deleted.

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s -check-prefix=RV64I
	; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s -check-prefix=RV64ZBT

	define signext i32 @cmix_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
	; RV64I-LABEL: cmix_i32:
	; RV64I: # %bb.0:
	; RV64I-NEXT: and a0, a1, a0
	; RV64I-NEXT: not a1, a1
	; RV64I-NEXT: and a1, a1, a2
	; RV64I-NEXT: or a0, a1, a0
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmix_i32:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: cmix a0, a1, a0, a2
	; RV64ZBT-NEXT: ret
	%and = and i32 %b, %a
	%neg = xor i32 %b, -1
	%and1 = and i32 %neg, %c
	%or = or i32 %and1, %and
	ret i32 %or
	}

	define signext i32 @cmix_i32_2(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
	; RV64I-LABEL: cmix_i32_2:
	; RV64I: # %bb.0:
	; RV64I-NEXT: xor a0, a0, a2
	; RV64I-NEXT: and a0, a0, a1
	; RV64I-NEXT: xor a0, a0, a2
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmix_i32_2:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: cmix a0, a1, a0, a2
	; RV64ZBT-NEXT: ret
	%xor = xor i32 %a, %c
	%and = and i32 %xor, %b
	%xor1 = xor i32 %and, %c
	ret i32 %xor1
	}

	define i64 @cmix_i64(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: cmix_i64:
	; RV64I: # %bb.0:
	; RV64I-NEXT: and a0, a1, a0
	; RV64I-NEXT: not a1, a1
	; RV64I-NEXT: and a1, a1, a2
	; RV64I-NEXT: or a0, a1, a0
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmix_i64:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: cmix a0, a1, a0, a2
	; RV64ZBT-NEXT: ret
	%and = and i64 %b, %a
	%neg = xor i64 %b, -1
	%and1 = and i64 %neg, %c
	%or = or i64 %and1, %and
	ret i64 %or
	}

	define i64 @cmix_i64_2(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: cmix_i64_2:
	; RV64I: # %bb.0:
	; RV64I-NEXT: xor a0, a1, a2
	; RV64I-NEXT: and a0, a0, a1
	; RV64I-NEXT: xor a0, a0, a2
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmix_i64_2:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: cmix a0, a1, a1, a2
	; RV64ZBT-NEXT: ret
	%xor = xor i64 %b, %c
	%and = and i64 %xor, %b
	%xor1 = xor i64 %and, %c
	ret i64 %xor1
	}

	define signext i32 @cmov_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
	; RV64I-LABEL: cmov_i32:
	; RV64I: # %bb.0:
	; RV64I-NEXT: beqz a1, .LBB4_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a2, a0
	; RV64I-NEXT: .LBB4_2:
	; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_i32:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: cmov a0, a1, a0, a2
	; RV64ZBT-NEXT: ret
	%tobool.not = icmp eq i32 %b, 0
	%cond = select i1 %tobool.not, i32 %c, i32 %a
	ret i32 %cond
	}

	define signext i32 @cmov_sle_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
	; RV64I-LABEL: cmov_sle_i32:
	; RV64I: # %bb.0:
	; RV64I-NEXT: bge a2, a1, .LBB5_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a3
	; RV64I-NEXT: .LBB5_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_sle_i32:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: slt a1, a2, a1
	; RV64ZBT-NEXT: cmov a0, a1, a3, a0
	; RV64ZBT-NEXT: ret
	%tobool = icmp sle i32 %b, %c
	%cond = select i1 %tobool, i32 %a, i32 %d
	ret i32 %cond
	}

	define signext i32 @cmov_sge_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
	; RV64I-LABEL: cmov_sge_i32:
	; RV64I: # %bb.0:
	; RV64I-NEXT: bge a1, a2, .LBB6_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a3
	; RV64I-NEXT: .LBB6_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_sge_i32:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: slt a1, a1, a2
	; RV64ZBT-NEXT: cmov a0, a1, a3, a0
	; RV64ZBT-NEXT: ret
	%tobool = icmp sge i32 %b, %c
	%cond = select i1 %tobool, i32 %a, i32 %d
	ret i32 %cond
	}

	define signext i32 @cmov_ule_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
	; RV64I-LABEL: cmov_ule_i32:
	; RV64I: # %bb.0:
	; RV64I-NEXT: bgeu a2, a1, .LBB7_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a3
	; RV64I-NEXT: .LBB7_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_ule_i32:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: sltu a1, a2, a1
	; RV64ZBT-NEXT: cmov a0, a1, a3, a0
	; RV64ZBT-NEXT: ret
	%tobool = icmp ule i32 %b, %c
	%cond = select i1 %tobool, i32 %a, i32 %d
	ret i32 %cond
	}

	define signext i32 @cmov_uge_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
	; RV64I-LABEL: cmov_uge_i32:
	; RV64I: # %bb.0:
	; RV64I-NEXT: bgeu a1, a2, .LBB8_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a3
	; RV64I-NEXT: .LBB8_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_uge_i32:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: sltu a1, a1, a2
	; RV64ZBT-NEXT: cmov a0, a1, a3, a0
	; RV64ZBT-NEXT: ret
	%tobool = icmp uge i32 %b, %c
	%cond = select i1 %tobool, i32 %a, i32 %d
	ret i32 %cond
	}

	define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: cmov_i64:
	; RV64I: # %bb.0:
	; RV64I-NEXT: beqz a1, .LBB9_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a2, a0
	; RV64I-NEXT: .LBB9_2:
	; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_i64:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: cmov a0, a1, a0, a2
	; RV64ZBT-NEXT: ret
	%tobool.not = icmp eq i64 %b, 0
	%cond = select i1 %tobool.not, i64 %c, i64 %a
	ret i64 %cond
	}

	define i64 @cmov_eq_i64_constant_2048(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: cmov_eq_i64_constant_2048:
	; RV64I: # %bb.0:
	; RV64I-NEXT: lui a3, 1
	; RV64I-NEXT: addiw a3, a3, -2048
	; RV64I-NEXT: beq a1, a3, .LBB10_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: .LBB10_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_eq_i64_constant_2048:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: addi a1, a1, -2048
	; RV64ZBT-NEXT: cmov a0, a1, a2, a0
	; RV64ZBT-NEXT: ret
	%tobool.not = icmp eq i64 %b, 2048
	%cond = select i1 %tobool.not, i64 %a, i64 %c
	ret i64 %cond
	}

	define i64 @cmov_eq_i64_constant_neg_2047(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: cmov_eq_i64_constant_neg_2047:
	; RV64I: # %bb.0:
	; RV64I-NEXT: li a3, -2047
	; RV64I-NEXT: beq a1, a3, .LBB11_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: .LBB11_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_eq_i64_constant_neg_2047:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: addi a1, a1, 2047
	; RV64ZBT-NEXT: cmov a0, a1, a2, a0
	; RV64ZBT-NEXT: ret
	%tobool.not = icmp eq i64 %b, -2047
	%cond = select i1 %tobool.not, i64 %a, i64 %c
	ret i64 %cond
	}

	define i64 @cmov_ne_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
	; RV64I-LABEL: cmov_ne_i64:
	; RV64I: # %bb.0:
	; RV64I-NEXT: bne a1, a2, .LBB12_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a3
	; RV64I-NEXT: .LBB12_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_ne_i64:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: xor a1, a1, a2
	; RV64ZBT-NEXT: cmov a0, a1, a0, a3
	; RV64ZBT-NEXT: ret
	%tobool.not = icmp ne i64 %b, %c
	%cond = select i1 %tobool.not, i64 %a, i64 %d
	ret i64 %cond
	}

	define i64 @cmov_ne_i64_constant_zero(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: cmov_ne_i64_constant_zero:
	; RV64I: # %bb.0:
	; RV64I-NEXT: bnez a1, .LBB13_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: .LBB13_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_ne_i64_constant_zero:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: cmov a0, a1, a0, a2
	; RV64ZBT-NEXT: ret
	%tobool.not = icmp ne i64 %b, 0
	%cond = select i1 %tobool.not, i64 %a, i64 %c
	ret i64 %cond
	}

	define i64 @cmov_ne_i64_constant_2048(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: cmov_ne_i64_constant_2048:
	; RV64I: # %bb.0:
	; RV64I-NEXT: lui a3, 1
	; RV64I-NEXT: addiw a3, a3, -2048
	; RV64I-NEXT: bne a1, a3, .LBB14_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: .LBB14_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_ne_i64_constant_2048:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: addi a1, a1, -2048
	; RV64ZBT-NEXT: cmov a0, a1, a0, a2
	; RV64ZBT-NEXT: ret
	%tobool.not = icmp ne i64 %b, 2048
	%cond = select i1 %tobool.not, i64 %a, i64 %c
	ret i64 %cond
	}

	define i64 @cmov_ne_i64_constant_neg_2047(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: cmov_ne_i64_constant_neg_2047:
	; RV64I: # %bb.0:
	; RV64I-NEXT: li a3, -2047
	; RV64I-NEXT: bne a1, a3, .LBB15_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: .LBB15_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_ne_i64_constant_neg_2047:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: addi a1, a1, 2047
	; RV64ZBT-NEXT: cmov a0, a1, a0, a2
	; RV64ZBT-NEXT: ret
	%tobool.not = icmp ne i64 %b, -2047
	%cond = select i1 %tobool.not, i64 %a, i64 %c
	ret i64 %cond
	}

	define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
	; RV64I-LABEL: cmov_sle_i64:
	; RV64I: # %bb.0:
	; RV64I-NEXT: bge a2, a1, .LBB16_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a3
	; RV64I-NEXT: .LBB16_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_sle_i64:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: slt a1, a2, a1
	; RV64ZBT-NEXT: cmov a0, a1, a3, a0
	; RV64ZBT-NEXT: ret
	%tobool = icmp sle i64 %b, %c
	%cond = select i1 %tobool, i64 %a, i64 %d
	ret i64 %cond
	}

	define i64 @cmov_sle_i64_constant_2046(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: cmov_sle_i64_constant_2046:
	; RV64I: # %bb.0:
	; RV64I-NEXT: li a3, 2047
	; RV64I-NEXT: blt a1, a3, .LBB17_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: .LBB17_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_sle_i64_constant_2046:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: slti a1, a1, 2047
	; RV64ZBT-NEXT: cmov a0, a1, a0, a2
	; RV64ZBT-NEXT: ret
	%tobool = icmp sle i64 %b, 2046
	%cond = select i1 %tobool, i64 %a, i64 %c
	ret i64 %cond
	}

	define i64 @cmov_sle_i64_constant_neg_2049(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: cmov_sle_i64_constant_neg_2049:
	; RV64I: # %bb.0:
	; RV64I-NEXT: li a3, -2048
	; RV64I-NEXT: blt a1, a3, .LBB18_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: .LBB18_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_sle_i64_constant_neg_2049:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: slti a1, a1, -2048
	; RV64ZBT-NEXT: cmov a0, a1, a0, a2
	; RV64ZBT-NEXT: ret
	%tobool = icmp sle i64 %b, -2049
	%cond = select i1 %tobool, i64 %a, i64 %c
	ret i64 %cond
	}

	define i64 @cmov_sgt_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
	; RV64I-LABEL: cmov_sgt_i64:
	; RV64I: # %bb.0:
	; RV64I-NEXT: blt a2, a1, .LBB19_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a3
	; RV64I-NEXT: .LBB19_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_sgt_i64:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: slt a1, a2, a1
	; RV64ZBT-NEXT: cmov a0, a1, a0, a3
	; RV64ZBT-NEXT: ret
	%tobool = icmp sgt i64 %b, %c
	%cond = select i1 %tobool, i64 %a, i64 %d
	ret i64 %cond
	}

	define i64 @cmov_sgt_i64_constant_2046(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: cmov_sgt_i64_constant_2046:
	; RV64I: # %bb.0:
	; RV64I-NEXT: li a3, 2046
	; RV64I-NEXT: blt a3, a1, .LBB20_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: .LBB20_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_sgt_i64_constant_2046:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: slti a1, a1, 2047
	; RV64ZBT-NEXT: cmov a0, a1, a2, a0
	; RV64ZBT-NEXT: ret
	%tobool = icmp sgt i64 %b, 2046
	%cond = select i1 %tobool, i64 %a, i64 %c
	ret i64 %cond
	}

	define i64 @cmov_sgt_i64_constant_neg_2049(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: cmov_sgt_i64_constant_neg_2049:
	; RV64I: # %bb.0:
	; RV64I-NEXT: lui a3, 1048575
	; RV64I-NEXT: addiw a3, a3, 2047
	; RV64I-NEXT: blt a3, a1, .LBB21_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: .LBB21_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_sgt_i64_constant_neg_2049:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: slti a1, a1, -2048
	; RV64ZBT-NEXT: cmov a0, a1, a2, a0
	; RV64ZBT-NEXT: ret
	%tobool = icmp sgt i64 %b, -2049
	%cond = select i1 %tobool, i64 %a, i64 %c
	ret i64 %cond
	}

	define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
	; RV64I-LABEL: cmov_sge_i64:
	; RV64I: # %bb.0:
	; RV64I-NEXT: bge a1, a2, .LBB22_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a3
	; RV64I-NEXT: .LBB22_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_sge_i64:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: slt a1, a1, a2
	; RV64ZBT-NEXT: cmov a0, a1, a3, a0
	; RV64ZBT-NEXT: ret
	%tobool = icmp sge i64 %b, %c
	%cond = select i1 %tobool, i64 %a, i64 %d
	ret i64 %cond
	}

	define i64 @cmov_sge_i64_constant_2047(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: cmov_sge_i64_constant_2047:
	; RV64I: # %bb.0:
	; RV64I-NEXT: li a3, 2046
	; RV64I-NEXT: blt a3, a1, .LBB23_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: .LBB23_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_sge_i64_constant_2047:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: slti a1, a1, 2047
	; RV64ZBT-NEXT: cmov a0, a1, a2, a0
	; RV64ZBT-NEXT: ret
	%tobool = icmp sge i64 %b, 2047
	%cond = select i1 %tobool, i64 %a, i64 %c
	ret i64 %cond
	}

	define i64 @cmov_sge_i64_constant_neg_2048(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: cmov_sge_i64_constant_neg_2048:
	; RV64I: # %bb.0:
	; RV64I-NEXT: lui a3, 1048575
	; RV64I-NEXT: addiw a3, a3, 2047
	; RV64I-NEXT: blt a3, a1, .LBB24_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: .LBB24_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_sge_i64_constant_neg_2048:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: slti a1, a1, -2048
	; RV64ZBT-NEXT: cmov a0, a1, a2, a0
	; RV64ZBT-NEXT: ret
	%tobool = icmp sge i64 %b, -2048
	%cond = select i1 %tobool, i64 %a, i64 %c
	ret i64 %cond
	}

	define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
	; RV64I-LABEL: cmov_ule_i64:
	; RV64I: # %bb.0:
	; RV64I-NEXT: bgeu a2, a1, .LBB25_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a3
	; RV64I-NEXT: .LBB25_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_ule_i64:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: sltu a1, a2, a1
	; RV64ZBT-NEXT: cmov a0, a1, a3, a0
	; RV64ZBT-NEXT: ret
	%tobool = icmp ule i64 %b, %c
	%cond = select i1 %tobool, i64 %a, i64 %d
	ret i64 %cond
	}

	define i64 @cmov_ule_i64_constant_2047(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: cmov_ule_i64_constant_2047:
	; RV64I: # %bb.0:
	; RV64I-NEXT: srli a1, a1, 11
	; RV64I-NEXT: beqz a1, .LBB26_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: .LBB26_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_ule_i64_constant_2047:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: srli a1, a1, 11
	; RV64ZBT-NEXT: cmov a0, a1, a2, a0
	; RV64ZBT-NEXT: ret
	%tobool = icmp ule i64 %b, 2047
	%cond = select i1 %tobool, i64 %a, i64 %c
	ret i64 %cond
	}

	define i64 @cmov_ule_i64_constant_neg_2049(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: cmov_ule_i64_constant_neg_2049:
	; RV64I: # %bb.0:
	; RV64I-NEXT: li a3, -2048
	; RV64I-NEXT: bltu a1, a3, .LBB27_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: .LBB27_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_ule_i64_constant_neg_2049:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: sltiu a1, a1, -2048
	; RV64ZBT-NEXT: cmov a0, a1, a0, a2
	; RV64ZBT-NEXT: ret
	%tobool = icmp ule i64 %b, 18446744073709549567
	%cond = select i1 %tobool, i64 %a, i64 %c
	ret i64 %cond
	}

	define i64 @cmov_ugt_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
	; RV64I-LABEL: cmov_ugt_i64:
	; RV64I: # %bb.0:
	; RV64I-NEXT: bltu a2, a1, .LBB28_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a3
	; RV64I-NEXT: .LBB28_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_ugt_i64:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: sltu a1, a2, a1
	; RV64ZBT-NEXT: cmov a0, a1, a0, a3
	; RV64ZBT-NEXT: ret
	%tobool = icmp ugt i64 %b, %c
	%cond = select i1 %tobool, i64 %a, i64 %d
	ret i64 %cond
	}

	define i64 @cmov_ugt_i64_constant_2046(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: cmov_ugt_i64_constant_2046:
	; RV64I: # %bb.0:
	; RV64I-NEXT: li a3, 2046
	; RV64I-NEXT: bltu a3, a1, .LBB29_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: .LBB29_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_ugt_i64_constant_2046:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: sltiu a1, a1, 2047
	; RV64ZBT-NEXT: cmov a0, a1, a2, a0
	; RV64ZBT-NEXT: ret
	%tobool = icmp ugt i64 %b, 2046
	%cond = select i1 %tobool, i64 %a, i64 %c
	ret i64 %cond
	}

	define i64 @cmov_ugt_i64_constant_neg_2049(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: cmov_ugt_i64_constant_neg_2049:
	; RV64I: # %bb.0:
	; RV64I-NEXT: lui a3, 1048575
	; RV64I-NEXT: addiw a3, a3, 2047
	; RV64I-NEXT: bltu a3, a1, .LBB30_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: .LBB30_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_ugt_i64_constant_neg_2049:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: sltiu a1, a1, -2048
	; RV64ZBT-NEXT: cmov a0, a1, a2, a0
	; RV64ZBT-NEXT: ret
	%tobool = icmp ugt i64 %b, 18446744073709549567
	%cond = select i1 %tobool, i64 %a, i64 %c
	ret i64 %cond
	}

	define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
	; RV64I-LABEL: cmov_uge_i64:
	; RV64I: # %bb.0:
	; RV64I-NEXT: bgeu a1, a2, .LBB31_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a3
	; RV64I-NEXT: .LBB31_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_uge_i64:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: sltu a1, a1, a2
	; RV64ZBT-NEXT: cmov a0, a1, a3, a0
	; RV64ZBT-NEXT: ret
	%tobool = icmp uge i64 %b, %c
	%cond = select i1 %tobool, i64 %a, i64 %d
	ret i64 %cond
	}

	define i64 @cmov_uge_i64_constant_2047(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: cmov_uge_i64_constant_2047:
	; RV64I: # %bb.0:
	; RV64I-NEXT: li a3, 2046
	; RV64I-NEXT: bltu a3, a1, .LBB32_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: .LBB32_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_uge_i64_constant_2047:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: sltiu a1, a1, 2047
	; RV64ZBT-NEXT: cmov a0, a1, a2, a0
	; RV64ZBT-NEXT: ret
	%tobool = icmp uge i64 %b, 2047
	%cond = select i1 %tobool, i64 %a, i64 %c
	ret i64 %cond
	}

	define i64 @cmov_uge_i64_constant_neg_2048(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: cmov_uge_i64_constant_neg_2048:
	; RV64I: # %bb.0:
	; RV64I-NEXT: lui a3, 1048575
	; RV64I-NEXT: addiw a3, a3, 2047
	; RV64I-NEXT: bltu a3, a1, .LBB33_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: .LBB33_2:
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: cmov_uge_i64_constant_neg_2048:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: sltiu a1, a1, -2048
	; RV64ZBT-NEXT: cmov a0, a1, a2, a0
	; RV64ZBT-NEXT: ret
	%tobool = icmp uge i64 %b, 18446744073709549568
	%cond = select i1 %tobool, i64 %a, i64 %c
	ret i64 %cond
	}

	declare i32 @llvm.fshl.i32(i32, i32, i32)

	define signext i32 @fshl_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
	; RV64I-LABEL: fshl_i32:
	; RV64I: # %bb.0:
	; RV64I-NEXT: slli a0, a0, 32
	; RV64I-NEXT: slli a1, a1, 32
	; RV64I-NEXT: srli a1, a1, 32
	; RV64I-NEXT: or a0, a0, a1
	; RV64I-NEXT: andi a1, a2, 31
	; RV64I-NEXT: sll a0, a0, a1
	; RV64I-NEXT: srai a0, a0, 32
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: fshl_i32:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: andi a2, a2, 31
	; RV64ZBT-NEXT: fslw a0, a0, a1, a2
	; RV64ZBT-NEXT: ret
	%1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c)
	ret i32 %1
	}

	; Similar to fshl_i32 but result is not sign extended.
	define void @fshl_i32_nosext(i32 signext %a, i32 signext %b, i32 signext %c, i32* %x) nounwind {
	; RV64I-LABEL: fshl_i32_nosext:
	; RV64I: # %bb.0:
	; RV64I-NEXT: slli a0, a0, 32
	; RV64I-NEXT: slli a1, a1, 32
	; RV64I-NEXT: srli a1, a1, 32
	; RV64I-NEXT: or a0, a0, a1
	; RV64I-NEXT: andi a1, a2, 31
	; RV64I-NEXT: sll a0, a0, a1
	; RV64I-NEXT: srli a0, a0, 32
	; RV64I-NEXT: sw a0, 0(a3)
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: fshl_i32_nosext:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: andi a2, a2, 31
	; RV64ZBT-NEXT: fslw a0, a0, a1, a2
	; RV64ZBT-NEXT: sw a0, 0(a3)
	; RV64ZBT-NEXT: ret
	%1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c)
	store i32 %1, i32* %x
	ret void
	}

	declare i64 @llvm.fshl.i64(i64, i64, i64)

	define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: fshl_i64:
	; RV64I: # %bb.0:
	; RV64I-NEXT: sll a0, a0, a2
	; RV64I-NEXT: not a2, a2
	; RV64I-NEXT: srli a1, a1, 1
	; RV64I-NEXT: srl a1, a1, a2
	; RV64I-NEXT: or a0, a0, a1
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: fshl_i64:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: andi a2, a2, 63
	; RV64ZBT-NEXT: fsl a0, a0, a1, a2
	; RV64ZBT-NEXT: ret
	%1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 %c)
	ret i64 %1
	}

	declare i32 @llvm.fshr.i32(i32, i32, i32)

	define signext i32 @fshr_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
	; RV64I-LABEL: fshr_i32:
	; RV64I: # %bb.0:
	; RV64I-NEXT: slli a0, a0, 32
	; RV64I-NEXT: slli a1, a1, 32
	; RV64I-NEXT: srli a1, a1, 32
	; RV64I-NEXT: or a0, a0, a1
	; RV64I-NEXT: andi a1, a2, 31
	; RV64I-NEXT: srl a0, a0, a1
	; RV64I-NEXT: sext.w a0, a0
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: fshr_i32:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: andi a2, a2, 31
	; RV64ZBT-NEXT: fsrw a0, a1, a0, a2
	; RV64ZBT-NEXT: ret
	%1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)
	ret i32 %1
	}

	; Similar to fshr_i32 but result is not sign extended.
	define void @fshr_i32_nosext(i32 signext %a, i32 signext %b, i32 signext %c, i32* %x) nounwind {
	; RV64I-LABEL: fshr_i32_nosext:
	; RV64I: # %bb.0:
	; RV64I-NEXT: slli a0, a0, 32
	; RV64I-NEXT: slli a1, a1, 32
	; RV64I-NEXT: srli a1, a1, 32
	; RV64I-NEXT: or a0, a0, a1
	; RV64I-NEXT: andi a1, a2, 31
	; RV64I-NEXT: srl a0, a0, a1
	; RV64I-NEXT: sw a0, 0(a3)
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: fshr_i32_nosext:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: andi a2, a2, 31
	; RV64ZBT-NEXT: fsrw a0, a1, a0, a2
	; RV64ZBT-NEXT: sw a0, 0(a3)
	; RV64ZBT-NEXT: ret
	%1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)
	store i32 %1, i32* %x
	ret void
	}

	declare i64 @llvm.fshr.i64(i64, i64, i64)

	define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind {
	; RV64I-LABEL: fshr_i64:
	; RV64I: # %bb.0:
	; RV64I-NEXT: srl a1, a1, a2
	; RV64I-NEXT: not a2, a2
	; RV64I-NEXT: slli a0, a0, 1
	; RV64I-NEXT: sll a0, a0, a2
	; RV64I-NEXT: or a0, a0, a1
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: fshr_i64:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: andi a2, a2, 63
	; RV64ZBT-NEXT: fsr a0, a1, a0, a2
	; RV64ZBT-NEXT: ret
	%1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 %c)
	ret i64 %1
	}

	define signext i32 @fshri_i32(i32 signext %a, i32 signext %b) nounwind {
	; RV64I-LABEL: fshri_i32:
	; RV64I: # %bb.0:
	; RV64I-NEXT: srliw a1, a1, 5
	; RV64I-NEXT: slliw a0, a0, 27
	; RV64I-NEXT: or a0, a0, a1
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: fshri_i32:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: fsriw a0, a1, a0, 5
	; RV64ZBT-NEXT: ret
	%1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 5)
	ret i32 %1
	}

	; Similar to fshr_i32 but result is not sign extended.
	define void @fshri_i32_nosext(i32 signext %a, i32 signext %b, i32* %x) nounwind {
	; RV64I-LABEL: fshri_i32_nosext:
	; RV64I: # %bb.0:
	; RV64I-NEXT: srliw a1, a1, 5
	; RV64I-NEXT: slli a0, a0, 27
	; RV64I-NEXT: or a0, a0, a1
	; RV64I-NEXT: sw a0, 0(a2)
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: fshri_i32_nosext:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: fsriw a0, a1, a0, 5
	; RV64ZBT-NEXT: sw a0, 0(a2)
	; RV64ZBT-NEXT: ret
	%1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 5)
	store i32 %1, i32* %x
	ret void
	}

	define i64 @fshri_i64(i64 %a, i64 %b) nounwind {
	; RV64I-LABEL: fshri_i64:
	; RV64I: # %bb.0:
	; RV64I-NEXT: srli a1, a1, 5
	; RV64I-NEXT: slli a0, a0, 59
	; RV64I-NEXT: or a0, a0, a1
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: fshri_i64:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: fsri a0, a1, a0, 5
	; RV64ZBT-NEXT: ret
	%1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 5)
	ret i64 %1
	}

	define signext i32 @fshli_i32(i32 signext %a, i32 signext %b) nounwind {
	; RV64I-LABEL: fshli_i32:
	; RV64I: # %bb.0:
	; RV64I-NEXT: srliw a1, a1, 27
	; RV64I-NEXT: slliw a0, a0, 5
	; RV64I-NEXT: or a0, a0, a1
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: fshli_i32:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: fsriw a0, a1, a0, 27
	; RV64ZBT-NEXT: ret
	%1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 5)
	ret i32 %1
	}

	; Similar to fshl_i32 but result is not sign extended.
	define void @fshli_i32_nosext(i32 signext %a, i32 signext %b, i32* %x) nounwind {
	; RV64I-LABEL: fshli_i32_nosext:
	; RV64I: # %bb.0:
	; RV64I-NEXT: srliw a1, a1, 27
	; RV64I-NEXT: slli a0, a0, 5
	; RV64I-NEXT: or a0, a0, a1
	; RV64I-NEXT: sw a0, 0(a2)
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: fshli_i32_nosext:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: fsriw a0, a1, a0, 27
	; RV64ZBT-NEXT: sw a0, 0(a2)
	; RV64ZBT-NEXT: ret
	%1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 5)
	store i32 %1, i32* %x
	ret void
	}

	define i64 @fshli_i64(i64 %a, i64 %b) nounwind {
	; RV64I-LABEL: fshli_i64:
	; RV64I: # %bb.0:
	; RV64I-NEXT: srli a1, a1, 59
	; RV64I-NEXT: slli a0, a0, 5
	; RV64I-NEXT: or a0, a0, a1
	; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: fshli_i64:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: fsri a0, a1, a0, 59
	; RV64ZBT-NEXT: ret
	%1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 5)
	ret i64 %1
	}

llvm/test/CodeGen/RISCV/sadd_sat.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc < %s -mtriple=riscv32 -mattr=+m \| FileCheck %s --check-prefix=RV32I			; RUN: llc < %s -mtriple=riscv32 -mattr=+m \| FileCheck %s --check-prefixes=RV32,RV32I
	; RUN: llc < %s -mtriple=riscv64 -mattr=+m \| FileCheck %s --check-prefix=RV64I			; RUN: llc < %s -mtriple=riscv64 -mattr=+m \| FileCheck %s --check-prefixes=RV64,RV64I
	; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb \| FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbNOZbt			; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb \| FileCheck %s --check-prefixes=RV32,RV32IZbb
	; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb \| FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbNOZbt			; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb \| FileCheck %s --check-prefixes=RV64,RV64IZbb
	; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb,+experimental-zbt \| FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbZbt
	; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb,+experimental-zbt \| FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbZbt

	declare i4 @llvm.sadd.sat.i4(i4, i4)			declare i4 @llvm.sadd.sat.i4(i4, i4)
	declare i8 @llvm.sadd.sat.i8(i8, i8)			declare i8 @llvm.sadd.sat.i8(i8, i8)
	declare i16 @llvm.sadd.sat.i16(i16, i16)			declare i16 @llvm.sadd.sat.i16(i16, i16)
	declare i32 @llvm.sadd.sat.i32(i32, i32)			declare i32 @llvm.sadd.sat.i32(i32, i32)
	declare i64 @llvm.sadd.sat.i64(i64, i64)			declare i64 @llvm.sadd.sat.i64(i64, i64)

	define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {			define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
	; RV32I-LABEL: func:			; RV32-LABEL: func:
	; RV32I: # %bb.0:			; RV32: # %bb.0:
	; RV32I-NEXT: mv a2, a0			; RV32-NEXT: mv a2, a0
	; RV32I-NEXT: add a0, a0, a1			; RV32-NEXT: add a0, a0, a1
	; RV32I-NEXT: slt a2, a0, a2			; RV32-NEXT: slt a2, a0, a2
	; RV32I-NEXT: slti a1, a1, 0			; RV32-NEXT: slti a1, a1, 0
	; RV32I-NEXT: beq a1, a2, .LBB0_2			; RV32-NEXT: beq a1, a2, .LBB0_2
	; RV32I-NEXT: # %bb.1:			; RV32-NEXT: # %bb.1:
	; RV32I-NEXT: srai a0, a0, 31			; RV32-NEXT: srai a0, a0, 31
	; RV32I-NEXT: lui a1, 524288			; RV32-NEXT: lui a1, 524288
	; RV32I-NEXT: xor a0, a0, a1			; RV32-NEXT: xor a0, a0, a1
	; RV32I-NEXT: .LBB0_2:			; RV32-NEXT: .LBB0_2:
	; RV32I-NEXT: ret			; RV32-NEXT: ret
	;			;
	; RV64I-LABEL: func:			; RV64I-LABEL: func:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: add a0, a0, a1			; RV64I-NEXT: add a0, a0, a1
	; RV64I-NEXT: lui a1, 524288			; RV64I-NEXT: lui a1, 524288
	; RV64I-NEXT: addiw a2, a1, -1			; RV64I-NEXT: addiw a2, a1, -1
	; RV64I-NEXT: bge a0, a2, .LBB0_3			; RV64I-NEXT: bge a0, a2, .LBB0_3
	; RV64I-NEXT: # %bb.1:			; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: bge a1, a0, .LBB0_4			; RV64I-NEXT: bge a1, a0, .LBB0_4
	; RV64I-NEXT: .LBB0_2:			; RV64I-NEXT: .LBB0_2:
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	; RV64I-NEXT: .LBB0_3:			; RV64I-NEXT: .LBB0_3:
	; RV64I-NEXT: mv a0, a2			; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: blt a1, a0, .LBB0_2			; RV64I-NEXT: blt a1, a0, .LBB0_2
	; RV64I-NEXT: .LBB0_4:			; RV64I-NEXT: .LBB0_4:
	; RV64I-NEXT: lui a0, 524288			; RV64I-NEXT: lui a0, 524288
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;			;
	; RV32IZbbNOZbt-LABEL: func:
	; RV32IZbbNOZbt: # %bb.0:
	; RV32IZbbNOZbt-NEXT: mv a2, a0
	; RV32IZbbNOZbt-NEXT: add a0, a0, a1
	; RV32IZbbNOZbt-NEXT: slt a2, a0, a2
	; RV32IZbbNOZbt-NEXT: slti a1, a1, 0
	; RV32IZbbNOZbt-NEXT: beq a1, a2, .LBB0_2
	; RV32IZbbNOZbt-NEXT: # %bb.1:
	; RV32IZbbNOZbt-NEXT: srai a0, a0, 31
	; RV32IZbbNOZbt-NEXT: lui a1, 524288
	; RV32IZbbNOZbt-NEXT: xor a0, a0, a1
	; RV32IZbbNOZbt-NEXT: .LBB0_2:
	; RV32IZbbNOZbt-NEXT: ret
	;
	; RV64IZbb-LABEL: func:			; RV64IZbb-LABEL: func:
	; RV64IZbb: # %bb.0:			; RV64IZbb: # %bb.0:
	; RV64IZbb-NEXT: add a0, a0, a1			; RV64IZbb-NEXT: add a0, a0, a1
	; RV64IZbb-NEXT: lui a1, 524288			; RV64IZbb-NEXT: lui a1, 524288
	; RV64IZbb-NEXT: addiw a2, a1, -1			; RV64IZbb-NEXT: addiw a2, a1, -1
	; RV64IZbb-NEXT: min a0, a0, a2			; RV64IZbb-NEXT: min a0, a0, a2
	; RV64IZbb-NEXT: max a0, a0, a1			; RV64IZbb-NEXT: max a0, a0, a1
	; RV64IZbb-NEXT: ret			; RV64IZbb-NEXT: ret
	;
	; RV32IZbbZbt-LABEL: func:
	; RV32IZbbZbt: # %bb.0:
	; RV32IZbbZbt-NEXT: add a2, a0, a1
	; RV32IZbbZbt-NEXT: slt a0, a2, a0
	; RV32IZbbZbt-NEXT: slti a1, a1, 0
	; RV32IZbbZbt-NEXT: xor a0, a1, a0
	; RV32IZbbZbt-NEXT: srai a1, a2, 31
	; RV32IZbbZbt-NEXT: lui a3, 524288
	; RV32IZbbZbt-NEXT: xor a1, a1, a3
	; RV32IZbbZbt-NEXT: cmov a0, a0, a1, a2
	; RV32IZbbZbt-NEXT: ret
	%tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y);			%tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y);
	ret i32 %tmp;			ret i32 %tmp;
	}			}

	define i64 @func2(i64 %x, i64 %y) nounwind {			define i64 @func2(i64 %x, i64 %y) nounwind {
	; RV32I-LABEL: func2:			; RV32I-LABEL: func2:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	; RV32I-NEXT: mv a4, a1			; RV32I-NEXT: mv a4, a1
	Show All 9 Lines
	; RV32I-NEXT: bgez a2, .LBB1_2			; RV32I-NEXT: bgez a2, .LBB1_2
	; RV32I-NEXT: # %bb.1:			; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: srai a0, a1, 31			; RV32I-NEXT: srai a0, a1, 31
	; RV32I-NEXT: lui a1, 524288			; RV32I-NEXT: lui a1, 524288
	; RV32I-NEXT: xor a1, a0, a1			; RV32I-NEXT: xor a1, a0, a1
	; RV32I-NEXT: .LBB1_2:			; RV32I-NEXT: .LBB1_2:
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV64I-LABEL: func2:			; RV64-LABEL: func2:
	; RV64I: # %bb.0:			; RV64: # %bb.0:
	; RV64I-NEXT: mv a2, a0			; RV64-NEXT: mv a2, a0
	; RV64I-NEXT: add a0, a0, a1			; RV64-NEXT: add a0, a0, a1
	; RV64I-NEXT: slt a2, a0, a2			; RV64-NEXT: slt a2, a0, a2
	; RV64I-NEXT: slti a1, a1, 0			; RV64-NEXT: slti a1, a1, 0
	; RV64I-NEXT: beq a1, a2, .LBB1_2			; RV64-NEXT: beq a1, a2, .LBB1_2
	; RV64I-NEXT: # %bb.1:			; RV64-NEXT: # %bb.1:
	; RV64I-NEXT: srai a0, a0, 63			; RV64-NEXT: srai a0, a0, 63
	; RV64I-NEXT: li a1, -1			; RV64-NEXT: li a1, -1
	; RV64I-NEXT: slli a1, a1, 63			; RV64-NEXT: slli a1, a1, 63
	; RV64I-NEXT: xor a0, a0, a1			; RV64-NEXT: xor a0, a0, a1
	; RV64I-NEXT: .LBB1_2:			; RV64-NEXT: .LBB1_2:
	; RV64I-NEXT: ret			; RV64-NEXT: ret
	;			;
	; RV32IZbbNOZbt-LABEL: func2:			; RV32IZbb-LABEL: func2:
	; RV32IZbbNOZbt: # %bb.0:			; RV32IZbb: # %bb.0:
	; RV32IZbbNOZbt-NEXT: mv a4, a1			; RV32IZbb-NEXT: mv a4, a1
	; RV32IZbbNOZbt-NEXT: mv a1, a0			; RV32IZbb-NEXT: mv a1, a0
	; RV32IZbbNOZbt-NEXT: add a5, a4, a3			; RV32IZbb-NEXT: add a5, a4, a3
	; RV32IZbbNOZbt-NEXT: add a0, a0, a2			; RV32IZbb-NEXT: add a0, a0, a2
	; RV32IZbbNOZbt-NEXT: sltu a1, a0, a1			; RV32IZbb-NEXT: sltu a1, a0, a1
	; RV32IZbbNOZbt-NEXT: add a1, a5, a1			; RV32IZbb-NEXT: add a1, a5, a1
	; RV32IZbbNOZbt-NEXT: xor a2, a4, a1			; RV32IZbb-NEXT: xor a2, a4, a1
	; RV32IZbbNOZbt-NEXT: xor a3, a4, a3			; RV32IZbb-NEXT: xor a3, a4, a3
	; RV32IZbbNOZbt-NEXT: andn a2, a2, a3			; RV32IZbb-NEXT: andn a2, a2, a3
	; RV32IZbbNOZbt-NEXT: bgez a2, .LBB1_2			; RV32IZbb-NEXT: bgez a2, .LBB1_2
	; RV32IZbbNOZbt-NEXT: # %bb.1:			; RV32IZbb-NEXT: # %bb.1:
	; RV32IZbbNOZbt-NEXT: srai a0, a1, 31			; RV32IZbb-NEXT: srai a0, a1, 31
	; RV32IZbbNOZbt-NEXT: lui a1, 524288			; RV32IZbb-NEXT: lui a1, 524288
	; RV32IZbbNOZbt-NEXT: xor a1, a0, a1			; RV32IZbb-NEXT: xor a1, a0, a1
	; RV32IZbbNOZbt-NEXT: .LBB1_2:			; RV32IZbb-NEXT: .LBB1_2:
	; RV32IZbbNOZbt-NEXT: ret			; RV32IZbb-NEXT: ret
	;
	; RV64IZbbNOZbt-LABEL: func2:
	; RV64IZbbNOZbt: # %bb.0:
	; RV64IZbbNOZbt-NEXT: mv a2, a0
	; RV64IZbbNOZbt-NEXT: add a0, a0, a1
	; RV64IZbbNOZbt-NEXT: slt a2, a0, a2
	; RV64IZbbNOZbt-NEXT: slti a1, a1, 0
	; RV64IZbbNOZbt-NEXT: beq a1, a2, .LBB1_2
	; RV64IZbbNOZbt-NEXT: # %bb.1:
	; RV64IZbbNOZbt-NEXT: srai a0, a0, 63
	; RV64IZbbNOZbt-NEXT: li a1, -1
	; RV64IZbbNOZbt-NEXT: slli a1, a1, 63
	; RV64IZbbNOZbt-NEXT: xor a0, a0, a1
	; RV64IZbbNOZbt-NEXT: .LBB1_2:
	; RV64IZbbNOZbt-NEXT: ret
	;
	; RV32IZbbZbt-LABEL: func2:
	; RV32IZbbZbt: # %bb.0:
	; RV32IZbbZbt-NEXT: add a4, a1, a3
	; RV32IZbbZbt-NEXT: add a2, a0, a2
	; RV32IZbbZbt-NEXT: sltu a0, a2, a0
	; RV32IZbbZbt-NEXT: add a0, a4, a0
	; RV32IZbbZbt-NEXT: srai a4, a0, 31
	; RV32IZbbZbt-NEXT: lui a5, 524288
	; RV32IZbbZbt-NEXT: xor a5, a4, a5
	; RV32IZbbZbt-NEXT: xor a6, a1, a0
	; RV32IZbbZbt-NEXT: xor a1, a1, a3
	; RV32IZbbZbt-NEXT: andn a1, a6, a1
	; RV32IZbbZbt-NEXT: slti a3, a1, 0
	; RV32IZbbZbt-NEXT: cmov a1, a3, a5, a0
	; RV32IZbbZbt-NEXT: cmov a0, a3, a4, a2
	; RV32IZbbZbt-NEXT: ret
	;
	; RV64IZbbZbt-LABEL: func2:
	; RV64IZbbZbt: # %bb.0:
	; RV64IZbbZbt-NEXT: add a2, a0, a1
	; RV64IZbbZbt-NEXT: slt a0, a2, a0
	; RV64IZbbZbt-NEXT: slti a1, a1, 0
	; RV64IZbbZbt-NEXT: xor a0, a1, a0
	; RV64IZbbZbt-NEXT: srai a1, a2, 63
	; RV64IZbbZbt-NEXT: li a3, -1
	; RV64IZbbZbt-NEXT: slli a3, a3, 63
	; RV64IZbbZbt-NEXT: xor a1, a1, a3
	; RV64IZbbZbt-NEXT: cmov a0, a0, a1, a2
	; RV64IZbbZbt-NEXT: ret
	%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y);			%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y);
	ret i64 %tmp;			ret i64 %tmp;
	}			}

	define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {			define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
	; RV32I-LABEL: func16:			; RV32I-LABEL: func16:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	; RV32I-NEXT: add a0, a0, a1			; RV32I-NEXT: add a0, a0, a1
	▲ Show 20 Lines • Show All 173 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/sadd_sat_plus.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc < %s -mtriple=riscv32 -mattr=+m \| FileCheck %s --check-prefix=RV32I			; RUN: llc < %s -mtriple=riscv32 -mattr=+m \| FileCheck %s --check-prefixes=RV32,RV32I
	; RUN: llc < %s -mtriple=riscv64 -mattr=+m \| FileCheck %s --check-prefix=RV64I			; RUN: llc < %s -mtriple=riscv64 -mattr=+m \| FileCheck %s --check-prefixes=RV64,RV64I
	; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb \| FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbNOZbt			; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb \| FileCheck %s --check-prefixes=RV32,RV32IZbb
	; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb \| FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbNOZbt			; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb \| FileCheck %s --check-prefixes=RV64,RV64IZbb
	; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb,+experimental-zbt \| FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbZbt
	; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb,+experimental-zbt \| FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbZbt

	declare i4 @llvm.sadd.sat.i4(i4, i4)			declare i4 @llvm.sadd.sat.i4(i4, i4)
	declare i8 @llvm.sadd.sat.i8(i8, i8)			declare i8 @llvm.sadd.sat.i8(i8, i8)
	declare i16 @llvm.sadd.sat.i16(i16, i16)			declare i16 @llvm.sadd.sat.i16(i16, i16)
	declare i32 @llvm.sadd.sat.i32(i32, i32)			declare i32 @llvm.sadd.sat.i32(i32, i32)
	declare i64 @llvm.sadd.sat.i64(i64, i64)			declare i64 @llvm.sadd.sat.i64(i64, i64)

	define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {			define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
	; RV32I-LABEL: func32:			; RV32-LABEL: func32:
	; RV32I: # %bb.0:			; RV32: # %bb.0:
	; RV32I-NEXT: mv a3, a0			; RV32-NEXT: mv a3, a0
	; RV32I-NEXT: mul a1, a1, a2			; RV32-NEXT: mul a1, a1, a2
	; RV32I-NEXT: add a0, a0, a1			; RV32-NEXT: add a0, a0, a1
	; RV32I-NEXT: slt a2, a0, a3			; RV32-NEXT: slt a2, a0, a3
	; RV32I-NEXT: slti a1, a1, 0			; RV32-NEXT: slti a1, a1, 0
	; RV32I-NEXT: beq a1, a2, .LBB0_2			; RV32-NEXT: beq a1, a2, .LBB0_2
	; RV32I-NEXT: # %bb.1:			; RV32-NEXT: # %bb.1:
	; RV32I-NEXT: srai a0, a0, 31			; RV32-NEXT: srai a0, a0, 31
	; RV32I-NEXT: lui a1, 524288			; RV32-NEXT: lui a1, 524288
	; RV32I-NEXT: xor a0, a0, a1			; RV32-NEXT: xor a0, a0, a1
	; RV32I-NEXT: .LBB0_2:			; RV32-NEXT: .LBB0_2:
	; RV32I-NEXT: ret			; RV32-NEXT: ret
	;			;
	; RV64I-LABEL: func32:			; RV64I-LABEL: func32:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: sext.w a0, a0			; RV64I-NEXT: sext.w a0, a0
	; RV64I-NEXT: mulw a1, a1, a2			; RV64I-NEXT: mulw a1, a1, a2
	; RV64I-NEXT: add a0, a0, a1			; RV64I-NEXT: add a0, a0, a1
	; RV64I-NEXT: lui a1, 524288			; RV64I-NEXT: lui a1, 524288
	; RV64I-NEXT: addiw a2, a1, -1			; RV64I-NEXT: addiw a2, a1, -1
	; RV64I-NEXT: bge a0, a2, .LBB0_3			; RV64I-NEXT: bge a0, a2, .LBB0_3
	; RV64I-NEXT: # %bb.1:			; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: bge a1, a0, .LBB0_4			; RV64I-NEXT: bge a1, a0, .LBB0_4
	; RV64I-NEXT: .LBB0_2:			; RV64I-NEXT: .LBB0_2:
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	; RV64I-NEXT: .LBB0_3:			; RV64I-NEXT: .LBB0_3:
	; RV64I-NEXT: mv a0, a2			; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: blt a1, a0, .LBB0_2			; RV64I-NEXT: blt a1, a0, .LBB0_2
	; RV64I-NEXT: .LBB0_4:			; RV64I-NEXT: .LBB0_4:
	; RV64I-NEXT: lui a0, 524288			; RV64I-NEXT: lui a0, 524288
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;			;
	; RV32IZbbNOZbt-LABEL: func32:
	; RV32IZbbNOZbt: # %bb.0:
	; RV32IZbbNOZbt-NEXT: mv a3, a0
	; RV32IZbbNOZbt-NEXT: mul a1, a1, a2
	; RV32IZbbNOZbt-NEXT: add a0, a0, a1
	; RV32IZbbNOZbt-NEXT: slt a2, a0, a3
	; RV32IZbbNOZbt-NEXT: slti a1, a1, 0
	; RV32IZbbNOZbt-NEXT: beq a1, a2, .LBB0_2
	; RV32IZbbNOZbt-NEXT: # %bb.1:
	; RV32IZbbNOZbt-NEXT: srai a0, a0, 31
	; RV32IZbbNOZbt-NEXT: lui a1, 524288
	; RV32IZbbNOZbt-NEXT: xor a0, a0, a1
	; RV32IZbbNOZbt-NEXT: .LBB0_2:
	; RV32IZbbNOZbt-NEXT: ret
	;
	; RV64IZbb-LABEL: func32:			; RV64IZbb-LABEL: func32:
	; RV64IZbb: # %bb.0:			; RV64IZbb: # %bb.0:
	; RV64IZbb-NEXT: sext.w a0, a0			; RV64IZbb-NEXT: sext.w a0, a0
	; RV64IZbb-NEXT: mulw a1, a1, a2			; RV64IZbb-NEXT: mulw a1, a1, a2
	; RV64IZbb-NEXT: add a0, a0, a1			; RV64IZbb-NEXT: add a0, a0, a1
	; RV64IZbb-NEXT: lui a1, 524288			; RV64IZbb-NEXT: lui a1, 524288
	; RV64IZbb-NEXT: addiw a2, a1, -1			; RV64IZbb-NEXT: addiw a2, a1, -1
	; RV64IZbb-NEXT: min a0, a0, a2			; RV64IZbb-NEXT: min a0, a0, a2
	; RV64IZbb-NEXT: max a0, a0, a1			; RV64IZbb-NEXT: max a0, a0, a1
	; RV64IZbb-NEXT: ret			; RV64IZbb-NEXT: ret
	;
	; RV32IZbbZbt-LABEL: func32:
	; RV32IZbbZbt: # %bb.0:
	; RV32IZbbZbt-NEXT: mul a1, a1, a2
	; RV32IZbbZbt-NEXT: add a2, a0, a1
	; RV32IZbbZbt-NEXT: slt a0, a2, a0
	; RV32IZbbZbt-NEXT: slti a1, a1, 0
	; RV32IZbbZbt-NEXT: xor a0, a1, a0
	; RV32IZbbZbt-NEXT: srai a1, a2, 31
	; RV32IZbbZbt-NEXT: lui a3, 524288
	; RV32IZbbZbt-NEXT: xor a1, a1, a3
	; RV32IZbbZbt-NEXT: cmov a0, a0, a1, a2
	; RV32IZbbZbt-NEXT: ret
	%a = mul i32 %y, %z			%a = mul i32 %y, %z
	%tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %a)			%tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %a)
	ret i32 %tmp			ret i32 %tmp
	}			}

	define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {			define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
	; RV32I-LABEL: func64:			; RV32I-LABEL: func64:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	Show All 10 Lines
	; RV32I-NEXT: bgez a2, .LBB1_2			; RV32I-NEXT: bgez a2, .LBB1_2
	; RV32I-NEXT: # %bb.1:			; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: srai a0, a1, 31			; RV32I-NEXT: srai a0, a1, 31
	; RV32I-NEXT: lui a1, 524288			; RV32I-NEXT: lui a1, 524288
	; RV32I-NEXT: xor a1, a0, a1			; RV32I-NEXT: xor a1, a0, a1
	; RV32I-NEXT: .LBB1_2:			; RV32I-NEXT: .LBB1_2:
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV64I-LABEL: func64:			; RV64-LABEL: func64:
	; RV64I: # %bb.0:			; RV64: # %bb.0:
	; RV64I-NEXT: mv a1, a0			; RV64-NEXT: mv a1, a0
	; RV64I-NEXT: add a0, a0, a2			; RV64-NEXT: add a0, a0, a2
	; RV64I-NEXT: slt a1, a0, a1			; RV64-NEXT: slt a1, a0, a1
	; RV64I-NEXT: slti a2, a2, 0			; RV64-NEXT: slti a2, a2, 0
	; RV64I-NEXT: beq a2, a1, .LBB1_2			; RV64-NEXT: beq a2, a1, .LBB1_2
	; RV64I-NEXT: # %bb.1:			; RV64-NEXT: # %bb.1:
	; RV64I-NEXT: srai a0, a0, 63			; RV64-NEXT: srai a0, a0, 63
	; RV64I-NEXT: li a1, -1			; RV64-NEXT: li a1, -1
	; RV64I-NEXT: slli a1, a1, 63			; RV64-NEXT: slli a1, a1, 63
	; RV64I-NEXT: xor a0, a0, a1			; RV64-NEXT: xor a0, a0, a1
	; RV64I-NEXT: .LBB1_2:			; RV64-NEXT: .LBB1_2:
	; RV64I-NEXT: ret			; RV64-NEXT: ret
	;			;
	; RV32IZbbNOZbt-LABEL: func64:			; RV32IZbb-LABEL: func64:
	; RV32IZbbNOZbt: # %bb.0:			; RV32IZbb: # %bb.0:
	; RV32IZbbNOZbt-NEXT: mv a2, a1			; RV32IZbb-NEXT: mv a2, a1
	; RV32IZbbNOZbt-NEXT: mv a1, a0			; RV32IZbb-NEXT: mv a1, a0
	; RV32IZbbNOZbt-NEXT: add a3, a2, a5			; RV32IZbb-NEXT: add a3, a2, a5
	; RV32IZbbNOZbt-NEXT: add a0, a0, a4			; RV32IZbb-NEXT: add a0, a0, a4
	; RV32IZbbNOZbt-NEXT: sltu a1, a0, a1			; RV32IZbb-NEXT: sltu a1, a0, a1
	; RV32IZbbNOZbt-NEXT: add a1, a3, a1			; RV32IZbb-NEXT: add a1, a3, a1
	; RV32IZbbNOZbt-NEXT: xor a3, a2, a1			; RV32IZbb-NEXT: xor a3, a2, a1
	; RV32IZbbNOZbt-NEXT: xor a2, a2, a5			; RV32IZbb-NEXT: xor a2, a2, a5
	; RV32IZbbNOZbt-NEXT: andn a2, a3, a2			; RV32IZbb-NEXT: andn a2, a3, a2
	; RV32IZbbNOZbt-NEXT: bgez a2, .LBB1_2			; RV32IZbb-NEXT: bgez a2, .LBB1_2
	; RV32IZbbNOZbt-NEXT: # %bb.1:			; RV32IZbb-NEXT: # %bb.1:
	; RV32IZbbNOZbt-NEXT: srai a0, a1, 31			; RV32IZbb-NEXT: srai a0, a1, 31
	; RV32IZbbNOZbt-NEXT: lui a1, 524288			; RV32IZbb-NEXT: lui a1, 524288
	; RV32IZbbNOZbt-NEXT: xor a1, a0, a1			; RV32IZbb-NEXT: xor a1, a0, a1
	; RV32IZbbNOZbt-NEXT: .LBB1_2:			; RV32IZbb-NEXT: .LBB1_2:
	; RV32IZbbNOZbt-NEXT: ret			; RV32IZbb-NEXT: ret
	;
	; RV64IZbbNOZbt-LABEL: func64:
	; RV64IZbbNOZbt: # %bb.0:
	; RV64IZbbNOZbt-NEXT: mv a1, a0
	; RV64IZbbNOZbt-NEXT: add a0, a0, a2
	; RV64IZbbNOZbt-NEXT: slt a1, a0, a1
	; RV64IZbbNOZbt-NEXT: slti a2, a2, 0
	; RV64IZbbNOZbt-NEXT: beq a2, a1, .LBB1_2
	; RV64IZbbNOZbt-NEXT: # %bb.1:
	; RV64IZbbNOZbt-NEXT: srai a0, a0, 63
	; RV64IZbbNOZbt-NEXT: li a1, -1
	; RV64IZbbNOZbt-NEXT: slli a1, a1, 63
	; RV64IZbbNOZbt-NEXT: xor a0, a0, a1
	; RV64IZbbNOZbt-NEXT: .LBB1_2:
	; RV64IZbbNOZbt-NEXT: ret
	;
	; RV32IZbbZbt-LABEL: func64:
	; RV32IZbbZbt: # %bb.0:
	; RV32IZbbZbt-NEXT: add a2, a1, a5
	; RV32IZbbZbt-NEXT: add a3, a0, a4
	; RV32IZbbZbt-NEXT: sltu a0, a3, a0
	; RV32IZbbZbt-NEXT: add a0, a2, a0
	; RV32IZbbZbt-NEXT: srai a2, a0, 31
	; RV32IZbbZbt-NEXT: lui a4, 524288
	; RV32IZbbZbt-NEXT: xor a4, a2, a4
	; RV32IZbbZbt-NEXT: xor a6, a1, a0
	; RV32IZbbZbt-NEXT: xor a1, a1, a5
	; RV32IZbbZbt-NEXT: andn a1, a6, a1
	; RV32IZbbZbt-NEXT: slti a5, a1, 0
	; RV32IZbbZbt-NEXT: cmov a1, a5, a4, a0
	; RV32IZbbZbt-NEXT: cmov a0, a5, a2, a3
	; RV32IZbbZbt-NEXT: ret
	;
	; RV64IZbbZbt-LABEL: func64:
	; RV64IZbbZbt: # %bb.0:
	; RV64IZbbZbt-NEXT: add a1, a0, a2
	; RV64IZbbZbt-NEXT: slt a0, a1, a0
	; RV64IZbbZbt-NEXT: slti a2, a2, 0
	; RV64IZbbZbt-NEXT: xor a0, a2, a0
	; RV64IZbbZbt-NEXT: srai a2, a1, 63
	; RV64IZbbZbt-NEXT: li a3, -1
	; RV64IZbbZbt-NEXT: slli a3, a3, 63
	; RV64IZbbZbt-NEXT: xor a2, a2, a3
	; RV64IZbbZbt-NEXT: cmov a0, a0, a2, a1
	; RV64IZbbZbt-NEXT: ret
	%a = mul i64 %y, %z			%a = mul i64 %y, %z
	%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z)			%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z)
	ret i64 %tmp			ret i64 %tmp
	}			}

	define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {			define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
	; RV32I-LABEL: func16:			; RV32I-LABEL: func16:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
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llvm/test/CodeGen/RISCV/select-and.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
	; RUN: \| FileCheck -check-prefix=RV32I %s			; RUN: \| FileCheck -check-prefix=RV32I %s
	; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
	; RUN: \| FileCheck -check-prefix=RV32IBT %s
	; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
	; RUN: \| FileCheck -check-prefix=RV64I %s			; RUN: \| FileCheck -check-prefix=RV64I %s
	; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \
	; RUN: \| FileCheck -check-prefix=RV64IBT %s

	;; There are a few different ways to lower (select (and A, B), X, Y). This test			;; There are a few different ways to lower (select (and A, B), X, Y). This test
	;; ensures that we do so with as few branches as possible.			;; ensures that we do so with as few branches as possible.

	define signext i32 @select_of_and(i1 zeroext %a, i1 zeroext %b, i32 signext %c, i32 signext %d) nounwind {			define signext i32 @select_of_and(i1 zeroext %a, i1 zeroext %b, i32 signext %c, i32 signext %d) nounwind {
	; RV32I-LABEL: select_of_and:			; RV32I-LABEL: select_of_and:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	; RV32I-NEXT: and a1, a0, a1			; RV32I-NEXT: and a1, a0, a1
	; RV32I-NEXT: mv a0, a2			; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: bnez a1, .LBB0_2			; RV32I-NEXT: bnez a1, .LBB0_2
	; RV32I-NEXT: # %bb.1:			; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a3			; RV32I-NEXT: mv a0, a3
	; RV32I-NEXT: .LBB0_2:			; RV32I-NEXT: .LBB0_2:
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32IBT-LABEL: select_of_and:
	; RV32IBT: # %bb.0:
	; RV32IBT-NEXT: and a0, a0, a1
	; RV32IBT-NEXT: cmov a0, a0, a2, a3
	; RV32IBT-NEXT: ret
	;
	; RV64I-LABEL: select_of_and:			; RV64I-LABEL: select_of_and:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: and a1, a0, a1			; RV64I-NEXT: and a1, a0, a1
	; RV64I-NEXT: mv a0, a2			; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: bnez a1, .LBB0_2			; RV64I-NEXT: bnez a1, .LBB0_2
	; RV64I-NEXT: # %bb.1:			; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a3			; RV64I-NEXT: mv a0, a3
	; RV64I-NEXT: .LBB0_2:			; RV64I-NEXT: .LBB0_2:
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;
	; RV64IBT-LABEL: select_of_and:
	; RV64IBT: # %bb.0:
	; RV64IBT-NEXT: and a0, a0, a1
	; RV64IBT-NEXT: cmov a0, a0, a2, a3
	; RV64IBT-NEXT: ret
	%1 = and i1 %a, %b			%1 = and i1 %a, %b
	%2 = select i1 %1, i32 %c, i32 %d			%2 = select i1 %1, i32 %c, i32 %d
	ret i32 %2			ret i32 %2
	}			}

	declare signext i32 @both() nounwind			declare signext i32 @both() nounwind
	declare signext i32 @neither() nounwind			declare signext i32 @neither() nounwind

	Show All 9 Lines
	; RV32I-NEXT: j .LBB1_3			; RV32I-NEXT: j .LBB1_3
	; RV32I-NEXT: .LBB1_2: # %if.else			; RV32I-NEXT: .LBB1_2: # %if.else
	; RV32I-NEXT: call neither@plt			; RV32I-NEXT: call neither@plt
	; RV32I-NEXT: .LBB1_3: # %if.end			; RV32I-NEXT: .LBB1_3: # %if.end
	; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload			; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
	; RV32I-NEXT: addi sp, sp, 16			; RV32I-NEXT: addi sp, sp, 16
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32IBT-LABEL: if_of_and:
	; RV32IBT: # %bb.0:
	; RV32IBT-NEXT: addi sp, sp, -16
	; RV32IBT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
	; RV32IBT-NEXT: and a0, a0, a1
	; RV32IBT-NEXT: beqz a0, .LBB1_2
	; RV32IBT-NEXT: # %bb.1: # %if.then
	; RV32IBT-NEXT: call both@plt
	; RV32IBT-NEXT: j .LBB1_3
	; RV32IBT-NEXT: .LBB1_2: # %if.else
	; RV32IBT-NEXT: call neither@plt
	; RV32IBT-NEXT: .LBB1_3: # %if.end
	; RV32IBT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
	; RV32IBT-NEXT: addi sp, sp, 16
	; RV32IBT-NEXT: ret
	;
	; RV64I-LABEL: if_of_and:			; RV64I-LABEL: if_of_and:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: addi sp, sp, -16			; RV64I-NEXT: addi sp, sp, -16
	; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill			; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
	; RV64I-NEXT: and a0, a0, a1			; RV64I-NEXT: and a0, a0, a1
	; RV64I-NEXT: beqz a0, .LBB1_2			; RV64I-NEXT: beqz a0, .LBB1_2
	; RV64I-NEXT: # %bb.1: # %if.then			; RV64I-NEXT: # %bb.1: # %if.then
	; RV64I-NEXT: call both@plt			; RV64I-NEXT: call both@plt
	; RV64I-NEXT: j .LBB1_3			; RV64I-NEXT: j .LBB1_3
	; RV64I-NEXT: .LBB1_2: # %if.else			; RV64I-NEXT: .LBB1_2: # %if.else
	; RV64I-NEXT: call neither@plt			; RV64I-NEXT: call neither@plt
	; RV64I-NEXT: .LBB1_3: # %if.end			; RV64I-NEXT: .LBB1_3: # %if.end
	; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload			; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
	; RV64I-NEXT: addi sp, sp, 16			; RV64I-NEXT: addi sp, sp, 16
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;
	; RV64IBT-LABEL: if_of_and:
	; RV64IBT: # %bb.0:
	; RV64IBT-NEXT: addi sp, sp, -16
	; RV64IBT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
	; RV64IBT-NEXT: and a0, a0, a1
	; RV64IBT-NEXT: beqz a0, .LBB1_2
	; RV64IBT-NEXT: # %bb.1: # %if.then
	; RV64IBT-NEXT: call both@plt
	; RV64IBT-NEXT: j .LBB1_3
	; RV64IBT-NEXT: .LBB1_2: # %if.else
	; RV64IBT-NEXT: call neither@plt
	; RV64IBT-NEXT: .LBB1_3: # %if.end
	; RV64IBT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
	; RV64IBT-NEXT: addi sp, sp, 16
	; RV64IBT-NEXT: ret
	%1 = and i1 %a, %b			%1 = and i1 %a, %b
	br i1 %1, label %if.then, label %if.else			br i1 %1, label %if.then, label %if.else

	if.then:			if.then:
	%2 = tail call i32 @both()			%2 = tail call i32 @both()
	br label %if.end			br label %if.end

	if.else:			if.else:
	%3 = tail call i32 @neither()			%3 = tail call i32 @neither()
	br label %if.end			br label %if.end

	if.end:			if.end:
	%4 = phi i32 [%2, %if.then], [%3, %if.else]			%4 = phi i32 [%2, %if.then], [%3, %if.else]
	ret i32 %4			ret i32 %4
	}			}

llvm/test/CodeGen/RISCV/select-bare.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s -check-prefix=RV32I			; RUN: \| FileCheck %s -check-prefix=RV32I
	; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s -check-prefix=RV32IBT

	define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {			define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
	; RV32I-LABEL: bare_select:			; RV32I-LABEL: bare_select:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	; RV32I-NEXT: andi a3, a0, 1			; RV32I-NEXT: andi a3, a0, 1
	; RV32I-NEXT: mv a0, a1			; RV32I-NEXT: mv a0, a1
	; RV32I-NEXT: bnez a3, .LBB0_2			; RV32I-NEXT: bnez a3, .LBB0_2
	; RV32I-NEXT: # %bb.1:			; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a2			; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: .LBB0_2:			; RV32I-NEXT: .LBB0_2:
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;
	; RV32IBT-LABEL: bare_select:
	; RV32IBT: # %bb.0:
	; RV32IBT-NEXT: andi a0, a0, 1
	; RV32IBT-NEXT: cmov a0, a0, a1, a2
	; RV32IBT-NEXT: ret
	%1 = select i1 %a, i32 %b, i32 %c			%1 = select i1 %a, i32 %b, i32 %c
	ret i32 %1			ret i32 %1
	}			}

	define float @bare_select_float(i1 %a, float %b, float %c) nounwind {			define float @bare_select_float(i1 %a, float %b, float %c) nounwind {
	; RV32I-LABEL: bare_select_float:			; RV32I-LABEL: bare_select_float:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	; RV32I-NEXT: andi a3, a0, 1			; RV32I-NEXT: andi a3, a0, 1
	; RV32I-NEXT: mv a0, a1			; RV32I-NEXT: mv a0, a1
	; RV32I-NEXT: bnez a3, .LBB1_2			; RV32I-NEXT: bnez a3, .LBB1_2
	; RV32I-NEXT: # %bb.1:			; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a2			; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: .LBB1_2:			; RV32I-NEXT: .LBB1_2:
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;
	; RV32IBT-LABEL: bare_select_float:
	; RV32IBT: # %bb.0:
	; RV32IBT-NEXT: andi a0, a0, 1
	; RV32IBT-NEXT: cmov a0, a0, a1, a2
	; RV32IBT-NEXT: ret
	%1 = select i1 %a, float %b, float %c			%1 = select i1 %a, float %b, float %c
	ret float %1			ret float %1
	}			}

llvm/test/CodeGen/RISCV/select-cc.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv32 -disable-block-placement -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv32 -disable-block-placement -verify-machineinstrs < %s \
	; RUN: \| FileCheck -check-prefixes=RV32I %s			; RUN: \| FileCheck -check-prefixes=RV32I %s
	; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -disable-block-placement -verify-machineinstrs < %s \
	; RUN: \| FileCheck -check-prefixes=RV32ZBT %s
	; RUN: llc -mtriple=riscv64 -disable-block-placement -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv64 -disable-block-placement -verify-machineinstrs < %s \
	; RUN: \| FileCheck -check-prefixes=RV64I %s			; RUN: \| FileCheck -check-prefixes=RV64I %s
	; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -disable-block-placement -verify-machineinstrs < %s \
	; RUN: \| FileCheck -check-prefixes=RV64ZBT %s

	define signext i32 @foo(i32 signext %a, i32 *%b) nounwind {			define signext i32 @foo(i32 signext %a, i32 *%b) nounwind {
	; RV32I-LABEL: foo:			; RV32I-LABEL: foo:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	; RV32I-NEXT: lw a2, 0(a1)			; RV32I-NEXT: lw a2, 0(a1)
	; RV32I-NEXT: beq a0, a2, .LBB0_2			; RV32I-NEXT: beq a0, a2, .LBB0_2
	; RV32I-NEXT: # %bb.1:			; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a2			; RV32I-NEXT: mv a0, a2
	▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
	; RV32I-NEXT: lw a1, 0(a1)			; RV32I-NEXT: lw a1, 0(a1)
	; RV32I-NEXT: li a3, 2046			; RV32I-NEXT: li a3, 2046
	; RV32I-NEXT: bltu a3, a2, .LBB0_28			; RV32I-NEXT: bltu a3, a2, .LBB0_28
	; RV32I-NEXT: # %bb.27:			; RV32I-NEXT: # %bb.27:
	; RV32I-NEXT: mv a0, a1			; RV32I-NEXT: mv a0, a1
	; RV32I-NEXT: .LBB0_28:			; RV32I-NEXT: .LBB0_28:
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBT-LABEL: foo:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: lw a2, 0(a1)
	; RV32ZBT-NEXT: lw a3, 0(a1)
	; RV32ZBT-NEXT: xor a4, a0, a2
	; RV32ZBT-NEXT: cmov a0, a4, a2, a0
	; RV32ZBT-NEXT: lw a2, 0(a1)
	; RV32ZBT-NEXT: xor a4, a0, a3
	; RV32ZBT-NEXT: cmov a0, a4, a0, a3
	; RV32ZBT-NEXT: lw a3, 0(a1)
	; RV32ZBT-NEXT: sltu a4, a2, a0
	; RV32ZBT-NEXT: cmov a0, a4, a0, a2
	; RV32ZBT-NEXT: lw a2, 0(a1)
	; RV32ZBT-NEXT: sltu a4, a0, a3
	; RV32ZBT-NEXT: cmov a0, a4, a3, a0
	; RV32ZBT-NEXT: lw a3, 0(a1)
	; RV32ZBT-NEXT: sltu a4, a0, a2
	; RV32ZBT-NEXT: cmov a0, a4, a0, a2
	; RV32ZBT-NEXT: lw a2, 0(a1)
	; RV32ZBT-NEXT: sltu a4, a3, a0
	; RV32ZBT-NEXT: cmov a0, a4, a3, a0
	; RV32ZBT-NEXT: lw a3, 0(a1)
	; RV32ZBT-NEXT: slt a4, a2, a0
	; RV32ZBT-NEXT: cmov a0, a4, a0, a2
	; RV32ZBT-NEXT: lw a2, 0(a1)
	; RV32ZBT-NEXT: slt a4, a0, a3
	; RV32ZBT-NEXT: cmov a0, a4, a3, a0
	; RV32ZBT-NEXT: lw a3, 0(a1)
	; RV32ZBT-NEXT: slt a4, a0, a2
	; RV32ZBT-NEXT: lw a5, 0(a1)
	; RV32ZBT-NEXT: cmov a0, a4, a0, a2
	; RV32ZBT-NEXT: slt a2, a3, a0
	; RV32ZBT-NEXT: cmov a0, a2, a3, a0
	; RV32ZBT-NEXT: slti a2, a5, 1
	; RV32ZBT-NEXT: lw a3, 0(a1)
	; RV32ZBT-NEXT: cmov a0, a2, a0, a5
	; RV32ZBT-NEXT: lw a2, 0(a1)
	; RV32ZBT-NEXT: slti a4, a5, 0
	; RV32ZBT-NEXT: cmov a0, a4, a3, a0
	; RV32ZBT-NEXT: lw a1, 0(a1)
	; RV32ZBT-NEXT: slti a3, a2, 1025
	; RV32ZBT-NEXT: cmov a0, a3, a2, a0
	; RV32ZBT-NEXT: sltiu a2, a5, 2047
	; RV32ZBT-NEXT: cmov a0, a2, a1, a0
	; RV32ZBT-NEXT: ret
	;
	; RV64I-LABEL: foo:			; RV64I-LABEL: foo:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: lw a2, 0(a1)			; RV64I-NEXT: lw a2, 0(a1)
	; RV64I-NEXT: beq a0, a2, .LBB0_2			; RV64I-NEXT: beq a0, a2, .LBB0_2
	; RV64I-NEXT: # %bb.1:			; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a2			; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: .LBB0_2:			; RV64I-NEXT: .LBB0_2:
	; RV64I-NEXT: lw a2, 0(a1)			; RV64I-NEXT: lw a2, 0(a1)
	▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
	; RV64I-NEXT: lw a1, 0(a1)			; RV64I-NEXT: lw a1, 0(a1)
	; RV64I-NEXT: li a3, 2046			; RV64I-NEXT: li a3, 2046
	; RV64I-NEXT: bltu a3, a2, .LBB0_28			; RV64I-NEXT: bltu a3, a2, .LBB0_28
	; RV64I-NEXT: # %bb.27:			; RV64I-NEXT: # %bb.27:
	; RV64I-NEXT: mv a0, a1			; RV64I-NEXT: mv a0, a1
	; RV64I-NEXT: .LBB0_28:			; RV64I-NEXT: .LBB0_28:
	; RV64I-NEXT: sext.w a0, a0			; RV64I-NEXT: sext.w a0, a0
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: foo:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: lw a2, 0(a1)
	; RV64ZBT-NEXT: lw a3, 0(a1)
	; RV64ZBT-NEXT: xor a4, a0, a2
	; RV64ZBT-NEXT: cmov a0, a4, a2, a0
	; RV64ZBT-NEXT: lw a2, 0(a1)
	; RV64ZBT-NEXT: xor a4, a0, a3
	; RV64ZBT-NEXT: cmov a0, a4, a0, a3
	; RV64ZBT-NEXT: lw a3, 0(a1)
	; RV64ZBT-NEXT: sltu a4, a2, a0
	; RV64ZBT-NEXT: cmov a0, a4, a0, a2
	; RV64ZBT-NEXT: lw a2, 0(a1)
	; RV64ZBT-NEXT: sltu a4, a0, a3
	; RV64ZBT-NEXT: cmov a0, a4, a3, a0
	; RV64ZBT-NEXT: lw a3, 0(a1)
	; RV64ZBT-NEXT: sltu a4, a0, a2
	; RV64ZBT-NEXT: cmov a0, a4, a0, a2
	; RV64ZBT-NEXT: lw a2, 0(a1)
	; RV64ZBT-NEXT: sltu a4, a3, a0
	; RV64ZBT-NEXT: cmov a0, a4, a3, a0
	; RV64ZBT-NEXT: sext.w a3, a0
	; RV64ZBT-NEXT: slt a3, a2, a3
	; RV64ZBT-NEXT: lw a4, 0(a1)
	; RV64ZBT-NEXT: cmov a0, a3, a0, a2
	; RV64ZBT-NEXT: sext.w a2, a0
	; RV64ZBT-NEXT: lw a3, 0(a1)
	; RV64ZBT-NEXT: slt a2, a2, a4
	; RV64ZBT-NEXT: cmov a0, a2, a4, a0
	; RV64ZBT-NEXT: sext.w a2, a0
	; RV64ZBT-NEXT: slt a2, a2, a3
	; RV64ZBT-NEXT: lw a4, 0(a1)
	; RV64ZBT-NEXT: cmov a0, a2, a0, a3
	; RV64ZBT-NEXT: lw a2, 0(a1)
	; RV64ZBT-NEXT: sext.w a3, a0
	; RV64ZBT-NEXT: slt a3, a4, a3
	; RV64ZBT-NEXT: cmov a0, a3, a4, a0
	; RV64ZBT-NEXT: slti a3, a2, 1
	; RV64ZBT-NEXT: lw a4, 0(a1)
	; RV64ZBT-NEXT: cmov a0, a3, a0, a2
	; RV64ZBT-NEXT: lw a3, 0(a1)
	; RV64ZBT-NEXT: slti a5, a2, 0
	; RV64ZBT-NEXT: cmov a0, a5, a4, a0
	; RV64ZBT-NEXT: lw a1, 0(a1)
	; RV64ZBT-NEXT: slti a4, a3, 1025
	; RV64ZBT-NEXT: cmov a0, a4, a3, a0
	; RV64ZBT-NEXT: sltiu a2, a2, 2047
	; RV64ZBT-NEXT: cmov a0, a2, a1, a0
	; RV64ZBT-NEXT: sext.w a0, a0
	; RV64ZBT-NEXT: ret
	%val1 = load volatile i32, i32* %b			%val1 = load volatile i32, i32* %b
	%tst1 = icmp eq i32 %a, %val1			%tst1 = icmp eq i32 %a, %val1
	%val2 = select i1 %tst1, i32 %a, i32 %val1			%val2 = select i1 %tst1, i32 %a, i32 %val1

	%val3 = load volatile i32, i32* %b			%val3 = load volatile i32, i32* %b
	%tst2 = icmp ne i32 %val2, %val3			%tst2 = icmp ne i32 %val2, %val3
	%val4 = select i1 %tst2, i32 %val2, i32 %val3			%val4 = select i1 %tst2, i32 %val2, i32 %val3

	▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
	; RV32I-NEXT: call bar@plt			; RV32I-NEXT: call bar@plt
	; RV32I-NEXT: .LBB1_4:			; RV32I-NEXT: .LBB1_4:
	; RV32I-NEXT: mv a0, s0			; RV32I-NEXT: mv a0, s0
	; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload			; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
	; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload			; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
	; RV32I-NEXT: addi sp, sp, 16			; RV32I-NEXT: addi sp, sp, 16
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBT-LABEL: numsignbits:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: addi sp, sp, -16
	; RV32ZBT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
	; RV32ZBT-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
	; RV32ZBT-NEXT: cmov s0, a0, a2, a3
	; RV32ZBT-NEXT: beqz a1, .LBB1_2
	; RV32ZBT-NEXT: # %bb.1:
	; RV32ZBT-NEXT: mv a0, s0
	; RV32ZBT-NEXT: call bar@plt
	; RV32ZBT-NEXT: .LBB1_2:
	; RV32ZBT-NEXT: mv a0, s0
	; RV32ZBT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
	; RV32ZBT-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
	; RV32ZBT-NEXT: addi sp, sp, 16
	; RV32ZBT-NEXT: ret
	;
	; RV64I-LABEL: numsignbits:			; RV64I-LABEL: numsignbits:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: addi sp, sp, -16			; RV64I-NEXT: addi sp, sp, -16
	; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill			; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
	; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill			; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
	; RV64I-NEXT: mv s0, a3			; RV64I-NEXT: mv s0, a3
	; RV64I-NEXT: beqz a0, .LBB1_2			; RV64I-NEXT: beqz a0, .LBB1_2
	; RV64I-NEXT: # %bb.1:			; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv s0, a2			; RV64I-NEXT: mv s0, a2
	; RV64I-NEXT: .LBB1_2:			; RV64I-NEXT: .LBB1_2:
	; RV64I-NEXT: beqz a1, .LBB1_4			; RV64I-NEXT: beqz a1, .LBB1_4
	; RV64I-NEXT: # %bb.3:			; RV64I-NEXT: # %bb.3:
	; RV64I-NEXT: mv a0, s0			; RV64I-NEXT: mv a0, s0
	; RV64I-NEXT: call bar@plt			; RV64I-NEXT: call bar@plt
	; RV64I-NEXT: .LBB1_4:			; RV64I-NEXT: .LBB1_4:
	; RV64I-NEXT: mv a0, s0			; RV64I-NEXT: mv a0, s0
	; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload			; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
	; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload			; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
	; RV64I-NEXT: addi sp, sp, 16			; RV64I-NEXT: addi sp, sp, 16
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: numsignbits:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: addi sp, sp, -16
	; RV64ZBT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
	; RV64ZBT-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
	; RV64ZBT-NEXT: cmov s0, a0, a2, a3
	; RV64ZBT-NEXT: beqz a1, .LBB1_2
	; RV64ZBT-NEXT: # %bb.1:
	; RV64ZBT-NEXT: mv a0, s0
	; RV64ZBT-NEXT: call bar@plt
	; RV64ZBT-NEXT: .LBB1_2:
	; RV64ZBT-NEXT: mv a0, s0
	; RV64ZBT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
	; RV64ZBT-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
	; RV64ZBT-NEXT: addi sp, sp, 16
	; RV64ZBT-NEXT: ret
	%5 = icmp eq i16 %0, 0			%5 = icmp eq i16 %0, 0
	%6 = select i1 %5, i16 %3, i16 %2			%6 = select i1 %5, i16 %3, i16 %2
	%7 = icmp eq i16 %1, 0			%7 = icmp eq i16 %1, 0
	br i1 %7, label %9, label %8			br i1 %7, label %9, label %8

	8: ; preds = %4			8: ; preds = %4
	tail call void @bar(i16 signext %6)			tail call void @bar(i16 signext %6)
	br label %9			br label %9
	Show All 11 Lines
	; RV32I-NEXT: addi a3, a3, -1			; RV32I-NEXT: addi a3, a3, -1
	; RV32I-NEXT: blt a3, a0, .LBB2_2			; RV32I-NEXT: blt a3, a0, .LBB2_2
	; RV32I-NEXT: # %bb.1:			; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a1, a2			; RV32I-NEXT: mv a1, a2
	; RV32I-NEXT: .LBB2_2:			; RV32I-NEXT: .LBB2_2:
	; RV32I-NEXT: mv a0, a1			; RV32I-NEXT: mv a0, a1
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBT-LABEL: select_sge_int16min:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: lui a3, 1048560
	; RV32ZBT-NEXT: addi a3, a3, -1
	; RV32ZBT-NEXT: slt a0, a3, a0
	; RV32ZBT-NEXT: cmov a0, a0, a1, a2
	; RV32ZBT-NEXT: ret
	;
	; RV64I-LABEL: select_sge_int16min:			; RV64I-LABEL: select_sge_int16min:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: lui a3, 1048560			; RV64I-NEXT: lui a3, 1048560
	; RV64I-NEXT: addiw a3, a3, -1			; RV64I-NEXT: addiw a3, a3, -1
	; RV64I-NEXT: blt a3, a0, .LBB2_2			; RV64I-NEXT: blt a3, a0, .LBB2_2
	; RV64I-NEXT: # %bb.1:			; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a1, a2			; RV64I-NEXT: mv a1, a2
	; RV64I-NEXT: .LBB2_2:			; RV64I-NEXT: .LBB2_2:
	; RV64I-NEXT: mv a0, a1			; RV64I-NEXT: mv a0, a1
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: select_sge_int16min:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: lui a3, 1048560
	; RV64ZBT-NEXT: addiw a3, a3, -1
	; RV64ZBT-NEXT: slt a0, a3, a0
	; RV64ZBT-NEXT: cmov a0, a0, a1, a2
	; RV64ZBT-NEXT: ret
	%a = icmp sge i32 %x, -65536			%a = icmp sge i32 %x, -65536
	%b = select i1 %a, i32 %y, i32 %z			%b = select i1 %a, i32 %y, i32 %z
	ret i32 %b			ret i32 %b
	}			}

	define i64 @select_sge_int32min(i64 %x, i64 %y, i64 %z) {			define i64 @select_sge_int32min(i64 %x, i64 %y, i64 %z) {
	; RV32I-LABEL: select_sge_int32min:			; RV32I-LABEL: select_sge_int32min:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	Show All 10 Lines
	; RV32I-NEXT: # %bb.4:			; RV32I-NEXT: # %bb.4:
	; RV32I-NEXT: mv a2, a4			; RV32I-NEXT: mv a2, a4
	; RV32I-NEXT: mv a3, a5			; RV32I-NEXT: mv a3, a5
	; RV32I-NEXT: .LBB3_5:			; RV32I-NEXT: .LBB3_5:
	; RV32I-NEXT: mv a0, a2			; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: mv a1, a3			; RV32I-NEXT: mv a1, a3
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32ZBT-LABEL: select_sge_int32min:
	; RV32ZBT: # %bb.0:
	; RV32ZBT-NEXT: slti a0, a0, 0
	; RV32ZBT-NEXT: addi a6, a1, 1
	; RV32ZBT-NEXT: slti a1, a1, 0
	; RV32ZBT-NEXT: xori a1, a1, 1
	; RV32ZBT-NEXT: cmov a1, a6, a1, a0
	; RV32ZBT-NEXT: cmov a0, a1, a2, a4
	; RV32ZBT-NEXT: cmov a1, a1, a3, a5
	; RV32ZBT-NEXT: ret
	;
	; RV64I-LABEL: select_sge_int32min:			; RV64I-LABEL: select_sge_int32min:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: lui a3, 524288			; RV64I-NEXT: lui a3, 524288
	; RV64I-NEXT: addi a3, a3, -1			; RV64I-NEXT: addi a3, a3, -1
	; RV64I-NEXT: blt a3, a0, .LBB3_2			; RV64I-NEXT: blt a3, a0, .LBB3_2
	; RV64I-NEXT: # %bb.1:			; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a1, a2			; RV64I-NEXT: mv a1, a2
	; RV64I-NEXT: .LBB3_2:			; RV64I-NEXT: .LBB3_2:
	; RV64I-NEXT: mv a0, a1			; RV64I-NEXT: mv a0, a1
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;
	; RV64ZBT-LABEL: select_sge_int32min:
	; RV64ZBT: # %bb.0:
	; RV64ZBT-NEXT: lui a3, 524288
	; RV64ZBT-NEXT: addi a3, a3, -1
	; RV64ZBT-NEXT: slt a0, a3, a0
	; RV64ZBT-NEXT: cmov a0, a0, a1, a2
	; RV64ZBT-NEXT: ret
	%a = icmp sge i64 %x, -2147483648			%a = icmp sge i64 %x, -2147483648
	%b = select i1 %a, i64 %y, i64 %z			%b = select i1 %a, i64 %y, i64 %z
	ret i64 %b			ret i64 %b
	}			}

llvm/test/CodeGen/RISCV/select-const.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv32 -target-abi=ilp32 -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv32 -target-abi=ilp32 -verify-machineinstrs < %s \
	; RUN: \| FileCheck -check-prefixes=RV32,RV32I %s			; RUN: \| FileCheck -check-prefixes=RV32,RV32I %s
	; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \
	; RUN: \| FileCheck -check-prefixes=RV32,RV32IF %s			; RUN: \| FileCheck -check-prefixes=RV32,RV32IF %s
	; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -target-abi=ilp32 -verify-machineinstrs < %s \
	; RUN: \| FileCheck -check-prefixes=RV32,RV32IBT %s
	; RUN: llc -mtriple=riscv32 -mattr=+f,+experimental-zbt -target-abi=ilp32 -verify-machineinstrs < %s \
	; RUN: \| FileCheck -check-prefixes=RV32,RV32IFBT %s
	; RUN: llc -mtriple=riscv64 -target-abi=lp64 -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv64 -target-abi=lp64 -verify-machineinstrs < %s \
	; RUN: \| FileCheck -check-prefixes=RV64,RV64I %s			; RUN: \| FileCheck -check-prefixes=RV64,RV64I %s
	; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi=lp64 -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi=lp64 -verify-machineinstrs < %s \
	; RUN: \| FileCheck -check-prefixes=RV64,RV64IFD %s			; RUN: \| FileCheck -check-prefixes=RV64,RV64IFD %s
	; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -target-abi=lp64 -verify-machineinstrs < %s \
	; RUN: \| FileCheck -check-prefixes=RV64,RV64IBT %s
	; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+experimental-zbt -target-abi=lp64 -verify-machineinstrs < %s \
	; RUN: \| FileCheck -check-prefixes=RV64,RV64IFDBT %s

	;; This tests how good we are at materialising constants using `select`. The aim			;; This tests how good we are at materialising constants using `select`. The aim
	;; is that we do so without a branch if possible (at the moment our lowering of			;; is that we do so without a branch if possible (at the moment our lowering of
	;; select always introduces a branch).			;; select always introduces a branch).
	;;			;;
	;; Currently the hook `convertSelectOfConstantsToMath` only is useful when the			;; Currently the hook `convertSelectOfConstantsToMath` only is useful when the
	;; constants are either 1 away from each other, or one is a power of two and			;; constants are either 1 away from each other, or one is a power of two and
	;; the other is zero.			;; the other is zero.
	Show All 36 Lines
	; RV64: # %bb.0:			; RV64: # %bb.0:
	; RV64-NEXT: slli a0, a0, 2			; RV64-NEXT: slli a0, a0, 2
	; RV64-NEXT: ret			; RV64-NEXT: ret
	%1 = select i1 %a, i32 4, i32 0			%1 = select i1 %a, i32 4, i32 0
	ret i32 %1			ret i32 %1
	}			}

	define signext i32 @select_const_int_harder(i1 zeroext %a) nounwind {			define signext i32 @select_const_int_harder(i1 zeroext %a) nounwind {
	; RV32I-LABEL: select_const_int_harder:			; RV32-LABEL: select_const_int_harder:
	; RV32I: # %bb.0:			; RV32: # %bb.0:
	; RV32I-NEXT: mv a1, a0			; RV32-NEXT: mv a1, a0
	; RV32I-NEXT: li a0, 6			; RV32-NEXT: li a0, 6
	; RV32I-NEXT: bnez a1, .LBB3_2			; RV32-NEXT: bnez a1, .LBB3_2
	; RV32I-NEXT: # %bb.1:			; RV32-NEXT: # %bb.1:
	; RV32I-NEXT: li a0, 38			; RV32-NEXT: li a0, 38
	; RV32I-NEXT: .LBB3_2:			; RV32-NEXT: .LBB3_2:
	; RV32I-NEXT: ret			; RV32-NEXT: ret
	;			;
	; RV32IF-LABEL: select_const_int_harder:			; RV64-LABEL: select_const_int_harder:
	; RV32IF: # %bb.0:			; RV64: # %bb.0:
	; RV32IF-NEXT: mv a1, a0			; RV64-NEXT: mv a1, a0
	; RV32IF-NEXT: li a0, 6			; RV64-NEXT: li a0, 6
	; RV32IF-NEXT: bnez a1, .LBB3_2			; RV64-NEXT: bnez a1, .LBB3_2
	; RV32IF-NEXT: # %bb.1:			; RV64-NEXT: # %bb.1:
	; RV32IF-NEXT: li a0, 38			; RV64-NEXT: li a0, 38
	; RV32IF-NEXT: .LBB3_2:			; RV64-NEXT: .LBB3_2:
	; RV32IF-NEXT: ret			; RV64-NEXT: ret
	;
	; RV32IBT-LABEL: select_const_int_harder:
	; RV32IBT: # %bb.0:
	; RV32IBT-NEXT: li a1, 38
	; RV32IBT-NEXT: li a2, 6
	; RV32IBT-NEXT: cmov a0, a0, a2, a1
	; RV32IBT-NEXT: ret
	;
	; RV32IFBT-LABEL: select_const_int_harder:
	; RV32IFBT: # %bb.0:
	; RV32IFBT-NEXT: li a1, 38
	; RV32IFBT-NEXT: li a2, 6
	; RV32IFBT-NEXT: cmov a0, a0, a2, a1
	; RV32IFBT-NEXT: ret
	;
	; RV64I-LABEL: select_const_int_harder:
	; RV64I: # %bb.0:
	; RV64I-NEXT: mv a1, a0
	; RV64I-NEXT: li a0, 6
	; RV64I-NEXT: bnez a1, .LBB3_2
	; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: li a0, 38
	; RV64I-NEXT: .LBB3_2:
	; RV64I-NEXT: ret
	;
	; RV64IFD-LABEL: select_const_int_harder:
	; RV64IFD: # %bb.0:
	; RV64IFD-NEXT: mv a1, a0
	; RV64IFD-NEXT: li a0, 6
	; RV64IFD-NEXT: bnez a1, .LBB3_2
	; RV64IFD-NEXT: # %bb.1:
	; RV64IFD-NEXT: li a0, 38
	; RV64IFD-NEXT: .LBB3_2:
	; RV64IFD-NEXT: ret
	;
	; RV64IBT-LABEL: select_const_int_harder:
	; RV64IBT: # %bb.0:
	; RV64IBT-NEXT: li a1, 38
	; RV64IBT-NEXT: li a2, 6
	; RV64IBT-NEXT: cmov a0, a0, a2, a1
	; RV64IBT-NEXT: ret
	;
	; RV64IFDBT-LABEL: select_const_int_harder:
	; RV64IFDBT: # %bb.0:
	; RV64IFDBT-NEXT: li a1, 38
	; RV64IFDBT-NEXT: li a2, 6
	; RV64IFDBT-NEXT: cmov a0, a0, a2, a1
	; RV64IFDBT-NEXT: ret
	%1 = select i1 %a, i32 6, i32 38			%1 = select i1 %a, i32 6, i32 38
	ret i32 %1			ret i32 %1
	}			}

	define float @select_const_fp(i1 zeroext %a) nounwind {			define float @select_const_fp(i1 zeroext %a) nounwind {
	; RV32I-LABEL: select_const_fp:			; RV32I-LABEL: select_const_fp:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	; RV32I-NEXT: mv a1, a0			; RV32I-NEXT: mv a1, a0
	Show All 13 Lines
	; RV32IF-NEXT: fmv.x.w a0, ft0			; RV32IF-NEXT: fmv.x.w a0, ft0
	; RV32IF-NEXT: ret			; RV32IF-NEXT: ret
	; RV32IF-NEXT: .LBB4_2:			; RV32IF-NEXT: .LBB4_2:
	; RV32IF-NEXT: lui a0, %hi(.LCPI4_1)			; RV32IF-NEXT: lui a0, %hi(.LCPI4_1)
	; RV32IF-NEXT: flw ft0, %lo(.LCPI4_1)(a0)			; RV32IF-NEXT: flw ft0, %lo(.LCPI4_1)(a0)
	; RV32IF-NEXT: fmv.x.w a0, ft0			; RV32IF-NEXT: fmv.x.w a0, ft0
	; RV32IF-NEXT: ret			; RV32IF-NEXT: ret
	;			;
	; RV32IBT-LABEL: select_const_fp:
	; RV32IBT: # %bb.0:
	; RV32IBT-NEXT: lui a1, 264192
	; RV32IBT-NEXT: lui a2, 263168
	; RV32IBT-NEXT: cmov a0, a0, a2, a1
	; RV32IBT-NEXT: ret
	;
	; RV32IFBT-LABEL: select_const_fp:
	; RV32IFBT: # %bb.0:
	; RV32IFBT-NEXT: bnez a0, .LBB4_2
	; RV32IFBT-NEXT: # %bb.1:
	; RV32IFBT-NEXT: lui a0, %hi(.LCPI4_0)
	; RV32IFBT-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
	; RV32IFBT-NEXT: fmv.x.w a0, ft0
	; RV32IFBT-NEXT: ret
	; RV32IFBT-NEXT: .LBB4_2:
	; RV32IFBT-NEXT: lui a0, %hi(.LCPI4_1)
	; RV32IFBT-NEXT: flw ft0, %lo(.LCPI4_1)(a0)
	; RV32IFBT-NEXT: fmv.x.w a0, ft0
	; RV32IFBT-NEXT: ret
	;
	; RV64I-LABEL: select_const_fp:			; RV64I-LABEL: select_const_fp:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: mv a1, a0			; RV64I-NEXT: mv a1, a0
	; RV64I-NEXT: lui a0, 263168			; RV64I-NEXT: lui a0, 263168
	; RV64I-NEXT: bnez a1, .LBB4_2			; RV64I-NEXT: bnez a1, .LBB4_2
	; RV64I-NEXT: # %bb.1:			; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: lui a0, 264192			; RV64I-NEXT: lui a0, 264192
	; RV64I-NEXT: .LBB4_2:			; RV64I-NEXT: .LBB4_2:
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;			;
	; RV64IFD-LABEL: select_const_fp:			; RV64IFD-LABEL: select_const_fp:
	; RV64IFD: # %bb.0:			; RV64IFD: # %bb.0:
	; RV64IFD-NEXT: bnez a0, .LBB4_2			; RV64IFD-NEXT: bnez a0, .LBB4_2
	; RV64IFD-NEXT: # %bb.1:			; RV64IFD-NEXT: # %bb.1:
	; RV64IFD-NEXT: lui a0, %hi(.LCPI4_0)			; RV64IFD-NEXT: lui a0, %hi(.LCPI4_0)
	; RV64IFD-NEXT: flw ft0, %lo(.LCPI4_0)(a0)			; RV64IFD-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
	; RV64IFD-NEXT: fmv.x.w a0, ft0			; RV64IFD-NEXT: fmv.x.w a0, ft0
	; RV64IFD-NEXT: ret			; RV64IFD-NEXT: ret
	; RV64IFD-NEXT: .LBB4_2:			; RV64IFD-NEXT: .LBB4_2:
	; RV64IFD-NEXT: lui a0, %hi(.LCPI4_1)			; RV64IFD-NEXT: lui a0, %hi(.LCPI4_1)
	; RV64IFD-NEXT: flw ft0, %lo(.LCPI4_1)(a0)			; RV64IFD-NEXT: flw ft0, %lo(.LCPI4_1)(a0)
	; RV64IFD-NEXT: fmv.x.w a0, ft0			; RV64IFD-NEXT: fmv.x.w a0, ft0
	; RV64IFD-NEXT: ret			; RV64IFD-NEXT: ret
	;
	; RV64IBT-LABEL: select_const_fp:
	; RV64IBT: # %bb.0:
	; RV64IBT-NEXT: lui a1, 264192
	; RV64IBT-NEXT: lui a2, 263168
	; RV64IBT-NEXT: cmov a0, a0, a2, a1
	; RV64IBT-NEXT: ret
	;
	; RV64IFDBT-LABEL: select_const_fp:
	; RV64IFDBT: # %bb.0:
	; RV64IFDBT-NEXT: bnez a0, .LBB4_2
	; RV64IFDBT-NEXT: # %bb.1:
	; RV64IFDBT-NEXT: lui a0, %hi(.LCPI4_0)
	; RV64IFDBT-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
	; RV64IFDBT-NEXT: fmv.x.w a0, ft0
	; RV64IFDBT-NEXT: ret
	; RV64IFDBT-NEXT: .LBB4_2:
	; RV64IFDBT-NEXT: lui a0, %hi(.LCPI4_1)
	; RV64IFDBT-NEXT: flw ft0, %lo(.LCPI4_1)(a0)
	; RV64IFDBT-NEXT: fmv.x.w a0, ft0
	; RV64IFDBT-NEXT: ret
	%1 = select i1 %a, float 3.0, float 4.0			%1 = select i1 %a, float 3.0, float 4.0
	ret float %1			ret float %1
	}			}

	define signext i32 @select_eq_zero_negone(i32 signext %a, i32 signext %b) nounwind {			define signext i32 @select_eq_zero_negone(i32 signext %a, i32 signext %b) nounwind {
	; RV32-LABEL: select_eq_zero_negone:			; RV32-LABEL: select_eq_zero_negone:
	; RV32: # %bb.0:			; RV32: # %bb.0:
	; RV32-NEXT: xor a0, a0, a1			; RV32-NEXT: xor a0, a0, a1
	▲ Show 20 Lines • Show All 253 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/select-optimize-multiple.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s -check-prefix=RV32I			; RUN: \| FileCheck %s -check-prefix=RV32I
	; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zbt -target-abi=ilp32 -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s -check-prefix=RV32IBT
	; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s -check-prefix=RV64I			; RUN: \| FileCheck %s -check-prefix=RV64I
	; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zbt -target-abi=lp64 -verify-machineinstrs < %s \
	; RUN: \| FileCheck %s -check-prefix=RV64IBT

	; Selects of wide values are split into two selects, which can easily cause			; Selects of wide values are split into two selects, which can easily cause
	; unnecessary control flow. Here we check some cases where we can currently			; unnecessary control flow. Here we check some cases where we can currently
	; emit a sequence of selects with shared control flow.			; emit a sequence of selects with shared control flow.

	define i64 @cmovcc64(i32 signext %a, i64 %b, i64 %c) nounwind {			define i64 @cmovcc64(i32 signext %a, i64 %b, i64 %c) nounwind {
	; RV32I-LABEL: cmovcc64:			; RV32I-LABEL: cmovcc64:
	; RV32I: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	; RV32I-NEXT: li a5, 123			; RV32I-NEXT: li a5, 123
	; RV32I-NEXT: beq a0, a5, .LBB0_2			; RV32I-NEXT: beq a0, a5, .LBB0_2
	; RV32I-NEXT: # %bb.1: # %entry			; RV32I-NEXT: # %bb.1: # %entry
	; RV32I-NEXT: mv a1, a3			; RV32I-NEXT: mv a1, a3
	; RV32I-NEXT: mv a2, a4			; RV32I-NEXT: mv a2, a4
	; RV32I-NEXT: .LBB0_2: # %entry			; RV32I-NEXT: .LBB0_2: # %entry
	; RV32I-NEXT: mv a0, a1			; RV32I-NEXT: mv a0, a1
	; RV32I-NEXT: mv a1, a2			; RV32I-NEXT: mv a1, a2
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32IBT-LABEL: cmovcc64:
	; RV32IBT: # %bb.0: # %entry
	; RV32IBT-NEXT: addi a5, a0, -123
	; RV32IBT-NEXT: cmov a0, a5, a3, a1
	; RV32IBT-NEXT: cmov a1, a5, a4, a2
	; RV32IBT-NEXT: ret
	;
	; RV64I-LABEL: cmovcc64:			; RV64I-LABEL: cmovcc64:
	; RV64I: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV64I-NEXT: li a3, 123			; RV64I-NEXT: li a3, 123
	; RV64I-NEXT: beq a0, a3, .LBB0_2			; RV64I-NEXT: beq a0, a3, .LBB0_2
	; RV64I-NEXT: # %bb.1: # %entry			; RV64I-NEXT: # %bb.1: # %entry
	; RV64I-NEXT: mv a1, a2			; RV64I-NEXT: mv a1, a2
	; RV64I-NEXT: .LBB0_2: # %entry			; RV64I-NEXT: .LBB0_2: # %entry
	; RV64I-NEXT: mv a0, a1			; RV64I-NEXT: mv a0, a1
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;
	; RV64IBT-LABEL: cmovcc64:
	; RV64IBT: # %bb.0: # %entry
	; RV64IBT-NEXT: addi a0, a0, -123
	; RV64IBT-NEXT: cmov a0, a0, a2, a1
	; RV64IBT-NEXT: ret
	entry:			entry:
	%cmp = icmp eq i32 %a, 123			%cmp = icmp eq i32 %a, 123
	%cond = select i1 %cmp, i64 %b, i64 %c			%cond = select i1 %cmp, i64 %b, i64 %c
	ret i64 %cond			ret i64 %cond
	}			}

	define i128 @cmovcc128(i64 signext %a, i128 %b, i128 %c) nounwind {			define i128 @cmovcc128(i64 signext %a, i128 %b, i128 %c) nounwind {
	; RV32I-LABEL: cmovcc128:			; RV32I-LABEL: cmovcc128:
	Show All 30 Lines
	; RV32I-NEXT: .LBB1_10: # %entry			; RV32I-NEXT: .LBB1_10: # %entry
	; RV32I-NEXT: lw a1, 0(a1)			; RV32I-NEXT: lw a1, 0(a1)
	; RV32I-NEXT: sw a1, 12(a0)			; RV32I-NEXT: sw a1, 12(a0)
	; RV32I-NEXT: sw a6, 8(a0)			; RV32I-NEXT: sw a6, 8(a0)
	; RV32I-NEXT: sw a5, 4(a0)			; RV32I-NEXT: sw a5, 4(a0)
	; RV32I-NEXT: sw a2, 0(a0)			; RV32I-NEXT: sw a2, 0(a0)
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32IBT-LABEL: cmovcc128:
	; RV32IBT: # %bb.0: # %entry
	; RV32IBT-NEXT: addi a5, a3, 12
	; RV32IBT-NEXT: addi a6, a4, 12
	; RV32IBT-NEXT: addi a7, a3, 8
	; RV32IBT-NEXT: addi t0, a4, 8
	; RV32IBT-NEXT: addi t1, a3, 4
	; RV32IBT-NEXT: addi t2, a4, 4
	; RV32IBT-NEXT: xori a1, a1, 123
	; RV32IBT-NEXT: or a1, a1, a2
	; RV32IBT-NEXT: cmov a2, a1, a4, a3
	; RV32IBT-NEXT: cmov a3, a1, t2, t1
	; RV32IBT-NEXT: cmov a4, a1, t0, a7
	; RV32IBT-NEXT: cmov a1, a1, a6, a5
	; RV32IBT-NEXT: lw a1, 0(a1)
	; RV32IBT-NEXT: lw a4, 0(a4)
	; RV32IBT-NEXT: lw a3, 0(a3)
	; RV32IBT-NEXT: lw a2, 0(a2)
	; RV32IBT-NEXT: sw a1, 12(a0)
	; RV32IBT-NEXT: sw a4, 8(a0)
	; RV32IBT-NEXT: sw a3, 4(a0)
	; RV32IBT-NEXT: sw a2, 0(a0)
	; RV32IBT-NEXT: ret
	;
	; RV64I-LABEL: cmovcc128:			; RV64I-LABEL: cmovcc128:
	; RV64I: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV64I-NEXT: li a5, 123			; RV64I-NEXT: li a5, 123
	; RV64I-NEXT: beq a0, a5, .LBB1_2			; RV64I-NEXT: beq a0, a5, .LBB1_2
	; RV64I-NEXT: # %bb.1: # %entry			; RV64I-NEXT: # %bb.1: # %entry
	; RV64I-NEXT: mv a1, a3			; RV64I-NEXT: mv a1, a3
	; RV64I-NEXT: mv a2, a4			; RV64I-NEXT: mv a2, a4
	; RV64I-NEXT: .LBB1_2: # %entry			; RV64I-NEXT: .LBB1_2: # %entry
	; RV64I-NEXT: mv a0, a1			; RV64I-NEXT: mv a0, a1
	; RV64I-NEXT: mv a1, a2			; RV64I-NEXT: mv a1, a2
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;
	; RV64IBT-LABEL: cmovcc128:
	; RV64IBT: # %bb.0: # %entry
	; RV64IBT-NEXT: addi a5, a0, -123
	; RV64IBT-NEXT: cmov a0, a5, a3, a1
	; RV64IBT-NEXT: cmov a1, a5, a4, a2
	; RV64IBT-NEXT: ret
	entry:			entry:
	%cmp = icmp eq i64 %a, 123			%cmp = icmp eq i64 %a, 123
	%cond = select i1 %cmp, i128 %b, i128 %c			%cond = select i1 %cmp, i128 %b, i128 %c
	ret i128 %cond			ret i128 %cond
	}			}

	define i64 @cmov64(i1 %a, i64 %b, i64 %c) nounwind {			define i64 @cmov64(i1 %a, i64 %b, i64 %c) nounwind {
	; RV32I-LABEL: cmov64:			; RV32I-LABEL: cmov64:
	; RV32I: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	; RV32I-NEXT: andi a5, a0, 1			; RV32I-NEXT: andi a5, a0, 1
	; RV32I-NEXT: mv a0, a1			; RV32I-NEXT: mv a0, a1
	; RV32I-NEXT: bnez a5, .LBB2_2			; RV32I-NEXT: bnez a5, .LBB2_2
	; RV32I-NEXT: # %bb.1: # %entry			; RV32I-NEXT: # %bb.1: # %entry
	; RV32I-NEXT: mv a0, a3			; RV32I-NEXT: mv a0, a3
	; RV32I-NEXT: mv a2, a4			; RV32I-NEXT: mv a2, a4
	; RV32I-NEXT: .LBB2_2: # %entry			; RV32I-NEXT: .LBB2_2: # %entry
	; RV32I-NEXT: mv a1, a2			; RV32I-NEXT: mv a1, a2
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32IBT-LABEL: cmov64:
	; RV32IBT: # %bb.0: # %entry
	; RV32IBT-NEXT: andi a5, a0, 1
	; RV32IBT-NEXT: cmov a0, a5, a1, a3
	; RV32IBT-NEXT: cmov a1, a5, a2, a4
	; RV32IBT-NEXT: ret
	;
	; RV64I-LABEL: cmov64:			; RV64I-LABEL: cmov64:
	; RV64I: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV64I-NEXT: andi a3, a0, 1			; RV64I-NEXT: andi a3, a0, 1
	; RV64I-NEXT: mv a0, a1			; RV64I-NEXT: mv a0, a1
	; RV64I-NEXT: bnez a3, .LBB2_2			; RV64I-NEXT: bnez a3, .LBB2_2
	; RV64I-NEXT: # %bb.1: # %entry			; RV64I-NEXT: # %bb.1: # %entry
	; RV64I-NEXT: mv a0, a2			; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: .LBB2_2: # %entry			; RV64I-NEXT: .LBB2_2: # %entry
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;
	; RV64IBT-LABEL: cmov64:
	; RV64IBT: # %bb.0: # %entry
	; RV64IBT-NEXT: andi a0, a0, 1
	; RV64IBT-NEXT: cmov a0, a0, a1, a2
	; RV64IBT-NEXT: ret
	entry:			entry:
	%cond = select i1 %a, i64 %b, i64 %c			%cond = select i1 %a, i64 %b, i64 %c
	ret i64 %cond			ret i64 %cond
	}			}

	define i128 @cmov128(i1 %a, i128 %b, i128 %c) nounwind {			define i128 @cmov128(i1 %a, i128 %b, i128 %c) nounwind {
	; RV32I-LABEL: cmov128:			; RV32I-LABEL: cmov128:
	; RV32I: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	Show All 28 Lines
	; RV32I-NEXT: .LBB3_10: # %entry			; RV32I-NEXT: .LBB3_10: # %entry
	; RV32I-NEXT: lw a1, 0(a1)			; RV32I-NEXT: lw a1, 0(a1)
	; RV32I-NEXT: sw a1, 12(a0)			; RV32I-NEXT: sw a1, 12(a0)
	; RV32I-NEXT: sw a6, 8(a0)			; RV32I-NEXT: sw a6, 8(a0)
	; RV32I-NEXT: sw a5, 4(a0)			; RV32I-NEXT: sw a5, 4(a0)
	; RV32I-NEXT: sw a4, 0(a0)			; RV32I-NEXT: sw a4, 0(a0)
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32IBT-LABEL: cmov128:
	; RV32IBT: # %bb.0: # %entry
	; RV32IBT-NEXT: addi a4, a3, 12
	; RV32IBT-NEXT: addi a5, a2, 12
	; RV32IBT-NEXT: addi a6, a3, 8
	; RV32IBT-NEXT: addi a7, a2, 8
	; RV32IBT-NEXT: addi t0, a3, 4
	; RV32IBT-NEXT: addi t1, a2, 4
	; RV32IBT-NEXT: andi a1, a1, 1
	; RV32IBT-NEXT: cmov a2, a1, a2, a3
	; RV32IBT-NEXT: cmov a3, a1, t1, t0
	; RV32IBT-NEXT: cmov a6, a1, a7, a6
	; RV32IBT-NEXT: cmov a1, a1, a5, a4
	; RV32IBT-NEXT: lw a1, 0(a1)
	; RV32IBT-NEXT: lw a4, 0(a6)
	; RV32IBT-NEXT: lw a3, 0(a3)
	; RV32IBT-NEXT: lw a2, 0(a2)
	; RV32IBT-NEXT: sw a1, 12(a0)
	; RV32IBT-NEXT: sw a4, 8(a0)
	; RV32IBT-NEXT: sw a3, 4(a0)
	; RV32IBT-NEXT: sw a2, 0(a0)
	; RV32IBT-NEXT: ret
	;
	; RV64I-LABEL: cmov128:			; RV64I-LABEL: cmov128:
	; RV64I: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV64I-NEXT: andi a5, a0, 1			; RV64I-NEXT: andi a5, a0, 1
	; RV64I-NEXT: mv a0, a1			; RV64I-NEXT: mv a0, a1
	; RV64I-NEXT: bnez a5, .LBB3_2			; RV64I-NEXT: bnez a5, .LBB3_2
	; RV64I-NEXT: # %bb.1: # %entry			; RV64I-NEXT: # %bb.1: # %entry
	; RV64I-NEXT: mv a0, a3			; RV64I-NEXT: mv a0, a3
	; RV64I-NEXT: mv a2, a4			; RV64I-NEXT: mv a2, a4
	; RV64I-NEXT: .LBB3_2: # %entry			; RV64I-NEXT: .LBB3_2: # %entry
	; RV64I-NEXT: mv a1, a2			; RV64I-NEXT: mv a1, a2
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;
	; RV64IBT-LABEL: cmov128:
	; RV64IBT: # %bb.0: # %entry
	; RV64IBT-NEXT: andi a5, a0, 1
	; RV64IBT-NEXT: cmov a0, a5, a1, a3
	; RV64IBT-NEXT: cmov a1, a5, a2, a4
	; RV64IBT-NEXT: ret
	entry:			entry:
	%cond = select i1 %a, i128 %b, i128 %c			%cond = select i1 %a, i128 %b, i128 %c
	ret i128 %cond			ret i128 %cond
	}			}

	define float @cmovfloat(i1 %a, float %b, float %c, float %d, float %e) nounwind {			define float @cmovfloat(i1 %a, float %b, float %c, float %d, float %e) nounwind {
	; RV32I-LABEL: cmovfloat:			; RV32I-LABEL: cmovfloat:
	; RV32I: # %bb.0: # %entry			; RV32I: # %bb.0: # %entry
	; RV32I-NEXT: andi a0, a0, 1			; RV32I-NEXT: andi a0, a0, 1
	; RV32I-NEXT: bnez a0, .LBB4_2			; RV32I-NEXT: bnez a0, .LBB4_2
	; RV32I-NEXT: # %bb.1: # %entry			; RV32I-NEXT: # %bb.1: # %entry
	; RV32I-NEXT: fmv.w.x ft0, a4			; RV32I-NEXT: fmv.w.x ft0, a4
	; RV32I-NEXT: fmv.w.x ft1, a2			; RV32I-NEXT: fmv.w.x ft1, a2
	; RV32I-NEXT: j .LBB4_3			; RV32I-NEXT: j .LBB4_3
	; RV32I-NEXT: .LBB4_2:			; RV32I-NEXT: .LBB4_2:
	; RV32I-NEXT: fmv.w.x ft0, a3			; RV32I-NEXT: fmv.w.x ft0, a3
	; RV32I-NEXT: fmv.w.x ft1, a1			; RV32I-NEXT: fmv.w.x ft1, a1
	; RV32I-NEXT: .LBB4_3: # %entry			; RV32I-NEXT: .LBB4_3: # %entry
	; RV32I-NEXT: fadd.s ft0, ft1, ft0			; RV32I-NEXT: fadd.s ft0, ft1, ft0
	; RV32I-NEXT: fmv.x.w a0, ft0			; RV32I-NEXT: fmv.x.w a0, ft0
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32IBT-LABEL: cmovfloat:
	; RV32IBT: # %bb.0: # %entry
	; RV32IBT-NEXT: andi a0, a0, 1
	; RV32IBT-NEXT: bnez a0, .LBB4_2
	; RV32IBT-NEXT: # %bb.1: # %entry
	; RV32IBT-NEXT: fmv.w.x ft0, a4
	; RV32IBT-NEXT: fmv.w.x ft1, a2
	; RV32IBT-NEXT: j .LBB4_3
	; RV32IBT-NEXT: .LBB4_2:
	; RV32IBT-NEXT: fmv.w.x ft0, a3
	; RV32IBT-NEXT: fmv.w.x ft1, a1
	; RV32IBT-NEXT: .LBB4_3: # %entry
	; RV32IBT-NEXT: fadd.s ft0, ft1, ft0
	; RV32IBT-NEXT: fmv.x.w a0, ft0
	; RV32IBT-NEXT: ret
	;
	; RV64I-LABEL: cmovfloat:			; RV64I-LABEL: cmovfloat:
	; RV64I: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV64I-NEXT: andi a0, a0, 1			; RV64I-NEXT: andi a0, a0, 1
	; RV64I-NEXT: bnez a0, .LBB4_2			; RV64I-NEXT: bnez a0, .LBB4_2
	; RV64I-NEXT: # %bb.1: # %entry			; RV64I-NEXT: # %bb.1: # %entry
	; RV64I-NEXT: fmv.w.x ft0, a4			; RV64I-NEXT: fmv.w.x ft0, a4
	; RV64I-NEXT: fmv.w.x ft1, a2			; RV64I-NEXT: fmv.w.x ft1, a2
	; RV64I-NEXT: j .LBB4_3			; RV64I-NEXT: j .LBB4_3
	; RV64I-NEXT: .LBB4_2:			; RV64I-NEXT: .LBB4_2:
	; RV64I-NEXT: fmv.w.x ft0, a3			; RV64I-NEXT: fmv.w.x ft0, a3
	; RV64I-NEXT: fmv.w.x ft1, a1			; RV64I-NEXT: fmv.w.x ft1, a1
	; RV64I-NEXT: .LBB4_3: # %entry			; RV64I-NEXT: .LBB4_3: # %entry
	; RV64I-NEXT: fadd.s ft0, ft1, ft0			; RV64I-NEXT: fadd.s ft0, ft1, ft0
	; RV64I-NEXT: fmv.x.w a0, ft0			; RV64I-NEXT: fmv.x.w a0, ft0
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;
	; RV64IBT-LABEL: cmovfloat:
	; RV64IBT: # %bb.0: # %entry
	; RV64IBT-NEXT: andi a0, a0, 1
	; RV64IBT-NEXT: bnez a0, .LBB4_2
	; RV64IBT-NEXT: # %bb.1: # %entry
	; RV64IBT-NEXT: fmv.w.x ft0, a4
	; RV64IBT-NEXT: fmv.w.x ft1, a2
	; RV64IBT-NEXT: j .LBB4_3
	; RV64IBT-NEXT: .LBB4_2:
	; RV64IBT-NEXT: fmv.w.x ft0, a3
	; RV64IBT-NEXT: fmv.w.x ft1, a1
	; RV64IBT-NEXT: .LBB4_3: # %entry
	; RV64IBT-NEXT: fadd.s ft0, ft1, ft0
	; RV64IBT-NEXT: fmv.x.w a0, ft0
	; RV64IBT-NEXT: ret
	entry:			entry:
	%cond1 = select i1 %a, float %b, float %c			%cond1 = select i1 %a, float %b, float %c
	%cond2 = select i1 %a, float %d, float %e			%cond2 = select i1 %a, float %d, float %e
	%ret = fadd float %cond1, %cond2			%ret = fadd float %cond1, %cond2
	ret float %ret			ret float %ret
	}			}

	define double @cmovdouble(i1 %a, double %b, double %c) nounwind {			define double @cmovdouble(i1 %a, double %b, double %c) nounwind {
	Show All 11 Lines
	; RV32I-NEXT: fld ft0, 8(sp)			; RV32I-NEXT: fld ft0, 8(sp)
	; RV32I-NEXT: .LBB5_2: # %entry			; RV32I-NEXT: .LBB5_2: # %entry
	; RV32I-NEXT: fsd ft0, 8(sp)			; RV32I-NEXT: fsd ft0, 8(sp)
	; RV32I-NEXT: lw a0, 8(sp)			; RV32I-NEXT: lw a0, 8(sp)
	; RV32I-NEXT: lw a1, 12(sp)			; RV32I-NEXT: lw a1, 12(sp)
	; RV32I-NEXT: addi sp, sp, 16			; RV32I-NEXT: addi sp, sp, 16
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32IBT-LABEL: cmovdouble:
	; RV32IBT: # %bb.0: # %entry
	; RV32IBT-NEXT: addi sp, sp, -16
	; RV32IBT-NEXT: sw a3, 8(sp)
	; RV32IBT-NEXT: sw a4, 12(sp)
	; RV32IBT-NEXT: fld ft0, 8(sp)
	; RV32IBT-NEXT: sw a1, 8(sp)
	; RV32IBT-NEXT: andi a0, a0, 1
	; RV32IBT-NEXT: sw a2, 12(sp)
	; RV32IBT-NEXT: beqz a0, .LBB5_2
	; RV32IBT-NEXT: # %bb.1:
	; RV32IBT-NEXT: fld ft0, 8(sp)
	; RV32IBT-NEXT: .LBB5_2: # %entry
	; RV32IBT-NEXT: fsd ft0, 8(sp)
	; RV32IBT-NEXT: lw a0, 8(sp)
	; RV32IBT-NEXT: lw a1, 12(sp)
	; RV32IBT-NEXT: addi sp, sp, 16
	; RV32IBT-NEXT: ret
	;
	; RV64I-LABEL: cmovdouble:			; RV64I-LABEL: cmovdouble:
	; RV64I: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV64I-NEXT: andi a0, a0, 1			; RV64I-NEXT: andi a0, a0, 1
	; RV64I-NEXT: bnez a0, .LBB5_2			; RV64I-NEXT: bnez a0, .LBB5_2
	; RV64I-NEXT: # %bb.1: # %entry			; RV64I-NEXT: # %bb.1: # %entry
	; RV64I-NEXT: fmv.d.x ft0, a2			; RV64I-NEXT: fmv.d.x ft0, a2
	; RV64I-NEXT: fmv.x.d a0, ft0			; RV64I-NEXT: fmv.x.d a0, ft0
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	; RV64I-NEXT: .LBB5_2:			; RV64I-NEXT: .LBB5_2:
	; RV64I-NEXT: fmv.d.x ft0, a1			; RV64I-NEXT: fmv.d.x ft0, a1
	; RV64I-NEXT: fmv.x.d a0, ft0			; RV64I-NEXT: fmv.x.d a0, ft0
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;
	; RV64IBT-LABEL: cmovdouble:
	; RV64IBT: # %bb.0: # %entry
	; RV64IBT-NEXT: andi a0, a0, 1
	; RV64IBT-NEXT: bnez a0, .LBB5_2
	; RV64IBT-NEXT: # %bb.1: # %entry
	; RV64IBT-NEXT: fmv.d.x ft0, a2
	; RV64IBT-NEXT: fmv.x.d a0, ft0
	; RV64IBT-NEXT: ret
	; RV64IBT-NEXT: .LBB5_2:
	; RV64IBT-NEXT: fmv.d.x ft0, a1
	; RV64IBT-NEXT: fmv.x.d a0, ft0
	; RV64IBT-NEXT: ret
	entry:			entry:
	%cond = select i1 %a, double %b, double %c			%cond = select i1 %a, double %b, double %c
	ret double %cond			ret double %cond
	}			}

	; Check that selects with dependencies on previous ones aren't incorrectly			; Check that selects with dependencies on previous ones aren't incorrectly
	; optimized.			; optimized.

	Show All 12 Lines
	; RV32I-NEXT: mv a1, a2			; RV32I-NEXT: mv a1, a2
	; RV32I-NEXT: mv a2, a1			; RV32I-NEXT: mv a2, a1
	; RV32I-NEXT: beq a0, a4, .LBB6_2			; RV32I-NEXT: beq a0, a4, .LBB6_2
	; RV32I-NEXT: .LBB6_4: # %entry			; RV32I-NEXT: .LBB6_4: # %entry
	; RV32I-NEXT: mv a2, a3			; RV32I-NEXT: mv a2, a3
	; RV32I-NEXT: add a0, a1, a2			; RV32I-NEXT: add a0, a1, a2
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32IBT-LABEL: cmovccdep:
	; RV32IBT: # %bb.0: # %entry
	; RV32IBT-NEXT: addi a0, a0, -123
	; RV32IBT-NEXT: cmov a1, a0, a2, a1
	; RV32IBT-NEXT: cmov a0, a0, a3, a1
	; RV32IBT-NEXT: add a0, a1, a0
	; RV32IBT-NEXT: ret
	;
	; RV64I-LABEL: cmovccdep:			; RV64I-LABEL: cmovccdep:
	; RV64I: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV64I-NEXT: li a4, 123			; RV64I-NEXT: li a4, 123
	; RV64I-NEXT: bne a0, a4, .LBB6_3			; RV64I-NEXT: bne a0, a4, .LBB6_3
	; RV64I-NEXT: # %bb.1: # %entry			; RV64I-NEXT: # %bb.1: # %entry
	; RV64I-NEXT: mv a2, a1			; RV64I-NEXT: mv a2, a1
	; RV64I-NEXT: bne a0, a4, .LBB6_4			; RV64I-NEXT: bne a0, a4, .LBB6_4
	; RV64I-NEXT: .LBB6_2: # %entry			; RV64I-NEXT: .LBB6_2: # %entry
	; RV64I-NEXT: addw a0, a1, a2			; RV64I-NEXT: addw a0, a1, a2
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	; RV64I-NEXT: .LBB6_3: # %entry			; RV64I-NEXT: .LBB6_3: # %entry
	; RV64I-NEXT: mv a1, a2			; RV64I-NEXT: mv a1, a2
	; RV64I-NEXT: mv a2, a1			; RV64I-NEXT: mv a2, a1
	; RV64I-NEXT: beq a0, a4, .LBB6_2			; RV64I-NEXT: beq a0, a4, .LBB6_2
	; RV64I-NEXT: .LBB6_4: # %entry			; RV64I-NEXT: .LBB6_4: # %entry
	; RV64I-NEXT: mv a2, a3			; RV64I-NEXT: mv a2, a3
	; RV64I-NEXT: addw a0, a1, a2			; RV64I-NEXT: addw a0, a1, a2
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;
	; RV64IBT-LABEL: cmovccdep:
	; RV64IBT: # %bb.0: # %entry
	; RV64IBT-NEXT: addi a0, a0, -123
	; RV64IBT-NEXT: cmov a1, a0, a2, a1
	; RV64IBT-NEXT: cmov a0, a0, a3, a1
	; RV64IBT-NEXT: addw a0, a1, a0
	; RV64IBT-NEXT: ret
	entry:			entry:
	%cmp = icmp eq i32 %a, 123			%cmp = icmp eq i32 %a, 123
	%cond1 = select i1 %cmp, i32 %b, i32 %c			%cond1 = select i1 %cmp, i32 %b, i32 %c
	%cond2 = select i1 %cmp, i32 %cond1, i32 %d			%cond2 = select i1 %cmp, i32 %cond1, i32 %d
	%ret = add i32 %cond1, %cond2			%ret = add i32 %cond1, %cond2
	ret i32 %ret			ret i32 %ret
	}			}

	Show All 13 Lines
	; RV32I-NEXT: .LBB7_3: # %entry			; RV32I-NEXT: .LBB7_3: # %entry
	; RV32I-NEXT: mv a2, a3			; RV32I-NEXT: mv a2, a3
	; RV32I-NEXT: bnez a0, .LBB7_2			; RV32I-NEXT: bnez a0, .LBB7_2
	; RV32I-NEXT: .LBB7_4: # %entry			; RV32I-NEXT: .LBB7_4: # %entry
	; RV32I-NEXT: mv a4, a5			; RV32I-NEXT: mv a4, a5
	; RV32I-NEXT: add a0, a2, a4			; RV32I-NEXT: add a0, a2, a4
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32IBT-LABEL: cmovdiffcc:
	; RV32IBT: # %bb.0: # %entry
	; RV32IBT-NEXT: andi a1, a1, 1
	; RV32IBT-NEXT: andi a0, a0, 1
	; RV32IBT-NEXT: cmov a0, a0, a2, a3
	; RV32IBT-NEXT: cmov a1, a1, a4, a5
	; RV32IBT-NEXT: add a0, a0, a1
	; RV32IBT-NEXT: ret
	;
	; RV64I-LABEL: cmovdiffcc:			; RV64I-LABEL: cmovdiffcc:
	; RV64I: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV64I-NEXT: andi a6, a0, 1			; RV64I-NEXT: andi a6, a0, 1
	; RV64I-NEXT: andi a0, a1, 1			; RV64I-NEXT: andi a0, a1, 1
	; RV64I-NEXT: beqz a6, .LBB7_3			; RV64I-NEXT: beqz a6, .LBB7_3
	; RV64I-NEXT: # %bb.1: # %entry			; RV64I-NEXT: # %bb.1: # %entry
	; RV64I-NEXT: beqz a0, .LBB7_4			; RV64I-NEXT: beqz a0, .LBB7_4
	; RV64I-NEXT: .LBB7_2: # %entry			; RV64I-NEXT: .LBB7_2: # %entry
	; RV64I-NEXT: addw a0, a2, a4			; RV64I-NEXT: addw a0, a2, a4
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	; RV64I-NEXT: .LBB7_3: # %entry			; RV64I-NEXT: .LBB7_3: # %entry
	; RV64I-NEXT: mv a2, a3			; RV64I-NEXT: mv a2, a3
	; RV64I-NEXT: bnez a0, .LBB7_2			; RV64I-NEXT: bnez a0, .LBB7_2
	; RV64I-NEXT: .LBB7_4: # %entry			; RV64I-NEXT: .LBB7_4: # %entry
	; RV64I-NEXT: mv a4, a5			; RV64I-NEXT: mv a4, a5
	; RV64I-NEXT: addw a0, a2, a4			; RV64I-NEXT: addw a0, a2, a4
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;
	; RV64IBT-LABEL: cmovdiffcc:
	; RV64IBT: # %bb.0: # %entry
	; RV64IBT-NEXT: andi a1, a1, 1
	; RV64IBT-NEXT: andi a0, a0, 1
	; RV64IBT-NEXT: cmov a0, a0, a2, a3
	; RV64IBT-NEXT: cmov a1, a1, a4, a5
	; RV64IBT-NEXT: addw a0, a0, a1
	; RV64IBT-NEXT: ret
	entry:			entry:
	%cond1 = select i1 %a, i32 %c, i32 %d			%cond1 = select i1 %a, i32 %c, i32 %d
	%cond2 = select i1 %b, i32 %e, i32 %f			%cond2 = select i1 %b, i32 %e, i32 %f
	%ret = add i32 %cond1, %cond2			%ret = add i32 %cond1, %cond2
	ret i32 %ret			ret i32 %ret
	}			}

	define float @CascadedSelect(float noundef %a) {			define float @CascadedSelect(float noundef %a) {
	Show All 9 Lines
	; RV32I-NEXT: flt.s a0, ft1, ft0			; RV32I-NEXT: flt.s a0, ft1, ft0
	; RV32I-NEXT: bnez a0, .LBB8_3			; RV32I-NEXT: bnez a0, .LBB8_3
	; RV32I-NEXT: # %bb.2: # %entry			; RV32I-NEXT: # %bb.2: # %entry
	; RV32I-NEXT: fmv.s ft0, ft1			; RV32I-NEXT: fmv.s ft0, ft1
	; RV32I-NEXT: .LBB8_3: # %entry			; RV32I-NEXT: .LBB8_3: # %entry
	; RV32I-NEXT: fmv.x.w a0, ft0			; RV32I-NEXT: fmv.x.w a0, ft0
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32IBT-LABEL: CascadedSelect:
	; RV32IBT: # %bb.0: # %entry
	; RV32IBT-NEXT: lui a1, %hi(.LCPI8_0)
	; RV32IBT-NEXT: flw ft0, %lo(.LCPI8_0)(a1)
	; RV32IBT-NEXT: fmv.w.x ft1, a0
	; RV32IBT-NEXT: flt.s a0, ft0, ft1
	; RV32IBT-NEXT: bnez a0, .LBB8_3
	; RV32IBT-NEXT: # %bb.1: # %entry
	; RV32IBT-NEXT: fmv.w.x ft0, zero
	; RV32IBT-NEXT: flt.s a0, ft1, ft0
	; RV32IBT-NEXT: bnez a0, .LBB8_3
	; RV32IBT-NEXT: # %bb.2: # %entry
	; RV32IBT-NEXT: fmv.s ft0, ft1
	; RV32IBT-NEXT: .LBB8_3: # %entry
	; RV32IBT-NEXT: fmv.x.w a0, ft0
	; RV32IBT-NEXT: ret
	;
	; RV64I-LABEL: CascadedSelect:			; RV64I-LABEL: CascadedSelect:
	; RV64I: # %bb.0: # %entry			; RV64I: # %bb.0: # %entry
	; RV64I-NEXT: lui a1, %hi(.LCPI8_0)			; RV64I-NEXT: lui a1, %hi(.LCPI8_0)
	; RV64I-NEXT: flw ft0, %lo(.LCPI8_0)(a1)			; RV64I-NEXT: flw ft0, %lo(.LCPI8_0)(a1)
	; RV64I-NEXT: fmv.w.x ft1, a0			; RV64I-NEXT: fmv.w.x ft1, a0
	; RV64I-NEXT: flt.s a0, ft0, ft1			; RV64I-NEXT: flt.s a0, ft0, ft1
	; RV64I-NEXT: bnez a0, .LBB8_3			; RV64I-NEXT: bnez a0, .LBB8_3
	; RV64I-NEXT: # %bb.1: # %entry			; RV64I-NEXT: # %bb.1: # %entry
	; RV64I-NEXT: fmv.w.x ft0, zero			; RV64I-NEXT: fmv.w.x ft0, zero
	; RV64I-NEXT: flt.s a0, ft1, ft0			; RV64I-NEXT: flt.s a0, ft1, ft0
	; RV64I-NEXT: bnez a0, .LBB8_3			; RV64I-NEXT: bnez a0, .LBB8_3
	; RV64I-NEXT: # %bb.2: # %entry			; RV64I-NEXT: # %bb.2: # %entry
	; RV64I-NEXT: fmv.s ft0, ft1			; RV64I-NEXT: fmv.s ft0, ft1
	; RV64I-NEXT: .LBB8_3: # %entry			; RV64I-NEXT: .LBB8_3: # %entry
	; RV64I-NEXT: fmv.x.w a0, ft0			; RV64I-NEXT: fmv.x.w a0, ft0
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;
	; RV64IBT-LABEL: CascadedSelect:
	; RV64IBT: # %bb.0: # %entry
	; RV64IBT-NEXT: lui a1, %hi(.LCPI8_0)
	; RV64IBT-NEXT: flw ft0, %lo(.LCPI8_0)(a1)
	; RV64IBT-NEXT: fmv.w.x ft1, a0
	; RV64IBT-NEXT: flt.s a0, ft0, ft1
	; RV64IBT-NEXT: bnez a0, .LBB8_3
	; RV64IBT-NEXT: # %bb.1: # %entry
	; RV64IBT-NEXT: fmv.w.x ft0, zero
	; RV64IBT-NEXT: flt.s a0, ft1, ft0
	; RV64IBT-NEXT: bnez a0, .LBB8_3
	; RV64IBT-NEXT: # %bb.2: # %entry
	; RV64IBT-NEXT: fmv.s ft0, ft1
	; RV64IBT-NEXT: .LBB8_3: # %entry
	; RV64IBT-NEXT: fmv.x.w a0, ft0
	; RV64IBT-NEXT: ret
	entry:			entry:
	%cmp = fcmp ogt float %a, 1.000000e+00			%cmp = fcmp ogt float %a, 1.000000e+00
	%cmp1 = fcmp olt float %a, 0.000000e+00			%cmp1 = fcmp olt float %a, 0.000000e+00
	%.a = select i1 %cmp1, float 0.000000e+00, float %a			%.a = select i1 %cmp1, float 0.000000e+00, float %a
	%retval.0 = select i1 %cmp, float 1.000000e+00, float %.a			%retval.0 = select i1 %cmp, float 1.000000e+00, float %.a
	ret float %retval.0			ret float %retval.0
	}			}

llvm/test/CodeGen/RISCV/select-optimize-multiple.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py		# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=finalize-isel -simplify-mir -o - %s \		# RUN: llc -mtriple=riscv32 -run-pass=finalize-isel -simplify-mir -o - %s \
# RUN: \| FileCheck -check-prefix=RV32I %s		# RUN: \| FileCheck -check-prefix=RV32I %s
# RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -run-pass=finalize-isel -simplify-mir -o - %s \
# RUN: \| FileCheck -check-prefix=RV32IBT %s
# RUN: llc -mtriple=riscv64 -run-pass=finalize-isel -simplify-mir -o - %s \		# RUN: llc -mtriple=riscv64 -run-pass=finalize-isel -simplify-mir -o - %s \
# RUN: \| FileCheck -check-prefix=RV64I %s		# RUN: \| FileCheck -check-prefix=RV64I %s
# RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -run-pass=finalize-isel -simplify-mir -o - %s \
# RUN: \| FileCheck -check-prefix=RV64IBT %s

# Provide dummy definitions of functions and just enough metadata to create a		# Provide dummy definitions of functions and just enough metadata to create a
# DBG_VALUE.		# DBG_VALUE.
--- \|		--- \|
define void @cmov_interleaved_bad() {		define void @cmov_interleaved_bad() {
ret void		ret void
}		}
define void @cmov_interleaved_debug_value() {		define void @cmov_interleaved_debug_value() {
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines	bb.0:
; RV32I-NEXT: {{ $}}		; RV32I-NEXT: {{ $}}
; RV32I-NEXT: .3:		; RV32I-NEXT: .3:
; RV32I-NEXT: {{ $}}		; RV32I-NEXT: {{ $}}
; RV32I-NEXT: .4:		; RV32I-NEXT: .4:
; RV32I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3		; RV32I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]		; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
; RV32I-NEXT: $x10 = COPY [[ADD]]		; RV32I-NEXT: $x10 = COPY [[ADD]]
; RV32I-NEXT: PseudoRET implicit $x10		; RV32I-NEXT: PseudoRET implicit $x10
; RV32IBT-LABEL: name: cmov_interleaved_bad
; RV32IBT: successors: %bb.1, %bb.2
; RV32IBT-NEXT: liveins: $x10, $x11, $x12, $x13
; RV32IBT-NEXT: {{ $}}
; RV32IBT-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
; RV32IBT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
; RV32IBT-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
; RV32IBT-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
; RV32IBT-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
; RV32IBT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; RV32IBT-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2
; RV32IBT-NEXT: {{ $}}
; RV32IBT-NEXT: .1:
; RV32IBT-NEXT: {{ $}}
; RV32IBT-NEXT: .2:
; RV32IBT-NEXT: successors: %bb.3, %bb.4
; RV32IBT-NEXT: {{ $}}
; RV32IBT-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
; RV32IBT-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
; RV32IBT-NEXT: BNE [[ANDI]], [[COPY4]], %bb.4
; RV32IBT-NEXT: {{ $}}
; RV32IBT-NEXT: .3:
; RV32IBT-NEXT: {{ $}}
; RV32IBT-NEXT: .4:
; RV32IBT-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
; RV32IBT-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
; RV32IBT-NEXT: $x10 = COPY [[ADD]]
; RV32IBT-NEXT: PseudoRET implicit $x10
; RV64I-LABEL: name: cmov_interleaved_bad		; RV64I-LABEL: name: cmov_interleaved_bad
; RV64I: successors: %bb.1, %bb.2		; RV64I: successors: %bb.1, %bb.2
; RV64I-NEXT: liveins: $x10, $x11, $x12, $x13		; RV64I-NEXT: liveins: $x10, $x11, $x12, $x13
; RV64I-NEXT: {{ $}}		; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13		; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12		; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11		; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10		; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
Show All 12 Lines	bb.0:
; RV64I-NEXT: {{ $}}		; RV64I-NEXT: {{ $}}
; RV64I-NEXT: .3:		; RV64I-NEXT: .3:
; RV64I-NEXT: {{ $}}		; RV64I-NEXT: {{ $}}
; RV64I-NEXT: .4:		; RV64I-NEXT: .4:
; RV64I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3		; RV64I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]		; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
; RV64I-NEXT: $x10 = COPY [[ADD]]		; RV64I-NEXT: $x10 = COPY [[ADD]]
; RV64I-NEXT: PseudoRET implicit $x10		; RV64I-NEXT: PseudoRET implicit $x10
; RV64IBT-LABEL: name: cmov_interleaved_bad
; RV64IBT: successors: %bb.1, %bb.2
; RV64IBT-NEXT: liveins: $x10, $x11, $x12, $x13
; RV64IBT-NEXT: {{ $}}
; RV64IBT-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
; RV64IBT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
; RV64IBT-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
; RV64IBT-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
; RV64IBT-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
; RV64IBT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; RV64IBT-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2
; RV64IBT-NEXT: {{ $}}
; RV64IBT-NEXT: .1:
; RV64IBT-NEXT: {{ $}}
; RV64IBT-NEXT: .2:
; RV64IBT-NEXT: successors: %bb.3, %bb.4
; RV64IBT-NEXT: {{ $}}
; RV64IBT-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
; RV64IBT-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
; RV64IBT-NEXT: BNE [[ANDI]], [[COPY4]], %bb.4
; RV64IBT-NEXT: {{ $}}
; RV64IBT-NEXT: .3:
; RV64IBT-NEXT: {{ $}}
; RV64IBT-NEXT: .4:
; RV64IBT-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
; RV64IBT-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
; RV64IBT-NEXT: $x10 = COPY [[ADD]]
; RV64IBT-NEXT: PseudoRET implicit $x10
%3:gpr = COPY $x13		%3:gpr = COPY $x13
%2:gpr = COPY $x12		%2:gpr = COPY $x12
%1:gpr = COPY $x11		%1:gpr = COPY $x11
%0:gpr = COPY $x10		%0:gpr = COPY $x10
%5:gpr = ANDI %0, 1		%5:gpr = ANDI %0, 1
%6:gpr = COPY $x0		%6:gpr = COPY $x0
%7:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %1, %2		%7:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %1, %2
%8:gpr = ADDI %7, 1		%8:gpr = ADDI %7, 1
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines	bb.0:
; RV32I-NEXT: .2:		; RV32I-NEXT: .2:
; RV32I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1		; RV32I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
; RV32I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1		; RV32I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
; RV32I-NEXT: DBG_VALUE [[PHI]], $noreg		; RV32I-NEXT: DBG_VALUE [[PHI]], $noreg
; RV32I-NEXT: DBG_VALUE [[PHI1]], $noreg		; RV32I-NEXT: DBG_VALUE [[PHI1]], $noreg
; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]		; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
; RV32I-NEXT: $x10 = COPY [[ADD]]		; RV32I-NEXT: $x10 = COPY [[ADD]]
; RV32I-NEXT: PseudoRET implicit $x10		; RV32I-NEXT: PseudoRET implicit $x10
; RV32IBT-LABEL: name: cmov_interleaved_debug_value
; RV32IBT: successors: %bb.1, %bb.2
; RV32IBT-NEXT: liveins: $x10, $x11, $x12, $x13
; RV32IBT-NEXT: {{ $}}
; RV32IBT-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
; RV32IBT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
; RV32IBT-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
; RV32IBT-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
; RV32IBT-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
; RV32IBT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; RV32IBT-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
; RV32IBT-NEXT: DBG_VALUE [[ADDI]], $noreg
; RV32IBT-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2
; RV32IBT-NEXT: {{ $}}
; RV32IBT-NEXT: .1:
; RV32IBT-NEXT: {{ $}}
; RV32IBT-NEXT: .2:
; RV32IBT-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
; RV32IBT-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
; RV32IBT-NEXT: DBG_VALUE [[PHI]], $noreg
; RV32IBT-NEXT: DBG_VALUE [[PHI1]], $noreg
; RV32IBT-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
; RV32IBT-NEXT: $x10 = COPY [[ADD]]
; RV32IBT-NEXT: PseudoRET implicit $x10
; RV64I-LABEL: name: cmov_interleaved_debug_value		; RV64I-LABEL: name: cmov_interleaved_debug_value
; RV64I: successors: %bb.1, %bb.2		; RV64I: successors: %bb.1, %bb.2
; RV64I-NEXT: liveins: $x10, $x11, $x12, $x13		; RV64I-NEXT: liveins: $x10, $x11, $x12, $x13
; RV64I-NEXT: {{ $}}		; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13		; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12		; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11		; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10		; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1		; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
; RV64I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0		; RV64I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1		; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
; RV64I-NEXT: DBG_VALUE [[ADDI]], $noreg		; RV64I-NEXT: DBG_VALUE [[ADDI]], $noreg
; RV64I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2		; RV64I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2
; RV64I-NEXT: {{ $}}		; RV64I-NEXT: {{ $}}
; RV64I-NEXT: .1:		; RV64I-NEXT: .1:
; RV64I-NEXT: {{ $}}		; RV64I-NEXT: {{ $}}
; RV64I-NEXT: .2:		; RV64I-NEXT: .2:
; RV64I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1		; RV64I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
; RV64I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1		; RV64I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
; RV64I-NEXT: DBG_VALUE [[PHI]], $noreg		; RV64I-NEXT: DBG_VALUE [[PHI]], $noreg
; RV64I-NEXT: DBG_VALUE [[PHI1]], $noreg		; RV64I-NEXT: DBG_VALUE [[PHI1]], $noreg
; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]		; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
; RV64I-NEXT: $x10 = COPY [[ADD]]		; RV64I-NEXT: $x10 = COPY [[ADD]]
; RV64I-NEXT: PseudoRET implicit $x10		; RV64I-NEXT: PseudoRET implicit $x10
; RV64IBT-LABEL: name: cmov_interleaved_debug_value
; RV64IBT: successors: %bb.1, %bb.2
; RV64IBT-NEXT: liveins: $x10, $x11, $x12, $x13
; RV64IBT-NEXT: {{ $}}
; RV64IBT-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
; RV64IBT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
; RV64IBT-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
; RV64IBT-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
; RV64IBT-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
; RV64IBT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; RV64IBT-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
; RV64IBT-NEXT: DBG_VALUE [[ADDI]], $noreg
; RV64IBT-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2
; RV64IBT-NEXT: {{ $}}
; RV64IBT-NEXT: .1:
; RV64IBT-NEXT: {{ $}}
; RV64IBT-NEXT: .2:
; RV64IBT-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
; RV64IBT-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
; RV64IBT-NEXT: DBG_VALUE [[PHI]], $noreg
; RV64IBT-NEXT: DBG_VALUE [[PHI1]], $noreg
; RV64IBT-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
; RV64IBT-NEXT: $x10 = COPY [[ADD]]
; RV64IBT-NEXT: PseudoRET implicit $x10
%3:gpr = COPY $x13		%3:gpr = COPY $x13
%2:gpr = COPY $x12		%2:gpr = COPY $x12
%1:gpr = COPY $x11		%1:gpr = COPY $x11
%0:gpr = COPY $x10		%0:gpr = COPY $x10
%5:gpr = ANDI %0, 1		%5:gpr = ANDI %0, 1
%6:gpr = COPY $x0		%6:gpr = COPY $x0
%7:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %1, %2		%7:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %1, %2
DBG_VALUE %7, $noreg		DBG_VALUE %7, $noreg
Show All 10 Lines

llvm/test/CodeGen/RISCV/select-or.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
	; RUN: \| FileCheck -check-prefix=RV32I %s			; RUN: \| FileCheck -check-prefix=RV32I %s
	; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
	; RUN: \| FileCheck -check-prefix=RV32IBT %s
	; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \			; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
	; RUN: \| FileCheck -check-prefix=RV64I %s			; RUN: \| FileCheck -check-prefix=RV64I %s
	; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \
	; RUN: \| FileCheck -check-prefix=RV64IBT %s

	;; There are a few different ways to lower (select (or A, B), X, Y). This test			;; There are a few different ways to lower (select (or A, B), X, Y). This test
	;; ensures that we do so with as few branches as possible.			;; ensures that we do so with as few branches as possible.

	define signext i32 @select_of_or(i1 zeroext %a, i1 zeroext %b, i32 signext %c, i32 signext %d) nounwind {			define signext i32 @select_of_or(i1 zeroext %a, i1 zeroext %b, i32 signext %c, i32 signext %d) nounwind {
	; RV32I-LABEL: select_of_or:			; RV32I-LABEL: select_of_or:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	; RV32I-NEXT: or a1, a0, a1			; RV32I-NEXT: or a1, a0, a1
	; RV32I-NEXT: mv a0, a2			; RV32I-NEXT: mv a0, a2
	; RV32I-NEXT: bnez a1, .LBB0_2			; RV32I-NEXT: bnez a1, .LBB0_2
	; RV32I-NEXT: # %bb.1:			; RV32I-NEXT: # %bb.1:
	; RV32I-NEXT: mv a0, a3			; RV32I-NEXT: mv a0, a3
	; RV32I-NEXT: .LBB0_2:			; RV32I-NEXT: .LBB0_2:
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32IBT-LABEL: select_of_or:
	; RV32IBT: # %bb.0:
	; RV32IBT-NEXT: or a0, a0, a1
	; RV32IBT-NEXT: cmov a0, a0, a2, a3
	; RV32IBT-NEXT: ret
	;
	; RV64I-LABEL: select_of_or:			; RV64I-LABEL: select_of_or:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: or a1, a0, a1			; RV64I-NEXT: or a1, a0, a1
	; RV64I-NEXT: mv a0, a2			; RV64I-NEXT: mv a0, a2
	; RV64I-NEXT: bnez a1, .LBB0_2			; RV64I-NEXT: bnez a1, .LBB0_2
	; RV64I-NEXT: # %bb.1:			; RV64I-NEXT: # %bb.1:
	; RV64I-NEXT: mv a0, a3			; RV64I-NEXT: mv a0, a3
	; RV64I-NEXT: .LBB0_2:			; RV64I-NEXT: .LBB0_2:
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;
	; RV64IBT-LABEL: select_of_or:
	; RV64IBT: # %bb.0:
	; RV64IBT-NEXT: or a0, a0, a1
	; RV64IBT-NEXT: cmov a0, a0, a2, a3
	; RV64IBT-NEXT: ret
	%1 = or i1 %a, %b			%1 = or i1 %a, %b
	%2 = select i1 %1, i32 %c, i32 %d			%2 = select i1 %1, i32 %c, i32 %d
	ret i32 %2			ret i32 %2
	}			}

	declare signext i32 @either() nounwind			declare signext i32 @either() nounwind
	declare signext i32 @neither() nounwind			declare signext i32 @neither() nounwind

	Show All 9 Lines
	; RV32I-NEXT: j .LBB1_3			; RV32I-NEXT: j .LBB1_3
	; RV32I-NEXT: .LBB1_2: # %if.else			; RV32I-NEXT: .LBB1_2: # %if.else
	; RV32I-NEXT: call neither@plt			; RV32I-NEXT: call neither@plt
	; RV32I-NEXT: .LBB1_3: # %if.end			; RV32I-NEXT: .LBB1_3: # %if.end
	; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload			; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
	; RV32I-NEXT: addi sp, sp, 16			; RV32I-NEXT: addi sp, sp, 16
	; RV32I-NEXT: ret			; RV32I-NEXT: ret
	;			;
	; RV32IBT-LABEL: if_of_or:
	; RV32IBT: # %bb.0:
	; RV32IBT-NEXT: addi sp, sp, -16
	; RV32IBT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
	; RV32IBT-NEXT: or a0, a0, a1
	; RV32IBT-NEXT: beqz a0, .LBB1_2
	; RV32IBT-NEXT: # %bb.1: # %if.then
	; RV32IBT-NEXT: call either@plt
	; RV32IBT-NEXT: j .LBB1_3
	; RV32IBT-NEXT: .LBB1_2: # %if.else
	; RV32IBT-NEXT: call neither@plt
	; RV32IBT-NEXT: .LBB1_3: # %if.end
	; RV32IBT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
	; RV32IBT-NEXT: addi sp, sp, 16
	; RV32IBT-NEXT: ret
	;
	; RV64I-LABEL: if_of_or:			; RV64I-LABEL: if_of_or:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: addi sp, sp, -16			; RV64I-NEXT: addi sp, sp, -16
	; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill			; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
	; RV64I-NEXT: or a0, a0, a1			; RV64I-NEXT: or a0, a0, a1
	; RV64I-NEXT: beqz a0, .LBB1_2			; RV64I-NEXT: beqz a0, .LBB1_2
	; RV64I-NEXT: # %bb.1: # %if.then			; RV64I-NEXT: # %bb.1: # %if.then
	; RV64I-NEXT: call either@plt			; RV64I-NEXT: call either@plt
	; RV64I-NEXT: j .LBB1_3			; RV64I-NEXT: j .LBB1_3
	; RV64I-NEXT: .LBB1_2: # %if.else			; RV64I-NEXT: .LBB1_2: # %if.else
	; RV64I-NEXT: call neither@plt			; RV64I-NEXT: call neither@plt
	; RV64I-NEXT: .LBB1_3: # %if.end			; RV64I-NEXT: .LBB1_3: # %if.end
	; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload			; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
	; RV64I-NEXT: addi sp, sp, 16			; RV64I-NEXT: addi sp, sp, 16
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;
	; RV64IBT-LABEL: if_of_or:
	; RV64IBT: # %bb.0:
	; RV64IBT-NEXT: addi sp, sp, -16
	; RV64IBT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
	; RV64IBT-NEXT: or a0, a0, a1
	; RV64IBT-NEXT: beqz a0, .LBB1_2
	; RV64IBT-NEXT: # %bb.1: # %if.then
	; RV64IBT-NEXT: call either@plt
	; RV64IBT-NEXT: j .LBB1_3
	; RV64IBT-NEXT: .LBB1_2: # %if.else
	; RV64IBT-NEXT: call neither@plt
	; RV64IBT-NEXT: .LBB1_3: # %if.end
	; RV64IBT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
	; RV64IBT-NEXT: addi sp, sp, 16
	; RV64IBT-NEXT: ret
	%1 = or i1 %a, %b			%1 = or i1 %a, %b
	br i1 %1, label %if.then, label %if.else			br i1 %1, label %if.then, label %if.else

	if.then:			if.then:
	%2 = tail call i32 @either()			%2 = tail call i32 @either()
	br label %if.end			br label %if.end

	if.else:			if.else:
	%3 = tail call i32 @neither()			%3 = tail call i32 @neither()
	br label %if.end			br label %if.end

	if.end:			if.end:
	%4 = phi i32 [%2, %if.then], [%3, %if.else]			%4 = phi i32 [%2, %if.then], [%3, %if.else]
	ret i32 %4			ret i32 %4
	}			}

llvm/test/CodeGen/RISCV/ssub_sat.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc < %s -mtriple=riscv32 -mattr=+m \| FileCheck %s --check-prefixes=RV32NoZbt,RV32I			; RUN: llc < %s -mtriple=riscv32 -mattr=+m \| FileCheck %s --check-prefixes=RV32,RV32I
	; RUN: llc < %s -mtriple=riscv64 -mattr=+m \| FileCheck %s --check-prefixes=RV64NoZbt,RV64I			; RUN: llc < %s -mtriple=riscv64 -mattr=+m \| FileCheck %s --check-prefixes=RV64,RV64I
	; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb \| FileCheck %s --check-prefixes=RV32NoZbt,RV32IZbb			; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb \| FileCheck %s --check-prefixes=RV32,RV32IZbb
	; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb \| FileCheck %s --check-prefixes=RV64NoZbt,RV64IZbb			; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb \| FileCheck %s --check-prefixes=RV64,RV64IZbb
	; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb,+experimental-zbt \| FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbZbt
	; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb,+experimental-zbt \| FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbZbt

	declare i4 @llvm.ssub.sat.i4(i4, i4)			declare i4 @llvm.ssub.sat.i4(i4, i4)
	declare i8 @llvm.ssub.sat.i8(i8, i8)			declare i8 @llvm.ssub.sat.i8(i8, i8)
	declare i16 @llvm.ssub.sat.i16(i16, i16)			declare i16 @llvm.ssub.sat.i16(i16, i16)
	declare i32 @llvm.ssub.sat.i32(i32, i32)			declare i32 @llvm.ssub.sat.i32(i32, i32)
	declare i64 @llvm.ssub.sat.i64(i64, i64)			declare i64 @llvm.ssub.sat.i64(i64, i64)

	define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {			define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
	; RV32NoZbt-LABEL: func:			; RV32-LABEL: func:
	; RV32NoZbt: # %bb.0:			; RV32: # %bb.0:
	; RV32NoZbt-NEXT: mv a2, a0			; RV32-NEXT: mv a2, a0
	; RV32NoZbt-NEXT: sgtz a3, a1			; RV32-NEXT: sgtz a3, a1
	; RV32NoZbt-NEXT: sub a0, a0, a1			; RV32-NEXT: sub a0, a0, a1
	; RV32NoZbt-NEXT: slt a1, a0, a2			; RV32-NEXT: slt a1, a0, a2
	; RV32NoZbt-NEXT: beq a3, a1, .LBB0_2			; RV32-NEXT: beq a3, a1, .LBB0_2
	; RV32NoZbt-NEXT: # %bb.1:			; RV32-NEXT: # %bb.1:
	; RV32NoZbt-NEXT: srai a0, a0, 31			; RV32-NEXT: srai a0, a0, 31
	; RV32NoZbt-NEXT: lui a1, 524288			; RV32-NEXT: lui a1, 524288
	; RV32NoZbt-NEXT: xor a0, a0, a1			; RV32-NEXT: xor a0, a0, a1
	; RV32NoZbt-NEXT: .LBB0_2:			; RV32-NEXT: .LBB0_2:
	; RV32NoZbt-NEXT: ret			; RV32-NEXT: ret
	;			;
	; RV64I-LABEL: func:			; RV64I-LABEL: func:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: sub a0, a0, a1			; RV64I-NEXT: sub a0, a0, a1
	; RV64I-NEXT: lui a1, 524288			; RV64I-NEXT: lui a1, 524288
	; RV64I-NEXT: addiw a2, a1, -1			; RV64I-NEXT: addiw a2, a1, -1
	; RV64I-NEXT: bge a0, a2, .LBB0_3			; RV64I-NEXT: bge a0, a2, .LBB0_3
	; RV64I-NEXT: # %bb.1:			; RV64I-NEXT: # %bb.1:
	Show All 10 Lines
	; RV64IZbb-LABEL: func:			; RV64IZbb-LABEL: func:
	; RV64IZbb: # %bb.0:			; RV64IZbb: # %bb.0:
	; RV64IZbb-NEXT: sub a0, a0, a1			; RV64IZbb-NEXT: sub a0, a0, a1
	; RV64IZbb-NEXT: lui a1, 524288			; RV64IZbb-NEXT: lui a1, 524288
	; RV64IZbb-NEXT: addiw a2, a1, -1			; RV64IZbb-NEXT: addiw a2, a1, -1
	; RV64IZbb-NEXT: min a0, a0, a2			; RV64IZbb-NEXT: min a0, a0, a2
	; RV64IZbb-NEXT: max a0, a0, a1			; RV64IZbb-NEXT: max a0, a0, a1
	; RV64IZbb-NEXT: ret			; RV64IZbb-NEXT: ret
	;
	; RV32IZbbZbt-LABEL: func:
	; RV32IZbbZbt: # %bb.0:
	; RV32IZbbZbt-NEXT: sgtz a2, a1
	; RV32IZbbZbt-NEXT: sub a1, a0, a1
	; RV32IZbbZbt-NEXT: slt a0, a1, a0
	; RV32IZbbZbt-NEXT: xor a0, a2, a0
	; RV32IZbbZbt-NEXT: srai a2, a1, 31
	; RV32IZbbZbt-NEXT: lui a3, 524288
	; RV32IZbbZbt-NEXT: xor a2, a2, a3
	; RV32IZbbZbt-NEXT: cmov a0, a0, a2, a1
	; RV32IZbbZbt-NEXT: ret
	%tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y);			%tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y);
	ret i32 %tmp;			ret i32 %tmp;
	}			}

	define i64 @func2(i64 %x, i64 %y) nounwind {			define i64 @func2(i64 %x, i64 %y) nounwind {
	; RV32NoZbt-LABEL: func2:			; RV32-LABEL: func2:
	; RV32NoZbt: # %bb.0:			; RV32: # %bb.0:
	; RV32NoZbt-NEXT: mv a4, a1			; RV32-NEXT: mv a4, a1
	; RV32NoZbt-NEXT: sltu a1, a0, a2			; RV32-NEXT: sltu a1, a0, a2
	; RV32NoZbt-NEXT: sub a5, a4, a3			; RV32-NEXT: sub a5, a4, a3
	; RV32NoZbt-NEXT: sub a1, a5, a1			; RV32-NEXT: sub a1, a5, a1
	; RV32NoZbt-NEXT: xor a5, a4, a1			; RV32-NEXT: xor a5, a4, a1
	; RV32NoZbt-NEXT: xor a3, a4, a3			; RV32-NEXT: xor a3, a4, a3
	; RV32NoZbt-NEXT: and a3, a3, a5			; RV32-NEXT: and a3, a3, a5
	; RV32NoZbt-NEXT: bltz a3, .LBB1_2			; RV32-NEXT: bltz a3, .LBB1_2
	; RV32NoZbt-NEXT: # %bb.1:			; RV32-NEXT: # %bb.1:
	; RV32NoZbt-NEXT: sub a0, a0, a2			; RV32-NEXT: sub a0, a0, a2
	; RV32NoZbt-NEXT: ret			; RV32-NEXT: ret
	; RV32NoZbt-NEXT: .LBB1_2:			; RV32-NEXT: .LBB1_2:
	; RV32NoZbt-NEXT: srai a0, a1, 31			; RV32-NEXT: srai a0, a1, 31
	; RV32NoZbt-NEXT: lui a1, 524288			; RV32-NEXT: lui a1, 524288
	; RV32NoZbt-NEXT: xor a1, a0, a1			; RV32-NEXT: xor a1, a0, a1
	; RV32NoZbt-NEXT: ret			; RV32-NEXT: ret
	;			;
	; RV64NoZbt-LABEL: func2:			; RV64-LABEL: func2:
	; RV64NoZbt: # %bb.0:			; RV64: # %bb.0:
	; RV64NoZbt-NEXT: mv a2, a0			; RV64-NEXT: mv a2, a0
	; RV64NoZbt-NEXT: sgtz a3, a1			; RV64-NEXT: sgtz a3, a1
	; RV64NoZbt-NEXT: sub a0, a0, a1			; RV64-NEXT: sub a0, a0, a1
	; RV64NoZbt-NEXT: slt a1, a0, a2			; RV64-NEXT: slt a1, a0, a2
	; RV64NoZbt-NEXT: beq a3, a1, .LBB1_2			; RV64-NEXT: beq a3, a1, .LBB1_2
	; RV64NoZbt-NEXT: # %bb.1:			; RV64-NEXT: # %bb.1:
	; RV64NoZbt-NEXT: srai a0, a0, 63			; RV64-NEXT: srai a0, a0, 63
	; RV64NoZbt-NEXT: li a1, -1			; RV64-NEXT: li a1, -1
	; RV64NoZbt-NEXT: slli a1, a1, 63			; RV64-NEXT: slli a1, a1, 63
	; RV64NoZbt-NEXT: xor a0, a0, a1			; RV64-NEXT: xor a0, a0, a1
	; RV64NoZbt-NEXT: .LBB1_2:			; RV64-NEXT: .LBB1_2:
	; RV64NoZbt-NEXT: ret			; RV64-NEXT: ret
	;
	; RV32IZbbZbt-LABEL: func2:
	; RV32IZbbZbt: # %bb.0:
	; RV32IZbbZbt-NEXT: sltu a4, a0, a2
	; RV32IZbbZbt-NEXT: sub a5, a1, a3
	; RV32IZbbZbt-NEXT: sub a4, a5, a4
	; RV32IZbbZbt-NEXT: srai a5, a4, 31
	; RV32IZbbZbt-NEXT: lui a6, 524288
	; RV32IZbbZbt-NEXT: xor a6, a5, a6
	; RV32IZbbZbt-NEXT: xor a7, a1, a4
	; RV32IZbbZbt-NEXT: xor a1, a1, a3
	; RV32IZbbZbt-NEXT: and a1, a1, a7
	; RV32IZbbZbt-NEXT: slti a3, a1, 0
	; RV32IZbbZbt-NEXT: cmov a1, a3, a6, a4
	; RV32IZbbZbt-NEXT: sub a0, a0, a2
	; RV32IZbbZbt-NEXT: cmov a0, a3, a5, a0
	; RV32IZbbZbt-NEXT: ret
	;
	; RV64IZbbZbt-LABEL: func2:
	; RV64IZbbZbt: # %bb.0:
	; RV64IZbbZbt-NEXT: sgtz a2, a1
	; RV64IZbbZbt-NEXT: sub a1, a0, a1
	; RV64IZbbZbt-NEXT: slt a0, a1, a0
	; RV64IZbbZbt-NEXT: xor a0, a2, a0
	; RV64IZbbZbt-NEXT: srai a2, a1, 63
	; RV64IZbbZbt-NEXT: li a3, -1
	; RV64IZbbZbt-NEXT: slli a3, a3, 63
	; RV64IZbbZbt-NEXT: xor a2, a2, a3
	; RV64IZbbZbt-NEXT: cmov a0, a0, a2, a1
	; RV64IZbbZbt-NEXT: ret
	%tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y);			%tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y);
	ret i64 %tmp;			ret i64 %tmp;
	}			}

	define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {			define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
	; RV32I-LABEL: func16:			; RV32I-LABEL: func16:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	; RV32I-NEXT: sub a0, a0, a1			; RV32I-NEXT: sub a0, a0, a1
	▲ Show 20 Lines • Show All 173 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/ssub_sat_plus.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc < %s -mtriple=riscv32 -mattr=+m \| FileCheck %s --check-prefixes=RV32NoZbt,RV32I			; RUN: llc < %s -mtriple=riscv32 -mattr=+m \| FileCheck %s --check-prefixes=RV32,RV32I
	; RUN: llc < %s -mtriple=riscv64 -mattr=+m \| FileCheck %s --check-prefixes=RV64NoZbt,RV64I			; RUN: llc < %s -mtriple=riscv64 -mattr=+m \| FileCheck %s --check-prefixes=RV64,RV64I
	; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb \| FileCheck %s --check-prefixes=RV32NoZbt,RV32IZbb			; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb \| FileCheck %s --check-prefixes=RV32,RV32IZbb
	; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb \| FileCheck %s --check-prefixes=RV64NoZbt,RV64IZbb			; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb \| FileCheck %s --check-prefixes=RV64,RV64IZbb
	; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb,+experimental-zbt \| FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbZbt
	; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb,+experimental-zbt \| FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbZbt

	declare i4 @llvm.ssub.sat.i4(i4, i4)			declare i4 @llvm.ssub.sat.i4(i4, i4)
	declare i8 @llvm.ssub.sat.i8(i8, i8)			declare i8 @llvm.ssub.sat.i8(i8, i8)
	declare i16 @llvm.ssub.sat.i16(i16, i16)			declare i16 @llvm.ssub.sat.i16(i16, i16)
	declare i32 @llvm.ssub.sat.i32(i32, i32)			declare i32 @llvm.ssub.sat.i32(i32, i32)
	declare i64 @llvm.ssub.sat.i64(i64, i64)			declare i64 @llvm.ssub.sat.i64(i64, i64)

	define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {			define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
	; RV32NoZbt-LABEL: func32:			; RV32-LABEL: func32:
	; RV32NoZbt: # %bb.0:			; RV32: # %bb.0:
	; RV32NoZbt-NEXT: mv a3, a0			; RV32-NEXT: mv a3, a0
	; RV32NoZbt-NEXT: mul a0, a1, a2			; RV32-NEXT: mul a0, a1, a2
	; RV32NoZbt-NEXT: sgtz a1, a0			; RV32-NEXT: sgtz a1, a0
	; RV32NoZbt-NEXT: sub a0, a3, a0			; RV32-NEXT: sub a0, a3, a0
	; RV32NoZbt-NEXT: slt a2, a0, a3			; RV32-NEXT: slt a2, a0, a3
	; RV32NoZbt-NEXT: beq a1, a2, .LBB0_2			; RV32-NEXT: beq a1, a2, .LBB0_2
	; RV32NoZbt-NEXT: # %bb.1:			; RV32-NEXT: # %bb.1:
	; RV32NoZbt-NEXT: srai a0, a0, 31			; RV32-NEXT: srai a0, a0, 31
	; RV32NoZbt-NEXT: lui a1, 524288			; RV32-NEXT: lui a1, 524288
	; RV32NoZbt-NEXT: xor a0, a0, a1			; RV32-NEXT: xor a0, a0, a1
	; RV32NoZbt-NEXT: .LBB0_2:			; RV32-NEXT: .LBB0_2:
	; RV32NoZbt-NEXT: ret			; RV32-NEXT: ret
	;			;
	; RV64I-LABEL: func32:			; RV64I-LABEL: func32:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: sext.w a0, a0			; RV64I-NEXT: sext.w a0, a0
	; RV64I-NEXT: mulw a1, a1, a2			; RV64I-NEXT: mulw a1, a1, a2
	; RV64I-NEXT: sub a0, a0, a1			; RV64I-NEXT: sub a0, a0, a1
	; RV64I-NEXT: lui a1, 524288			; RV64I-NEXT: lui a1, 524288
	; RV64I-NEXT: addiw a2, a1, -1			; RV64I-NEXT: addiw a2, a1, -1
	Show All 14 Lines
	; RV64IZbb-NEXT: sext.w a0, a0			; RV64IZbb-NEXT: sext.w a0, a0
	; RV64IZbb-NEXT: mulw a1, a1, a2			; RV64IZbb-NEXT: mulw a1, a1, a2
	; RV64IZbb-NEXT: sub a0, a0, a1			; RV64IZbb-NEXT: sub a0, a0, a1
	; RV64IZbb-NEXT: lui a1, 524288			; RV64IZbb-NEXT: lui a1, 524288
	; RV64IZbb-NEXT: addiw a2, a1, -1			; RV64IZbb-NEXT: addiw a2, a1, -1
	; RV64IZbb-NEXT: min a0, a0, a2			; RV64IZbb-NEXT: min a0, a0, a2
	; RV64IZbb-NEXT: max a0, a0, a1			; RV64IZbb-NEXT: max a0, a0, a1
	; RV64IZbb-NEXT: ret			; RV64IZbb-NEXT: ret
	;
	; RV32IZbbZbt-LABEL: func32:
	; RV32IZbbZbt: # %bb.0:
	; RV32IZbbZbt-NEXT: mul a1, a1, a2
	; RV32IZbbZbt-NEXT: sgtz a2, a1
	; RV32IZbbZbt-NEXT: sub a1, a0, a1
	; RV32IZbbZbt-NEXT: slt a0, a1, a0
	; RV32IZbbZbt-NEXT: xor a0, a2, a0
	; RV32IZbbZbt-NEXT: srai a2, a1, 31
	; RV32IZbbZbt-NEXT: lui a3, 524288
	; RV32IZbbZbt-NEXT: xor a2, a2, a3
	; RV32IZbbZbt-NEXT: cmov a0, a0, a2, a1
	; RV32IZbbZbt-NEXT: ret
	%a = mul i32 %y, %z			%a = mul i32 %y, %z
	%tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %a)			%tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %a)
	ret i32 %tmp			ret i32 %tmp
	}			}

	define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {			define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
	; RV32NoZbt-LABEL: func64:			; RV32-LABEL: func64:
	; RV32NoZbt: # %bb.0:			; RV32: # %bb.0:
	; RV32NoZbt-NEXT: mv a2, a1			; RV32-NEXT: mv a2, a1
	; RV32NoZbt-NEXT: sltu a1, a0, a4			; RV32-NEXT: sltu a1, a0, a4
	; RV32NoZbt-NEXT: sub a3, a2, a5			; RV32-NEXT: sub a3, a2, a5
	; RV32NoZbt-NEXT: sub a1, a3, a1			; RV32-NEXT: sub a1, a3, a1
	; RV32NoZbt-NEXT: xor a3, a2, a1			; RV32-NEXT: xor a3, a2, a1
	; RV32NoZbt-NEXT: xor a2, a2, a5			; RV32-NEXT: xor a2, a2, a5
	; RV32NoZbt-NEXT: and a2, a2, a3			; RV32-NEXT: and a2, a2, a3
	; RV32NoZbt-NEXT: bltz a2, .LBB1_2			; RV32-NEXT: bltz a2, .LBB1_2
	; RV32NoZbt-NEXT: # %bb.1:			; RV32-NEXT: # %bb.1:
	; RV32NoZbt-NEXT: sub a0, a0, a4			; RV32-NEXT: sub a0, a0, a4
	; RV32NoZbt-NEXT: ret			; RV32-NEXT: ret
	; RV32NoZbt-NEXT: .LBB1_2:			; RV32-NEXT: .LBB1_2:
	; RV32NoZbt-NEXT: srai a0, a1, 31			; RV32-NEXT: srai a0, a1, 31
	; RV32NoZbt-NEXT: lui a1, 524288			; RV32-NEXT: lui a1, 524288
	; RV32NoZbt-NEXT: xor a1, a0, a1			; RV32-NEXT: xor a1, a0, a1
	; RV32NoZbt-NEXT: ret			; RV32-NEXT: ret
	;			;
	; RV64NoZbt-LABEL: func64:			; RV64-LABEL: func64:
	; RV64NoZbt: # %bb.0:			; RV64: # %bb.0:
	; RV64NoZbt-NEXT: mv a1, a0			; RV64-NEXT: mv a1, a0
	; RV64NoZbt-NEXT: sgtz a3, a2			; RV64-NEXT: sgtz a3, a2
	; RV64NoZbt-NEXT: sub a0, a0, a2			; RV64-NEXT: sub a0, a0, a2
	; RV64NoZbt-NEXT: slt a1, a0, a1			; RV64-NEXT: slt a1, a0, a1
	; RV64NoZbt-NEXT: beq a3, a1, .LBB1_2			; RV64-NEXT: beq a3, a1, .LBB1_2
	; RV64NoZbt-NEXT: # %bb.1:			; RV64-NEXT: # %bb.1:
	; RV64NoZbt-NEXT: srai a0, a0, 63			; RV64-NEXT: srai a0, a0, 63
	; RV64NoZbt-NEXT: li a1, -1			; RV64-NEXT: li a1, -1
	; RV64NoZbt-NEXT: slli a1, a1, 63			; RV64-NEXT: slli a1, a1, 63
	; RV64NoZbt-NEXT: xor a0, a0, a1			; RV64-NEXT: xor a0, a0, a1
	; RV64NoZbt-NEXT: .LBB1_2:			; RV64-NEXT: .LBB1_2:
	; RV64NoZbt-NEXT: ret			; RV64-NEXT: ret
	;
	; RV32IZbbZbt-LABEL: func64:
	; RV32IZbbZbt: # %bb.0:
	; RV32IZbbZbt-NEXT: sltu a2, a0, a4
	; RV32IZbbZbt-NEXT: sub a3, a1, a5
	; RV32IZbbZbt-NEXT: sub a2, a3, a2
	; RV32IZbbZbt-NEXT: srai a3, a2, 31
	; RV32IZbbZbt-NEXT: lui a6, 524288
	; RV32IZbbZbt-NEXT: xor a6, a3, a6
	; RV32IZbbZbt-NEXT: xor a7, a1, a2
	; RV32IZbbZbt-NEXT: xor a1, a1, a5
	; RV32IZbbZbt-NEXT: and a1, a1, a7
	; RV32IZbbZbt-NEXT: slti a5, a1, 0
	; RV32IZbbZbt-NEXT: cmov a1, a5, a6, a2
	; RV32IZbbZbt-NEXT: sub a0, a0, a4
	; RV32IZbbZbt-NEXT: cmov a0, a5, a3, a0
	; RV32IZbbZbt-NEXT: ret
	;
	; RV64IZbbZbt-LABEL: func64:
	; RV64IZbbZbt: # %bb.0:
	; RV64IZbbZbt-NEXT: sgtz a1, a2
	; RV64IZbbZbt-NEXT: sub a2, a0, a2
	; RV64IZbbZbt-NEXT: slt a0, a2, a0
	; RV64IZbbZbt-NEXT: xor a0, a1, a0
	; RV64IZbbZbt-NEXT: srai a1, a2, 63
	; RV64IZbbZbt-NEXT: li a3, -1
	; RV64IZbbZbt-NEXT: slli a3, a3, 63
	; RV64IZbbZbt-NEXT: xor a1, a1, a3
	; RV64IZbbZbt-NEXT: cmov a0, a0, a1, a2
	; RV64IZbbZbt-NEXT: ret
	%a = mul i64 %y, %z			%a = mul i64 %y, %z
	%tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %z)			%tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %z)
	ret i64 %tmp			ret i64 %tmp
	}			}

	define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {			define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
	; RV32I-LABEL: func16:			; RV32I-LABEL: func16:
	; RV32I: # %bb.0:			; RV32I: # %bb.0:
	▲ Show 20 Lines • Show All 229 Lines • Show Last 20 Lines

llvm/test/MC/RISCV/rv32zbt-invalid.s

This file was deleted.

	# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbt < %s 2>&1 \| FileCheck %s

	# Too few operands
	cmix t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
	# Too few operands
	cmov t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
	# Too few operands
	fsl t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
	# Too few operands
	fsr t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
	# Too few operands
	fsri t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
	# Immediate operand out of range
	fsri t0, t1, t2, 32 # CHECK: :[[@LINE]]:18: error: immediate must be an integer in the range [0, 31]
	fsri t0, t1, t2, -1 # CHECK: :[[@LINE]]:18: error: immediate must be an integer in the range [0, 31]
	fslw t0, t1, t2, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
	fsrw t0, t1, t2, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
	fsriw t0, t1, t2, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}

llvm/test/MC/RISCV/rv32zbt-valid.s

This file was deleted.

	# With Bitmanip ternary extension:
	# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbt -show-encoding \
	# RUN: \| FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
	# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbt < %s \
	# RUN: \| llvm-objdump --mattr=+experimental-zbt -d -r - \
	# RUN: \| FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s

	# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
	# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
	cmix t0, t1, t2, t3
	# CHECK-ASM-AND-OBJ: cmov t0, t1, t2, t3
	# CHECK-ASM: encoding: [0xb3,0xd2,0x63,0xe6]
	cmov t0, t1, t2, t3
	# CHECK-ASM-AND-OBJ: fsl t0, t1, t2, t3
	# CHECK-ASM: encoding: [0xb3,0x12,0xc3,0x3d]
	fsl t0, t1, t2, t3
	# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
	# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
	fsr t0, t1, t2, t3
	# CHECK-ASM-AND-OBJ: fsri t0, t1, t2, 0
	# CHECK-ASM: encoding: [0x93,0x52,0x03,0x3c]
	fsri t0, t1, t2, 0

llvm/test/MC/RISCV/rv64zbt-invalid.s

This file was deleted.

	# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbt < %s 2>&1 \| FileCheck %s

	# Too few operands
	fslw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
	# Too few operands
	fsrw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
	# Immediate operand out of range
	fsriw t0, t1, t2, 32 # CHECK: :[[@LINE]]:19: error: immediate must be an integer in the range [0, 31]
	fsriw t0, t1, t2, -1 # CHECK: :[[@LINE]]:19: error: immediate must be an integer in the range [0, 31]

llvm/test/MC/RISCV/rv64zbt-valid.s

This file was deleted.

	# With Bitmanip ternary extension:
	# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbt -show-encoding \
	# RUN: \| FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
	# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbt < %s \
	# RUN: \| llvm-objdump --mattr=+experimental-zbt -d -r - \
	# RUN: \| FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s

	# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
	# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
	cmix t0, t1, t2, t3
	# CHECK-ASM-AND-OBJ: cmov t0, t1, t2, t3
	# CHECK-ASM: encoding: [0xb3,0xd2,0x63,0xe6]
	cmov t0, t1, t2, t3
	# CHECK-ASM-AND-OBJ: fsl t0, t1, t2, t3
	# CHECK-ASM: encoding: [0xb3,0x12,0xc3,0x3d]
	fsl t0, t1, t2, t3
	# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
	# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
	fsr t0, t1, t2, t3
	# CHECK-ASM-AND-OBJ: fsri t0, t1, t2, 0
	# CHECK-ASM: encoding: [0x93,0x52,0x03,0x3c]
	fsri t0, t1, t2, 0
	# CHECK-ASM-AND-OBJ: fslw t0, t1, t2, t3
	# CHECK-ASM: encoding: [0xbb,0x12,0xc3,0x3d]
	fslw t0, t1, t2, t3
	# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3
	# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
	fsrw t0, t1, t2, t3
	# CHECK-ASM-AND-OBJ: fsriw t0, t1, t2, 0
	# CHECK-ASM: encoding: [0x9b,0x52,0x03,0x3c]
	fsriw t0, t1, t2, 0

This is an archive of the discontinued LLVM Phabricator instance.

[RISCV] Remove support for the unratified Zbt extension.ClosedPublic

Details

Diff Detail

Event Timeline

Revision Contents

Diff 459976

clang/include/clang/Basic/BuiltinsRISCV.def

clang/lib/CodeGen/CGBuiltin.cpp

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbt.c

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbt.c

llvm/docs/RISCVUsage.rst

llvm/docs/ReleaseNotes.rst

llvm/include/llvm/IR/IntrinsicsRISCV.td

llvm/lib/Target/RISCV/RISCV.td

llvm/lib/Target/RISCV/RISCVISelLowering.h

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

llvm/lib/Target/RISCV/RISCVSchedRocket.td

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

llvm/lib/Target/RISCV/RISCVScheduleB.td

llvm/lib/Target/RISCV/RISCVSubtarget.h

llvm/test/CodeGen/RISCV/attributes.ll

llvm/test/CodeGen/RISCV/div-pow2.ll

llvm/test/CodeGen/RISCV/iabs.ll

llvm/test/CodeGen/RISCV/neg-abs.ll

llvm/test/CodeGen/RISCV/rv32zbt-intrinsic.ll

llvm/test/CodeGen/RISCV/rv32zbt.ll

llvm/test/CodeGen/RISCV/rv64zbt-intrinsic.ll

llvm/test/CodeGen/RISCV/rv64zbt.ll

llvm/test/CodeGen/RISCV/sadd_sat.ll

llvm/test/CodeGen/RISCV/sadd_sat_plus.ll

llvm/test/CodeGen/RISCV/select-and.ll

llvm/test/CodeGen/RISCV/select-bare.ll

llvm/test/CodeGen/RISCV/select-cc.ll

llvm/test/CodeGen/RISCV/select-const.ll

llvm/test/CodeGen/RISCV/select-optimize-multiple.ll

llvm/test/CodeGen/RISCV/select-optimize-multiple.mir

llvm/test/CodeGen/RISCV/select-or.ll

llvm/test/CodeGen/RISCV/ssub_sat.ll

llvm/test/CodeGen/RISCV/ssub_sat_plus.ll

llvm/test/MC/RISCV/rv32zbt-invalid.s

llvm/test/MC/RISCV/rv32zbt-valid.s

llvm/test/MC/RISCV/rv64zbt-invalid.s

llvm/test/MC/RISCV/rv64zbt-valid.s

[RISCV] Remove support for the unratified Zbt extension.
ClosedPublic