[RISCV] Add MC support of RISCV Zcb Extension

[VincentWu]

Summary

This patch add the instructions of Zcb extension.

Instructions in zcb extensions shorten part of bit manipulation instructions.

[MaskRay]

llvm/test/MC/RISCV/rv32zcb-Invalid.s

1 ↗

(On Diff #449868)

< %s => %s

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

11

Is this the right version?

54

80 columns

68

80 columns

99

Please fill out the scheduling information to match the non-compressed forms.

103

Does these require Zbb as well or does Zcb imply Zbb?

109

Does this require M or Zmmul or does Zcb imply M/Zmmul?

llvm/test/MC/RISCV/rv32zcb-Invalid.s

1 ↗

(On Diff #449868)

Don't capitalize "Invalid" in the test name.

llvm/test/MC/RISCV/rv64zcb-Invalid.s

1 ↗

(On Diff #449868)

Don't capitalize Invalid in the test name

[kito-cheng]

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

109

Krste say m require zmmul here:

https://github.com/riscv/riscv-isa-manual/issues/869#issuecomment-1186043486

[kito-cheng]

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

109

Oh you mean require m or zmmul here , just ignore my comments :P

[VincentWu]

rebase & address comments

[VincentWu]

correct Predicates

[craig.topper]

llvm/lib/Target/RISCV/RISCV.td

366 ↗

(On Diff #455059)

Should this implication also be in RISCVISAInfo.cpp? Right now I think specifying Zcb in the -march will put zca in the ELF attributes, but won't define __riscv_zca.

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

121

Use the Sched information for LBU.

122

Please indent the body of this.

129

Use the Sched information for LHU.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

132

Indent

139

Indent

162

Need InstAliases for load/store with no immediate specified. Similar to this alias from RISCVInstrInfoC.td

def : InstAlias<"c.lw $rd, (${rs1})", (C_LW GPRC:$rd, GPRC:$rs1, 0)>;

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

19 ↗

(On Diff #455059)

If we put the write Sched information to match the uncompressed forms, is this still needed?

llvm/test/MC/RISCV/rv32zcb-valid.s

14

Please check to end of line using {{$}}

llvm/test/MC/RISCV/rv64zcb-invalid.s

1 ↗

(On Diff #455059)

Use a single test file for riscv32 and riscv64

llvm/test/MC/RISCV/rv64zcb-valid.s

2

Use a single test file for riscv32 and riscv64. Except for riscv64 only instructions.

[craig.topper]

Are you going to add the CompressPats in a different patch?

[VincentWu]

address comments

[VincentWu]

In D131141#3753861, @craig.topper wrote:

Are you going to add the CompressPats in a different patch?

yes, I plan submit it as CodeGen part.
But I can add it into this patch if it is required.

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

19 ↗

(On Diff #455059)

Sorry, could you explain what is "uncompressed forms"? and where it is?

[craig.topper]

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

19 ↗

(On Diff #455059)

Every compressed instruction in Zcb has an equivalent instruction with a 32-bit encoding. Both instructions should have the same scheduling information.

[VincentWu]

set zcb inst Sched info same as their uncompressed forms

[VincentWu]

Add CompressPats for zcb

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

170

This feels wrong to me, but decompression is a bit dodgy if you can have all of Zcb without some of the extensions that its instructions decompress to?

178

Space after // (repeated multiple times)

196

These comments are pointless (repeated multiple times)

216

These don't line up, either pad them properly or don't bother at all

240

These aren't indented anywhere in llvm/lib/Target/RISCV

241

Why do you have at least two spaces after the comma here for every line? If you want to make them line up then there should be at least one where there's only one space.

[VincentWu]

address comments

[craig.topper]

llvm/lib/Target/RISCV/RISCV.td

368 ↗

(On Diff #456542)

The A should be lined up with the " on the line above.

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

171

The second CompressPat needs let isCompressOnly = true in. See the CompressPats for C_ADD.

223

I think C_LW the wrong instruction?

223

Do you have tests for these patterns?

llvm/test/MC/RISCV/rv32zcb-valid.s

22

Needs {{$}} at the end of the line.

97

ANDI -> andi

145

ADDI -> addi

But what is this testing?

149

What is this testing?

llvm/test/MC/RISCV/rv64zcb-valid.s

17

Need {{$}} at the end of the line.

[VincentWu]

address comments

[craig.topper]

Please rebase

[craig.topper]

Rebase

[craig.topper]

Add back the new files

[craig.topper]

Add CSZN format as named in the spec.
Reuse CLoad_ri/CStore_rri classes instead of creating new ones that were almost the same.
Use CS_ALU class for c.mul.

[craig.topper]

Update for rename CS_ALU to CA_ALU

[craig.topper]

Merge uimm32_zc into uimm2.
Add RISCVOp::OPERAND_UIMM2_LSB0

[craig.topper]

Fix typo in RISCVBaseInfo.h

[craig.topper]

Fix RUN line that was duplicate testing riscv64

[VincentWu]

rebase to upstream

[VincentWu]

reset HEAD back to Diff 492315.

[craig.topper]

@VincentWu are you ok with the changes I made?

[craig.topper]

Update RISCVUsage.rst

[VincentWu]

In D131141#4081778, @craig.topper wrote:

@VincentWu are you ok with the changes I made?

sure, thank you for your work )

[VincentWu]

should I update zcb to v1.0 in this patch?
or create a new one

[craig.topper]

In D131141#4082469, @VincentWu wrote:

should I update zcb to v1.0 in this patch?
or create a new one

Let's go ahead and commit this as is. I'll add Zcb to my version bump patch D142596

[craig.topper]

LGTM

[luismarques]

Possibly we want to add this change to the release notes?

llvm/lib/Target/RISCV/RISCVFeatures.td

304–308

Is there any particular reason why this is described as a "shortened format" instead of the more common "compressed"?

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

10–11

Ditto "Code-size reduction" -> "compressed"?

[craig.topper]

Address @luismarques comments

[craig.topper]

Update tests

[luismarques]

LGTM, with some in-line caveats.

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

2

Zc -> Zc*

llvm/test/MC/RISCV/rv32zcb-valid.s

22

Still has the old message phrasing with the "shortened".

[craig.topper]

Update file header

clang/test/Preprocessor/riscv-target-features.c

 // CHECK-NOT: __riscv_zkt
 // CHECK-NOT: __riscv_zk
 // CHECK-NOT: __riscv_zicbom
 // CHECK-NOT: __riscv_zicboz
 // CHECK-NOT: __riscv_svnapot
 // CHECK-NOT: __riscv_svpbmt
 // CHECK-NOT: __riscv_svinval
 // CHECK-NOT: __riscv_xventanacondops
+// CHECK-NOT: __riscv_zca
+// CHECK-NOT: __riscv_zcb
 // CHECK-NOT: __riscv_zcd
 // CHECK-NOT: __riscv_zcf
 // CHECK-NOT: __riscv_h
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s

 // RUN: %clang -target riscv64 -march=rv64ixventanacondops -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-XVENTANACONDOPS-EXT %s
 // CHECK-XVENTANACONDOPS-EXT: __riscv_xventanacondops 1000000{{$}}
 
 // RUN: %clang -target riscv64 -march=rv64ixtheadvdot -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-XTHEADVDOT-EXT %s
 // CHECK-XTHEADVDOT-EXT: __riscv_xtheadvdot 1000000{{$}}
 
+// RUN: %clang -target riscv32 -march=rv32izca0p70 -menable-experimental-extensions \
+// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCA-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izca0p70 -menable-experimental-extensions \
+// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCA-EXT %s
+// CHECK-ZCA-EXT: __riscv_zca 70000{{$}}
+
+// RUN: %clang -target riscv32 -march=rv32izcb0p70 -menable-experimental-extensions \
+// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCB-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izcb0p70 -menable-experimental-extensions \
+// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCB-EXT %s
+// CHECK-ZCB-EXT: __riscv_zca 70000{{$}}
+// CHECK-ZCB-EXT: __riscv_zcb 70000{{$}}
+
 // RUN: %clang -target riscv32 -march=rv32izcd0p70 -menable-experimental-extensions \
 // RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCD-EXT %s
 // RUN: %clang -target riscv64 -march=rv64izcd0p70 -menable-experimental-extensions \
 // RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCD-EXT %s
 // CHECK-ZCD-EXT: __riscv_zcd 70000{{$}}
 
 // RUN: %clang -target riscv32 -march=rv32izcf0p70 -menable-experimental-extensions \
 // RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCF-EXT %s
 // CHECK-ZCF-EXT: __riscv_zcf 70000{{$}}

llvm/docs/RISCVUsage.rst

``experimental-zca``
   LLVM implements the `0.70 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/V0.70.1-TOOLCHAIN-DEV>`_.
 
 ``experimental-zcd``
   LLVM implements the `0.70 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/V0.70.1-TOOLCHAIN-DEV>`_.
 
 ``experimental-zcf``
   LLVM implements the `0.70 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/V0.70.1-TOOLCHAIN-DEV>`_.
 
+``experimental-zcb``
+  LLVM implements the `0.70 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/V0.70.1-TOOLCHAIN-DEV>`_.
+
 ``experimental-zihintntl``
   LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220831-bf5a151>`_.
 
 ``experimental-ztso``
   LLVM implements the `v0.1 proposed specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf>`_ (see Chapter 25).  Using will set appropriate ELF flags and attributes, but does not yet change code generation.
 
 ``experimental-zvfh``
   LLVM implements `this draft text <https://github.com/riscv/riscv-v-spec/pull/780>`_.

llvm/docs/ReleaseNotes.rst

 Changes to the PowerPC Backend
 ------------------------------
 
 * ...
 
 Changes to the RISC-V Backend
 -----------------------------
 
+* Assembler support for the Zcb extension was added.
+
 Changes to the WebAssembly Backend
 ----------------------------------
 
 * ...
 
 Changes to the Windows Target
 -----------------------------
 

llvm/lib/Support/RISCVISAInfo.cpp

static const RISCVSupportedExtension SupportedExtensions[] = {
     {"xventanacondops", RISCVExtensionVersion{1, 0}},
     {"xtheadvdot", RISCVExtensionVersion{1, 0}},
 };
 
 static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
     {"zihintntl", RISCVExtensionVersion{0, 2}},
 
     {"zca", RISCVExtensionVersion{0, 70}},
+    {"zcb", RISCVExtensionVersion{0, 70}},
     {"zcd", RISCVExtensionVersion{0, 70}},
     {"zcf", RISCVExtensionVersion{0, 70}},
     {"zvfh", RISCVExtensionVersion{0, 1}},
     {"zawrs", RISCVExtensionVersion{1, 0}},
     {"ztso", RISCVExtensionVersion{0, 1}},
 };
 
 static bool stripExperimentalPrefix(StringRef &Ext) {

 static const char *ImpliedExtsZvl128b[] = {"zvl64b"};
 static const char *ImpliedExtsZvl64b[] = {"zvl32b"};
 static const char *ImpliedExtsZk[] = {"zkn", "zkt", "zkr"};
 static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx",
                                        "zkne", "zknd", "zknh"};
 static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
 static const char *ImpliedExtsZvfh[] = {"zve32f"};
 static const char *ImpliedExtsXTHeadVdot[] = {"v"};
+static const char *ImpliedExtsZcb[] = {"zca"};
 
 struct ImpliedExtsEntry {
   StringLiteral Name;
   ArrayRef<const char *> Exts;
 
   bool operator<(const ImpliedExtsEntry &Other) const {
     return Name < Other.Name;
   }
 
   bool operator<(StringRef Other) const { return Name < Other; }
 };
 
 // Note: The table needs to be sorted by name.
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
     {{"v"}, {ImpliedExtsV}},
     {{"xtheadvdot"}, {ImpliedExtsXTHeadVdot}},
+    {{"zcb"}, {ImpliedExtsZcb}},
     {{"zdinx"}, {ImpliedExtsZdinx}},
     {{"zfh"}, {ImpliedExtsZfh}},
     {{"zfhmin"}, {ImpliedExtsZfhmin}},
     {{"zhinx"}, {ImpliedExtsZhinx}},
     {{"zhinxmin"}, {ImpliedExtsZhinxmin}},
     {{"zk"}, {ImpliedExtsZk}},
     {{"zkn"}, {ImpliedExtsZkn}},
     {{"zks"}, {ImpliedExtsZks}},

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

bool isCLUIImm() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     return IsConstantImm && (Imm != 0) &&
            (isUInt<5>(Imm) || (Imm >= 0xfffe0 && Imm <= 0xfffff)) &&
            VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isUImm2Lsb0() const {
+    if (!isImm())
+      return false;
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && isShiftedUInt<1, 1>(Imm) &&
+           VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
   bool isUImm7Lsb00() const {
     if (!isImm())
       return false;
     int64_t Imm;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     return IsConstantImm && isShiftedUInt<5, 2>(Imm) &&
            VK == RISCVMCExpr::VK_RISCV_None;
if (isRV64())
       return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 6) - 1);
     return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1);
   case Match_InvalidUImmLog2XLenHalf:
     if (isRV64())
       return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1);
   case Match_InvalidUImm2:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 2) - 1);
+  case Match_InvalidUImm2Lsb0:
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 2,
+                                      "immediate must be one of");
   case Match_InvalidUImm3:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 3) - 1);
   case Match_InvalidUImm5:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
   case Match_InvalidUImm7:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 7) - 1);
   case Match_InvalidSImm5:
     return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 4),

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

enum {
   InstFormatCI = 9,
   InstFormatCSS = 10,
   InstFormatCIW = 11,
   InstFormatCL = 12,
   InstFormatCS = 13,
   InstFormatCA = 14,
   InstFormatCB = 15,
   InstFormatCJ = 16,
-  InstFormatOther = 17,
+  InstFormatCSZN = 17,
+  InstFormatOther = 18,
 
   InstFormatMask = 31,
   InstFormatShift = 0,
 
   ConstraintShift = InstFormatShift + 5,
   ConstraintMask = 0b111 << ConstraintShift,
 
   VLMulShift = ConstraintShift + 3,
enum {
   MO_DIRECT_FLAG_MASK = 15
 };
 } // namespace RISCVII
 
 namespace RISCVOp {
 enum OperandType : unsigned {
   OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
   OPERAND_UIMM2 = OPERAND_FIRST_RISCV_IMM,
+  OPERAND_UIMM2_LSB0,
   OPERAND_UIMM3,
   OPERAND_UIMM4,
   OPERAND_UIMM5,
   OPERAND_UIMM7,
   OPERAND_UIMM7_LSB00,
   OPERAND_UIMM8_LSB00,
   OPERAND_UIMM8_LSB000,
   OPERAND_UIMM12,

llvm/lib/Target/RISCV/RISCVFeatures.td

 
 def HasStdExtCOrZca
     : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZca()">,
                 AssemblerPredicate<(any_of FeatureStdExtC, FeatureExtZca),
                                    "'C' (Compressed Instructions) or "
                                    "'Zca' (part of the C extension, excluding "
                                    "compressed floating point loads/stores)">;
 
+def FeatureExtZcb
+    : SubtargetFeature<"experimental-zcb", "HasStdExtZcb", "true",
+                       "'Zcb' (Compressed basic bit manipulation instructions)",
+                       [FeatureExtZca]>;
+def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
+                             AssemblerPredicate<(all_of FeatureExtZcb),
+                             "'Zcb' (Compressed basic bit manipulation instructions)">;
+
 def FeatureExtZcd
     : SubtargetFeature<"experimental-zcd", "HasStdExtZcd", "true",
                        "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
 
 def HasStdExtCOrZcd
     : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcd()">,
                 AssemblerPredicate<(any_of FeatureStdExtC, FeatureExtZcd),
                                    "'C' (Compressed Instructions) or "

llvm/lib/Target/RISCV/RISCVInstrFormats.td

 def InstFormatCI     : InstFormat<9>;
 def InstFormatCSS    : InstFormat<10>;
 def InstFormatCIW    : InstFormat<11>;
 def InstFormatCL     : InstFormat<12>;
 def InstFormatCS     : InstFormat<13>;
 def InstFormatCA     : InstFormat<14>;
 def InstFormatCB     : InstFormat<15>;
 def InstFormatCJ     : InstFormat<16>;
-def InstFormatOther  : InstFormat<17>;
+def InstFormatCSZN   : InstFormat<17>;
+def InstFormatOther  : InstFormat<18>;
 
 class RISCVVConstraint<bits<3> val> {
   bits<3> Value = val;
 }
 def NoConstraint  : RISCVVConstraint<0b000>;
 def VS2Constraint : RISCVVConstraint<0b001>;
 def VS1Constraint : RISCVVConstraint<0b010>;
 def VMConstraint  : RISCVVConstraint<0b100>;

llvm/lib/Target/RISCV/RISCVInstrFormatsC.td

class RVInst16CJ<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
   let Inst{10-9} = offset{8-7};
   let Inst{8} = offset{9};
   let Inst{7} = offset{5};
   let Inst{6} = offset{6};
   let Inst{5-3} = offset{2-0};
   let Inst{2} = offset{4};
   let Inst{1-0} = opcode;
 }
+
+class RVInst16CSZN<bits<6> funct6, bits<5> funct5, bits<2> opcode, dag outs,
+                   dag ins, string opcodestr, string argstr>
+    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSZN>{
+  bits<3> rd;
+
+  let Inst{15-10} = funct6;
+  let Inst{9-7} = rd;
+  let Inst{6-2} = funct5;
+  let Inst{1-0} = opcode;
+}

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

#define CASE_OPERAND_UIMM(NUM)                                                 \
   case RISCVOp::OPERAND_UIMM##NUM:                                             \
     Ok = isUInt<NUM>(Imm);                                                     \
     break;
         CASE_OPERAND_UIMM(2)
         CASE_OPERAND_UIMM(3)
         CASE_OPERAND_UIMM(4)
         CASE_OPERAND_UIMM(5)
         CASE_OPERAND_UIMM(7)
+        CASE_OPERAND_UIMM(12)
+        CASE_OPERAND_UIMM(20)
+          // clang-format on
+        case RISCVOp::OPERAND_UIMM2_LSB0:
+          Ok = isShiftedUInt<1, 1>(Imm);
+          break;
         case RISCVOp::OPERAND_UIMM7_LSB00:
           Ok = isShiftedUInt<5, 2>(Imm);
           break;
         case RISCVOp::OPERAND_UIMM8_LSB00:
           Ok = isShiftedUInt<6, 2>(Imm);
           break;
         case RISCVOp::OPERAND_UIMM8_LSB000:
           Ok = isShiftedUInt<5, 3>(Imm);
           break;
-        CASE_OPERAND_UIMM(12)
-        CASE_OPERAND_UIMM(20)
-          // clang-format on
         case RISCVOp::OPERAND_SIMM10_LSB0000_NONZERO:
           Ok = isShiftedInt<6, 4>(Imm) && (Imm != 0);
           break;
         case RISCVOp::OPERAND_ZERO:
           Ok = Imm == 0;
           break;
         case RISCVOp::OPERAND_SIMM5:
           Ok = isInt<5>(Imm);

llvm/lib/Target/RISCV/RISCVInstrInfo.td

let MCOperandPredicate = [{
     if (STI.getTargetTriple().isArch64Bit())
       return isUInt<6>(Imm);
     return isUInt<5>(Imm);
   }];
   let OperandType = "OPERAND_UIMMLOG2XLEN";
   let OperandNamespace = "RISCVOp";
 }
 
-def uimm2 : Operand<XLenVT> {
+def uimm2 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]> {
   let ParserMatchClass = UImmAsmOperand<2>;
   let DecoderMethod = "decodeUImmOperand<2>";
   let OperandType = "OPERAND_UIMM2";
   let OperandNamespace = "RISCVOp";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+    return isUInt<2>(Imm);
+  }];
 }
 
 def uimm3 : Operand<XLenVT> {
   let ParserMatchClass = UImmAsmOperand<3>;
   let DecoderMethod = "decodeUImmOperand<3>";
   let OperandType = "OPERAND_UIMM3";
   let OperandNamespace = "RISCVOp";
 }

 //===----------------------------------------------------------------------===//
 
 include "RISCVInstrInfoM.td"
 include "RISCVInstrInfoA.td"
 include "RISCVInstrInfoF.td"
 include "RISCVInstrInfoD.td"
 include "RISCVInstrInfoC.td"
 include "RISCVInstrInfoZb.td"
+include "RISCVInstrInfoZc.td"
 include "RISCVInstrInfoZk.td"
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZfh.td"
 include "RISCVInstrInfoZicbo.td"
 
 //===----------------------------------------------------------------------===//
 // Vendor extensions
 //===----------------------------------------------------------------------===//
 
 include "RISCVInstrInfoXVentana.td"
 include "RISCVInstrInfoXTHead.td"

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

+//===-- RISCVInstrInfoZc.td - RISC-V 'Zc*' instructions ----*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// This file describes the RISC-V instructions from the 'Zc*' compressed
+/// instruction extensions, version 0.70.4.
+/// This version is still experimental as the 'Zc*' extensions haven't been
+/// ratified yet.
+///
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def uimm2_lsb0 : Operand<XLenVT>,
+                 ImmLeaf<XLenVT, [{return isShiftedUInt<1, 1>(Imm);}]> {
+  let ParserMatchClass = UImmAsmOperand<2, "Lsb0">;
+  let EncoderMethod = "getImmOpValue";
+  let DecoderMethod = "decodeUImmOperand<2>";
+  let OperandType = "OPERAND_UIMM2_LSB0";
+  let OperandNamespace = "RISCVOp";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+    return isShiftedUInt<1, 1>(Imm);
+  }];
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction Class Templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVZcArith_r<bits<5> funct5, string OpcodeStr> :
+  RVInst16CSZN<0b100111, funct5, 0b01, (outs GPRC:$rd_wb), (ins GPRC:$rd),
+               OpcodeStr, "$rd"> {
+  let Constraints = "$rd = $rd_wb";
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64] in
+def C_ZEXT_W  : RVZcArith_r<0b11100 , "c.zext.w">,
+                Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
+
+let Predicates = [HasStdExtZcb, HasStdExtZbb] in {
+def C_ZEXT_H  : RVZcArith_r<0b11010 , "c.zext.h">,
+                Sched<[WriteIALU, ReadIALU]>;
+def C_SEXT_B  : RVZcArith_r<0b11001 , "c.sext.b">,
+                Sched<[WriteIALU, ReadIALU]>;
+def C_SEXT_H  : RVZcArith_r<0b11011 , "c.sext.h">,
+                Sched<[WriteIALU, ReadIALU]>;
+}
+
+let Predicates = [HasStdExtZcb] in
+def C_ZEXT_B  : RVZcArith_r<0b11000 , "c.zext.b">,
+                Sched<[WriteIALU, ReadIALU]>;
+
+let Predicates = [HasStdExtZcb, HasStdExtMOrZmmul] in
+def C_MUL     : CA_ALU<0b100111, 0b10, "c.mul", GPRC>,
+                Sched<[WriteIMul, ReadIMul, ReadIMul]>;
+
+let Predicates = [HasStdExtZcb] in {
+def C_NOT : RVZcArith_r<0b11101 , "c.not">,
+            Sched<[WriteIALU, ReadIALU]>;
+
+def C_LBU : CLoad_ri<0b100, "c.lbu", GPRC, uimm2>,
+            Sched<[WriteLDB, ReadMemBase]> {
+  bits<2> imm;
+
+  let Inst{12-10} = 0b000;
+  let Inst{6-5} = imm{0,1};
+}
+
+def C_LHU : CLoad_ri<0b100, "c.lhu", GPRC, uimm2_lsb0>,
+            Sched<[WriteLDH, ReadMemBase]> {
+  bits<2> imm;
+
+  let Inst{12-10} = 0b001;
+  let Inst{6} = 0b0;
+  let Inst{5} = imm{1};
+}
+
+def C_LH  : CLoad_ri<0b100, "c.lh", GPRC, uimm2_lsb0>,
+            Sched<[WriteLDH, ReadMemBase]> {
+  bits<2> imm;
+
+  let Inst{12-10} = 0b001;
+  let Inst{6} = 0b1;
+  let Inst{5} = imm{1};
+}
+
+def C_SB : CStore_rri<0b100, "c.sb", GPRC, uimm2>,
+           Sched<[WriteSTB, ReadStoreData, ReadMemBase]> {
+  bits<2> imm;
+
+  let Inst{12-10} = 0b010;
+  let Inst{6-5} = imm{0,1};
+}
+
+def C_SH : CStore_rri<0b100, "c.sh", GPRC, uimm2_lsb0>, 
+           Sched<[WriteSTH, ReadStoreData, ReadMemBase]> {
+  bits<2> imm;
+
+  let Inst{12-10} = 0b011;
+  let Inst{6} = 0b1;
+  let Inst{5} = imm{1};
+}
+}
+
+let Predicates = [HasStdExtZcb, HasStdExtMOrZmmul] in{
+def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
+                  (C_MUL GPRC:$rs1, GPRC:$rs2)>;
+let isCompressOnly = true in
+def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
+                  (C_MUL GPRC:$rs1, GPRC:$rs2)>;
+} // Predicates = [HasStdExtZcb, HasStdExtMOrZmmul]
+
+let Predicates = [HasStdExtZcb, HasStdExtZbb] in{
+def : CompressPat<(SEXT_B GPRC:$rs1, GPRC:$rs1),
+                  (C_SEXT_B GPRC:$rs1, GPRC:$rs1)>;
+def : CompressPat<(SEXT_H GPRC:$rs1, GPRC:$rs1),
+                  (C_SEXT_H GPRC:$rs1, GPRC:$rs1)>;
+} // Predicates = [HasStdExtZcb, HasStdExtZbb]
+
+let Predicates = [HasStdExtZcb, HasStdExtZbb] in{
+def : CompressPat<(ZEXT_H_RV32 GPRC:$rs1, GPRC:$rs1),
+                  (C_ZEXT_H GPRC:$rs1, GPRC:$rs1)>;
+def : CompressPat<(ZEXT_H_RV64 GPRC:$rs1, GPRC:$rs1),
+                  (C_ZEXT_H GPRC:$rs1, GPRC:$rs1)>;
+} // Predicates = [HasStdExtZcb, HasStdExtZbb]
+
+let Predicates = [HasStdExtZcb] in{
+def : CompressPat<(ANDI GPRC:$rs1, GPRC:$rs1, 255),
+                  (C_ZEXT_B GPRC:$rs1, GPRC:$rs1)>;
+} // Predicates = [HasStdExtZcb]
+
+let Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64] in{
+def : CompressPat<(ADD_UW GPRC:$rs1, GPRC:$rs1, X0),
+                  (C_ZEXT_W GPRC:$rs1, GPRC:$rs1)>;
+} // Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64]
+
+let Predicates = [HasStdExtZcb] in{
+def : CompressPat<(XORI GPRC:$rs1, GPRC:$rs1, -1),
+                  (C_NOT GPRC:$rs1, GPRC:$rs1)>;
+}
+
+let Predicates = [HasStdExtZcb] in{
+def : CompressPat<(LBU GPRC:$rd, GPRCMem:$rs1, uimm2:$imm),
+                  (C_LBU GPRC:$rd, GPRCMem:$rs1, uimm2:$imm)>;
+def : CompressPat<(LHU GPRC:$rd, GPRCMem:$rs1, uimm2_lsb0:$imm),
+                  (C_LHU GPRC:$rd, GPRCMem:$rs1, uimm2_lsb0:$imm)>;
+def : CompressPat<(LH GPRC:$rd, GPRCMem:$rs1, uimm2_lsb0:$imm),
+                  (C_LH GPRC:$rd, GPRCMem:$rs1, uimm2_lsb0:$imm)>;
+def : CompressPat<(SB GPRC:$rs2, GPRCMem:$rs1, uimm2:$imm),
+                  (C_SB GPRC:$rs2, GPRCMem:$rs1, uimm2:$imm)>;
+def : CompressPat<(SH GPRC:$rs2, GPRCMem:$rs1, uimm2_lsb0:$imm),
+                  (C_SH GPRC:$rs2, GPRCMem:$rs1, uimm2_lsb0:$imm)>;
+}// Predicates = [HasStdExtZcb]
+
+
+//===----------------------------------------------------------------------===//
+// Pseudo Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZcb] in {
+def : InstAlias<"c.lbu $rd, (${rs1})",(C_LBU GPRC:$rd, GPRC:$rs1, 0)>;
+def : InstAlias<"c.lhu $rd, (${rs1})",(C_LHU GPRC:$rd, GPRC:$rs1, 0)>;
+def : InstAlias<"c.lh $rd, (${rs1})", (C_LH GPRC:$rd, GPRC:$rs1, 0)>;
+def : InstAlias<"c.sb $rd, (${rs1})", (C_SB GPRC:$rd, GPRC:$rs1, 0)>;
+def : InstAlias<"c.sh $rd, (${rs1})", (C_SH GPRC:$rd, GPRC:$rs1, 0)>;
+}

llvm/test/CodeGen/RISCV/attributes.ll

 ; RUN: llc -mtriple=riscv32 -mattr=+zbkb,+zbkc,+zbkx,+zksed,+zksh %s -o - | FileCheck --check-prefix=RV32COMBINEINTOZKS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV32ZICBOM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV32ZICBOP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV32SVNAPOT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefix=RV32SVPBMT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV32SVINVAL %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV32ZCA %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefix=RV32ZCB %s
 
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefix=RV64MZMMUL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s
 ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s

 ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svpbmt %s -o - | FileCheck --check-prefix=RV64SVPBMT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefix=RV64XVENTANACONDOPS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefix=RV64XTHEADVDOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV64ZCA %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefix=RV64ZCB %s
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
 ; RV32ZMMUL: .attribute 5, "rv32i2p0_zmmul1p0"
 ; RV32MZMMUL: .attribute 5, "rv32i2p0_m2p0_zmmul1p0"
 ; RV32A: .attribute 5, "rv32i2p0_a2p0"
 ; RV32F: .attribute 5, "rv32i2p0_f2p0"
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"

 ; RV32COMBINEINTOZKS: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
 ; RV32ZICBOM: .attribute 5, "rv32i2p0_zicbom1p0"
 ; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
 ; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0"
 ; RV32SVPBMT: .attribute 5, "rv32i2p0_svpbmt1p0"
 ; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
 ; RV32ZCA: .attribute 5, "rv32i2p0_zca0p70"
+; RV32ZCB: .attribute 5, "rv32i2p0_zca0p70_zcb0p70"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
 ; RV64MZMMUL: .attribute 5, "rv64i2p0_m2p0_zmmul1p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
 ; RV64F: .attribute 5, "rv64i2p0_f2p0"
 ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
 ; RV64C: .attribute 5, "rv64i2p0_c2p0"

 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
 ; RV64SVPBMT: .attribute 5, "rv64i2p0_svpbmt1p0"
 ; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
 ; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
 ; RV64XTHEADVDOT: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 ; RV64ZCA: .attribute 5, "rv64i2p0_zca0p70"
+; RV64ZCB: .attribute 5, "rv64i2p0_zca0p70_zcb0p70"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
   ret i32 %1
 }

llvm/test/MC/RISCV/attribute-arch.s

 # CHECK: attribute      5, "rv32i2p0_c2p0_zihintntl0p2"
 
 .attribute arch, "rv32if_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
 # CHECK: attribute      5, "rv32i2p0_f2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
 
 .attribute arch, "rv32izca0p70"
 # CHECK: attribute      5, "rv32i2p0_zca0p70"
 
+.attribute arch, "rv32izcb0p70"
+# CHECK: attribute      5, "rv32i2p0_zca0p70_zcb0p70"
+
 .attribute arch, "rv32izawrs1p0"
 # CHECK: attribute      5, "rv32i2p0_zawrs1p0"
 
 .attribute arch, "rv32iztso0p1"
 # CHECK: attribute      5, "rv32i2p0_ztso0p1"

llvm/test/MC/RISCV/rv32zcb-invalid.s

+# RUN: not llvm-mc -triple=riscv32 -mattr=experimental-zcb -riscv-no-aliases -show-encoding %s 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-ERROR %s
+# RUN: not llvm-mc -triple=riscv64 -mattr=experimental-zcb -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-ERROR %s
+
+# CHECK-ERROR: error: immediate must be an integer in the range [0, 3]
+c.lbu a5, 10(a4)
+
+# CHECK-ERROR: error: immediate must be one of [0, 2]
+c.lhu a5, 10(a4)
+
+# CHECK-ERROR: error: immediate must be one of [0, 2]
+c.lh a5, 10(a4)
+
+# CHECK-ERROR: error: immediate must be an integer in the range [0, 3]
+c.sb a5, 10(a4)
+
+# CHECK-ERROR: error: immediate must be one of [0, 2]
+c.sh a5, 10(a4)

llvm/test/MC/RISCV/rv32zcb-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+m,+zbb,+zba,+experimental-zcb -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+m,+zbb,+zba,+experimental-zcb < %s \
+# RUN:     | llvm-objdump --mattr=+m,+zbb,+zba,+experimental-zcb -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+m,+zbb,+zba,+experimental-zcb -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+m,+zbb,+zba,+experimental-zcb < %s \
+# RUN:     | llvm-objdump --mattr=+m,+zbb,+zba,experimental-zcb -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 \
+# RUN:     -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 \
+# RUN:     -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: c.zext.b s0
+# CHECK-ASM: encoding: [0x61,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.zext.b s0
+
+# CHECK-ASM-AND-OBJ: c.sext.b s0
+# CHECK-ASM: encoding: [0x65,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation), 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.sext.b s0
+
+# CHECK-ASM-AND-OBJ: c.zext.h s0
+# CHECK-ASM: encoding: [0x69,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation), 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.zext.h s0
+
+# CHECK-ASM-AND-OBJ: c.sext.h s0
+# CHECK-ASM: encoding: [0x6d,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation), 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.sext.h s0
+
+# CHECK-ASM-AND-OBJ: c.not s0
+# CHECK-ASM: encoding: [0x75,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.not s0
+
+# CHECK-ASM-AND-OBJ: c.mul s0, s1
+# CHECK-ASM: encoding: [0x45,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'M' (Integer Multiplication and Division) or 'Zmmul' (Integer Multiplication), 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.mul s0, s1
+
+# CHECK-ASM-AND-OBJ: c.lbu a5, 2(a4)
+# CHECK-ASM: encoding: [0x3c,0x83]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.lbu a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.lhu a5, 2(a4)
+# CHECK-ASM: encoding: [0x3c,0x87]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.lhu a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.lh a5, 2(a4)
+# CHECK-ASM: encoding: [0x7c,0x87]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.lh a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.sb a5, 2(a4)
+# CHECK-ASM: encoding: [0x3c,0x8b]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.sb a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.sh a5, 2(a4)
+# CHECK-ASM: encoding: [0x7c,0x8f]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.sh a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.mul s0, s1
+# CHECK-ASM: encoding: [0x45,0x9c]
+mul s0, s1, s0
+
+# CHECK-ASM-AND-OBJ: c.mul s0, s1
+# CHECK-ASM: encoding: [0x45,0x9c]
+mul s0, s0, s1
+
+# CHECK-ASM-AND-OBJ: c.sext.b s0
+# CHECK-ASM: encoding: [0x65,0x9c]
+sext.b s0, s0
+
+# CHECK-ASM-AND-OBJ: c.sext.h s0
+# CHECK-ASM: encoding: [0x6d,0x9c]
+sext.h s0, s0
+
+# CHECK-ASM-AND-OBJ: c.zext.h s0
+# CHECK-ASM: encoding: [0x69,0x9c]
+zext.h s0, s0
+
+# CHECK-ASM-AND-OBJ: c.zext.b s0
+# CHECK-ASM: encoding: [0x61,0x9c]
+andi s0, s0, 255
+
+# CHECK-ASM-AND-OBJ: c.not s0
+# CHECK-ASM: encoding: [0x75,0x9c]
+xori s0, s0, -1
+
+# CHECK-ASM-AND-OBJ: c.lh a5, 2(a4)
+# CHECK-ASM: encoding: [0x7c,0x87]
+lh a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.lbu a5, 2(a4)
+# CHECK-ASM: encoding: [0x3c,0x83]
+lbu a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.lhu a5, 2(a4)
+# CHECK-ASM: encoding: [0x3c,0x87]
+lhu a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.sb a5, 2(a4)
+# CHECK-ASM: encoding: [0x3c,0x8b]
+sb a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.sh a5, 2(a4)
+# CHECK-ASM: encoding: [0x7c,0x8f]
+sh a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.lbu s0, 0(s1)
+# CHECK-ASM: encoding: [0x80,0x80]
+c.lbu s0, (s1)
+
+# CHECK-ASM-AND-OBJ: c.lhu s0, 0(s1)
+# CHECK-ASM: encoding: [0x80,0x84]
+c.lhu s0, (s1)
+
+# CHECK-ASM-AND-OBJ: c.lh s0, 0(s1)
+# CHECK-ASM: encoding: [0xc0,0x84]
+c.lh s0, (s1)
+
+# CHECK-ASM-AND-OBJ: c.sb s0, 0(s1)
+# CHECK-ASM: encoding: [0x80,0x88]
+c.sb s0, (s1)
+
+# CHECK-ASM-AND-OBJ: c.sh s0, 0(s1)
+# CHECK-ASM: encoding: [0xc0,0x8c]
+c.sh s0, (s1)

llvm/test/MC/RISCV/rv64zcb-valid.s

+# RUN: llvm-mc %s -triple=riscv64 -mattr=+m,+zbb,+zba,+experimental-zcb -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+m,+zbb,+zba,+experimental-zcb < %s \
+# RUN:     | llvm-objdump --mattr=+m,+zbb,+zba,experimental-zcb -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv64 \
+# RUN:     -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+m,+zbb,+zba,+experimental-zcb \
+# RUN:     -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-NO-RV64 %s
+
+# CHECK-ASM-AND-OBJ: c.zext.w s0
+# CHECK-ASM: encoding: [0x71,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zba' (Address Generation Instructions), 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+c.zext.w s0
+
+# CHECK-ASM-AND-OBJ: c.zext.w s0
+# CHECK-ASM: encoding: [0x71,0x9c]
+add.uw s0, s0, zero