[X86] Add RDPRU instruction

[probinson]

Summary

Add support for the RDPRU instruction on Zen2 processors.

User-facing features:

• Clang option -m[no-]rdpru to enable/disable the feature
• Support is implicit for znver2/znver3 processors
• Preprocessor symbol RDPRU to indicate support
• Header rdpruintrin.h to define intrinsics
• "rdpru" mnemonic supported for assembler code

Internal features:

• Clang builtin __builtin_ia32_rdpru
• IR intrinsic @llvm.x86.rdpru

[probinson]

If this patch is too big, I'm happy to break it into two (LLVM/Clang) or 4 (piecemeal features) parts.

Two questions:

• Should the clang builtin be in BuiltinsX86_64.td instead of BuiltinsX86.td? It's supported only by Zen.
• I didn't need to add a case for this in CGBuiltin.cpp, which was surprising; just adding the entry to BuiltinsX86.def was enough to automatically lower the Clang builtin to the IR intrinsic. Does that auto-magic mean there are cases that could be removed from CGBuiltin.cpp?

[probinson]

Oh, third question: We invented a new header for this. If gcc or somebody has added different intrinsics, or a different header, or whatever, let me know and I'm happy to adjust.

[craig.topper]

In D128934#3623182, @probinson wrote:

If this patch is too big, I'm happy to break it into two (LLVM/Clang) or 4 (piecemeal features) parts.

Two questions:

• Should the clang builtin be in BuiltinsX86_64.td instead of BuiltinsX86.td? It's supported only by Zen.

BuiltinsX86_64.def generates a check that the triple is x86_64 and not i386/i686. It doesn't look like this instruction is 64-bit mode only so BuiltinsX86.def is the right place

• I didn't need to add a case for this in CGBuiltin.cpp, which was surprising; just adding the entry to BuiltinsX86.def was enough to automatically lower the Clang builtin to the IR intrinsic. Does that auto-magic mean there are cases that could be removed from CGBuiltin.cpp?

The ClangBuiltin in IntrinsicsX86.td sets this up. All X86 code in CGBuiltin.cpp should be for builtins that don't appear in ClangBuiltin because they require some special handling.

[craig.topper]

llvm/lib/Target/X86/X86InstrSystem.td

742

I think TB here should be PS. Per table "Table A-8. Opcode 01h ModRM Extensions", the instruction is not valid with a 0xF2 or 0xF3 prefix. PS is our marker for that.

llvm/test/CodeGen/X86/rdpru.ll

3

Add i686 command lines to test the ReplaceNodeResults code.

llvm/test/MC/X86/x86-64.s

1581 ↗

(On Diff #441474)

Please add a disassembler test too.

[RKSimon]

For reference the instruction is documented here: https://www.amd.com/system/files/TechDocs/24594.pdf (AMD64 APM Volume 3: General Purpose and System Instructions)

[RKSimon]

We definitely need to add i686 codegen test coverage (clang, llvm ir + mc) - as the instruction returns the timer values in EDX:EAX and we need to confirm that this is handled correctly

[probinson]

Address review comments. Encode/decode test moved into its own file.

[probinson]

i686 tests added, but I have to leave it to the subject-matter experts whether they are correct.

llvm/lib/Target/X86/X86InstrSystem.td

742

Done, but is there a way I should be testing this?

[craig.topper]

32-bit codegen looks ok. 64-bit values are returned in edx:eax like the instruction.

llvm/lib/Target/X86/X86InstrSystem.td

742

You'd need to make sure it didn't disassemble with 0xf2 or 0xf3 before the regular instruction, but we're pretty lax on testing those cases for other instructions so it's not a big deal.

[RKSimon]

Please can you add a disassembler test?

Other than that - does anyone have any further comments?

llvm/test/CodeGen/X86/rdpru.ll

6

Worth adding -mcpu=znver2/znver3 tests?

[pengfei]

1. Update ReleaseNotes;
2. Update clang/lib/Headers/cpuid.h and llvm/lib/Support/Host.cpp if there's a new bit for it;
3. Add macro test in clang/test/Preprocessor/x86_target_features.c

clang/lib/Headers/rdpruintrin.h

25

Conflicted with line 11. Use x86intrin.h instead. The same below.

[probinson]

Add __RDPRU__ test, release note, fix doc for intrinsics.

[probinson]

In D128934#3629653, @pengfei wrote:

1. Update ReleaseNotes;

Done, thanks for the reminder!

2. Update clang/lib/Headers/cpuid.h and llvm/lib/Support/Host.cpp if there's a new bit for it;

Not done; I had considered this, but the bit lives in a CPUID leaf that is not currently supported at all by the header or Host.cpp. I'm willing to add RDPRU, with FIXMEs for the other feature bits, if people want it.

3. Add macro test in clang/test/Preprocessor/x86_target_features.c

Done. For some reason I thought the clang intrinsic test would verify this, but actually it doesn't.

[probinson]

In D128934#3629404, @RKSimon wrote:

Please can you add a disassembler test?

Isn't that what test/MC/X86/RDPRU.s does (via llvm-objdump)? If "disassembler test" means something else, please point to an example.

[probinson]

Add znver2/znver3 cases to rdpru.ll test

[RKSimon]

In D128934#3630807, @probinson wrote:

In D128934#3629404, @RKSimon wrote:

Please can you add a disassembler test?

Isn't that what test/MC/X86/RDPRU.s does (via llvm-objdump)? If "disassembler test" means something else, please point to an example.

https://github.com/llvm/llvm-project/tree/main/llvm/test/MC/Disassembler/X86 - they're kept inside the MC section, but its the "reverse lookup" disasm tests

[probinson]

Add MC/Disassembler/X86 tests

[probinson]

@RKSimon is this what you meant?

[RKSimon]

Yes - thank you!

@pengfei any more comments?

[pengfei]

LGTM.

llvm/docs/ReleaseNotes.rst

166–167

Nit: It's no ideal to put Clang info here. Maybe move it to Clang's Release Notes?

[probinson]

llvm/docs/ReleaseNotes.rst

166–167

Will do.

[probinson]

In D128934#3630800, @probinson wrote:

In D128934#3629653, @pengfei wrote:

2. Update clang/lib/Headers/cpuid.h and llvm/lib/Support/Host.cpp if there's a new bit for it;

Not done; I had considered this, but the bit lives in a CPUID leaf that is not currently supported at all by the header or Host.cpp. I'm willing to add RDPRU, with FIXMEs for the other feature bits, if people want it.

@RKSimon pointed out to me that I was mistaken about this. Not sure how I missed it... I'm about to go on holiday so he is authorized to clean up my mess.

clang/docs/ReleaseNotes.rst

 X86 Support in Clang
 --------------------
 
 - Support ``-mharden-sls=[none|all|return|indirect-jmp]`` for straight-line
   speculation hardening.
 - Support for the ``_Float16`` type has been added for all targets with SSE2.
   When AVX512-FP16 is not available, arithmetic on ``_Float16`` is emulated
   using ``float``.
+- Added the ``-m[no-]rdpru`` flag to enable/disable the RDPRU instruction
+  provided by AMD Zen2 and later processors. Defined intrinsics for using
+  this instruction (see rdpruintrin.h).
 
 DWARF Support in Clang
 ----------------------
 
 - clang now adds DWARF information for inline strings in C/C++ programs,
   allowing ``line:column`` symbolization of strings. Some debugging programs may
   require updating, as this takes advantage of DWARF ``DW_TAG_variable``
   structures *without* a ``DW_AT_name`` field, which is valid DWARF, but may be

clang/include/clang/Basic/BuiltinsX86.def

 TARGET_BUILTIN(__builtin_ia32_xtest, "i", "n", "rtm")
 
 BUILTIN(__builtin_ia32_rdpmc, "UOii", "")
 BUILTIN(__builtin_ia32_rdtsc, "UOi", "")
 BUILTIN(__rdtsc, "UOi", "")
 BUILTIN(__builtin_ia32_rdtscp, "UOiUi*", "")
 
 TARGET_BUILTIN(__builtin_ia32_rdpid, "Ui", "n", "rdpid")
+TARGET_BUILTIN(__builtin_ia32_rdpru, "ULLii", "n", "rdpru")
 
 // PKU
 TARGET_BUILTIN(__builtin_ia32_rdpkru, "Ui", "n", "pku")
 TARGET_BUILTIN(__builtin_ia32_wrpkru, "vUi", "n", "pku")
 
 // AVX-512
 TARGET_BUILTIN(__builtin_ia32_sqrtpd512, "V8dV8dIi", "ncV:512:", "avx512f")
 TARGET_BUILTIN(__builtin_ia32_sqrtps512, "V16fV16fIi", "ncV:512:", "avx512f")

clang/include/clang/Driver/Options.td

 def mprefetchwt1 : Flag<["-"], "mprefetchwt1">, Group<m_x86_Features_Group>;
 def mno_prefetchwt1 : Flag<["-"], "mno-prefetchwt1">, Group<m_x86_Features_Group>;
 def mprfchw : Flag<["-"], "mprfchw">, Group<m_x86_Features_Group>;
 def mno_prfchw : Flag<["-"], "mno-prfchw">, Group<m_x86_Features_Group>;
 def mptwrite : Flag<["-"], "mptwrite">, Group<m_x86_Features_Group>;
 def mno_ptwrite : Flag<["-"], "mno-ptwrite">, Group<m_x86_Features_Group>;
 def mrdpid : Flag<["-"], "mrdpid">, Group<m_x86_Features_Group>;
 def mno_rdpid : Flag<["-"], "mno-rdpid">, Group<m_x86_Features_Group>;
+def mrdpru : Flag<["-"], "mrdpru">, Group<m_x86_Features_Group>;
+def mno_rdpru : Flag<["-"], "mno-rdpru">, Group<m_x86_Features_Group>;
 def mrdrnd : Flag<["-"], "mrdrnd">, Group<m_x86_Features_Group>;
 def mno_rdrnd : Flag<["-"], "mno-rdrnd">, Group<m_x86_Features_Group>;
 def mrtm : Flag<["-"], "mrtm">, Group<m_x86_Features_Group>;
 def mno_rtm : Flag<["-"], "mno-rtm">, Group<m_x86_Features_Group>;
 def mrdseed : Flag<["-"], "mrdseed">, Group<m_x86_Features_Group>;
 def mno_rdseed : Flag<["-"], "mno-rdseed">, Group<m_x86_Features_Group>;
 def msahf : Flag<["-"], "msahf">, Group<m_x86_Features_Group>;
 def mno_sahf : Flag<["-"], "mno-sahf">, Group<m_x86_Features_Group>;

clang/lib/Basic/Targets/X86.h

class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
   bool HasCLDEMOTE = false;
   bool HasPCONFIG = false;
   bool HasPKU = false;
   bool HasCLFLUSHOPT = false;
   bool HasCLWB = false;
   bool HasMOVBE = false;
   bool HasPREFETCHWT1 = false;
   bool HasRDPID = false;
+  bool HasRDPRU = false;
   bool HasRetpolineExternalThunk = false;
   bool HasLAHFSAHF = false;
   bool HasWBNOINVD = false;
   bool HasWAITPKG = false;
   bool HasMOVDIRI = false;
   bool HasMOVDIR64B = false;
   bool HasPTWRITE = false;
   bool HasINVPCID = false;

clang/lib/Basic/Targets/X86.cpp

for (const auto &Feature : Features) {
     } else if (Feature == "+prefetchwt1") {
       HasPREFETCHWT1 = true;
     } else if (Feature == "+clzero") {
       HasCLZERO = true;
     } else if (Feature == "+cldemote") {
       HasCLDEMOTE = true;
     } else if (Feature == "+rdpid") {
       HasRDPID = true;
+    } else if (Feature == "+rdpru") {
+      HasRDPRU = true;
     } else if (Feature == "+kl") {
       HasKL = true;
     } else if (Feature == "+widekl") {
       HasWIDEKL = true;
     } else if (Feature == "+retpoline-external-thunk") {
       HasRetpolineExternalThunk = true;
     } else if (Feature == "+sahf") {
       HasLAHFSAHF = true;
void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
   if (HasCLZERO)
     Builder.defineMacro("__CLZERO__");
   if (HasKL)
     Builder.defineMacro("__KL__");
   if (HasWIDEKL)
     Builder.defineMacro("__WIDEKL__");
   if (HasRDPID)
     Builder.defineMacro("__RDPID__");
+  if (HasRDPRU)
+    Builder.defineMacro("__RDPRU__");
   if (HasCLDEMOTE)
     Builder.defineMacro("__CLDEMOTE__");
   if (HasWAITPKG)
     Builder.defineMacro("__WAITPKG__");
   if (HasMOVDIRI)
     Builder.defineMacro("__MOVDIRI__");
   if (HasMOVDIR64B)
     Builder.defineMacro("__MOVDIR64B__");
return llvm::StringSwitch<bool>(Name)
       .Case("pclmul", true)
       .Case("pconfig", true)
       .Case("pku", true)
       .Case("popcnt", true)
       .Case("prefetchwt1", true)
       .Case("prfchw", true)
       .Case("ptwrite", true)
       .Case("rdpid", true)
+      .Case("rdpru", true)
       .Case("rdrnd", true)
       .Case("rdseed", true)
       .Case("rtm", true)
       .Case("sahf", true)
       .Case("serialize", true)
       .Case("sgx", true)
       .Case("sha", true)
       .Case("shstk", true)
return llvm::StringSwitch<bool>(Feature)
       .Case("pclmul", HasPCLMUL)
       .Case("pconfig", HasPCONFIG)
       .Case("pku", HasPKU)
       .Case("popcnt", HasPOPCNT)
       .Case("prefetchwt1", HasPREFETCHWT1)
       .Case("prfchw", HasPRFCHW)
       .Case("ptwrite", HasPTWRITE)
       .Case("rdpid", HasRDPID)
+      .Case("rdpru", HasRDPRU)
       .Case("rdrnd", HasRDRND)
       .Case("rdseed", HasRDSEED)
       .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
       .Case("rtm", HasRTM)
       .Case("sahf", HasLAHFSAHF)
       .Case("serialize", HasSERIALIZE)
       .Case("sgx", HasSGX)
       .Case("sha", HasSHA)

clang/lib/Headers/CMakeLists.txt

# Intrinsics
   mwaitxintrin.h
   nmmintrin.h
   pconfigintrin.h
   pkuintrin.h
   pmmintrin.h
   popcntintrin.h
   prfchwintrin.h
   ptwriteintrin.h
+  rdpruintrin.h
   rdseedintrin.h
   rtmintrin.h
   serializeintrin.h
   sgxintrin.h
   shaintrin.h
   smmintrin.h
   tbmintrin.h
   tmmintrin.h

clang/lib/Headers/rdpruintrin.h

+/*===---- rdpruintrin.h - RDPRU intrinsics ---------------------------------===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===-----------------------------------------------------------------------===
+ */
+
+#if !defined __X86INTRIN_H
+#error "Never use <rdpruintrin.h> directly; include <x86intrin.h> instead."
+#endif
+
+#ifndef __RDPRUINTRIN_H
+#define __RDPRUINTRIN_H
+
+/* Define the default attributes for the functions in this file. */
+#define __DEFAULT_FN_ATTRS \
+  __attribute__((__always_inline__, __nodebug__,  __target__("rdpru")))
+
+
+/// Reads the content of a processor register.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the <c> RDPRU </c> instruction.
+///
+/// \param reg_id
+///    A processor register identifier.
+static __inline__ unsigned long long __DEFAULT_FN_ATTRS
+__rdpru (int reg_id)
+{
+  return __builtin_ia32_rdpru(reg_id);
+}
+
+#define __RDPRU_MPERF 0
+#define __RDPRU_APERF 1
+
+/// Reads the content of processor register MPERF.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic generates instruction <c> RDPRU </c> to read the value of
+/// register MPERF.
+#define __mperf() __builtin_ia32_rdpru(__RDPRU_MPERF)
+
+/// Reads the content of processor register APERF.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic generates instruction <c> RDPRU </c> to read the value of
+/// register APERF.
+#define __aperf() __builtin_ia32_rdpru(__RDPRU_APERF)
+
+#undef __DEFAULT_FN_ATTRS
+
+#endif /* __RDPRUINTRIN_H */

clang/lib/Headers/x86intrin.h

 #include <mwaitxintrin.h>
 #endif
 
 #if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
     defined(__CLZERO__)
 #include <clzerointrin.h>
 #endif
 
+#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
+    defined(__RDPRU__)
+#include <rdpruintrin.h>
+#endif
 
 #endif /* __X86INTRIN_H */

clang/test/CodeGen/rdpru-builtins.c

+// RUN: %clang_cc1 -ffreestanding %s -triple=i686-- -target-feature +rdpru -emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-- -target-feature +rdpru -emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-- -target-cpu znver2 -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include <x86intrin.h>
+
+// NOTE: This should correspond to the tests in llvm/test/CodeGen/X86/rdpru.ll
+
+unsigned long long test_rdpru(int regid) {
+  // CHECK-LABEL: test_rdpru
+  // CHECK: [[RESULT:%.*]] = call i64 @llvm.x86.rdpru(i32 %{{.*}})
+  // CHECK-NEXT: ret i64 [[RESULT]]
+  return __rdpru(regid);
+}
+
+unsigned long long test_mperf() {
+  // CHECK-LABEL: test_mperf
+  // CHECK: [[RESULT:%.*]] = call i64 @llvm.x86.rdpru(i32 0)
+  // CHECK-NEXT: ret i64 [[RESULT]]
+  return __mperf();
+}
+
+unsigned long long test_aperf() {
+  // CHECK-LABEL: test_aperf
+  // CHECK: [[RESULT:%.*]] = call i64 @llvm.x86.rdpru(i32 1)
+  // CHECK-NEXT: ret i64 [[RESULT]]
+  return __aperf();
+}
+
+void test_direct_calls_to_builtin_rdpru(int regid) {
+  // CHECK: call i64 @llvm.x86.rdpru(i32 0)
+  // CHECK: call i64 @llvm.x86.rdpru(i32 1)
+  // CHECK: call i64 @llvm.x86.rdpru(i32 %{{.*}})
+  (void) __builtin_ia32_rdpru(0);
+  (void) __builtin_ia32_rdpru(1);
+  (void) __builtin_ia32_rdpru(regid);
+}

clang/test/Driver/x86-target-features.c

 // VP2INTERSECT: "-target-feature" "+avx512vp2intersect"
 // NO-VP2INTERSECT: "-target-feature" "-avx512vp2intersect"
 
 // RUN: %clang --target=i386 -march=i386 -mrdpid %s -### 2>&1 | FileCheck -check-prefix=RDPID %s
 // RUN: %clang --target=i386 -march=i386 -mno-rdpid %s -### 2>&1 | FileCheck -check-prefix=NO-RDPID %s
 // RDPID: "-target-feature" "+rdpid"
 // NO-RDPID: "-target-feature" "-rdpid"
 
+// RUN: %clang --target=i386 -march=i386 -mrdpru %s -### 2>&1 | FileCheck -check-prefix=RDPRU %s
+// RUN: %clang --target=i386 -march=i386 -mno-rdpru %s -### 2>&1 | FileCheck -check-prefix=NO-RDPRU %s
+// RDPRU: "-target-feature" "+rdpru"
+// NO-RDPRU: "-target-feature" "-rdpru"
+
 // RUN: %clang -target i386-linux-gnu -mretpoline %s -### 2>&1 | FileCheck -check-prefix=RETPOLINE %s
 // RUN: %clang -target i386-linux-gnu -mno-retpoline %s -### 2>&1 | FileCheck -check-prefix=NO-RETPOLINE %s
 // RETPOLINE: "-target-feature" "+retpoline-indirect-calls" "-target-feature" "+retpoline-indirect-branches"
 // NO-RETPOLINE-NOT: retpoline
 
 // RUN: %clang -target i386-linux-gnu -mretpoline -mretpoline-external-thunk %s -### 2>&1 | FileCheck -check-prefix=RETPOLINE-EXTERNAL-THUNK %s
 // RUN: %clang -target i386-linux-gnu -mretpoline -mno-retpoline-external-thunk %s -### 2>&1 | FileCheck -check-prefix=NO-RETPOLINE-EXTERNAL-THUNK %s
 // RETPOLINE-EXTERNAL-THUNK: "-target-feature" "+retpoline-external-thunk"

clang/test/Preprocessor/x86_target_features.c

 
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mcrc32 -x c -E -dM -o - %s | FileCheck -check-prefix=CRC32 %s
 
 // CRC32: #define __CRC32__ 1
 
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-crc32 -x c -E -dM -o - %s | FileCheck -check-prefix=NOCRC32 %s
 
 // NOCRC32-NOT: #define __CRC32__ 1
+
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mrdpru -x c -E -dM -o - %s | FileCheck -check-prefix=RDPRU %s
+
+// RDPRU: #define __RDPRU__ 1
+
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-rdpru -x c -E -dM -o - %s | FileCheck -check-prefix=NORDPRU %s
+
+// NORDPRU-NOT: #define __RDPRU__ 1

llvm/docs/ReleaseNotes.rst

 ----------------------------------
 
 * ...
 
 Changes to the X86 Backend
 --------------------------
 
 * Support ``half`` type on SSE2 and above targets.
+* Support ``rdpru`` instruction on Zen2 and above targets.
 
 Changes to the OCaml bindings
 -----------------------------
 
 
 Changes to the C API
 --------------------
 
 * Add ``LLVMGetCastOpcode`` function to aid users of ``LLVMBuildCast`` in

llvm/include/llvm/IR/IntrinsicsX86.td

let TargetPrefix = "x86" in {
   def int_x86_atomic_bts : Intrinsic<[llvm_anyint_ty], [llvm_ptr_ty, llvm_i8_ty],
                                      [ImmArg<ArgIndex<1>>]>;
   def int_x86_atomic_btc : Intrinsic<[llvm_anyint_ty], [llvm_ptr_ty, llvm_i8_ty],
                                      [ImmArg<ArgIndex<1>>]>;
   def int_x86_atomic_btr : Intrinsic<[llvm_anyint_ty], [llvm_ptr_ty, llvm_i8_ty],
                                      [ImmArg<ArgIndex<1>>]>;
 }
 
+// Read Processor Register.
+let TargetPrefix = "x86" in {
+  def int_x86_rdpru : ClangBuiltin<"__builtin_ia32_rdpru">,
+              Intrinsic<[llvm_i64_ty], [llvm_i32_ty], []>;
+}
+
 //===----------------------------------------------------------------------===//
 // CET SS
 let TargetPrefix = "x86" in {
   def int_x86_incsspd : ClangBuiltin<"__builtin_ia32_incsspd">,
               Intrinsic<[], [llvm_i32_ty], []>;
   def int_x86_incsspq : ClangBuiltin<"__builtin_ia32_incsspq">,
               Intrinsic<[], [llvm_i64_ty], []>;
   def int_x86_rdsspd : ClangBuiltin<"__builtin_ia32_rdsspd">,

llvm/include/llvm/Support/X86TargetParser.def

 X86_FEATURE       (MOVDIRI,         "movdiri")
 X86_FEATURE       (MWAITX,          "mwaitx")
 X86_FEATURE       (PCONFIG,         "pconfig")
 X86_FEATURE       (PKU,             "pku")
 X86_FEATURE       (PREFETCHWT1,     "prefetchwt1")
 X86_FEATURE       (PRFCHW,          "prfchw")
 X86_FEATURE       (PTWRITE,         "ptwrite")
 X86_FEATURE       (RDPID,           "rdpid")
+X86_FEATURE       (RDPRU,           "rdpru")
 X86_FEATURE       (RDRND,           "rdrnd")
 X86_FEATURE       (RDSEED,          "rdseed")
 X86_FEATURE       (RTM,             "rtm")
 X86_FEATURE       (SAHF,            "sahf")
 X86_FEATURE       (SERIALIZE,       "serialize")
 X86_FEATURE       (SGX,             "sgx")
 X86_FEATURE       (SHA,             "sha")
 X86_FEATURE       (SHSTK,           "shstk")

llvm/lib/Support/X86TargetParser.cpp

constexpr FeatureBitset FeaturesZNVER1 =
     FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
     FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT |
     FeatureF16C | FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT |
     FeatureMMX | FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
     FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
     FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
     FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
     FeatureXSAVEOPT | FeatureXSAVES;
-constexpr FeatureBitset FeaturesZNVER2 =
-    FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD;
+constexpr FeatureBitset FeaturesZNVER2 = FeaturesZNVER1 | FeatureCLWB |
+                                         FeatureRDPID | FeatureRDPRU |
+                                         FeatureWBNOINVD;
 static constexpr FeatureBitset FeaturesZNVER3 = FeaturesZNVER2 |
                                                 FeatureINVPCID | FeaturePKU |
                                                 FeatureVAES | FeatureVPCLMULQDQ;
 
 constexpr ProcInfo Processors[] = {
   // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
   { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B },
   // i386-generation processors.

 constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {};
 constexpr FeatureBitset ImpliedFeaturesPCONFIG = {};
 constexpr FeatureBitset ImpliedFeaturesPOPCNT = {};
 constexpr FeatureBitset ImpliedFeaturesPKU = {};
 constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {};
 constexpr FeatureBitset ImpliedFeaturesPRFCHW = {};
 constexpr FeatureBitset ImpliedFeaturesPTWRITE = {};
 constexpr FeatureBitset ImpliedFeaturesRDPID = {};
+constexpr FeatureBitset ImpliedFeaturesRDPRU = {};
 constexpr FeatureBitset ImpliedFeaturesRDRND = {};
 constexpr FeatureBitset ImpliedFeaturesRDSEED = {};
 constexpr FeatureBitset ImpliedFeaturesRTM = {};
 constexpr FeatureBitset ImpliedFeaturesSAHF = {};
 constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {};
 constexpr FeatureBitset ImpliedFeaturesSGX = {};
 constexpr FeatureBitset ImpliedFeaturesSHSTK = {};
 constexpr FeatureBitset ImpliedFeaturesTBM = {};

llvm/lib/Target/X86/X86.td

 def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
                                       "Flush A Cache Line Optimized">;
 def FeatureCLWB    : SubtargetFeature<"clwb", "HasCLWB", "true",
                                       "Cache Line Write Back">;
 def FeatureWBNOINVD    : SubtargetFeature<"wbnoinvd", "HasWBNOINVD", "true",
                                       "Write Back No Invalidate">;
 def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true",
                                     "Support RDPID instructions">;
+def FeatureRDPRU : SubtargetFeature<"rdpru", "HasRDPRU", "true",
+                                    "Support RDPRU instructions">;
 def FeatureWAITPKG  : SubtargetFeature<"waitpkg", "HasWAITPKG", "true",
                                       "Wait and pause enhancements">;
 def FeatureENQCMD : SubtargetFeature<"enqcmd", "HasENQCMD", "true",
                                      "Has ENQCMD instructions">;
 def FeatureKL  : SubtargetFeature<"kl", "HasKL", "true",
                                   "Support Key Locker kl Instructions",
                                   [FeatureSSE2]>;
 def FeatureWIDEKL  : SubtargetFeature<"widekl", "HasWIDEKL", "true",
list<SubtargetFeature> ZNTuning = [TuningFastLZCNT,
                                      TuningFastScalarShiftMasks,
                                      TuningFastVariablePerLaneShuffle,
                                      TuningFastMOVBE,
                                      TuningSlowSHLD,
                                      TuningSBBDepBreaking,
                                      TuningInsertVZEROUPPER];
   list<SubtargetFeature> ZN2AdditionalFeatures = [FeatureCLWB,
                                                   FeatureRDPID,
+                                                  FeatureRDPRU,
                                                   FeatureWBNOINVD];
   list<SubtargetFeature> ZN2Tuning = ZNTuning;
   list<SubtargetFeature> ZN2Features =
     !listconcat(ZNFeatures, ZN2AdditionalFeatures);
   list<SubtargetFeature> ZN3AdditionalFeatures = [FeatureFSRM,
                                                   FeatureINVPCID,
                                                   FeaturePKU,
                                                   FeatureVAES,

llvm/lib/Target/X86/X86ISelLowering.cpp

static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget &Subtarget,
   case RDTSC: {
     SmallVector<SDValue, 2> Results;
     getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
                             Results);
     return DAG.getMergeValues(Results, dl);
   }
   // Read Performance Monitoring Counters.
   case RDPMC:
+  // Read Processor Register.
+  case RDPRU:
   // GetExtended Control Register.
   case XGETBV: {
     SmallVector<SDValue, 2> Results;
 
     // RDPMC uses ECX to select the index of the performance counter to read.
+    // RDPRU uses ECX to select the processor register to read.
     // XGETBV uses ECX to select the index of the XCR register to return.
     // The result is stored into registers EDX:EAX.
     expandIntrinsicWChainHelper(Op.getNode(), dl, DAG, IntrData->Opc0, X86::ECX,
                                 Subtarget, Results);
     return DAG.getMergeValues(Results, dl);
   }
   // XTEST intrinsics.
   case XTEST: {
case Intrinsic::x86_rdtsc:
                                      Results);
     case Intrinsic::x86_rdtscp:
       return getReadTimeStampCounter(N, dl, X86::RDTSCP, DAG, Subtarget,
                                      Results);
     case Intrinsic::x86_rdpmc:
       expandIntrinsicWChainHelper(N, dl, DAG, X86::RDPMC, X86::ECX, Subtarget,
                                   Results);
       return;
+    case Intrinsic::x86_rdpru:
+      expandIntrinsicWChainHelper(N, dl, DAG, X86::RDPRU, X86::ECX, Subtarget,
+        Results);
+      return;
     case Intrinsic::x86_xgetbv:
       expandIntrinsicWChainHelper(N, dl, DAG, X86::XGETBV, X86::ECX, Subtarget,
                                   Results);
       return;
     }
   }
   case ISD::READCYCLECOUNTER: {
     return getReadTimeStampCounter(N, dl, X86::RDTSC, DAG, Subtarget, Results);

llvm/lib/Target/X86/X86InstrInfo.td

 def HasPTWRITE   : Predicate<"Subtarget->hasPTWRITE()">;
 def FPStackf32   : Predicate<"!Subtarget->hasSSE1()">;
 def FPStackf64   : Predicate<"!Subtarget->hasSSE2()">;
 def HasSHSTK     : Predicate<"Subtarget->hasSHSTK()">;
 def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">;
 def HasCLWB      : Predicate<"Subtarget->hasCLWB()">;
 def HasWBNOINVD  : Predicate<"Subtarget->hasWBNOINVD()">;
 def HasRDPID     : Predicate<"Subtarget->hasRDPID()">;
+def HasRDPRU     : Predicate<"Subtarget->hasRDPRU()">;
 def HasWAITPKG   : Predicate<"Subtarget->hasWAITPKG()">;
 def HasINVPCID   : Predicate<"Subtarget->hasINVPCID()">;
 def HasCX8       : Predicate<"Subtarget->hasCX8()">;
 def HasCX16      : Predicate<"Subtarget->hasCX16()">;
 def HasPCONFIG   : Predicate<"Subtarget->hasPCONFIG()">;
 def HasENQCMD    : Predicate<"Subtarget->hasENQCMD()">;
 def HasKL        : Predicate<"Subtarget->hasKL()">;
 def HasWIDEKL    : Predicate<"Subtarget->hasWIDEKL()">;

llvm/lib/Target/X86/X86InstrSystem.td

def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst),
                  "ptwrite{l}\t$dst", [(int_x86_ptwrite32 GR32:$dst)]>, XS,
                     Requires<[HasPTWRITE]>;
 def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),
                     "ptwrite{q}\t$dst", [(int_x86_ptwrite64 GR64:$dst)]>, XS,
                     Requires<[In64BitMode, HasPTWRITE]>;
 } // SchedRW
 
 //===----------------------------------------------------------------------===//
+// RDPRU - Read Processor Register instruction.
+
+let SchedRW = [WriteSystem] in {
+let Uses = [ECX], Defs = [EAX, EDX] in
+   def RDPRU : I<0x01, MRM_FD, (outs), (ins), "rdpru", []>, PS,
+               Requires<[HasRDPRU]>;
+}
+
+//===----------------------------------------------------------------------===//
 // Platform Configuration instruction
 
 // From ISA docs:
 //  "This instruction is used to execute functions for configuring platform
 //   features.
 //   EAX: Leaf function to be invoked.
 //   RBX/RCX/RDX: Leaf-specific purpose."
 //  "Successful execution of the leaf clears RAX (set to zero) and ZF, CF, PF,

llvm/lib/Target/X86/X86IntrinsicsInfo.h

enum IntrinsicType : uint16_t {
   INTR_TYPE_1OP_MASK, INTR_TYPE_2OP_MASK,
   IFMA_OP, VPERM_2OP, INTR_TYPE_SCALAR_MASK, INTR_TYPE_SCALAR_MASK_SAE,
   INTR_TYPE_SCALAR_MASK_RND,
   INTR_TYPE_3OP_SCALAR_MASK_SAE,
   COMPRESS_EXPAND_IN_REG,
   TRUNCATE_TO_REG, CVTPS2PH_MASK, CVTPD2DQ_MASK, CVTQQ2PS_MASK,
   TRUNCATE_TO_MEM_VI8, TRUNCATE_TO_MEM_VI16, TRUNCATE_TO_MEM_VI32,
   FIXUPIMM, FIXUPIMM_MASKZ, GATHER_AVX2,
-  ROUNDP, ROUNDS
+  ROUNDP, ROUNDS, RDPRU
 };
 
 struct IntrinsicData {
 
   uint16_t      Id;
   IntrinsicType Type;
   uint16_t      Opc0;
   uint16_t      Opc1;
static const IntrinsicData IntrinsicsWithChain[] = {
   X86_INTRINSIC_DATA(avx512_scattersiv2_di, SCATTER, 0, 0),
   X86_INTRINSIC_DATA(avx512_scattersiv4_df, SCATTER, 0, 0),
   X86_INTRINSIC_DATA(avx512_scattersiv4_di, SCATTER, 0, 0),
   X86_INTRINSIC_DATA(avx512_scattersiv4_sf, SCATTER, 0, 0),
   X86_INTRINSIC_DATA(avx512_scattersiv4_si, SCATTER, 0, 0),
   X86_INTRINSIC_DATA(avx512_scattersiv8_sf, SCATTER, 0, 0),
   X86_INTRINSIC_DATA(avx512_scattersiv8_si, SCATTER, 0, 0),
   X86_INTRINSIC_DATA(rdpmc,     RDPMC,  X86::RDPMC, 0),
+  X86_INTRINSIC_DATA(rdpru,     RDPRU,  X86::RDPRU, 0),
   X86_INTRINSIC_DATA(rdrand_16, RDRAND, X86ISD::RDRAND, 0),
   X86_INTRINSIC_DATA(rdrand_32, RDRAND, X86ISD::RDRAND, 0),
   X86_INTRINSIC_DATA(rdrand_64, RDRAND, X86ISD::RDRAND, 0),
   X86_INTRINSIC_DATA(rdseed_16, RDSEED, X86ISD::RDSEED, 0),
   X86_INTRINSIC_DATA(rdseed_32, RDSEED, X86ISD::RDSEED, 0),
   X86_INTRINSIC_DATA(rdseed_64, RDSEED, X86ISD::RDSEED, 0),
   X86_INTRINSIC_DATA(rdtsc,     RDTSC,  X86::RDTSC, 0),
   X86_INTRINSIC_DATA(rdtscp,    RDTSC,  X86::RDTSCP, 0),

llvm/test/CodeGen/X86/rdpru.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- -mattr=+rdpru | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=i686-- -mattr=+rdpru -fast-isel | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+rdpru | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+rdpru -fast-isel | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver2 | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 -fast-isel | FileCheck %s --check-prefix=X64
+
+define void @rdpru_asm() {
+; X86-LABEL: rdpru_asm:
+; X86:       # %bb.0: # %entry
+; X86-NEXT:    #APP
+; X86-NEXT:    rdpru
+; X86-NEXT:    #NO_APP
+; X86-NEXT:    retl
+;
+; X64-LABEL: rdpru_asm:
+; X64:       # %bb.0: # %entry
+; X64-NEXT:    #APP
+; X64-NEXT:    rdpru
+; X64-NEXT:    #NO_APP
+; X64-NEXT:    retq
+entry:
+  call void asm sideeffect "rdpru", "~{dirflag},~{fpsr},~{flags}"()
+  ret void
+}
+
+define i64 @rdpru_param(i32 %regid) local_unnamed_addr {
+; X86-LABEL: rdpru_param:
+; X86:       # %bb.0: # %entry
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT:    rdpru
+; X86-NEXT:    retl
+;
+; X64-LABEL: rdpru_param:
+; X64:       # %bb.0: # %entry
+; X64-NEXT:    movl %edi, %ecx
+; X64-NEXT:    rdpru
+; X64-NEXT:    shlq $32, %rdx
+; X64-NEXT:    orq %rdx, %rax
+; X64-NEXT:    retq
+entry:
+  %0 = tail call i64 @llvm.x86.rdpru(i32 %regid)
+  ret i64 %0
+}
+
+define i64 @rdpru_mperf() local_unnamed_addr {
+; X86-LABEL: rdpru_mperf:
+; X86:       # %bb.0: # %entry
+; X86-NEXT:    xorl %ecx, %ecx
+; X86-NEXT:    rdpru
+; X86-NEXT:    retl
+;
+; X64-LABEL: rdpru_mperf:
+; X64:       # %bb.0: # %entry
+; X64-NEXT:    xorl %ecx, %ecx
+; X64-NEXT:    rdpru
+; X64-NEXT:    shlq $32, %rdx
+; X64-NEXT:    orq %rdx, %rax
+; X64-NEXT:    retq
+entry:
+  %0 = tail call i64 @llvm.x86.rdpru(i32 0)
+  ret i64 %0
+}
+
+define i64 @rdpru_aperf() local_unnamed_addr {
+; X86-LABEL: rdpru_aperf:
+; X86:       # %bb.0: # %entry
+; X86-NEXT:    movl $1, %ecx
+; X86-NEXT:    rdpru
+; X86-NEXT:    retl
+;
+; X64-LABEL: rdpru_aperf:
+; X64:       # %bb.0: # %entry
+; X64-NEXT:    movl $1, %ecx
+; X64-NEXT:    rdpru
+; X64-NEXT:    shlq $32, %rdx
+; X64-NEXT:    orq %rdx, %rax
+; X64-NEXT:    retq
+entry:
+  %0 = tail call i64 @llvm.x86.rdpru(i32 1)
+  ret i64 %0
+}
+
+declare i64 @llvm.x86.rdpru(i32)

llvm/test/MC/Disassembler/X86/x86-32.txt

 # CHECK: pvalidate
 0xf2 0x0f 0x01 0xff
 
 #CHECK: tdcall
 0x66 0x0f 0x01 0xcc
 
 # CHECK: hreset $1
 0xf3 0x0f 0x3a 0xf0 0xc0 0x01
+
+# CHECK: rdpru
+0x0f,0x01,0xfd

llvm/test/MC/Disassembler/X86/x86-64.txt

 # CHECK: senduipi %rdx
 0xf3,0x0f,0xc7,0xf2
 
 # CHECK: senduipi %r8
 0xf3,0x41,0x0f,0xc7,0xf0
 
 # CHECK: senduipi %r13
 0xf3,0x41,0x0f,0xc7,0xf5
+
+# CHECK: rdpru
+0x0f,0x01,0xfd

llvm/test/MC/X86/RDPRU.s

+/// Encoding and disassembly of rdpru.
+
+// RUN: llvm-mc -triple i686-- --show-encoding %s |\
+// RUN:   FileCheck %s --check-prefixes=CHECK,ENCODING
+
+// RUN: llvm-mc -triple i686-- -filetype=obj %s |\
+// RUN:   llvm-objdump -d - | FileCheck %s
+
+// RUN: llvm-mc -triple x86_64-- --show-encoding %s |\
+// RUN:   FileCheck %s --check-prefixes=CHECK,ENCODING
+
+// RUN: llvm-mc -triple x86_64-- -filetype=obj %s |\
+// RUN:   llvm-objdump -d - | FileCheck %s
+
+// CHECK: rdpru
+// ENCODING:  encoding: [0x0f,0x01,0xfd]
+rdpru