- User Since
- Apr 25 2016, 3:58 AM (64 w, 3 d)
Tue, Jul 18
Simon! If you are fine, can you please commit the patch on my behalf. I am yet to get commit access rights. Probably, after this patch, I will try to get it.
Patch update: For newer testcases.
Mon, Jul 17
Updated as per Javed's review comments!
Sun, Jul 16
Updated as per the review comments.
Wed, Jul 12
Feb 8 2017
Thank you @craig.topper.
@craig.topper If you are okay, can you please commit the changes on my behalf?
I think it is okay even if we don't set the mayStore attribute.
I wrote a simple test to check the following
- Schedules based on the instruction attribute
- Side-effect handling
Feb 7 2017
Updated the test file "x86-32.s" for clzero only test!
Updated the builtins test for "__builtin_ia32_clzero"
Updated for review comments.
Updated for the review comments
Feb 1 2017
Jan 9 2017
If Okay, can you please commit these on my behalf. I don't have write access.
Yes. True I mentioned that for the grouping or the order of the features enabled. These initFeatureMap are done based on the intrinsics and the CodeGen part.
Adding znver1 to following tests.
b. Slow SHLD
c. slow unaligned memory
Fallback to CK_BTVER1 is ok but not to CK_BTVER2. This is not possible because of the partial YMM writes. They have different behavior for znver1 with AVX and their legacy SIMD counterparts. So, as of now leaving them to alphabetical order.
Jan 8 2017
The clzero intrinsic handling and feature addition will be handled as a separate patch.
Added movbe and sse4a into ISA list of znver1.
The clzero builtins and feature addition will be handled separately in another patch.
SSE4a and movbe are added to the ISA list.
Dec 21 2016
I am preparing a patch which doesn't include the clzero feature patch.
I will submit a separate patch for clzero feature patch.
May 17 2016
May 13 2016
Added FeatureMWAITX to bdver4.
May 11 2016
Incorporated comments from Simon!
May 9 2016