[AArch64] Add target feature "all"

[MaskRay]

Summary

This is used by disassemblers: llvm-mc -disassemble -mattr= and llvm-objdump --mattr=.
The main use case is for llvm-objdump to disassemble all known instructions
(D128030).

In user-facing tools, "all" is intentionally not supported in producers:
integrated assembler (.arch_extension all), clang -march (-march=armv9.3a+all).
Due to the code structure, llvm-mc -mattr=+all llc -mattr=+all are not
rejected (they are internal tool). Add llvm/test/CodeGen/AArch64/mattr-all.ll
to catch behavior changes.

AArch64SysReg::SysReg::haveFeatures: check FeatureAll to print
AArch64SysReg::SysReg::AltName for some system registers (e.g. ERRIDR_EL1, RNDR).

AArch64.td: add AssemblerPredicateWithAll to additionally test FeatureAll.
Change all AssemblerPredicate (except UseNegativeImmediates) to AssemblerPredicateWithAll.

utils/TableGen/{DecoderEmitter,SubtargetFeatureInfo}.cpp: support arbitrarily
nested all_of, any_of, and not.

Note: A predicate supports all_of, any_of, and not. For a target (though
currently not for AArch64) an encoding may be disassembled differently with
different target features.
Note: AArch64MCCodeEmitter::computeAvailableFeatures is not available to
the disassembler.

[c-rhodes]

llvm/lib/Target/AArch64/AArch64.td

558–566

I think this will introduce a bit of a maintenance burden and I can see new features being missed, could this be generated by tablegen?

[nickdesaulniers]

Should https://reviews.llvm.org/D128030 be marked in phab as a child to this patch, to show the dependency?

[nickdesaulniers]

Honestly, I think this feature list should just exist in the disassembler. Is this generally useful when building code? I don't think so; its meaning and ABI will change over time as more extensions are added to the architecture.

llvm/lib/Target/AArch64/AArch64.td

558–566

Or perhaps an assertion somewhere if the possible feature list grows to alert this needs to be updated?

[MaskRay]

In D128029#3592359, @nickdesaulniers wrote:

Honestly, I think this feature list should just exist in the disassembler. Is this generally useful when building code? I don't think so; its meaning and ABI will change over time as more extensions are added to the architecture.

It is generally not useful when building code, so I have emphasized that clang -march= does not support all. I think such a feature list does not exist in the disassembler.
There is some maintenance cost, but lacking some stuff when new target features emerge does not matter: people running llvm-objdump may notice and we can add new target features to "all".

I think for some targets there are conflicting encodings. Then the "all" feature may probably need to pick the mostly likely instruction sets users expect.

[nickdesaulniers]

Do we have equivalent "all" features for other architectures? It might be nice to have an interface architectures can provide to list a list of all possible features. Then we have one place to keep up to date, then other call sites can share that code. That might help us notice sooner when the "all" list is missing a new addition if there's more than one user, eventually.

[MaskRay]

In D128029#3592617, @nickdesaulniers wrote:

Do we have equivalent "all" features for other architectures? It might be nice to have an interface architectures can provide to list a list of all possible features. Then we have one place to keep up to date, then other call sites can share that code. That might help us notice sooner when the "all" list is missing a new addition if there's more than one user, eventually.

PowerPC has -mcpu=future (see D127824), which is more or less "all" features.
Note that some targets may have conflicting instruction sets, at which point an all feature will not exist. (IIRC PowerPC's Signal Processing Engine extension falls into this case, so -mcpu=future likely cannot decode some instructions).
We may have several choices of all: (a) great common divisor (b) all target features user mostly likely expect.

In llvm/lib/Target/Mips/MipsInstrInfo.td, there are assembler predicates using not operator, e.g. AssemblerPredicate<(all_of (not FeatureMips3))>. Apparently there are conflicting instruction sets.

[MaskRay]

llvm/lib/Target/AArch64/AArch64.td

558–566

Explained in a main comment:

but lacking some stuff when new target features emerge does not matter: people running llvm-objdump may notice and we can add new target features to "all".

This controversy is the main point that we do not add a user-facing (e.g. clang -march) support for all.

[srhines]

llvm/lib/Target/AArch64/AArch64.td

558–566

I'm inclined to believe that this is a reasonable maintenance burden, but perhaps someone from ARM should weigh in here. It's in precisely the best place to be noticed when adding a new AArch64 subtarget/feature. Ultimately this is being added to support improved experiences for llvm-objdump, and it does that. If there are missing subtargets/features in the future, it seems relatively straightforward to add them here.

[dmgreen]

The general idea sounds useful to me, but FeatureTME seems to be missing (as one I randomly tried). I've added some more reviewers who might have more of an opinion on the best way to structure it.

[lenary]

I'm very supportive of this, as I wanted it the other day.

I do agree this should not be exposed through -march - instead it should be exposed only through --mattr which I feel is not quite as user-facing as -march and friends.

I wonder whether a better approach to reduce the maintenance burden might be the following:

def FeatureAll : SubtargetFeature<"all", "IsAll", "true", "Enable all instructions", []>;

// or for AArch64
class ARMAssemblerPredicate<dag cond, string name=""> : AssemblerPredicate<(any_of FeatureAll, cond), name>;

This might even be something to move into llvm/include/llvm/Target/Target.td (I don't know, by changing class AssemblerPredicate to class AssemblerPredicateBase and then calling what i've defined as ARMAssemblerPredicate as AssemblerPredicate?

[peter.smith]

I definitely agree that there should be the functionality in the disassembler. By default Arm's proprietary toolchain operates in this mode, for want of a better word, we called it universal disassembly. There is an option for architecture aware disassembly by giving it a CPU. For most of Arm (some unfortunate overlap with some mutually exclusive M-profile and A profile extensions) and all of AArch64 there are no overlapping encodings so universal tends to work well.

Main reason for mentioning that is to ask the question; is -mattr=all too low level a concept to model universal disassembly on the command line? I'm thinking it is fine for llvm-mc but perhaps llvm-objdump could do with something a bit more high-level.

While I do think updating all could be fixed by process, i.e. when adding a new architecture remember to add to "all", however if there is a way to do this automatically it would be useful to have that in TableGen. Perhaps something like computeAvailableFeatures(). For example setAllFeatures() which just calls Features.set(Feature_...) for all Subtarget features. With perhaps a backend specific option to toggle off specific features if needed.

[MaskRay]

Use AssemblerPredicateWithAll

[MaskRay]

Thanks for the positive feedback and suggestions.

In D128029#3601099, @lenary wrote:

I'm very supportive of this, as I wanted it the other day.

I do agree this should not be exposed through -march - instead it should be exposed only through --mattr which I feel is not quite as user-facing as -march and friends.

I wonder whether a better approach to reduce the maintenance burden might be the following:

def FeatureAll : SubtargetFeature<"all", "IsAll", "true", "Enable all instructions", []>;

// or for AArch64
class ARMAssemblerPredicate<dag cond, string name=""> : AssemblerPredicate<(any_of FeatureAll, cond), name>;

This might even be something to move into llvm/include/llvm/Target/Target.td (I don't know, by changing class AssemblerPredicate to class AssemblerPredicateBase and then calling what i've defined as ARMAssemblerPredicate as AssemblerPredicate?

Thanks for the suggestion. It requires some changes to the generic TableGen code which I just did.

As the updated summary says, an encoding may be disassembled differently with different target features.
For many(most?) targets without conflicting encoding, there would be a good user experience improvement but I am not so sure that we may be able to update the generic AssemblerPredicate.
In any case, if we ever need to update it, it may be a future day when we have more experience with various targets in llvm updated.

While I do think updating all could be fixed by process, i.e. when adding a new architecture remember to add to "all", however if there is a way to do this automatically it would be useful to have that in TableGen. Perhaps something like computeAvailableFeatures(). For example setAllFeatures() which just calls Features.set(Feature_...) for all Subtarget features. With perhaps a backend specific option to toggle off specific features if needed.

Due to the code structure, AArch64MCCodeEmitter::computeAvailableFeatures is not available to the disassembler. In addition, not all feature bits indicate some instruction set support.
I think for now the most promising approach without imposing too much burden is class AssemblerPredicateWithAll as implemented by the latest revision.
We may be able to do something like computeAvailableFeatures for disassemblers but that be a larger change.

[MaskRay]

Don't change UseNegativeImmediates (though it doesn't matter anyway because the all_of (not ...) is used in a way that whether FeatureAll is tested does not matter)

[lenary]

I didn't realise you couldn't nest any_of and all_of before this patch. Thanks for catching that.

In D128029#3601135, @peter.smith wrote:

Main reason for mentioning that is to ask the question; is -mattr=all too low level a concept to model universal disassembly on the command line? I'm thinking it is fine for llvm-mc but perhaps llvm-objdump could do with something a bit more high-level.

I'm not sure how much -mattr is a part of the public/backwards-compatible command-line interface for llvm-objdump. I think we could absolutely include an option for this in a command-line interface we commit to not changing, usually the target-specific options are behind llvm-objdump -M, which I believe should have enough access to the subtarget to be able to enable features.

The only other suggestion I have apart from the one below is whether we should change the definition of SysAlias::haveFeatures in llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h to also check for FeatureAll - I think how those tables are currently structured, they don't use AssemblyPredicates, they use feature bitsets directly, which is maybe not optimal. If you want to leave this refactoring for later, that would make sense to me too.

llvm/test/MC/AArch64/directive-arch_extension.s

99

Can you move this test into directive-arch_extension-negative.s, where we already expect the directive to fail and emit errors?

[MaskRay]

Move isValidSysReg's FeatureAll change to llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h

[MaskRay]

In D128029#3604070, @lenary wrote:

I didn't realise you couldn't nest any_of and all_of before this patch. Thanks for catching that.

In D128029#3601135, @peter.smith wrote:

Main reason for mentioning that is to ask the question; is -mattr=all too low level a concept to model universal disassembly on the command line? I'm thinking it is fine for llvm-mc but perhaps llvm-objdump could do with something a bit more high-level.

I'm not sure how much -mattr is a part of the public/backwards-compatible command-line interface for llvm-objdump. I think we could absolutely include an option for this in a command-line interface we commit to not changing, usually the target-specific options are behind llvm-objdump -M, which I believe should have enough access to the subtarget to be able to enable features.

The only other suggestion I have apart from the one below is whether we should change the definition of SysAlias::haveFeatures in llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h to also check for FeatureAll - I think how those tables are currently structured, they don't use AssemblyPredicates, they use feature bitsets directly, which is maybe not optimal. If you want to leave this refactoring for later, that would make sense to me too.

Thanks. Changing SysAlias::haveFeatures is better. Updated.

[lenary]

I'm happy with this (and I satisfy "someone from Arm" in the comment above). I think others are too, but maybe wait for another @peter.smith comment before landing?

In reply to @nickdesaulniers comment, we can probably move some of the non-aarch64-specific tablegen changes into the target-independent tablegen in a follow-up commit, which will also need IsAll to be moved to the subtarget base class. That seems routine and easy, I hope.

[MaskRay]

@peter.smith ^

[peter.smith]

No objections from me. I'm not an expert in this area so I've got a few questions/suggestions based on trying to understand the changes.

llvm/test/TableGen/AsmPredicateCombining.td

53

IIUC code has been added to be able to nest any_of and all_of could we add a test for that case.

llvm/utils/TableGen/DecoderEmitter.cpp

1231

Could you explain what Outer is precisely. To me the name implies it is meant to be true only when there is an expression with parens. For example any_of(x, y, z) when processing y assuming it isn't another any_of or all_of then I would expect Outer to be false (an inner if you like). It looks like Outer is set when processing an all_of or any_of with more than 1 parameter. If I'm right it might lead to more parentheses than we'd need, but this isn't a problem for correctness.

1252

One thing I haven't been able to work out is whether it is possible for Paren to be true and D->Args() > 0 so that we get OS << '(' then OS << LS which I assume would end up as (&& or (|| this doesn't look to be happening in the test cases, but I can't quite rule it out from the code here.

llvm/utils/TableGen/SubtargetFeatureInfo.cpp

154

Worth adding a false /* Outer */?

[MaskRay]

address comments

llvm/test/MC/AArch64/directive-arch_extension.s

99

Done. For many tests, I think using one file for both positive and negative tests may be clearer. Since directive-arch_extension-negative.s exists, I'll not change it in this patch :-)

llvm/utils/TableGen/DecoderEmitter.cpp

1231

Thanks for the comments. Added a comment.

Outer is simplified from a more complex recursive expression printer.

a * (b + c)
    ------- current recursive call

For a recursive call where OuterPrecedence indicates *, if the inner expression uses an operator (e.g. +) which binds less than the outer operator, a pair of () is needed.

In our case, for the following expression

a && (b && c)
     ________

we print a pair of superfluous parentheses. But for most cases, the new algorithm prints fewer () than before.

1252

ListSeparator does not print a delimiter for the first << call. (&& or (|| cannot happen.

llvm/utils/TableGen/SubtargetFeatureInfo.cpp

154

I pick /*ParenIfBinOp=*/false. This style is allowed by both clang-format and clang-tidy's bugprone-argument-comment check.

[MaskRay]

minor adjustment

[peter.smith]

Thanks for the updates, LGTM too.

[DavidSpickett]

Thanks for implementing this!

I've been trying to use it in lldb's disassembler and found that for the "predres" extension +all doesn't work as expected.

$ ./bin/llvm-mc --triple aarch64 --assemble -o - -mattr=+all --show-encoding <<< "cfp rctx, x0"
        .text
<stdin>:1:5: error: CFPRCTX requires: predres
cfp rctx, x0
    ^

I think I know what causes this and it's that AArch64AsmParser::parseSysAlias uses the feature bits from the SubTargetInfo. This is before "+all" has set all the other feature bits. It should be using the feature bits stored in the AsmParser, so I'm looking at changing it to do that.

Anything that isn't a sys instruction alias is fine.

[DavidSpickett]

Turns out there was a much simpler soloution: https://reviews.llvm.org/D129147

llvm/lib/Target/AArch64/AArch64.td

def HasV8_0rOps : SubtargetFeature<
   FeaturePAuth, FeatureRCPC,
   //v8.4
   FeatureDotProd, FeatureTRACEV8_4, FeatureTLB_RMI,
   FeatureFlagM, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO,
   // Not mandatory in v8.0-R, but included here on the grounds that it
   // only enables names of system registers
   FeatureSpecRestrict
   ]>;
 
+// Only intended to be used by disassemblers.
+def FeatureAll
+    : SubtargetFeature<"all", "IsAll", "true", "Enable all instructions", []>;
+
+class AssemblerPredicateWithAll<dag cond, string name="">
+    : AssemblerPredicate<(any_of FeatureAll, cond), name>;
+
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
 include "AArch64RegisterInfo.td"
 include "AArch64RegisterBanks.td"
 include "AArch64CallingConvention.td"
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // AArch64 Instruction definitions.
 //
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // ARM Instruction Predicate Definitions.
 //
 def HasV8_1a         : Predicate<"Subtarget->hasV8_1aOps()">,
-                                 AssemblerPredicate<(all_of HasV8_1aOps), "armv8.1a">;
+                                 AssemblerPredicateWithAll<(all_of HasV8_1aOps), "armv8.1a">;
 def HasV8_2a         : Predicate<"Subtarget->hasV8_2aOps()">,
-                                 AssemblerPredicate<(all_of HasV8_2aOps), "armv8.2a">;
+                                 AssemblerPredicateWithAll<(all_of HasV8_2aOps), "armv8.2a">;
 def HasV8_3a         : Predicate<"Subtarget->hasV8_3aOps()">,
-                                 AssemblerPredicate<(all_of HasV8_3aOps), "armv8.3a">;
+                                 AssemblerPredicateWithAll<(all_of HasV8_3aOps), "armv8.3a">;
 def HasV8_4a         : Predicate<"Subtarget->hasV8_4aOps()">,
-                                 AssemblerPredicate<(all_of HasV8_4aOps), "armv8.4a">;
+                                 AssemblerPredicateWithAll<(all_of HasV8_4aOps), "armv8.4a">;
 def HasV8_5a         : Predicate<"Subtarget->hasV8_5aOps()">,
-                                 AssemblerPredicate<(all_of HasV8_5aOps), "armv8.5a">;
+                                 AssemblerPredicateWithAll<(all_of HasV8_5aOps), "armv8.5a">;
 def HasV8_6a         : Predicate<"Subtarget->hasV8_6aOps()">,
-                                 AssemblerPredicate<(all_of HasV8_6aOps), "armv8.6a">;
+                                 AssemblerPredicateWithAll<(all_of HasV8_6aOps), "armv8.6a">;
 def HasV8_7a         : Predicate<"Subtarget->hasV8_7aOps()">,
-                                 AssemblerPredicate<(all_of HasV8_7aOps), "armv8.7a">;
+                                 AssemblerPredicateWithAll<(all_of HasV8_7aOps), "armv8.7a">;
 def HasV9_0a         : Predicate<"Subtarget->hasV9_0aOps()">,
-                                 AssemblerPredicate<(all_of HasV9_0aOps), "armv9-a">;
+                                 AssemblerPredicateWithAll<(all_of HasV9_0aOps), "armv9-a">;
 def HasV9_1a         : Predicate<"Subtarget->hasV9_1aOps()">,
-                                 AssemblerPredicate<(all_of HasV9_1aOps), "armv9.1a">;
+                                 AssemblerPredicateWithAll<(all_of HasV9_1aOps), "armv9.1a">;
 def HasV9_2a         : Predicate<"Subtarget->hasV9_2aOps()">,
-                                 AssemblerPredicate<(all_of HasV9_2aOps), "armv9.2a">;
+                                 AssemblerPredicateWithAll<(all_of HasV9_2aOps), "armv9.2a">;
 def HasV9_3a         : Predicate<"Subtarget->hasV9_3aOps()">,
-                                 AssemblerPredicate<(all_of HasV9_3aOps), "armv9.3a">;
+                                 AssemblerPredicateWithAll<(all_of HasV9_3aOps), "armv9.3a">;
 def HasV8_0r         : Predicate<"Subtarget->hasV8_0rOps()">,
-                                 AssemblerPredicate<(all_of HasV8_0rOps), "armv8-r">;
+                                 AssemblerPredicateWithAll<(all_of HasV8_0rOps), "armv8-r">;
 
 def HasEL2VMSA       : Predicate<"Subtarget->hasEL2VMSA()">,
-                       AssemblerPredicate<(all_of FeatureEL2VMSA), "el2vmsa">;
+                       AssemblerPredicateWithAll<(all_of FeatureEL2VMSA), "el2vmsa">;
 
 def HasEL3           : Predicate<"Subtarget->hasEL3()">,
-                       AssemblerPredicate<(all_of FeatureEL3), "el3">;
+                       AssemblerPredicateWithAll<(all_of FeatureEL3), "el3">;
 
 def HasVH            : Predicate<"Subtarget->hasVH()">,
-                       AssemblerPredicate<(all_of FeatureVH), "vh">;
+                       AssemblerPredicateWithAll<(all_of FeatureVH), "vh">;
 
 def HasLOR           : Predicate<"Subtarget->hasLOR()">,
-                       AssemblerPredicate<(all_of FeatureLOR), "lor">;
+                       AssemblerPredicateWithAll<(all_of FeatureLOR), "lor">;
 
 def HasPAuth         : Predicate<"Subtarget->hasPAuth()">,
-                       AssemblerPredicate<(all_of FeaturePAuth), "pauth">;
+                       AssemblerPredicateWithAll<(all_of FeaturePAuth), "pauth">;
 
 def HasJS            : Predicate<"Subtarget->hasJS()">,
-                       AssemblerPredicate<(all_of FeatureJS), "jsconv">;
+                       AssemblerPredicateWithAll<(all_of FeatureJS), "jsconv">;
 
 def HasCCIDX         : Predicate<"Subtarget->hasCCIDX()">,
-                       AssemblerPredicate<(all_of FeatureCCIDX), "ccidx">;
+                       AssemblerPredicateWithAll<(all_of FeatureCCIDX), "ccidx">;
 
 def HasComplxNum      : Predicate<"Subtarget->hasComplxNum()">,
-                       AssemblerPredicate<(all_of FeatureComplxNum), "complxnum">;
+                       AssemblerPredicateWithAll<(all_of FeatureComplxNum), "complxnum">;
 
 def HasNV            : Predicate<"Subtarget->hasNV()">,
-                       AssemblerPredicate<(all_of FeatureNV), "nv">;
+                       AssemblerPredicateWithAll<(all_of FeatureNV), "nv">;
 
 def HasMPAM          : Predicate<"Subtarget->hasMPAM()">,
-                       AssemblerPredicate<(all_of FeatureMPAM), "mpam">;
+                       AssemblerPredicateWithAll<(all_of FeatureMPAM), "mpam">;
 
 def HasDIT           : Predicate<"Subtarget->hasDIT()">,
-                       AssemblerPredicate<(all_of FeatureDIT), "dit">;
+                       AssemblerPredicateWithAll<(all_of FeatureDIT), "dit">;
 
 def HasTRACEV8_4         : Predicate<"Subtarget->hasTRACEV8_4()">,
-                       AssemblerPredicate<(all_of FeatureTRACEV8_4), "tracev8.4">;
+                       AssemblerPredicateWithAll<(all_of FeatureTRACEV8_4), "tracev8.4">;
 
 def HasAM            : Predicate<"Subtarget->hasAM()">,
-                       AssemblerPredicate<(all_of FeatureAM), "am">;
+                       AssemblerPredicateWithAll<(all_of FeatureAM), "am">;
 
 def HasSEL2          : Predicate<"Subtarget->hasSEL2()">,
-                       AssemblerPredicate<(all_of FeatureSEL2), "sel2">;
+                       AssemblerPredicateWithAll<(all_of FeatureSEL2), "sel2">;
 
 def HasTLB_RMI          : Predicate<"Subtarget->hasTLB_RMI()">,
-                       AssemblerPredicate<(all_of FeatureTLB_RMI), "tlb-rmi">;
+                       AssemblerPredicateWithAll<(all_of FeatureTLB_RMI), "tlb-rmi">;
 
 def HasFlagM         : Predicate<"Subtarget->hasFlagM()">,
-                       AssemblerPredicate<(all_of FeatureFlagM), "flagm">;
+                       AssemblerPredicateWithAll<(all_of FeatureFlagM), "flagm">;
 
 def HasRCPC_IMMO      : Predicate<"Subtarget->hasRCPCImm()">,
-                       AssemblerPredicate<(all_of FeatureRCPC_IMMO), "rcpc-immo">;
+                       AssemblerPredicateWithAll<(all_of FeatureRCPC_IMMO), "rcpc-immo">;
 
 def HasFPARMv8       : Predicate<"Subtarget->hasFPARMv8()">,
-                               AssemblerPredicate<(all_of FeatureFPARMv8), "fp-armv8">;
+                               AssemblerPredicateWithAll<(all_of FeatureFPARMv8), "fp-armv8">;
 def HasNEON          : Predicate<"Subtarget->hasNEON()">,
-                                 AssemblerPredicate<(all_of FeatureNEON), "neon">;
+                                 AssemblerPredicateWithAll<(all_of FeatureNEON), "neon">;
 def HasCrypto        : Predicate<"Subtarget->hasCrypto()">,
-                                 AssemblerPredicate<(all_of FeatureCrypto), "crypto">;
+                                 AssemblerPredicateWithAll<(all_of FeatureCrypto), "crypto">;
 def HasSM4           : Predicate<"Subtarget->hasSM4()">,
-                                 AssemblerPredicate<(all_of FeatureSM4), "sm4">;
+                                 AssemblerPredicateWithAll<(all_of FeatureSM4), "sm4">;
 def HasSHA3          : Predicate<"Subtarget->hasSHA3()">,
-                                 AssemblerPredicate<(all_of FeatureSHA3), "sha3">;
+                                 AssemblerPredicateWithAll<(all_of FeatureSHA3), "sha3">;
 def HasSHA2          : Predicate<"Subtarget->hasSHA2()">,
-                                 AssemblerPredicate<(all_of FeatureSHA2), "sha2">;
+                                 AssemblerPredicateWithAll<(all_of FeatureSHA2), "sha2">;
 def HasAES           : Predicate<"Subtarget->hasAES()">,
-                                 AssemblerPredicate<(all_of FeatureAES), "aes">;
+                                 AssemblerPredicateWithAll<(all_of FeatureAES), "aes">;
 def HasDotProd       : Predicate<"Subtarget->hasDotProd()">,
-                                 AssemblerPredicate<(all_of FeatureDotProd), "dotprod">;
+                                 AssemblerPredicateWithAll<(all_of FeatureDotProd), "dotprod">;
 def HasCRC           : Predicate<"Subtarget->hasCRC()">,
-                                 AssemblerPredicate<(all_of FeatureCRC), "crc">;
+                                 AssemblerPredicateWithAll<(all_of FeatureCRC), "crc">;
 def HasLSE           : Predicate<"Subtarget->hasLSE()">,
-                                 AssemblerPredicate<(all_of FeatureLSE), "lse">;
+                                 AssemblerPredicateWithAll<(all_of FeatureLSE), "lse">;
 def HasNoLSE         : Predicate<"!Subtarget->hasLSE()">;
 def HasRAS           : Predicate<"Subtarget->hasRAS()">,
-                                 AssemblerPredicate<(all_of FeatureRAS), "ras">;
+                                 AssemblerPredicateWithAll<(all_of FeatureRAS), "ras">;
 def HasRDM           : Predicate<"Subtarget->hasRDM()">,
-                                 AssemblerPredicate<(all_of FeatureRDM), "rdm">;
+                                 AssemblerPredicateWithAll<(all_of FeatureRDM), "rdm">;
 def HasPerfMon       : Predicate<"Subtarget->hasPerfMon()">;
 def HasFullFP16      : Predicate<"Subtarget->hasFullFP16()">,
-                                 AssemblerPredicate<(all_of FeatureFullFP16), "fullfp16">;
+                                 AssemblerPredicateWithAll<(all_of FeatureFullFP16), "fullfp16">;
 def HasFP16FML       : Predicate<"Subtarget->hasFP16FML()">,
-                                 AssemblerPredicate<(all_of FeatureFP16FML), "fp16fml">;
+                                 AssemblerPredicateWithAll<(all_of FeatureFP16FML), "fp16fml">;
 def HasSPE           : Predicate<"Subtarget->hasSPE()">,
-                                 AssemblerPredicate<(all_of FeatureSPE), "spe">;
+                                 AssemblerPredicateWithAll<(all_of FeatureSPE), "spe">;
 def HasFuseAES       : Predicate<"Subtarget->hasFuseAES()">,
-                                 AssemblerPredicate<(all_of FeatureFuseAES),
+                                 AssemblerPredicateWithAll<(all_of FeatureFuseAES),
                                  "fuse-aes">;
 def HasSVE           : Predicate<"Subtarget->hasSVE()">,
-                                 AssemblerPredicate<(all_of FeatureSVE), "sve">;
+                                 AssemblerPredicateWithAll<(all_of FeatureSVE), "sve">;
 def HasSVE2          : Predicate<"Subtarget->hasSVE2()">,
-                                 AssemblerPredicate<(all_of FeatureSVE2), "sve2">;
+                                 AssemblerPredicateWithAll<(all_of FeatureSVE2), "sve2">;
 def HasSVE2AES       : Predicate<"Subtarget->hasSVE2AES()">,
-                                 AssemblerPredicate<(all_of FeatureSVE2AES), "sve2-aes">;
+                                 AssemblerPredicateWithAll<(all_of FeatureSVE2AES), "sve2-aes">;
 def HasSVE2SM4       : Predicate<"Subtarget->hasSVE2SM4()">,
-                                 AssemblerPredicate<(all_of FeatureSVE2SM4), "sve2-sm4">;
+                                 AssemblerPredicateWithAll<(all_of FeatureSVE2SM4), "sve2-sm4">;
 def HasSVE2SHA3      : Predicate<"Subtarget->hasSVE2SHA3()">,
-                                 AssemblerPredicate<(all_of FeatureSVE2SHA3), "sve2-sha3">;
+                                 AssemblerPredicateWithAll<(all_of FeatureSVE2SHA3), "sve2-sha3">;
 def HasSVE2BitPerm   : Predicate<"Subtarget->hasSVE2BitPerm()">,
-                                 AssemblerPredicate<(all_of FeatureSVE2BitPerm), "sve2-bitperm">;
+                                 AssemblerPredicateWithAll<(all_of FeatureSVE2BitPerm), "sve2-bitperm">;
 def HasSME           : Predicate<"Subtarget->hasSME()">,
-                                 AssemblerPredicate<(all_of FeatureSME), "sme">;
+                                 AssemblerPredicateWithAll<(all_of FeatureSME), "sme">;
 def HasSMEF64        : Predicate<"Subtarget->hasSMEF64()">,
-                                 AssemblerPredicate<(all_of FeatureSMEF64), "sme-f64">;
+                                 AssemblerPredicateWithAll<(all_of FeatureSMEF64), "sme-f64">;
 def HasSMEI64        : Predicate<"Subtarget->hasSMEI64()">,
-                                 AssemblerPredicate<(all_of FeatureSMEI64), "sme-i64">;
+                                 AssemblerPredicateWithAll<(all_of FeatureSMEI64), "sme-i64">;
 // A subset of SVE(2) instructions are legal in Streaming SVE execution mode,
 // they should be enabled if either has been specified.
 def HasSVEorSME
     : Predicate<"Subtarget->hasSVE() || Subtarget->hasSME()">,
-                AssemblerPredicate<(any_of FeatureSVE, FeatureSME),
+                AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME),
                 "sve or sme">;
 def HasSVE2orSME
     : Predicate<"Subtarget->hasSVE2() || Subtarget->hasSME()">,
-                AssemblerPredicate<(any_of FeatureSVE2, FeatureSME),
+                AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSME),
                 "sve2 or sme">;
 // A subset of NEON instructions are legal in Streaming SVE execution mode,
 // they should be enabled if either has been specified.
 def HasNEONorSME
     : Predicate<"Subtarget->hasNEON() || Subtarget->hasSME()">,
-                AssemblerPredicate<(any_of FeatureNEON, FeatureSME),
+                AssemblerPredicateWithAll<(any_of FeatureNEON, FeatureSME),
                 "neon or sme">;
 def HasRCPC          : Predicate<"Subtarget->hasRCPC()">,
-                                 AssemblerPredicate<(all_of FeatureRCPC), "rcpc">;
+                                 AssemblerPredicateWithAll<(all_of FeatureRCPC), "rcpc">;
 def HasLDAPR         : Predicate<"Subtarget->hasLDAPR()">,
-                                 AssemblerPredicate<(all_of FeatureLDAPR), "ldapr">;
+                                 AssemblerPredicateWithAll<(all_of FeatureLDAPR), "ldapr">;
 def HasAltNZCV       : Predicate<"Subtarget->hasAlternativeNZCV()">,
-                       AssemblerPredicate<(all_of FeatureAltFPCmp), "altnzcv">;
+                       AssemblerPredicateWithAll<(all_of FeatureAltFPCmp), "altnzcv">;
 def HasFRInt3264     : Predicate<"Subtarget->hasFRInt3264()">,
-                       AssemblerPredicate<(all_of FeatureFRInt3264), "frint3264">;
+                       AssemblerPredicateWithAll<(all_of FeatureFRInt3264), "frint3264">;
 def HasSB            : Predicate<"Subtarget->hasSB()">,
-                       AssemblerPredicate<(all_of FeatureSB), "sb">;
+                       AssemblerPredicateWithAll<(all_of FeatureSB), "sb">;
 def HasPredRes      : Predicate<"Subtarget->hasPredRes()">,
-                       AssemblerPredicate<(all_of FeaturePredRes), "predres">;
+                       AssemblerPredicateWithAll<(all_of FeaturePredRes), "predres">;
 def HasCCDP          : Predicate<"Subtarget->hasCCDP()">,
-                       AssemblerPredicate<(all_of FeatureCacheDeepPersist), "ccdp">;
+                       AssemblerPredicateWithAll<(all_of FeatureCacheDeepPersist), "ccdp">;
 def HasBTI           : Predicate<"Subtarget->hasBTI()">,
-                       AssemblerPredicate<(all_of FeatureBranchTargetId), "bti">;
+                       AssemblerPredicateWithAll<(all_of FeatureBranchTargetId), "bti">;
 def HasMTE           : Predicate<"Subtarget->hasMTE()">,
-                       AssemblerPredicate<(all_of FeatureMTE), "mte">;
+                       AssemblerPredicateWithAll<(all_of FeatureMTE), "mte">;
 def HasTME           : Predicate<"Subtarget->hasTME()">,
-                       AssemblerPredicate<(all_of FeatureTME), "tme">;
+                       AssemblerPredicateWithAll<(all_of FeatureTME), "tme">;
 def HasETE           : Predicate<"Subtarget->hasETE()">,
-                       AssemblerPredicate<(all_of FeatureETE), "ete">;
+                       AssemblerPredicateWithAll<(all_of FeatureETE), "ete">;
 def HasTRBE          : Predicate<"Subtarget->hasTRBE()">,
-                       AssemblerPredicate<(all_of FeatureTRBE), "trbe">;
+                       AssemblerPredicateWithAll<(all_of FeatureTRBE), "trbe">;
 def HasBF16          : Predicate<"Subtarget->hasBF16()">,
-                       AssemblerPredicate<(all_of FeatureBF16), "bf16">;
+                       AssemblerPredicateWithAll<(all_of FeatureBF16), "bf16">;
 def HasMatMulInt8    : Predicate<"Subtarget->hasMatMulInt8()">,
-                       AssemblerPredicate<(all_of FeatureMatMulInt8), "i8mm">;
+                       AssemblerPredicateWithAll<(all_of FeatureMatMulInt8), "i8mm">;
 def HasMatMulFP32    : Predicate<"Subtarget->hasMatMulFP32()">,
-                       AssemblerPredicate<(all_of FeatureMatMulFP32), "f32mm">;
+                       AssemblerPredicateWithAll<(all_of FeatureMatMulFP32), "f32mm">;
 def HasMatMulFP64    : Predicate<"Subtarget->hasMatMulFP64()">,
-                       AssemblerPredicate<(all_of FeatureMatMulFP64), "f64mm">;
+                       AssemblerPredicateWithAll<(all_of FeatureMatMulFP64), "f64mm">;
 def HasXS            : Predicate<"Subtarget->hasXS()">,
-                       AssemblerPredicate<(all_of FeatureXS), "xs">;
+                       AssemblerPredicateWithAll<(all_of FeatureXS), "xs">;
 def HasWFxT          : Predicate<"Subtarget->hasWFxT()">,
-                       AssemblerPredicate<(all_of FeatureWFxT), "wfxt">;
+                       AssemblerPredicateWithAll<(all_of FeatureWFxT), "wfxt">;
 def HasLS64          : Predicate<"Subtarget->hasLS64()">,
-                       AssemblerPredicate<(all_of FeatureLS64), "ls64">;
+                       AssemblerPredicateWithAll<(all_of FeatureLS64), "ls64">;
 def HasBRBE          : Predicate<"Subtarget->hasBRBE()">,
-                       AssemblerPredicate<(all_of FeatureBRBE), "brbe">;
+                       AssemblerPredicateWithAll<(all_of FeatureBRBE), "brbe">;
 def HasSPE_EEF       : Predicate<"Subtarget->hasSPE_EEF()">,
-                       AssemblerPredicate<(all_of FeatureSPE_EEF), "spe-eef">;
+                       AssemblerPredicateWithAll<(all_of FeatureSPE_EEF), "spe-eef">;
 def HasHBC           : Predicate<"Subtarget->hasHBC()">,
-                       AssemblerPredicate<(all_of FeatureHBC), "hbc">;
+                       AssemblerPredicateWithAll<(all_of FeatureHBC), "hbc">;
 def HasMOPS          : Predicate<"Subtarget->hasMOPS()">,
-                       AssemblerPredicate<(all_of FeatureMOPS), "mops">;
+                       AssemblerPredicateWithAll<(all_of FeatureMOPS), "mops">;
 def IsLE             : Predicate<"Subtarget->isLittleEndian()">;
 def IsBE             : Predicate<"!Subtarget->isLittleEndian()">;
 def IsWindows        : Predicate<"Subtarget->isTargetWindows()">;
 def UseExperimentalZeroingPseudos
     : Predicate<"Subtarget->useExperimentalZeroingPseudos()">;
 def UseAlternateSExtLoadCVTF32
     : Predicate<"Subtarget->useAlternateSExtLoadCVTF32Pattern()">;
 
 def UseNegativeImmediates
-    : Predicate<"false">, AssemblerPredicate<(all_of (not FeatureNoNegativeImmediates)),
+    : Predicate<"false">, AssemblerPredicateWithAll<(all_of (not FeatureNoNegativeImmediates)),
                                              "NegativeImmediates">;
 
 def UseScalarIncVL : Predicate<"Subtarget->useScalarIncVL()">;
 
 def AArch64LocalRecover : SDNode<"ISD::LOCAL_RECOVER",
                                   SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
                                                        SDTCisInt<1>]>>;
 

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 
 include "llvm/TableGen/SearchableTable.td"
 
 //===----------------------------------------------------------------------===//
 // Features that, for the compiler, only enable system operands and PStates
 //===----------------------------------------------------------------------===//
 
 def HasCCPP    : Predicate<"Subtarget->hasCCPP()">,
-                 AssemblerPredicate<(all_of FeatureCCPP), "ccpp">;
+                 AssemblerPredicateWithAll<(all_of FeatureCCPP), "ccpp">;
 
 def HasPAN     : Predicate<"Subtarget->hasPAN()">,
-                 AssemblerPredicate<(all_of FeaturePAN),
+                 AssemblerPredicateWithAll<(all_of FeaturePAN),
                  "ARM v8.1  Privileged Access-Never extension">;
 
 def HasPsUAO   : Predicate<"Subtarget->hasPsUAO()">,
-                 AssemblerPredicate<(all_of FeaturePsUAO),
+                 AssemblerPredicateWithAll<(all_of FeaturePsUAO),
                  "ARM v8.2 UAO PState extension (psuao)">;
 
 def HasPAN_RWV : Predicate<"Subtarget->hasPAN_RWV()">,
-                 AssemblerPredicate<(all_of FeaturePAN_RWV),
+                 AssemblerPredicateWithAll<(all_of FeaturePAN_RWV),
                  "ARM v8.2 PAN AT S1E1R and AT S1E1W Variation">;
 
 def HasCONTEXTIDREL2
                : Predicate<"Subtarget->hasCONTEXTIDREL2()">,
-                 AssemblerPredicate<(all_of FeatureCONTEXTIDREL2),
+                 AssemblerPredicateWithAll<(all_of FeatureCONTEXTIDREL2),
                  "Target contains CONTEXTIDR_EL2 RW operand">;
 
 //===----------------------------------------------------------------------===//
 // AT (address translate) instruction options.
 //===----------------------------------------------------------------------===//
 
 class AT<string name, bits<3> op1, bits<4> crn, bits<4> crm,
          bits<3> op2> : SearchableTable {

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

if (!Name.empty())
     O << Name;
   else
     O << "#" << Val;
 }
 
 static bool isValidSysReg(const AArch64SysReg::SysReg *Reg, bool Read,
                           const MCSubtargetInfo &STI) {
   return (Reg && (Read ? Reg->Readable : Reg->Writeable) &&
-          Reg->haveFeatures(STI.getFeatureBits()));
+          (STI.hasFeature(AArch64::FeatureAll) ||
+           Reg->haveFeatures(STI.getFeatureBits())));
 }
 
 // Looks up a system register either by encoding or by name. Some system
 // registers share the same encoding between different architectures,
 // therefore a tablegen lookup by encoding will return an entry regardless
 // of the register's predication on a specific subtarget feature. To work
 // around this problem we keep an alternative name for such registers and
 // look them up by that name if the first lookup was unsuccessful.

llvm/test/CodeGen/AArch64/mattr-all.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+;; -mattr=+all is not intended to be used for code emitters. Nevertheless,
+;; llc does not reject it. This test intends to catch behavior changes.
+; RUN: llc -mtriple=aarch64 -mattr=+all < %s | FileCheck %s
+
+define half @bf16() nounwind {
+; CHECK-LABEL: bf16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    adrp x8, .LCPI0_0
+; CHECK-NEXT:    ldr h0, [x8, :lo12:.LCPI0_0]
+; CHECK-NEXT:    ret
+  ret half 0xH0000
+}
+
+define i64 @perfmon() nounwind {
+; CHECK-LABEL: perfmon:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x0, xzr
+; CHECK-NEXT:    ret
+  %tmp0 = call i64 @llvm.readcyclecounter()
+  ret i64 %tmp0
+}
+
+declare i64 @llvm.readcyclecounter()

llvm/test/MC/AArch64/armv8.6a-bf16.s

 // RUN:     llvm-mc -triple aarch64 -show-encoding  -mattr=+bf16 < %s       | FileCheck %s
 // RUN:     llvm-mc -triple aarch64 -show-encoding  -mattr=+v8.6a < %s      | FileCheck %s
+// RUN:     llvm-mc -triple aarch64 -show-encoding  -mattr=+all %s          | FileCheck %s
 // RUN: not llvm-mc -triple aarch64 -show-encoding  -mattr=-bf16  < %s 2>&1 | FileCheck %s --check-prefix=NOBF16
 // RUN: not llvm-mc -triple aarch64 -show-encoding  < %s 2>&1 | FileCheck %s --check-prefix=NOBF16
 
 
 bfdot v2.2s, v3.4h, v4.4h
 bfdot v2.4s, v3.8h, v4.8h
 // CHECK: bfdot v2.2s, v3.4h, v4.4h      // encoding: [0x62,0xfc,0x44,0x2e]
 // CHECK: bfdot v2.4s, v3.8h, v4.8h      // encoding: [0x62,0xfc,0x44,0x6e]

llvm/test/MC/AArch64/directive-arch_extension.s

 // RUN: llvm-mc -triple aarch64 -filetype asm -o - %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 --defsym err=1 %s 2>&1 | FileCheck %s --check-prefix=ERR
 
+.ifndef err
 .arch_extension crc
 crc32cx w0, w1, x3
 // CHECK: crc32cx w0, w1, x3
 
 .arch_extension sm4
 sm4e v2.4s, v15.4s
 // CHECK: sm4e v2.4s, v15.4s
 

 .arch_extension hbc
 lbl:
     bc.eq lbl
 // CHECK: bc.eq lbl
 
 .arch_extension mops
 cpyfp [x0]!, [x1]!, x2!
 // CHECK: cpyfp [x0]!, [x1]!, x2!
+.else
+
+.arch_extension all
+// ERR: :[[#@LINE-1]]:17: error: unknown architectural extension: all
+.endif

llvm/test/MC/Disassembler/AArch64/mattr-all.txt

+# RUN: llvm-mc -triple=aarch64 -mattr=+all -disassemble %s 2>&1 | FileCheck %s
+
+## aes
+# CHECK: aese v0.16b, v1.16b
+[0x20,0x48,0x28,0x4e]
+
+## ete
+# CHECK: mrs x0, TRCRSR
+[0x00,0x0a,0x31,0xd5]
+
+## fp16fml
+# CHECK: fmlal v0.2s, v1.2h, v2.2h
+[0x20,0xec,0x22,0x0e]
+
+## armv8.2a ras
+# CHECK: mrs x0, ERRIDR_EL1
+[0x00,0x53,0x38,0xd5]
+
+## armv8.5a mte
+# CHECK: irg x0, x1
+[0x20,0x10,0xdf,0x9a]
+
+## armv8.5a rand
+# CHECK: mrs x0, RNDR
+[0x00,0x24,0x3b,0xd5]
+
+## armv8.6a matmul
+# CHECK: smmla v1.4s, v16.16b, v31.16b
+[0x01,0xa6,0x9f,0x4e]
+
+## armv8.8a-hbc
+# CHECK: bc.eq #4
+[0x30,0x00,0x00,0x54]
+
+## armv9a rme
+# CHECK: mrs x0, MFAR_EL3
+[0xa0,0x60,0x3e,0xd5]

llvm/test/TableGen/AsmPredicateCombining.td

 def AsmCond1 : SubtargetFeature<"cond1", "cond1", "true", "">;
 def AsmCond2a: SubtargetFeature<"cond2a", "cond2a", "true", "">;
 def AsmCond2b: SubtargetFeature<"cond2b", "cond2b", "true", "">;
 def AsmCond3a: SubtargetFeature<"cond3a", "cond3a", "true", "">;
 def AsmCond3b: SubtargetFeature<"cond3b", "cond3b", "true", "">;
 
 def AsmPred1 : Predicate<"Pred1">, AssemblerPredicate<(all_of AsmCond1)>;
 def AsmPred2 : Predicate<"Pred2">, AssemblerPredicate<(all_of AsmCond2a, AsmCond2b)>;
 def AsmPred3 : Predicate<"Pred3">, AssemblerPredicate<(any_of AsmCond3a, AsmCond3b)>;
 // MATCHER:      if (FB[arch::AsmCond1])
 // MATCHER-NEXT:   Features.set(Feature_AsmPred1Bit);
 // MATCHER-NEXT: if (FB[arch::AsmCond2a] && FB[arch::AsmCond2b])
 // MATCHER-NEXT:   Features.set(Feature_AsmPred2Bit);
-// MATCHER-NEXT: if ((FB[arch::AsmCond3a] || FB[arch::AsmCond3b]))
+// MATCHER-NEXT: if (FB[arch::AsmCond3a] || FB[arch::AsmCond3b])
 // MATCHER-NEXT:   Features.set(Feature_AsmPred3Bit);
 
 def insn1 : TestInsn<1, [AsmPred1]>;
 // DISASS: return (Bits[arch::AsmCond1]);
 
 def insn2 : TestInsn<2, [AsmPred2]>;
 // DISASS: return (Bits[arch::AsmCond2a] && Bits[arch::AsmCond2b])
 
 def insn3 : TestInsn<3, [AsmPred3]>;
-// DISASS: return ((Bits[arch::AsmCond3a] || Bits[arch::AsmCond3b]))
+// DISASS: return (Bits[arch::AsmCond3a] || Bits[arch::AsmCond3b])
 
 def insn4 : TestInsn<4, [AsmPred1, AsmPred2]>;
-// DISASS: return (Bits[arch::AsmCond1] && Bits[arch::AsmCond2a] && Bits[arch::AsmCond2b])
+// DISASS: return (Bits[arch::AsmCond1] && (Bits[arch::AsmCond2a] && Bits[arch::AsmCond2b]))
 
 def insn5 : TestInsn<5, [AsmPred1, AsmPred3]>;
 // DISASS: return (Bits[arch::AsmCond1] && (Bits[arch::AsmCond3a] || Bits[arch::AsmCond3b]))
 
 def insn6 : TestInsn<6, []>;
 def : InstAlias<"alias1", (insn6 R0)> { let Predicates = [AsmPred1]; }
 // WRITER:      // (insn6 R0)
 // WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R0},

llvm/utils/TableGen/AsmWriterEmitter.cpp

for (auto &Alias : Aliases.second) {
       for (Record *const R : ReqFeatures) {
         const DagInit *D = R->getValueAsDag("AssemblerCondDag");
         std::string CombineType = D->getOperator()->getAsString();
         if (CombineType != "any_of" && CombineType != "all_of")
           PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
         if (D->getNumArgs() == 0)
           PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
         bool IsOr = CombineType == "any_of";
+        // Concatenate (any_of FeatureAll, (any_of ...)) if FeatureAll is
+        // present.
+        if (IsOr && D->getNumArgs() == 2 && isa<DagInit>(D->getArg(1))) {
+          DagInit *RHS = dyn_cast<DagInit>(D->getArg(1));
+          SmallVector<Init *> Args{D->getArg(0)};
+          SmallVector<StringInit *> ArgNames{D->getArgName(0)};
+          for (unsigned i = 0, e = RHS->getNumArgs(); i != e; ++i) {
+            Args.push_back(RHS->getArg(i));
+            ArgNames.push_back(RHS->getArgName(i));
+          }
+          D = DagInit::get(D->getOperator(), nullptr, Args, ArgNames);
+        }
 
         for (auto *Arg : D->getArgs()) {
           bool IsNeg = false;
           if (auto *NotArg = dyn_cast<DagInit>(Arg)) {
             if (NotArg->getOperator()->getAsString() != "not" ||
                 NotArg->getNumArgs() != 1)
               PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
             Arg = NotArg->getArg(0);

llvm/utils/TableGen/DecoderEmitter.cpp

unsigned getIslands(std::vector<unsigned> &StartBits,
                       std::vector<unsigned> &EndBits,
                       std::vector<uint64_t> &FieldVals,
                       const insn_t &Insn) const;
 
   // Emits code to check the Predicates member of an instruction are true.
   // Returns true if predicate matches were emitted, false otherwise.
   bool emitPredicateMatch(raw_ostream &o, unsigned &Indentation,
                           unsigned Opc) const;
+  bool emitPredicateMatchAux(const Init &Val, bool Outer,
+                             raw_ostream &OS) const;
 
   bool doesOpcodeNeedPredicate(unsigned Opc) const;
   unsigned getPredicateIndex(DecoderTableInfo &TableInfo, StringRef P) const;
   void emitPredicateTableEntry(DecoderTableInfo &TableInfo,
                                unsigned Opc) const;
 
   void emitSoftFailTableEntry(DecoderTableInfo &TableInfo,
                               unsigned Opc) const;
unsigned FilterChooser::getDecoderIndex(DecoderSet &Decoders,
 
   // Make sure the predicate is in the table.
   Decoders.insert(CachedHashString(Decoder));
   // Now figure out the index for when we write out the table.
   DecoderSet::const_iterator P = find(Decoders, Decoder.str());
   return (unsigned)(P - Decoders.begin());
 }
 
+bool FilterChooser::emitPredicateMatchAux(const Init &Val, bool Outer,
+                                          raw_ostream &OS) const {
+  if (auto *D = dyn_cast<DefInit>(&Val)) {
+    if (!D->getDef()->isSubClassOf("SubtargetFeature"))
+      return true;
+    OS << "Bits[" << Emitter->PredicateNamespace << "::" << D->getAsString()
+       << "]";
+    return false;
+  }
+  if (auto *D = dyn_cast<DagInit>(&Val)) {
+    std::string Op = D->getOperator()->getAsString();
+    if (Op == "not" && D->getNumArgs() == 1) {
+      OS << '!';
+      return emitPredicateMatchAux(*D->getArg(0), true, OS);
+    }
+    if ((Op == "any_of" || Op == "all_of") && D->getNumArgs() > 0) {
+      bool Paren = D->getNumArgs() > 1 && std::exchange(Outer, true);
+      if (Paren)
+        OS << '(';
+      ListSeparator LS(Op == "any_of" ? " || " : " && ");
+      for (auto *Arg : D->getArgs()) {
+        OS << LS;
+        if (emitPredicateMatchAux(*Arg, Outer, OS))
+          return true;
+      }
+      if (Paren)
+        OS << ')';
+      return false;
+    }
+  }
+  return true;
+}
+
 bool FilterChooser::emitPredicateMatch(raw_ostream &o, unsigned &Indentation,
                                        unsigned Opc) const {
   ListInit *Predicates =
       AllInstructions[Opc].EncodingDef->getValueAsListInit("Predicates");
   bool IsFirstEmission = true;
   for (unsigned i = 0; i < Predicates->size(); ++i) {
     Record *Pred = Predicates->getElementAsRecord(i);
     if (!Pred->getValue("AssemblerMatcherPredicate"))
       continue;
 
     if (!isa<DagInit>(Pred->getValue("AssemblerCondDag")->getValue()))
       continue;
 
-    const DagInit *D = Pred->getValueAsDag("AssemblerCondDag");
-    std::string CombineType = D->getOperator()->getAsString();
-    if (CombineType != "any_of" && CombineType != "all_of")
-      PrintFatalError(Pred->getLoc(), "Invalid AssemblerCondDag!");
-    if (D->getNumArgs() == 0)
-      PrintFatalError(Pred->getLoc(), "Invalid AssemblerCondDag!");
-    bool IsOr = CombineType == "any_of";
-
     if (!IsFirstEmission)
       o << " && ";
-
-    if (IsOr)
-      o << "(";
-
-    ListSeparator LS(IsOr ? " || " : " && ");
-    for (auto *Arg : D->getArgs()) {
-      o << LS;
-      if (auto *NotArg = dyn_cast<DagInit>(Arg)) {
-        if (NotArg->getOperator()->getAsString() != "not" ||
-            NotArg->getNumArgs() != 1)
-          PrintFatalError(Pred->getLoc(), "Invalid AssemblerCondDag!");
-        Arg = NotArg->getArg(0);
-        o << "!";
-      }
-      if (!isa<DefInit>(Arg) ||
-          !cast<DefInit>(Arg)->getDef()->isSubClassOf("SubtargetFeature"))
-        PrintFatalError(Pred->getLoc(), "Invalid AssemblerCondDag!");
-      o << "Bits[" << Emitter->PredicateNamespace << "::" << Arg->getAsString()
-        << "]";
-    }
-
-    if (IsOr)
-      o << ")";
-
+    if (emitPredicateMatchAux(*Pred->getValueAsDag("AssemblerCondDag"),
+                              Predicates->size() > 1, o))
     IsFirstEmission = false;
   }
   return !Predicates->empty();
 }
 
 bool FilterChooser::doesOpcodeNeedPredicate(unsigned Opc) const {
   ListInit *Predicates =
       AllInstructions[Opc].EncodingDef->getValueAsListInit("Predicates");

llvm/utils/TableGen/SubtargetFeatureInfo.cpp

for (const auto &SF : SubtargetFeatures) {
 
     OS << "  if (" << CondStr << ")\n";
     OS << "    Features.set(" << SFI.getEnumBitName() << ");\n";
   }
   OS << "  return Features;\n";
   OS << "}\n\n";
 }
 
+static bool emitFeaturesAux(StringRef TargetName, const Init &Val, bool Outer,
+                            raw_ostream &OS) {
+  if (auto *D = dyn_cast<DefInit>(&Val)) {
+    if (!D->getDef()->isSubClassOf("SubtargetFeature"))
+      return true;
+    OS << "FB[" << TargetName << "::" << D->getAsString() << "]";
+    return false;
+  }
+  if (auto *D = dyn_cast<DagInit>(&Val)) {
+    std::string Op = D->getOperator()->getAsString();
+    if (Op == "not" && D->getNumArgs() == 1) {
+      OS << '!';
+      return emitFeaturesAux(TargetName, *D->getArg(0), true, OS);
+    }
+    if ((Op == "any_of" || Op == "all_of") && D->getNumArgs() > 0) {
+      bool Paren = D->getNumArgs() > 1 && std::exchange(Outer, true);
+      if (Paren)
+        OS << '(';
+      ListSeparator LS(Op == "any_of" ? " || " : " && ");
+      for (auto *Arg : D->getArgs()) {
+        OS << LS;
+        if (emitFeaturesAux(TargetName, *Arg, Outer, OS))
+          return true;
+      }
+      if (Paren)
+        OS << ')';
+      return false;
+    }
+  }
+  return true;
+}
+
 void SubtargetFeatureInfo::emitComputeAssemblerAvailableFeatures(
     StringRef TargetName, StringRef ClassName, StringRef FuncName,
     SubtargetFeatureInfoMap &SubtargetFeatures, raw_ostream &OS) {
   OS << "FeatureBitset " << TargetName << ClassName << "::\n"
      << FuncName << "(const FeatureBitset &FB) const {\n";
   OS << "  FeatureBitset Features;\n";
   for (const auto &SF : SubtargetFeatures) {
     const SubtargetFeatureInfo &SFI = SF.second;
 
     OS << "  if (";
-
-    const DagInit *D = SFI.TheDef->getValueAsDag("AssemblerCondDag");
-    std::string CombineType = D->getOperator()->getAsString();
-    if (CombineType != "any_of" && CombineType != "all_of")
-      PrintFatalError(SFI.TheDef->getLoc(), "Invalid AssemblerCondDag!");
-    if (D->getNumArgs() == 0)
-      PrintFatalError(SFI.TheDef->getLoc(), "Invalid AssemblerCondDag!");
-    bool IsOr = CombineType == "any_of";
-
-    if (IsOr)
-      OS << "(";
-
-    ListSeparator LS(IsOr ? " || " : " && ");
-    for (auto *Arg : D->getArgs()) {
-      OS << LS;
-      if (auto *NotArg = dyn_cast<DagInit>(Arg)) {
-        if (NotArg->getOperator()->getAsString() != "not" ||
-            NotArg->getNumArgs() != 1)
-          PrintFatalError(SFI.TheDef->getLoc(), "Invalid AssemblerCondDag!");
-        Arg = NotArg->getArg(0);
-        OS << "!";
-      }
-      if (!isa<DefInit>(Arg) ||
-          !cast<DefInit>(Arg)->getDef()->isSubClassOf("SubtargetFeature"))
-        PrintFatalError(SFI.TheDef->getLoc(), "Invalid AssemblerCondDag!");
-      OS << "FB[" << TargetName << "::" << Arg->getAsString() << "]";
-    }
-
-    if (IsOr)
-      OS << ")";
-
+    emitFeaturesAux(TargetName, *SFI.TheDef->getValueAsDag("AssemblerCondDag"),
+                    false, OS);
     OS << ")\n";
     OS << "    Features.set(" << SFI.getEnumBitName() << ");\n";
   }
   OS << "  return Features;\n";
   OS << "}\n\n";
 }