[llvm][AArch64] Fix "+all" feature for sysreg aliases

[DavidSpickett]

Summary

For example the predres extension adds one instruction that
is a sys alias. Previously this wasn't disassembled properly
with "+all".

This was because a check for "+all" was added to haveFeatures
in AArch64SysReg but not in SysAlias.

[DavidSpickett]

clang-format

llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h

struct SysAlias {
   uint16_t Encoding;
   FeatureBitset FeaturesRequired;
 
   constexpr SysAlias(const char *N, uint16_t E) : Name(N), Encoding(E) {}
   constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F)
       : Name(N), Encoding(E), FeaturesRequired(F) {}
 
   bool haveFeatures(FeatureBitset ActiveFeatures) const {
-    return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
+    return ActiveFeatures[llvm::AArch64::FeatureAll] ||
+           (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
   }
 
   FeatureBitset getRequiredFeatures() const { return FeaturesRequired; }
 };
 
 struct SysAliasReg : SysAlias {
   bool NeedsReg;
   constexpr SysAliasReg(const char *N, uint16_t E, bool R)

llvm/test/MC/Disassembler/AArch64/mattr-all.txt

 
 ## armv8.8a-hbc
 # CHECK: bc.eq #4
 [0x30,0x00,0x00,0x54]
 
 ## armv9a rme
 # CHECK: mrs x0, MFAR_EL3
 [0xa0,0x60,0x3e,0xd5]
+
+## predres (to make sure sysreg aliases work)
+# CHECK: cfp rctx, x0
+[0x80,0x73,0x0b,0xd5]