[llvm-objdump] Default to --mcpu=future for PPC64

[MaskRay]

Summary

It's user friendly if a disassembler supports most target features and
tries to disassemble all instructions by default.
Since PowerPC has a future which intends to support all non-conflicting
features, it seems wise to default to it.

[jhenderson]

Seems reasonable to me, but needs a Power PC person to do the review, I think.

Does this behaviour need documenting somewhere?

[nemanjai]

Just for posterity - I have no objections to this in a very delayed post-commit review.

llvm/docs/CommandGuide/llvm-objdump.rst

 
 .. option:: -a, --archive-headers
 
   Display the information contained within an archive's headers.
 
 .. option:: -d, --disassemble
 
   Disassemble all executable sections found in the input files. On some
-  architectures (AArch64, x86), all known instructions are disassembled by
+  architectures (AArch64, PPC64, x86), all known instructions are disassembled by
   default. On the others, :option:`--mcpu` or :option:`--mattr` is needed to
   enable some instruction sets. Disabled instructions are displayed as
   ``<unknown>``.
 
 .. option:: -D, --disassemble-all
 
   Disassemble all sections found in the input files.
 

llvm/lib/Object/ELFObjectFile.cpp

default:
     return SubtargetFeatures();
   }
 }
 
 Optional<StringRef> ELFObjectFileBase::tryGetCPUName() const {
   switch (getEMachine()) {
   case ELF::EM_AMDGPU:
     return getAMDGPUCPUName();
+  case ELF::EM_PPC64:
+    return StringRef("future");
   default:
     return None;
   }
 }
 
 StringRef ELFObjectFileBase::getAMDGPUCPUName() const {
   assert(getEMachine() == ELF::EM_AMDGPU);
   unsigned CPU = getPlatformFlags() & ELF::EF_AMDGPU_MACH;

llvm/test/MC/PowerPC/ppc64-prefix-align-labels.s

# CHECK-LE-NEXT: 8:       40 00 00 48
   trap
   trap
   trap
 1:
 2:  paddi 1, 2, 8589934576, 0  # 8 Byte Instruction
 3:
   blr
 # CHECK-BE:      3c:       60 00 00 00     nop
-# CHECK-BE-NEXT: 40:       06 01 ff ff
-# CHECK-BE-NEXT: 44:       38 22 ff f0
+# CHECK-BE-NEXT: 40:       06 01 ff ff 38 22 ff f0 paddi 1, 2, 8589934576, 0
 # CHECK-BE-NEXT: 48:       4e 80 00 20
 # CHECK-LE:      3c:       00 00 00 60     nop
-# CHECK-LE-NEXT: 40:       ff ff 01 06
-# CHECK-LE-NEXT: 44:       f0 ff 22 38
+# CHECK-LE-NEXT: 40:       ff ff 01 06 f0 ff 22 38 paddi 1, 2, 8589934576, 0
 # CHECK-LE-NEXT: 48:       20 00 80 4e
 

llvm/test/MC/PowerPC/ppc64-prefix-align.s

 paddi 1, 2, 8589934576, 0 # 48
 paddi 1, 2, 8589934576, 0 # 56
 addi 2, 3, 15             # 60
 # Below the lines 40: and 44: contain the 8 byte instruction.
 # We check to make sure that the nop is added at 3c: so that the 8 byte
 # instruction can start at 40: which is 64 bytes aligned.
 # CHECK-BE:      38:  38 43 00 0f
 # CHECK-BE-NEXT: 3c:  60 00 00 00   nop
-# CHECK-BE-NEXT: 40:  06 01 ff ff
-# CHECK-BE-NEXT: 44:  38 22 ff f0
+# CHECK-BE-NEXT: 40:  06 01 ff ff 38 22 ff f0  paddi 1, 2, 8589934576, 0
 # CHECK-LE:      38:  0f 00 43 38
 # CHECK-LE-NEXT: 3c:  00 00 00 60   nop
-# CHECK-LE-NEXT: 40:  ff ff 01 06
-# CHECK-LE-NEXT: 44:  f0 ff 22 38
+# CHECK-LE-NEXT: 40:  ff ff 01 06 f0 ff 22 38  paddi 1, 2, 8589934576, 0
 paddi 1, 2, 8589934576, 0
 paddi 1, 2, 8589934576, 0
 paddi 1, 2, 8589934576, 0
 paddi 1, 2, 8589934576, 0
 paddi 1, 2, 8589934576, 0
 paddi 1, 2, 8589934576, 0
 paddi 1, 2, 8589934576, 0
 paddi 1, 2, 8589934576, 0 # 64
 paddi 1, 2, 8589934576, 0
 paddi 1, 2, 8589934576, 0
 paddi 1, 2, 8589934576, 0
 paddi 1, 2, 8589934576, 0
 paddi 1, 2, 8589934576, 0
 paddi 1, 2, 8589934576, 0
 paddi 1, 2, 8589934576, 0
 addi 2, 3, 15             # 60
 # CHECK-BE:      b8:  38 43 00 0f
 # CHECK-BE-NEXT: bc:  60 00 00 00   nop
 # CHECK-BE:      <LAB1>:
-# CHECK-BE-NEXT: c0:  06 01 ff ff
-# CHECK-BE-NEXT: c4:  38 22 ff f0
+# CHECK-BE-NEXT: c0:  06 01 ff ff 38 22 ff f0  paddi 1, 2, 8589934576, 0
 # CHECK-LE:      b8:  0f 00 43 38
 # CHECK-LE-NEXT: bc:  00 00 00 60   nop
 # CHECK-LE:      <LAB1>:
-# CHECK-LE-NEXT: c0:  ff ff 01 06
-# CHECK-LE-NEXT: c4:  f0 ff 22 38
+# CHECK-LE-NEXT: c0:  ff ff 01 06 f0 ff 22 38  paddi 1, 2, 8589934576, 0
 LAB1: paddi 1, 2, 8589934576, 0
 paddi 1, 2, 8589934576, 0
 paddi 1, 2, 8589934576, 0
 paddi 1, 2, 8589934576, 0
 paddi 1, 2, 8589934576, 0
 paddi 1, 2, 8589934576, 0
 paddi 1, 2, 8589934576, 0
 addi 2, 3, 15             # 60
 # CHECK-BE:      f8:  38 43 00 0f
 # CHECK-BE:      <LAB2>:
 # CHECK-BE-NEXT: fc:  60 00 00 00   nop
-# CHECK-BE-NEXT: 100: 06 01 ff ff
-# CHECK-BE-NEXT: 104: 38 22 ff f0
+# CHECK-BE-NEXT: 100: 06 01 ff ff 38 22 ff f0  paddi 1, 2, 8589934576, 0
 # CHECK-LE:      f8:  0f 00 43 38
 # CHECK-LE:      <LAB2>:
 # CHECK-LE-NEXT: fc:  00 00 00 60   nop
-# CHECK-LE-NEXT: 100: ff ff 01 06
-# CHECK-LE-NEXT: 104: f0 ff 22 38
+# CHECK-LE-NEXT: 100: ff ff 01 06 f0 ff 22 38  paddi 1, 2, 8589934576, 0
 LAB2:
   paddi 1, 2, 8589934576, 0
 
 
 

llvm/test/tools/llvm-objdump/ELF/PowerPC/mcpu.s

+## Test that we default to --mcpu=future and disassemble all known instructions.
+## The default is different from producers (e.g. Clang).
+# RUN: llvm-mc -triple=powerpc64le -filetype=obj %s -o %t
+# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s --check-prefixes=CHECK,FUTURE
+# RUN: llvm-objdump -d --no-show-raw-insn --mcpu=future %t | FileCheck %s --check-prefixes=CHECK,FUTURE
+# RUN: llvm-objdump -d --no-show-raw-insn --mcpu=pwr9 %t | FileCheck %s --check-prefixes=CHECK,UNKNOWN
+
+# CHECK-LABEL: <_start>:
+# FUTURE-NEXT:   pld 3, 0(0), 1
+# UNKNOWN-COUNT-2: <unknown>
+# CHECK-EMPTY:
+
+.globl _start
+_start:
+  pld 3, 0(0), 1