[RISCV] Use knowledge of VLEN to avoid over-aligning the stack

[frasercrmck]

Summary

With D125787, the size of the RVV portion of the stack is a
16-byte-aligned to help maintain the overall alignment of the stack as a
whole. Alignments of the RVV objects themselves are also correctly
aligned.

The naive implementation in that patch ensured these alignments while
ignoring the effect that the implicit multiplication by VLENB has on
alignment. Since VLEN is a power of two we often take on extra
alignment when calculating the final object offsets.

This patch now takes VLEN into account when calculating RVV object
offsets by reducing the required alignment by the known 8-byte multiple
we receive from VLEN.

[reames]

I'm a bit confused by this patch. Where does the VLEN > 32 bit come from? All I kind find in the spec is that VLEN >= ELEN, and must be a power of 2. Given ELEN only has to be 8, shouldn't the smallest VLEN also be 8? This seems like an utterly useless configuration, but the spec seems to allow it?

[craig.topper]

In D126465#3540599, @reames wrote:

I'm a bit confused by this patch. Where does the VLEN > 32 bit come from? All I kind find in the spec is that VLEN >= ELEN, and must be a power of 2. Given ELEN only has to be 8, shouldn't the smallest VLEN also be 8? This seems like an utterly useless configuration, but the spec seems to allow it?

VLEN is determined by the Zvl32b, Zvl64b, Zvl128b, etc. extensions. V implies Zvl128b. Zve64* implies Zvl64b. Zve32* implies Zvl32b. VLEN can never be less than 32 with the currently defined extensions. And our support VLEN == 32 is broken in many ways. We should probably discuss that at some point.

[craig.topper]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

928

VLEN can be 32. But our calculation of vscale and scalable types is broken for it.

[reames]

In D126465#3540602, @craig.topper wrote:

In D126465#3540599, @reames wrote:

I'm a bit confused by this patch. Where does the VLEN > 32 bit come from? All I kind find in the spec is that VLEN >= ELEN, and must be a power of 2. Given ELEN only has to be 8, shouldn't the smallest VLEN also be 8? This seems like an utterly useless configuration, but the spec seems to allow it?

VLEN is determined by the Zvl32b, Zvl64b, Zvl128b, etc. extensions. V implies Zvl128b. Zve64* implies Zvl64b. Zve32* implies Zvl32b. VLEN can never be less than 32 with the currently defined extensions.

Thanks for the pointer. The wording here is as follows:
"Note: Explicit use of the Zvl32b extension string is not required for any standard vector extension as they all effectively mandate at least this minimum, but the string can be useful when stating hardware capabilities."

Reviewing 18.2 and 18.3 confirms that none of the proposed vector variants allow VLEN < 32.

[frasercrmck]

In D126465#3540710, @reames wrote:

In D126465#3540602, @craig.topper wrote:

In D126465#3540599, @reames wrote:

I'm a bit confused by this patch. Where does the VLEN > 32 bit come from? All I kind find in the spec is that VLEN >= ELEN, and must be a power of 2. Given ELEN only has to be 8, shouldn't the smallest VLEN also be 8? This seems like an utterly useless configuration, but the spec seems to allow it?

VLEN is determined by the Zvl32b, Zvl64b, Zvl128b, etc. extensions. V implies Zvl128b. Zve64* implies Zvl64b. Zve32* implies Zvl32b. VLEN can never be less than 32 with the currently defined extensions.

Thanks for the pointer. The wording here is as follows:
"Note: Explicit use of the Zvl32b extension string is not required for any standard vector extension as they all effectively mandate at least this minimum, but the string can be useful when stating hardware capabilities."

Reviewing 18.2 and 18.3 confirms that none of the proposed vector variants allow VLEN < 32.

It's a fair point. I don't really suppose it's worth mentioning that it's at least 32 as this should work for any power of two at least 8. Do you think specifically mentioning 32 may make people assume it relies on that property?

A note on this patch I forgot to add yesterday - it does affect the nominal offsets we compute for RVV frame objects (see wrong-stack-offset-for-rvv-object.mir - the object is now "at" offset -8 rather than -16). Another option could be to keep the offset calculation as it is now but change how we materialize the instructions to reach those offsets. I thought this way was perhaps slightly cleaner and less error-prone: it's one place, rather than forcing all disparate users of this info to compute offsets correctly. Just it crossed my mind that someone reading offset: -8 may be forgiven for thinking that we're not correctly aligning objects. Let me know what you think. I think both ways have their drawbacks - neither are super intuitive.

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

928

Ah yes, thanks - slip of the fingers. I wanted to say greater than or equal to 32. It's probably not worth a caveat here that we don't properly support 32 here, is it? It's largely irrelevant since the calculation works for any power of two.

[frasercrmck]

rebase/ping

[reames]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

924

Everything above this line appears to be an NFC change + an early return. Please split that, land, and rebase.

This is minor, but since I've now looked at this code several time when glancing at this patch, I'd rather not spend time glancing at it again.

936

This really doesn't look correct to me.

Given an object aligned to 32 bytes, knowing that it's a multiple of 16 bytes does not allow you to align it only to 2 bytes. Which, unless I'm missing something, is what this code does.

I think what you need here is to compute the running alignment, use the MinVLen information to update that alignment, then if the required alignment is greater than that, adjust the offset.

It's entirely possible I'm misreading this though. Having a ObjectSize which is a integer for an object which is inherently variable sized doesn't make sense to me. I'm not entirely sure what ObjectSize actually represents here. Maybe there's just some missing comments in the original code?

[frasercrmck]

rebase on split patch

[frasercrmck]

fix typo

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

924

Landed separately, thanks for the suggestion.

928

(finally) fixed this typo.

936

Right, that's basically what it does. I think it's correct.

The ObjectSize is the "known min size" portion of the scalable type size in bytes. The scalable portion is implicitly left for us (the target) to handle. We're artificially lowering the scalable parts of the offsets knowing that they'll all later be multiplied by VLENB. Since we're in control of the vscale multiplying, as long as all scalable objects are consistently treated in this manner, it should work out correct.

[kito-cheng]

LGTM

[frasercrmck]

rebase

[frasercrmck]

restore manual mir test checks for wrong-stack-offset-for-rvv-object

[frasercrmck]

Thanks for the review, @kito-cheng! I'll use this opportunity to ping this patch once again as I'm not super comfortable landing it if there's still objections from people, e.g. @reames

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

RISCVFrameLowering::assignRVVStackObjectOffsets(MachineFunction &MF) const {
   // The minimum alignment is 16 bytes.
   Align RVVStackAlign(16);
   const auto &ST = MF.getSubtarget<RISCVSubtarget>();
 
   if (!ST.hasVInstructions()) {
     assert(ObjectsToAllocate.empty() &&
            "Can't allocate scalable-vector objects without V instructions");
     return std::make_pair(0, RVVStackAlign);
   }
 
+  // All offsets here are multiplied by VLENB, which carries with it its own
+  // alignment. We can take this into account to avoid over-aligning the stack.
+  // Since VLEN is always a power of two greater than 32, knowing the minimum
+  // VLEN is enough to ensure the same alignment with larger VLENs.
+  auto VLenBits = ST.getRealMinVLen();
+  const unsigned VLenKnown8ByteMultiple = std::max(VLenBits, 64u) / 64;
+
+  auto AlignWithImplicitVLenAlign = [VLenKnown8ByteMultiple](Align A) {
+    return MaybeAlign(A.value() / VLenKnown8ByteMultiple).valueOrOne();
+  };
+
   // Allocate all RVV locals and spills
   int64_t Offset = 0;
   for (int FI : ObjectsToAllocate) {
     // ObjectSize in bytes.
     int64_t ObjectSize = MFI.getObjectSize(FI);
     auto ObjectAlign = std::max(Align(8), MFI.getObjectAlign(FI));
     // If the data type is the fractional vector type, reserve one vector
     // register for it.
     if (ObjectSize < 8)
       ObjectSize = 8;
-    Offset = alignTo(Offset + ObjectSize, ObjectAlign);
+    Offset =
+        alignTo(Offset + ObjectSize, AlignWithImplicitVLenAlign(ObjectAlign));
     MFI.setObjectOffset(FI, -Offset);
     // Update the maximum alignment of the RVV stack section
     RVVStackAlign = std::max(RVVStackAlign, ObjectAlign);
   }
 
   // Ensure the alignment of the RVV stack. Since we want the most-aligned
   // object right at the bottom (i.e., any padding at the top of the frame),
   // readjust all RVV objects down by the alignment padding.
   uint64_t StackSize = Offset;
-  if (auto AlignmentPadding = offsetToAlignment(StackSize, RVVStackAlign)) {
+  if (auto AlignmentPadding = offsetToAlignment(
+          StackSize, AlignWithImplicitVLenAlign(RVVStackAlign))) {
     StackSize += AlignmentPadding;
     for (int FI : ObjectsToAllocate)
       MFI.setObjectOffset(FI, MFI.getObjectOffset(FI) - AlignmentPadding);
   }
 
   return std::make_pair(StackSize, RVVStackAlign);
 }
 

llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll

 @__const._Z3foov.var_40 = private unnamed_addr constant [2 x i16] [i16 -19932, i16 -26252], align 2
 
 define void @_Z3foov() {
 ; CHECK-LABEL: _Z3foov:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    li a1, 10
-; CHECK-NEXT:    mul a0, a0, a1
+; CHECK-NEXT:    slli a1, a0, 3
+; CHECK-NEXT:    add a0, a1, a0
 ; CHECK-NEXT:    sub sp, sp, a0
 ; CHECK-NEXT:    lui a0, %hi(.L__const._Z3foov.var_49)
 ; CHECK-NEXT:    addi a0, a0, %lo(.L__const._Z3foov.var_49)
 ; CHECK-NEXT:    vsetivli zero, 2, e16, m2, ta, mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    lui a0, %hi(.L__const._Z3foov.var_48)
 ; CHECK-NEXT:    addi a0, a0, %lo(.L__const._Z3foov.var_48)
 ; CHECK-NEXT:    vle8.v v10, (a0)

 ; CHECK-NEXT:    add a0, sp, a0
 ; CHECK-NEXT:    addi a0, a0, 16
 ; CHECK-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
 ; CHECK-NEXT:    vsext.vf2 v10, v8, v0.t
 ; CHECK-NEXT:    lui a0, %hi(var_47)
 ; CHECK-NEXT:    addi a0, a0, %lo(var_47)
 ; CHECK-NEXT:    vsseg4e16.v v10, (a0)
 ; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    li a1, 10
-; CHECK-NEXT:    mul a0, a0, a1
+; CHECK-NEXT:    slli a1, a0, 3
+; CHECK-NEXT:    add a0, a1, a0
 ; CHECK-NEXT:    add sp, sp, a0
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
 entry:
   %0 = tail call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.i64(<vscale x 8 x i16> undef, ptr nonnull @__const._Z3foov.var_49, i64 2)
   %1 = tail call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.i64(<vscale x 8 x i8> undef, ptr nonnull @__const._Z3foov.var_48, i64 2)
   %2 = tail call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.i64(<vscale x 8 x i16> undef, ptr nonnull @__const._Z3foov.var_46, i64 2)
   %3 = tail call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.i64(<vscale x 8 x i16> undef, ptr nonnull @__const._Z3foov.var_45, i64 2)

llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll

declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(
   i64);
 
 define <vscale x 1 x i64> @access_fixed_and_vector_objects(i64 *%val) {
 ; RV64IV-LABEL: access_fixed_and_vector_objects:
 ; RV64IV:       # %bb.0:
 ; RV64IV-NEXT:    addi sp, sp, -528
 ; RV64IV-NEXT:    .cfi_def_cfa_offset 528
 ; RV64IV-NEXT:    csrr a0, vlenb
-; RV64IV-NEXT:    slli a0, a0, 1
 ; RV64IV-NEXT:    sub sp, sp, a0
 ; RV64IV-NEXT:    addi a0, sp, 8
 ; RV64IV-NEXT:    vl1re64.v v8, (a0)
 ; RV64IV-NEXT:    addi a0, sp, 528
 ; RV64IV-NEXT:    ld a1, 520(sp)
 ; RV64IV-NEXT:    vl1re64.v v9, (a0)
 ; RV64IV-NEXT:    vsetvli zero, a1, e64, m1, ta, mu
 ; RV64IV-NEXT:    vadd.vv v8, v8, v9
 ; RV64IV-NEXT:    csrr a0, vlenb
-; RV64IV-NEXT:    slli a0, a0, 1
 ; RV64IV-NEXT:    add sp, sp, a0
 ; RV64IV-NEXT:    addi sp, sp, 528
 ; RV64IV-NEXT:    ret
   %local = alloca i64
   %vector = alloca <vscale x 1 x i64>
   %array = alloca [64 x i64]
   %vptr = bitcast [64 x i64]* %array to <vscale x 1 x i64>*
   %v1 = load <vscale x 1 x i64>, <vscale x 1 x i64>* %vptr

llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir

bb.0:
     ; CHECK-NEXT: SD killed $x1, $x2, 2024 :: (store (s64) into %stack.3)
     ; CHECK-NEXT: SD killed $x8, $x2, 2016 :: (store (s64) into %stack.4)
     ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8
     ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16
     ; CHECK-NEXT: $x8 = frame-setup ADDI $x2, 2032
     ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $x8, 0
     ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -240
     ; CHECK-NEXT: $x12 = frame-setup PseudoReadVLENB
-    ; CHECK-NEXT: $x12 = frame-setup SLLI killed $x12, 1
     ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x12
     ; CHECK-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x11, 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
     ; CHECK-NEXT: renamable $v8 = PseudoVLE64_V_M1 killed renamable $x10, $noreg, 6 /* e64 */, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
     ; CHECK-NEXT: $x11 = PseudoReadVLENB
-    ; CHECK-NEXT: $x11 = SLLI killed $x11, 1
     ; CHECK-NEXT: $x10 = LUI 1048575
     ; CHECK-NEXT: $x10 = ADDIW killed $x10, 1824
     ; CHECK-NEXT: $x10 = ADD $x8, killed $x10
     ; CHECK-NEXT: $x10 = SUB killed $x10, killed $x11
     ; CHECK-NEXT: VS1R_V killed renamable $v8, killed renamable $x10
     ; CHECK-NEXT: $x2 = frame-destroy ADDI $x8, -2048
     ; CHECK-NEXT: $x2 = frame-destroy ADDI killed $x2, -224
     ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 240

llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s \
-; RUN:    | FileCheck %s
+; RUN:    | FileCheck %s --check-prefixes=CHECK,NOZBA
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zba -verify-machineinstrs < %s \
-; RUN:    | FileCheck %s
+; RUN:    | FileCheck %s --check-prefixes=CHECK,ZBA
 
 define void @lmul1() nounwind {
 ; CHECK-LABEL: lmul1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    slli a0, a0, 1
 ; CHECK-NEXT:    sub sp, sp, a0
 ; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    slli a0, a0, 1
 ; CHECK-NEXT:    add sp, sp, a0
 ; CHECK-NEXT:    ret
   %v = alloca <vscale x 1 x i64>
   ret void
 }
 
 define void @lmul2() nounwind {
 ; CHECK-LABEL: lmul2:

 ; CHECK-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 80
 ; CHECK-NEXT:    ret
   %v = alloca <vscale x 8 x i64>
   ret void
 }
 
 define void @lmul1_and_2() nounwind {
-; CHECK-LABEL: lmul1_and_2:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    slli a0, a0, 2
-; CHECK-NEXT:    sub sp, sp, a0
-; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    slli a0, a0, 2
-; CHECK-NEXT:    add sp, sp, a0
-; CHECK-NEXT:    ret
+; NOZBA-LABEL: lmul1_and_2:
+; NOZBA:       # %bb.0:
+; NOZBA-NEXT:    csrr a0, vlenb
+; NOZBA-NEXT:    slli a1, a0, 1
+; NOZBA-NEXT:    add a0, a1, a0
+; NOZBA-NEXT:    sub sp, sp, a0
+; NOZBA-NEXT:    csrr a0, vlenb
+; NOZBA-NEXT:    slli a1, a0, 1
+; NOZBA-NEXT:    add a0, a1, a0
+; NOZBA-NEXT:    add sp, sp, a0
+; NOZBA-NEXT:    ret
+;
+; ZBA-LABEL: lmul1_and_2:
+; ZBA:       # %bb.0:
+; ZBA-NEXT:    csrr a0, vlenb
+; ZBA-NEXT:    sh1add a0, a0, a0
+; ZBA-NEXT:    sub sp, sp, a0
+; ZBA-NEXT:    csrr a0, vlenb
+; ZBA-NEXT:    sh1add a0, a0, a0
+; ZBA-NEXT:    add sp, sp, a0
+; ZBA-NEXT:    ret
   %v1 = alloca <vscale x 1 x i64>
   %v2 = alloca <vscale x 2 x i64>
   ret void
 }
 
 define void @lmul2_and_4() nounwind {
 ; CHECK-LABEL: lmul2_and_4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -48
 ; CHECK-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    addi s0, sp, 48
 ; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    slli a0, a0, 3
+; CHECK-NEXT:    li a1, 6
+; CHECK-NEXT:    mul a0, a0, a1
 ; CHECK-NEXT:    sub sp, sp, a0
 ; CHECK-NEXT:    andi sp, sp, -32
 ; CHECK-NEXT:    addi sp, s0, -48
 ; CHECK-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 48
 ; CHECK-NEXT:    ret
   %v1 = alloca <vscale x 2 x i64>
   %v2 = alloca <vscale x 4 x i64>
   ret void
 }
 
 define void @lmul1_and_4() nounwind {
 ; CHECK-LABEL: lmul1_and_4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -48
 ; CHECK-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    addi s0, sp, 48
 ; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    slli a0, a0, 3
+; CHECK-NEXT:    li a1, 6
+; CHECK-NEXT:    mul a0, a0, a1
 ; CHECK-NEXT:    sub sp, sp, a0
 ; CHECK-NEXT:    andi sp, sp, -32
 ; CHECK-NEXT:    addi sp, s0, -48
 ; CHECK-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 48
 ; CHECK-NEXT:    ret
   %v1 = alloca <vscale x 1 x i64>
   %v2 = alloca <vscale x 4 x i64>
   ret void
 }
 
 define void @lmul2_and_1() nounwind {
-; CHECK-LABEL: lmul2_and_1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    slli a0, a0, 2
-; CHECK-NEXT:    sub sp, sp, a0
-; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    slli a0, a0, 2
-; CHECK-NEXT:    add sp, sp, a0
-; CHECK-NEXT:    ret
+; NOZBA-LABEL: lmul2_and_1:
+; NOZBA:       # %bb.0:
+; NOZBA-NEXT:    csrr a0, vlenb
+; NOZBA-NEXT:    slli a1, a0, 1
+; NOZBA-NEXT:    add a0, a1, a0
+; NOZBA-NEXT:    sub sp, sp, a0
+; NOZBA-NEXT:    csrr a0, vlenb
+; NOZBA-NEXT:    slli a1, a0, 1
+; NOZBA-NEXT:    add a0, a1, a0
+; NOZBA-NEXT:    add sp, sp, a0
+; NOZBA-NEXT:    ret
+;
+; ZBA-LABEL: lmul2_and_1:
+; ZBA:       # %bb.0:
+; ZBA-NEXT:    csrr a0, vlenb
+; ZBA-NEXT:    sh1add a0, a0, a0
+; ZBA-NEXT:    sub sp, sp, a0
+; ZBA-NEXT:    csrr a0, vlenb
+; ZBA-NEXT:    sh1add a0, a0, a0
+; ZBA-NEXT:    add sp, sp, a0
+; ZBA-NEXT:    ret
   %v1 = alloca <vscale x 2 x i64>
   %v2 = alloca <vscale x 1 x i64>
   ret void
 }
 
 define void @lmul4_and_1() nounwind {
 ; CHECK-LABEL: lmul4_and_1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -48
 ; CHECK-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    addi s0, sp, 48
 ; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    slli a0, a0, 3
+; CHECK-NEXT:    li a1, 6
+; CHECK-NEXT:    mul a0, a0, a1
 ; CHECK-NEXT:    sub sp, sp, a0
 ; CHECK-NEXT:    andi sp, sp, -32
 ; CHECK-NEXT:    addi sp, s0, -48
 ; CHECK-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 48
 ; CHECK-NEXT:    ret
   %v1 = alloca <vscale x 4 x i64>
   %v2 = alloca <vscale x 1 x i64>
   ret void
 }
 
 define void @lmul4_and_2() nounwind {
 ; CHECK-LABEL: lmul4_and_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -48
 ; CHECK-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    addi s0, sp, 48
 ; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    slli a0, a0, 3
+; CHECK-NEXT:    li a1, 6
+; CHECK-NEXT:    mul a0, a0, a1
 ; CHECK-NEXT:    sub sp, sp, a0
 ; CHECK-NEXT:    andi sp, sp, -32
 ; CHECK-NEXT:    addi sp, s0, -48
 ; CHECK-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 48
 ; CHECK-NEXT:    ret
   %v1 = alloca <vscale x 4 x i64>
   %v2 = alloca <vscale x 2 x i64>
   ret void
 }
 
 define void @lmul4_and_2_x2_0() nounwind {
 ; CHECK-LABEL: lmul4_and_2_x2_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -48
 ; CHECK-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    addi s0, sp, 48
 ; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    slli a0, a0, 4
+; CHECK-NEXT:    li a1, 12
+; CHECK-NEXT:    mul a0, a0, a1
 ; CHECK-NEXT:    sub sp, sp, a0
 ; CHECK-NEXT:    andi sp, sp, -32
 ; CHECK-NEXT:    addi sp, s0, -48
 ; CHECK-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 48
 ; CHECK-NEXT:    ret
   %v1 = alloca <vscale x 4 x i64>
; CHECK-NEXT:    ret
   %v3 = alloca <vscale x 4 x i64>
   %v2 = alloca <vscale x 2 x i64>
   %v4 = alloca <vscale x 2 x i64>
   ret void
 }
 
 
 define void @gpr_and_lmul1_and_2() nounwind {
-; CHECK-LABEL: gpr_and_lmul1_and_2:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    slli a0, a0, 2
-; CHECK-NEXT:    sub sp, sp, a0
-; CHECK-NEXT:    li a0, 3
-; CHECK-NEXT:    sd a0, 8(sp)
-; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    slli a0, a0, 2
-; CHECK-NEXT:    add sp, sp, a0
-; CHECK-NEXT:    addi sp, sp, 16
-; CHECK-NEXT:    ret
+; NOZBA-LABEL: gpr_and_lmul1_and_2:
+; NOZBA:       # %bb.0:
+; NOZBA-NEXT:    addi sp, sp, -16
+; NOZBA-NEXT:    csrr a0, vlenb
+; NOZBA-NEXT:    slli a1, a0, 1
+; NOZBA-NEXT:    add a0, a1, a0
+; NOZBA-NEXT:    sub sp, sp, a0
+; NOZBA-NEXT:    li a0, 3
+; NOZBA-NEXT:    sd a0, 8(sp)
+; NOZBA-NEXT:    csrr a0, vlenb
+; NOZBA-NEXT:    slli a1, a0, 1
+; NOZBA-NEXT:    add a0, a1, a0
+; NOZBA-NEXT:    add sp, sp, a0
+; NOZBA-NEXT:    addi sp, sp, 16
+; NOZBA-NEXT:    ret
+;
+; ZBA-LABEL: gpr_and_lmul1_and_2:
+; ZBA:       # %bb.0:
+; ZBA-NEXT:    addi sp, sp, -16
+; ZBA-NEXT:    csrr a0, vlenb
+; ZBA-NEXT:    sh1add a0, a0, a0
+; ZBA-NEXT:    sub sp, sp, a0
+; ZBA-NEXT:    li a0, 3
+; ZBA-NEXT:    sd a0, 8(sp)
+; ZBA-NEXT:    csrr a0, vlenb
+; ZBA-NEXT:    sh1add a0, a0, a0
+; ZBA-NEXT:    add sp, sp, a0
+; ZBA-NEXT:    addi sp, sp, 16
+; ZBA-NEXT:    ret
   %x1 = alloca i64
   %v1 = alloca <vscale x 1 x i64>
   %v2 = alloca <vscale x 2 x i64>
   store volatile i64 3, i64* %x1
   ret void
 }
 
 define void @gpr_and_lmul1_and_4() nounwind {
 ; CHECK-LABEL: gpr_and_lmul1_and_4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -48
 ; CHECK-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    addi s0, sp, 48
 ; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    slli a0, a0, 3
+; CHECK-NEXT:    li a1, 6
+; CHECK-NEXT:    mul a0, a0, a1
 ; CHECK-NEXT:    sub sp, sp, a0
 ; CHECK-NEXT:    andi sp, sp, -32
 ; CHECK-NEXT:    li a0, 3
 ; CHECK-NEXT:    sd a0, 8(sp)
 ; CHECK-NEXT:    addi sp, s0, -48
 ; CHECK-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 48

llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir

body:             |
   ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $x24, -72
   ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $x25, -80
   ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $x26, -88
   ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $x27, -96
   ; CHECK-NEXT:   $x8 = frame-setup ADDI $x2, 2032
   ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa $x8, 0
   ; CHECK-NEXT:   $x2 = frame-setup ADDI $x2, -272
   ; CHECK-NEXT:   $x10 = frame-setup PseudoReadVLENB
-  ; CHECK-NEXT:   $x11 = frame-setup ADDI killed $x0, 52
+  ; CHECK-NEXT:   $x11 = frame-setup ADDI killed $x0, 51
   ; CHECK-NEXT:   $x10 = frame-setup MUL killed $x10, killed $x11
   ; CHECK-NEXT:   $x2 = frame-setup SUB $x2, killed $x10
   ; CHECK-NEXT:   $x2 = frame-setup ANDI $x2, -128
   ; CHECK-NEXT:   dead renamable $x15 = PseudoVSETIVLI 1, 72 /* e16, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
   ; CHECK-NEXT:   renamable $v25 = PseudoVMV_V_X_M1 killed renamable $x12, $noreg, 4 /* e16 */, implicit $vl, implicit $vtype
   ; CHECK-NEXT:   $x11 = PseudoReadVLENB
   ; CHECK-NEXT:   $x10 = ADDI killed $x0, 50
   ; CHECK-NEXT:   $x11 = MUL killed $x11, killed $x10

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll

 ; RV32-NEXT:    vsoxei32.v v16, (a0), v8, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vpscatter_baseidx_v32i32_v32f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
 ; RV64-NEXT:    csrr a3, vlenb
-; RV64-NEXT:    li a4, 10
-; RV64-NEXT:    mul a3, a3, a4
+; RV64-NEXT:    slli a4, a3, 3
+; RV64-NEXT:    add a3, a4, a3
 ; RV64-NEXT:    sub sp, sp, a3
 ; RV64-NEXT:    li a3, 32
 ; RV64-NEXT:    vsetvli zero, a3, e32, m8, ta, mu
 ; RV64-NEXT:    vle32.v v24, (a1)
 ; RV64-NEXT:    csrr a1, vlenb
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vs8r.v v24, (a1) # Unknown-size Folded Spill

 ; RV64-NEXT:    vl8re8.v v8, (a2) # Unknown-size Folded Reload
 ; RV64-NEXT:    vslidedown.vi v8, v8, 16
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf2 v24, v8
 ; RV64-NEXT:    vsll.vi v8, v24, 3
 ; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
 ; RV64-NEXT:    vsoxei64.v v16, (a0), v8, v0.t
 ; RV64-NEXT:    csrr a0, vlenb
-; RV64-NEXT:    li a1, 10
-; RV64-NEXT:    mul a0, a0, a1
+; RV64-NEXT:    slli a1, a0, 3
+; RV64-NEXT:    add a0, a1, a0
 ; RV64-NEXT:    add sp, sp, a0
 ; RV64-NEXT:    addi sp, sp, 16
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds double, double* %base, <32 x i32> %idxs
   call void @llvm.vp.scatter.v32f64.v32p0f64(<32 x double> %val, <32 x double*> %ptrs, <32 x i1> %m, i32 %evl)
   ret void
 }
 

llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll

 ; CHECK-NEXT:    sd s0, 80(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    sd s1, 72(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    .cfi_offset ra, -8
 ; CHECK-NEXT:    .cfi_offset s0, -16
 ; CHECK-NEXT:    .cfi_offset s1, -24
 ; CHECK-NEXT:    addi s0, sp, 96
 ; CHECK-NEXT:    .cfi_def_cfa s0, 0
 ; CHECK-NEXT:    csrr a1, vlenb
-; CHECK-NEXT:    slli a1, a1, 1
 ; CHECK-NEXT:    sub sp, sp, a1
 ; CHECK-NEXT:    andi sp, sp, -16
 ; CHECK-NEXT:    mv s1, sp
 ; CHECK-NEXT:    lw t0, 44(s1)
 ; CHECK-NEXT:    lw a2, 40(s1)
 ; CHECK-NEXT:    lw a3, 36(s1)
 ; CHECK-NEXT:    lw a4, 32(s1)
 ; CHECK-NEXT:    lw a5, 28(s1)

llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+v -O0 < %s \
 ; RUN:    | FileCheck --check-prefix=SPILL-O0 %s
 ; RUN: llc -mtriple=riscv32 -mattr=+v -O2 < %s \
 ; RUN:    | FileCheck --check-prefix=SPILL-O2 %s
 
 define <vscale x 1 x i32> @spill_lmul_mf2(<vscale x 1 x i32> %va) nounwind {
 ; SPILL-O0-LABEL: spill_lmul_mf2:
 ; SPILL-O0:       # %bb.0: # %entry
 ; SPILL-O0-NEXT:    addi sp, sp, -16
 ; SPILL-O0-NEXT:    csrr a0, vlenb
-; SPILL-O0-NEXT:    slli a0, a0, 1
 ; SPILL-O0-NEXT:    sub sp, sp, a0
 ; SPILL-O0-NEXT:    addi a0, sp, 16
 ; SPILL-O0-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
 ; SPILL-O0-NEXT:    #APP
 ; SPILL-O0-NEXT:    #NO_APP
 ; SPILL-O0-NEXT:    addi a0, sp, 16
 ; SPILL-O0-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
 ; SPILL-O0-NEXT:    csrr a0, vlenb
-; SPILL-O0-NEXT:    slli a0, a0, 1
 ; SPILL-O0-NEXT:    add sp, sp, a0
 ; SPILL-O0-NEXT:    addi sp, sp, 16
 ; SPILL-O0-NEXT:    ret
 ;
 ; SPILL-O2-LABEL: spill_lmul_mf2:
 ; SPILL-O2:       # %bb.0: # %entry
 ; SPILL-O2-NEXT:    addi sp, sp, -16
 ; SPILL-O2-NEXT:    csrr a0, vlenb
-; SPILL-O2-NEXT:    slli a0, a0, 1
 ; SPILL-O2-NEXT:    sub sp, sp, a0
 ; SPILL-O2-NEXT:    addi a0, sp, 16
 ; SPILL-O2-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
 ; SPILL-O2-NEXT:    #APP
 ; SPILL-O2-NEXT:    #NO_APP
 ; SPILL-O2-NEXT:    addi a0, sp, 16
 ; SPILL-O2-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
 ; SPILL-O2-NEXT:    csrr a0, vlenb
-; SPILL-O2-NEXT:    slli a0, a0, 1
 ; SPILL-O2-NEXT:    add sp, sp, a0
 ; SPILL-O2-NEXT:    addi sp, sp, 16
 ; SPILL-O2-NEXT:    ret
 entry:
   call void asm sideeffect "",
   "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
 
   ret <vscale x 1 x i32> %va
 }
 
 define <vscale x 2 x i32> @spill_lmul_1(<vscale x 2 x i32> %va) nounwind {
 ; SPILL-O0-LABEL: spill_lmul_1:
 ; SPILL-O0:       # %bb.0: # %entry
 ; SPILL-O0-NEXT:    addi sp, sp, -16
 ; SPILL-O0-NEXT:    csrr a0, vlenb
-; SPILL-O0-NEXT:    slli a0, a0, 1
 ; SPILL-O0-NEXT:    sub sp, sp, a0
 ; SPILL-O0-NEXT:    addi a0, sp, 16
 ; SPILL-O0-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
 ; SPILL-O0-NEXT:    #APP
 ; SPILL-O0-NEXT:    #NO_APP
 ; SPILL-O0-NEXT:    addi a0, sp, 16
 ; SPILL-O0-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
 ; SPILL-O0-NEXT:    csrr a0, vlenb
-; SPILL-O0-NEXT:    slli a0, a0, 1
 ; SPILL-O0-NEXT:    add sp, sp, a0
 ; SPILL-O0-NEXT:    addi sp, sp, 16
 ; SPILL-O0-NEXT:    ret
 ;
 ; SPILL-O2-LABEL: spill_lmul_1:
 ; SPILL-O2:       # %bb.0: # %entry
 ; SPILL-O2-NEXT:    addi sp, sp, -16
 ; SPILL-O2-NEXT:    csrr a0, vlenb
-; SPILL-O2-NEXT:    slli a0, a0, 1
 ; SPILL-O2-NEXT:    sub sp, sp, a0
 ; SPILL-O2-NEXT:    addi a0, sp, 16
 ; SPILL-O2-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
 ; SPILL-O2-NEXT:    #APP
 ; SPILL-O2-NEXT:    #NO_APP
 ; SPILL-O2-NEXT:    addi a0, sp, 16
 ; SPILL-O2-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
 ; SPILL-O2-NEXT:    csrr a0, vlenb
-; SPILL-O2-NEXT:    slli a0, a0, 1
 ; SPILL-O2-NEXT:    add sp, sp, a0
 ; SPILL-O2-NEXT:    addi sp, sp, 16
 ; SPILL-O2-NEXT:    ret
 entry:
   call void asm sideeffect "",
   "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
 
   ret <vscale x 2 x i32> %va

llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+v -mattr=+m -O0 < %s \
 ; RUN:    | FileCheck --check-prefix=SPILL-O0 %s
 ; RUN: llc -mtriple=riscv32 -mattr=+v -mattr=+m -O2 < %s \
 ; RUN:    | FileCheck --check-prefix=SPILL-O2 %s
 
 define <vscale x 1 x i32> @spill_zvlsseg_nxv1i32(i32* %base, i32 %vl) nounwind {
 ; SPILL-O0-LABEL: spill_zvlsseg_nxv1i32:
 ; SPILL-O0:       # %bb.0: # %entry
 ; SPILL-O0-NEXT:    addi sp, sp, -16
 ; SPILL-O0-NEXT:    csrr a2, vlenb
-; SPILL-O0-NEXT:    slli a2, a2, 1
 ; SPILL-O0-NEXT:    sub sp, sp, a2
 ; SPILL-O0-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu
 ; SPILL-O0-NEXT:    vlseg2e32.v v8, (a0)
 ; SPILL-O0-NEXT:    vmv1r.v v8, v9
 ; SPILL-O0-NEXT:    addi a0, sp, 16
 ; SPILL-O0-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
 ; SPILL-O0-NEXT:    #APP
 ; SPILL-O0-NEXT:    #NO_APP
 ; SPILL-O0-NEXT:    addi a0, sp, 16
 ; SPILL-O0-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
 ; SPILL-O0-NEXT:    csrr a0, vlenb
-; SPILL-O0-NEXT:    slli a0, a0, 1
 ; SPILL-O0-NEXT:    add sp, sp, a0
 ; SPILL-O0-NEXT:    addi sp, sp, 16
 ; SPILL-O0-NEXT:    ret
 ;
 ; SPILL-O2-LABEL: spill_zvlsseg_nxv1i32:
 ; SPILL-O2:       # %bb.0: # %entry
 ; SPILL-O2-NEXT:    addi sp, sp, -16
 ; SPILL-O2-NEXT:    csrr a2, vlenb
entry:
   ret <vscale x 1 x i32> %1
 }
 
 define <vscale x 2 x i32> @spill_zvlsseg_nxv2i32(i32* %base, i32 %vl) nounwind {
 ; SPILL-O0-LABEL: spill_zvlsseg_nxv2i32:
 ; SPILL-O0:       # %bb.0: # %entry
 ; SPILL-O0-NEXT:    addi sp, sp, -16
 ; SPILL-O0-NEXT:    csrr a2, vlenb
-; SPILL-O0-NEXT:    slli a2, a2, 1
 ; SPILL-O0-NEXT:    sub sp, sp, a2
 ; SPILL-O0-NEXT:    vsetvli zero, a1, e32, m1, ta, mu
 ; SPILL-O0-NEXT:    vlseg2e32.v v8, (a0)
 ; SPILL-O0-NEXT:    vmv1r.v v8, v9
 ; SPILL-O0-NEXT:    addi a0, sp, 16
 ; SPILL-O0-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
 ; SPILL-O0-NEXT:    #APP
 ; SPILL-O0-NEXT:    #NO_APP
 ; SPILL-O0-NEXT:    addi a0, sp, 16
 ; SPILL-O0-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
 ; SPILL-O0-NEXT:    csrr a0, vlenb
-; SPILL-O0-NEXT:    slli a0, a0, 1
 ; SPILL-O0-NEXT:    add sp, sp, a0
 ; SPILL-O0-NEXT:    addi sp, sp, 16
 ; SPILL-O0-NEXT:    ret
 ;
 ; SPILL-O2-LABEL: spill_zvlsseg_nxv2i32:
 ; SPILL-O2:       # %bb.0: # %entry
 ; SPILL-O2-NEXT:    addi sp, sp, -16
 ; SPILL-O2-NEXT:    csrr a2, vlenb

llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+v -O0 < %s \
 ; RUN:    | FileCheck --check-prefix=SPILL-O0 %s
 ; RUN: llc -mtriple=riscv64 -mattr=+v -O2 < %s \
 ; RUN:    | FileCheck --check-prefix=SPILL-O2 %s
 
 define <vscale x 1 x i64> @spill_lmul_1(<vscale x 1 x i64> %va) nounwind {
 ; SPILL-O0-LABEL: spill_lmul_1:
 ; SPILL-O0:       # %bb.0: # %entry
 ; SPILL-O0-NEXT:    addi sp, sp, -16
 ; SPILL-O0-NEXT:    csrr a0, vlenb
-; SPILL-O0-NEXT:    slli a0, a0, 1
 ; SPILL-O0-NEXT:    sub sp, sp, a0
 ; SPILL-O0-NEXT:    addi a0, sp, 16
 ; SPILL-O0-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
 ; SPILL-O0-NEXT:    #APP
 ; SPILL-O0-NEXT:    #NO_APP
 ; SPILL-O0-NEXT:    addi a0, sp, 16
 ; SPILL-O0-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
 ; SPILL-O0-NEXT:    csrr a0, vlenb
-; SPILL-O0-NEXT:    slli a0, a0, 1
 ; SPILL-O0-NEXT:    add sp, sp, a0
 ; SPILL-O0-NEXT:    addi sp, sp, 16
 ; SPILL-O0-NEXT:    ret
 ;
 ; SPILL-O2-LABEL: spill_lmul_1:
 ; SPILL-O2:       # %bb.0: # %entry
 ; SPILL-O2-NEXT:    addi sp, sp, -16
 ; SPILL-O2-NEXT:    csrr a0, vlenb
-; SPILL-O2-NEXT:    slli a0, a0, 1
 ; SPILL-O2-NEXT:    sub sp, sp, a0
 ; SPILL-O2-NEXT:    addi a0, sp, 16
 ; SPILL-O2-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
 ; SPILL-O2-NEXT:    #APP
 ; SPILL-O2-NEXT:    #NO_APP
 ; SPILL-O2-NEXT:    addi a0, sp, 16
 ; SPILL-O2-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
 ; SPILL-O2-NEXT:    csrr a0, vlenb
-; SPILL-O2-NEXT:    slli a0, a0, 1
 ; SPILL-O2-NEXT:    add sp, sp, a0
 ; SPILL-O2-NEXT:    addi sp, sp, 16
 ; SPILL-O2-NEXT:    ret
 entry:
   call void asm sideeffect "",
   "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
 
   ret <vscale x 1 x i64> %va

llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+v -mattr=+m -O0 < %s \
 ; RUN:    | FileCheck --check-prefix=SPILL-O0 %s
 ; RUN: llc -mtriple=riscv64 -mattr=+v -mattr=+m -O2 < %s \
 ; RUN:    | FileCheck --check-prefix=SPILL-O2 %s
 
 define <vscale x 1 x i32> @spill_zvlsseg_nxv1i32(i32* %base, i64 %vl) nounwind {
 ; SPILL-O0-LABEL: spill_zvlsseg_nxv1i32:
 ; SPILL-O0:       # %bb.0: # %entry
 ; SPILL-O0-NEXT:    addi sp, sp, -16
 ; SPILL-O0-NEXT:    csrr a2, vlenb
-; SPILL-O0-NEXT:    slli a2, a2, 1
 ; SPILL-O0-NEXT:    sub sp, sp, a2
 ; SPILL-O0-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu
 ; SPILL-O0-NEXT:    vlseg2e32.v v8, (a0)
 ; SPILL-O0-NEXT:    vmv1r.v v8, v9
 ; SPILL-O0-NEXT:    addi a0, sp, 16
 ; SPILL-O0-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
 ; SPILL-O0-NEXT:    #APP
 ; SPILL-O0-NEXT:    #NO_APP
 ; SPILL-O0-NEXT:    addi a0, sp, 16
 ; SPILL-O0-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
 ; SPILL-O0-NEXT:    csrr a0, vlenb
-; SPILL-O0-NEXT:    slli a0, a0, 1
 ; SPILL-O0-NEXT:    add sp, sp, a0
 ; SPILL-O0-NEXT:    addi sp, sp, 16
 ; SPILL-O0-NEXT:    ret
 ;
 ; SPILL-O2-LABEL: spill_zvlsseg_nxv1i32:
 ; SPILL-O2:       # %bb.0: # %entry
 ; SPILL-O2-NEXT:    addi sp, sp, -16
 ; SPILL-O2-NEXT:    csrr a2, vlenb
entry:
   ret <vscale x 1 x i32> %1
 }
 
 define <vscale x 2 x i32> @spill_zvlsseg_nxv2i32(i32* %base, i64 %vl) nounwind {
 ; SPILL-O0-LABEL: spill_zvlsseg_nxv2i32:
 ; SPILL-O0:       # %bb.0: # %entry
 ; SPILL-O0-NEXT:    addi sp, sp, -16
 ; SPILL-O0-NEXT:    csrr a2, vlenb
-; SPILL-O0-NEXT:    slli a2, a2, 1
 ; SPILL-O0-NEXT:    sub sp, sp, a2
 ; SPILL-O0-NEXT:    vsetvli zero, a1, e32, m1, ta, mu
 ; SPILL-O0-NEXT:    vlseg2e32.v v8, (a0)
 ; SPILL-O0-NEXT:    vmv1r.v v8, v9
 ; SPILL-O0-NEXT:    addi a0, sp, 16
 ; SPILL-O0-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
 ; SPILL-O0-NEXT:    #APP
 ; SPILL-O0-NEXT:    #NO_APP
 ; SPILL-O0-NEXT:    addi a0, sp, 16
 ; SPILL-O0-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
 ; SPILL-O0-NEXT:    csrr a0, vlenb
-; SPILL-O0-NEXT:    slli a0, a0, 1
 ; SPILL-O0-NEXT:    add sp, sp, a0
 ; SPILL-O0-NEXT:    addi sp, sp, 16
 ; SPILL-O0-NEXT:    ret
 ;
 ; SPILL-O2-LABEL: spill_zvlsseg_nxv2i32:
 ; SPILL-O2:       # %bb.0: # %entry
 ; SPILL-O2-NEXT:    addi sp, sp, -16
 ; SPILL-O2-NEXT:    csrr a2, vlenb

llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s
 
 define void @rvv_vla(i64 %n, i64 %i) nounwind {
 ; CHECK-LABEL: rvv_vla:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -32
 ; CHECK-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    addi s0, sp, 32
 ; CHECK-NEXT:    csrr a2, vlenb
-; CHECK-NEXT:    slli a2, a2, 2
+; CHECK-NEXT:    slli a3, a2, 1
+; CHECK-NEXT:    add a2, a3, a2
 ; CHECK-NEXT:    sub sp, sp, a2
 ; CHECK-NEXT:    slli a0, a0, 2
 ; CHECK-NEXT:    addi a0, a0, 15
 ; CHECK-NEXT:    andi a0, a0, -16
 ; CHECK-NEXT:    sub a0, sp, a0
 ; CHECK-NEXT:    mv sp, a0
 ; CHECK-NEXT:    csrr a2, vlenb
 ; CHECK-NEXT:    sub a2, s0, a2
 ; CHECK-NEXT:    addi a2, a2, -32
 ; CHECK-NEXT:    vl1re64.v v8, (a2)
 ; CHECK-NEXT:    csrr a2, vlenb
-; CHECK-NEXT:    slli a2, a2, 2
+; CHECK-NEXT:    slli a3, a2, 1
+; CHECK-NEXT:    add a2, a3, a2
 ; CHECK-NEXT:    sub a2, s0, a2
 ; CHECK-NEXT:    addi a2, a2, -32
 ; CHECK-NEXT:    vl2re64.v v8, (a2)
 ; CHECK-NEXT:    slli a1, a1, 2
 ; CHECK-NEXT:    add a0, a0, a1
 ; CHECK-NEXT:    lw a0, 0(a0)
 ; CHECK-NEXT:    addi sp, s0, -32
 ; CHECK-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload

 define void @rvv_overaligned() nounwind {
 ; CHECK-LABEL: rvv_overaligned:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -128
 ; CHECK-NEXT:    sd ra, 120(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    sd s0, 112(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    addi s0, sp, 128
 ; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    slli a0, a0, 2
+; CHECK-NEXT:    slli a1, a0, 1
+; CHECK-NEXT:    add a0, a1, a0
 ; CHECK-NEXT:    sub sp, sp, a0
 ; CHECK-NEXT:    andi sp, sp, -64
 ; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    slli a1, a0, 1
-; CHECK-NEXT:    add a0, a1, a0
+; CHECK-NEXT:    slli a0, a0, 1
 ; CHECK-NEXT:    add a0, sp, a0
 ; CHECK-NEXT:    addi a0, a0, 112
 ; CHECK-NEXT:    vl1re64.v v8, (a0)
 ; CHECK-NEXT:    addi a0, sp, 112
 ; CHECK-NEXT:    vl2re64.v v8, (a0)
 ; CHECK-NEXT:    lw a0, 64(sp)
 ; CHECK-NEXT:    addi sp, s0, -128
 ; CHECK-NEXT:    ld ra, 120(sp) # 8-byte Folded Reload

 ; CHECK-LABEL: rvv_vla_and_overaligned:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -144
 ; CHECK-NEXT:    sd ra, 136(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    sd s0, 128(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    sd s1, 120(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    addi s0, sp, 144
 ; CHECK-NEXT:    csrr a2, vlenb
-; CHECK-NEXT:    slli a2, a2, 2
+; CHECK-NEXT:    slli a3, a2, 1
+; CHECK-NEXT:    add a2, a3, a2
 ; CHECK-NEXT:    sub sp, sp, a2
 ; CHECK-NEXT:    andi sp, sp, -64
 ; CHECK-NEXT:    mv s1, sp
 ; CHECK-NEXT:    slli a0, a0, 2
 ; CHECK-NEXT:    addi a0, a0, 15
 ; CHECK-NEXT:    andi a0, a0, -16
 ; CHECK-NEXT:    sub a0, sp, a0
 ; CHECK-NEXT:    mv sp, a0
 ; CHECK-NEXT:    csrr a2, vlenb
-; CHECK-NEXT:    slli a3, a2, 1
-; CHECK-NEXT:    add a2, a3, a2
+; CHECK-NEXT:    slli a2, a2, 1
 ; CHECK-NEXT:    add a2, s1, a2
 ; CHECK-NEXT:    addi a2, a2, 112
 ; CHECK-NEXT:    vl1re64.v v8, (a2)
 ; CHECK-NEXT:    addi a2, s1, 112
 ; CHECK-NEXT:    vl2re64.v v8, (a2)
 ; CHECK-NEXT:    lw a2, 64(s1)
 ; CHECK-NEXT:    slli a1, a1, 2
 ; CHECK-NEXT:    add a0, a0, a1

llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir

 # NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 # RUN: llc -mtriple riscv32 -mattr=+zve64x -start-before=prologepilog -o - \
-# RUN:     -verify-machineinstrs %s | FileCheck %s --check-prefix=RV32
+# RUN:     -verify-machineinstrs %s | FileCheck %s --check-prefix=RV32-VLEN64
 # RUN: llc -mtriple riscv32 -mattr=+v -start-before=prologepilog -o - \
-# RUN:     -verify-machineinstrs %s | FileCheck %s --check-prefix=RV32
+# RUN:     -verify-machineinstrs %s | FileCheck %s --check-prefix=RV32-VLEN128
 # RUN: llc -mtriple riscv64 -mattr=+zve64x -start-before=prologepilog -o - \
-# RUN:     -verify-machineinstrs %s | FileCheck %s --check-prefix=RV64
+# RUN:     -verify-machineinstrs %s | FileCheck %s --check-prefix=RV64-VLEN64
 # RUN: llc -mtriple riscv64 -mattr=+v -start-before=prologepilog -o - \
-# RUN:     -verify-machineinstrs %s | FileCheck %s --check-prefix=RV64
+# RUN:     -verify-machineinstrs %s | FileCheck %s --check-prefix=RV64-VLEN128
 --- |
   target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
   target triple = "riscv64"
 
   declare void @extern(<vscale x 4 x i32>*)
 
   define void @rvv_stack_align8() #0 {
-  ; RV32-LABEL: rvv_stack_align8:
-  ; RV32:       # %bb.0:
-  ; RV32-NEXT:    addi sp, sp, -48
-  ; RV32-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
-  ; RV32-NEXT:    csrr a0, vlenb
-  ; RV32-NEXT:    slli a0, a0, 1
-  ; RV32-NEXT:    sub sp, sp, a0
-  ; RV32-NEXT:    addi a0, sp, 32
-  ; RV32-NEXT:    addi a1, sp, 16
-  ; RV32-NEXT:    addi a2, sp, 8
-  ; RV32-NEXT:    call extern@plt
-  ; RV32-NEXT:    csrr a0, vlenb
-  ; RV32-NEXT:    slli a0, a0, 1
-  ; RV32-NEXT:    add sp, sp, a0
-  ; RV32-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
-  ; RV32-NEXT:    addi sp, sp, 48
-  ; RV32-NEXT:    ret
+  ; RV32-VLEN64-LABEL: rvv_stack_align8:
+  ; RV32-VLEN64:       # %bb.0:
+  ; RV32-VLEN64-NEXT:    addi sp, sp, -48
+  ; RV32-VLEN64-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+  ; RV32-VLEN64-NEXT:    csrr a0, vlenb
+  ; RV32-VLEN64-NEXT:    slli a0, a0, 1
+  ; RV32-VLEN64-NEXT:    sub sp, sp, a0
+  ; RV32-VLEN64-NEXT:    addi a0, sp, 32
+  ; RV32-VLEN64-NEXT:    addi a1, sp, 16
+  ; RV32-VLEN64-NEXT:    addi a2, sp, 8
+  ; RV32-VLEN64-NEXT:    call extern@plt
+  ; RV32-VLEN64-NEXT:    csrr a0, vlenb
+  ; RV32-VLEN64-NEXT:    slli a0, a0, 1
+  ; RV32-VLEN64-NEXT:    add sp, sp, a0
+  ; RV32-VLEN64-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+  ; RV32-VLEN64-NEXT:    addi sp, sp, 48
+  ; RV32-VLEN64-NEXT:    ret
   ;
-  ; RV64-LABEL: rvv_stack_align8:
-  ; RV64:       # %bb.0:
-  ; RV64-NEXT:    addi sp, sp, -48
-  ; RV64-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
-  ; RV64-NEXT:    csrr a0, vlenb
-  ; RV64-NEXT:    slli a0, a0, 1
-  ; RV64-NEXT:    sub sp, sp, a0
-  ; RV64-NEXT:    addi a0, sp, 32
-  ; RV64-NEXT:    addi a1, sp, 16
-  ; RV64-NEXT:    addi a2, sp, 8
-  ; RV64-NEXT:    call extern@plt
-  ; RV64-NEXT:    csrr a0, vlenb
-  ; RV64-NEXT:    slli a0, a0, 1
-  ; RV64-NEXT:    add sp, sp, a0
-  ; RV64-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
-  ; RV64-NEXT:    addi sp, sp, 48
-  ; RV64-NEXT:    ret
+  ; RV32-VLEN128-LABEL: rvv_stack_align8:
+  ; RV32-VLEN128:       # %bb.0:
+  ; RV32-VLEN128-NEXT:    addi sp, sp, -48
+  ; RV32-VLEN128-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+  ; RV32-VLEN128-NEXT:    csrr a0, vlenb
+  ; RV32-VLEN128-NEXT:    slli a0, a0, 1
+  ; RV32-VLEN128-NEXT:    sub sp, sp, a0
+  ; RV32-VLEN128-NEXT:    addi a0, sp, 32
+  ; RV32-VLEN128-NEXT:    addi a1, sp, 16
+  ; RV32-VLEN128-NEXT:    addi a2, sp, 8
+  ; RV32-VLEN128-NEXT:    call extern@plt
+  ; RV32-VLEN128-NEXT:    csrr a0, vlenb
+  ; RV32-VLEN128-NEXT:    slli a0, a0, 1
+  ; RV32-VLEN128-NEXT:    add sp, sp, a0
+  ; RV32-VLEN128-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+  ; RV32-VLEN128-NEXT:    addi sp, sp, 48
+  ; RV32-VLEN128-NEXT:    ret
+  ;
+  ; RV64-VLEN64-LABEL: rvv_stack_align8:
+  ; RV64-VLEN64:       # %bb.0:
+  ; RV64-VLEN64-NEXT:    addi sp, sp, -48
+  ; RV64-VLEN64-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
+  ; RV64-VLEN64-NEXT:    csrr a0, vlenb
+  ; RV64-VLEN64-NEXT:    slli a0, a0, 1
+  ; RV64-VLEN64-NEXT:    sub sp, sp, a0
+  ; RV64-VLEN64-NEXT:    addi a0, sp, 32
+  ; RV64-VLEN64-NEXT:    addi a1, sp, 16
+  ; RV64-VLEN64-NEXT:    addi a2, sp, 8
+  ; RV64-VLEN64-NEXT:    call extern@plt
+  ; RV64-VLEN64-NEXT:    csrr a0, vlenb
+  ; RV64-VLEN64-NEXT:    slli a0, a0, 1
+  ; RV64-VLEN64-NEXT:    add sp, sp, a0
+  ; RV64-VLEN64-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
+  ; RV64-VLEN64-NEXT:    addi sp, sp, 48
+  ; RV64-VLEN64-NEXT:    ret
+  ;
+  ; RV64-VLEN128-LABEL: rvv_stack_align8:
+  ; RV64-VLEN128:       # %bb.0:
+  ; RV64-VLEN128-NEXT:    addi sp, sp, -48
+  ; RV64-VLEN128-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
+  ; RV64-VLEN128-NEXT:    csrr a0, vlenb
+  ; RV64-VLEN128-NEXT:    slli a0, a0, 1
+  ; RV64-VLEN128-NEXT:    sub sp, sp, a0
+  ; RV64-VLEN128-NEXT:    addi a0, sp, 32
+  ; RV64-VLEN128-NEXT:    addi a1, sp, 16
+  ; RV64-VLEN128-NEXT:    addi a2, sp, 8
+  ; RV64-VLEN128-NEXT:    call extern@plt
+  ; RV64-VLEN128-NEXT:    csrr a0, vlenb
+  ; RV64-VLEN128-NEXT:    slli a0, a0, 1
+  ; RV64-VLEN128-NEXT:    add sp, sp, a0
+  ; RV64-VLEN128-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
+  ; RV64-VLEN128-NEXT:    addi sp, sp, 48
+  ; RV64-VLEN128-NEXT:    ret
     %a = alloca <vscale x 4 x i32>, align 8
     %b = alloca i64
     %c = alloca i64
     call void @extern(<vscale x 4 x i32>* %a)
     ret void
   }
 
   define void @rvv_stack_align16() #0 {
-  ; RV32-LABEL: rvv_stack_align16:
-  ; RV32:       # %bb.0:
-  ; RV32-NEXT:    addi sp, sp, -48
-  ; RV32-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
-  ; RV32-NEXT:    csrr a0, vlenb
-  ; RV32-NEXT:    slli a0, a0, 1
-  ; RV32-NEXT:    sub sp, sp, a0
-  ; RV32-NEXT:    addi a0, sp, 32
-  ; RV32-NEXT:    addi a1, sp, 16
-  ; RV32-NEXT:    addi a2, sp, 8
-  ; RV32-NEXT:    call extern@plt
-  ; RV32-NEXT:    csrr a0, vlenb
-  ; RV32-NEXT:    slli a0, a0, 1
-  ; RV32-NEXT:    add sp, sp, a0
-  ; RV32-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
-  ; RV32-NEXT:    addi sp, sp, 48
-  ; RV32-NEXT:    ret
+  ; RV32-VLEN64-LABEL: rvv_stack_align16:
+  ; RV32-VLEN64:       # %bb.0:
+  ; RV32-VLEN64-NEXT:    addi sp, sp, -48
+  ; RV32-VLEN64-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+  ; RV32-VLEN64-NEXT:    csrr a0, vlenb
+  ; RV32-VLEN64-NEXT:    slli a0, a0, 1
+  ; RV32-VLEN64-NEXT:    sub sp, sp, a0
+  ; RV32-VLEN64-NEXT:    addi a0, sp, 32
+  ; RV32-VLEN64-NEXT:    addi a1, sp, 16
+  ; RV32-VLEN64-NEXT:    addi a2, sp, 8
+  ; RV32-VLEN64-NEXT:    call extern@plt
+  ; RV32-VLEN64-NEXT:    csrr a0, vlenb
+  ; RV32-VLEN64-NEXT:    slli a0, a0, 1
+  ; RV32-VLEN64-NEXT:    add sp, sp, a0
+  ; RV32-VLEN64-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+  ; RV32-VLEN64-NEXT:    addi sp, sp, 48
+  ; RV32-VLEN64-NEXT:    ret
+  ;
+  ; RV32-VLEN128-LABEL: rvv_stack_align16:
+  ; RV32-VLEN128:       # %bb.0:
+  ; RV32-VLEN128-NEXT:    addi sp, sp, -48
+  ; RV32-VLEN128-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+  ; RV32-VLEN128-NEXT:    csrr a0, vlenb
+  ; RV32-VLEN128-NEXT:    slli a0, a0, 1
+  ; RV32-VLEN128-NEXT:    sub sp, sp, a0
+  ; RV32-VLEN128-NEXT:    addi a0, sp, 32
+  ; RV32-VLEN128-NEXT:    addi a1, sp, 16
+  ; RV32-VLEN128-NEXT:    addi a2, sp, 8
+  ; RV32-VLEN128-NEXT:    call extern@plt
+  ; RV32-VLEN128-NEXT:    csrr a0, vlenb
+  ; RV32-VLEN128-NEXT:    slli a0, a0, 1
+  ; RV32-VLEN128-NEXT:    add sp, sp, a0
+  ; RV32-VLEN128-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+  ; RV32-VLEN128-NEXT:    addi sp, sp, 48
+  ; RV32-VLEN128-NEXT:    ret
   ;
-  ; RV64-LABEL: rvv_stack_align16:
-  ; RV64:       # %bb.0:
-  ; RV64-NEXT:    addi sp, sp, -48
-  ; RV64-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
-  ; RV64-NEXT:    csrr a0, vlenb
-  ; RV64-NEXT:    slli a0, a0, 1
-  ; RV64-NEXT:    sub sp, sp, a0
-  ; RV64-NEXT:    addi a0, sp, 32
-  ; RV64-NEXT:    addi a1, sp, 16
-  ; RV64-NEXT:    addi a2, sp, 8
-  ; RV64-NEXT:    call extern@plt
-  ; RV64-NEXT:    csrr a0, vlenb
-  ; RV64-NEXT:    slli a0, a0, 1
-  ; RV64-NEXT:    add sp, sp, a0
-  ; RV64-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
-  ; RV64-NEXT:    addi sp, sp, 48
-  ; RV64-NEXT:    ret
+  ; RV64-VLEN64-LABEL: rvv_stack_align16:
+  ; RV64-VLEN64:       # %bb.0:
+  ; RV64-VLEN64-NEXT:    addi sp, sp, -48
+  ; RV64-VLEN64-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
+  ; RV64-VLEN64-NEXT:    csrr a0, vlenb
+  ; RV64-VLEN64-NEXT:    slli a0, a0, 1
+  ; RV64-VLEN64-NEXT:    sub sp, sp, a0
+  ; RV64-VLEN64-NEXT:    addi a0, sp, 32
+  ; RV64-VLEN64-NEXT:    addi a1, sp, 16
+  ; RV64-VLEN64-NEXT:    addi a2, sp, 8
+  ; RV64-VLEN64-NEXT:    call extern@plt
+  ; RV64-VLEN64-NEXT:    csrr a0, vlenb
+  ; RV64-VLEN64-NEXT:    slli a0, a0, 1
+  ; RV64-VLEN64-NEXT:    add sp, sp, a0
+  ; RV64-VLEN64-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
+  ; RV64-VLEN64-NEXT:    addi sp, sp, 48
+  ; RV64-VLEN64-NEXT:    ret
+  ;
+  ; RV64-VLEN128-LABEL: rvv_stack_align16:
+  ; RV64-VLEN128:       # %bb.0:
+  ; RV64-VLEN128-NEXT:    addi sp, sp, -48
+  ; RV64-VLEN128-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
+  ; RV64-VLEN128-NEXT:    csrr a0, vlenb
+  ; RV64-VLEN128-NEXT:    slli a0, a0, 1
+  ; RV64-VLEN128-NEXT:    sub sp, sp, a0
+  ; RV64-VLEN128-NEXT:    addi a0, sp, 32
+  ; RV64-VLEN128-NEXT:    addi a1, sp, 16
+  ; RV64-VLEN128-NEXT:    addi a2, sp, 8
+  ; RV64-VLEN128-NEXT:    call extern@plt
+  ; RV64-VLEN128-NEXT:    csrr a0, vlenb
+  ; RV64-VLEN128-NEXT:    slli a0, a0, 1
+  ; RV64-VLEN128-NEXT:    add sp, sp, a0
+  ; RV64-VLEN128-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
+  ; RV64-VLEN128-NEXT:    addi sp, sp, 48
+  ; RV64-VLEN128-NEXT:    ret
     %a = alloca <vscale x 4 x i32>, align 16
     %b = alloca i64
     %c = alloca i64
     call void @extern(<vscale x 4 x i32>* %a)
     ret void
   }
 
   define void @rvv_stack_align32() #0 {
-  ; RV32-LABEL: rvv_stack_align32:
-  ; RV32:       # %bb.0:
-  ; RV32-NEXT:    addi sp, sp, -48
-  ; RV32-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
-  ; RV32-NEXT:    sw s0, 40(sp) # 4-byte Folded Spill
-  ; RV32-NEXT:    addi s0, sp, 48
-  ; RV32-NEXT:    csrr a0, vlenb
-  ; RV32-NEXT:    slli a0, a0, 2
-  ; RV32-NEXT:    sub sp, sp, a0
-  ; RV32-NEXT:    andi sp, sp, -32
-  ; RV32-NEXT:    addi a0, sp, 32
-  ; RV32-NEXT:    addi a1, sp, 16
-  ; RV32-NEXT:    addi a2, sp, 8
-  ; RV32-NEXT:    call extern@plt
-  ; RV32-NEXT:    addi sp, s0, -48
-  ; RV32-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
-  ; RV32-NEXT:    lw s0, 40(sp) # 4-byte Folded Reload
-  ; RV32-NEXT:    addi sp, sp, 48
-  ; RV32-NEXT:    ret
+  ; RV32-VLEN64-LABEL: rvv_stack_align32:
+  ; RV32-VLEN64:       # %bb.0:
+  ; RV32-VLEN64-NEXT:    addi sp, sp, -48
+  ; RV32-VLEN64-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+  ; RV32-VLEN64-NEXT:    sw s0, 40(sp) # 4-byte Folded Spill
+  ; RV32-VLEN64-NEXT:    addi s0, sp, 48
+  ; RV32-VLEN64-NEXT:    csrr a0, vlenb
+  ; RV32-VLEN64-NEXT:    slli a0, a0, 2
+  ; RV32-VLEN64-NEXT:    sub sp, sp, a0
+  ; RV32-VLEN64-NEXT:    andi sp, sp, -32
+  ; RV32-VLEN64-NEXT:    addi a0, sp, 32
+  ; RV32-VLEN64-NEXT:    addi a1, sp, 16
+  ; RV32-VLEN64-NEXT:    addi a2, sp, 8
+  ; RV32-VLEN64-NEXT:    call extern@plt
+  ; RV32-VLEN64-NEXT:    addi sp, s0, -48
+  ; RV32-VLEN64-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+  ; RV32-VLEN64-NEXT:    lw s0, 40(sp) # 4-byte Folded Reload
+  ; RV32-VLEN64-NEXT:    addi sp, sp, 48
+  ; RV32-VLEN64-NEXT:    ret
+  ;
+  ; RV32-VLEN128-LABEL: rvv_stack_align32:
+  ; RV32-VLEN128:       # %bb.0:
+  ; RV32-VLEN128-NEXT:    addi sp, sp, -48
+  ; RV32-VLEN128-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+  ; RV32-VLEN128-NEXT:    sw s0, 40(sp) # 4-byte Folded Spill
+  ; RV32-VLEN128-NEXT:    addi s0, sp, 48
+  ; RV32-VLEN128-NEXT:    csrr a0, vlenb
+  ; RV32-VLEN128-NEXT:    slli a0, a0, 1
+  ; RV32-VLEN128-NEXT:    sub sp, sp, a0
+  ; RV32-VLEN128-NEXT:    andi sp, sp, -32
+  ; RV32-VLEN128-NEXT:    addi a0, sp, 32
+  ; RV32-VLEN128-NEXT:    addi a1, sp, 16
+  ; RV32-VLEN128-NEXT:    addi a2, sp, 8
+  ; RV32-VLEN128-NEXT:    call extern@plt
+  ; RV32-VLEN128-NEXT:    addi sp, s0, -48
+  ; RV32-VLEN128-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+  ; RV32-VLEN128-NEXT:    lw s0, 40(sp) # 4-byte Folded Reload
+  ; RV32-VLEN128-NEXT:    addi sp, sp, 48
+  ; RV32-VLEN128-NEXT:    ret
+  ;
+  ; RV64-VLEN64-LABEL: rvv_stack_align32:
+  ; RV64-VLEN64:       # %bb.0:
+  ; RV64-VLEN64-NEXT:    addi sp, sp, -80
+  ; RV64-VLEN64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill
+  ; RV64-VLEN64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill
+  ; RV64-VLEN64-NEXT:    addi s0, sp, 80
+  ; RV64-VLEN64-NEXT:    csrr a0, vlenb
+  ; RV64-VLEN64-NEXT:    slli a0, a0, 2
+  ; RV64-VLEN64-NEXT:    sub sp, sp, a0
+  ; RV64-VLEN64-NEXT:    andi sp, sp, -32
+  ; RV64-VLEN64-NEXT:    addi a0, sp, 64
+  ; RV64-VLEN64-NEXT:    addi a1, sp, 40
+  ; RV64-VLEN64-NEXT:    addi a2, sp, 32
+  ; RV64-VLEN64-NEXT:    call extern@plt
+  ; RV64-VLEN64-NEXT:    addi sp, s0, -80
+  ; RV64-VLEN64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
+  ; RV64-VLEN64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
+  ; RV64-VLEN64-NEXT:    addi sp, sp, 80
+  ; RV64-VLEN64-NEXT:    ret
   ;
-  ; RV64-LABEL: rvv_stack_align32:
-  ; RV64:       # %bb.0:
-  ; RV64-NEXT:    addi sp, sp, -80
-  ; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill
-  ; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill
-  ; RV64-NEXT:    addi s0, sp, 80
-  ; RV64-NEXT:    csrr a0, vlenb
-  ; RV64-NEXT:    slli a0, a0, 2
-  ; RV64-NEXT:    sub sp, sp, a0
-  ; RV64-NEXT:    andi sp, sp, -32
-  ; RV64-NEXT:    addi a0, sp, 64
-  ; RV64-NEXT:    addi a1, sp, 40
-  ; RV64-NEXT:    addi a2, sp, 32
-  ; RV64-NEXT:    call extern@plt
-  ; RV64-NEXT:    addi sp, s0, -80
-  ; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
-  ; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
-  ; RV64-NEXT:    addi sp, sp, 80
-  ; RV64-NEXT:    ret
+  ; RV64-VLEN128-LABEL: rvv_stack_align32:
+  ; RV64-VLEN128:       # %bb.0:
+  ; RV64-VLEN128-NEXT:    addi sp, sp, -80
+  ; RV64-VLEN128-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill
+  ; RV64-VLEN128-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill
+  ; RV64-VLEN128-NEXT:    addi s0, sp, 80
+  ; RV64-VLEN128-NEXT:    csrr a0, vlenb
+  ; RV64-VLEN128-NEXT:    slli a0, a0, 1
+  ; RV64-VLEN128-NEXT:    sub sp, sp, a0
+  ; RV64-VLEN128-NEXT:    andi sp, sp, -32
+  ; RV64-VLEN128-NEXT:    addi a0, sp, 64
+  ; RV64-VLEN128-NEXT:    addi a1, sp, 40
+  ; RV64-VLEN128-NEXT:    addi a2, sp, 32
+  ; RV64-VLEN128-NEXT:    call extern@plt
+  ; RV64-VLEN128-NEXT:    addi sp, s0, -80
+  ; RV64-VLEN128-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
+  ; RV64-VLEN128-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
+  ; RV64-VLEN128-NEXT:    addi sp, sp, 80
+  ; RV64-VLEN128-NEXT:    ret
     %a = alloca <vscale x 4 x i32>, align 32
     %b = alloca i64
     %c = alloca i64
     call void @extern(<vscale x 4 x i32>* %a)
     ret void
   }
 
   attributes #0 = { nounwind nofree nosync }

llvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zve64x -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s --check-prefix=RV32
+; RUN:   | FileCheck %s --check-prefix=RV32-VLEN64
 ; RUN: llc -mtriple=riscv64 -mattr=+zve64x -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s --check-prefix=RV64
+; RUN:   | FileCheck %s --check-prefix=RV64-VLEN64
 ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s --check-prefix=RV32
+; RUN:   | FileCheck %s --check-prefix=RV32-VLEN128
 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s --check-prefix=RV64
-
-; FIXME: We are over-aligning the stack on V, wasting stack space.
+; RUN:   | FileCheck %s --check-prefix=RV64-VLEN128
 
 define i64* @scalar_stack_align16() nounwind {
-; RV32-LABEL: scalar_stack_align16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -48
-; RV32-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
-; RV32-NEXT:    csrr a0, vlenb
-; RV32-NEXT:    slli a0, a0, 1
-; RV32-NEXT:    sub sp, sp, a0
-; RV32-NEXT:    addi a0, sp, 32
-; RV32-NEXT:    call extern@plt
-; RV32-NEXT:    addi a0, sp, 16
-; RV32-NEXT:    csrr a1, vlenb
-; RV32-NEXT:    slli a1, a1, 1
-; RV32-NEXT:    add sp, sp, a1
-; RV32-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
-; RV32-NEXT:    addi sp, sp, 48
-; RV32-NEXT:    ret
+; RV32-VLEN64-LABEL: scalar_stack_align16:
+; RV32-VLEN64:       # %bb.0:
+; RV32-VLEN64-NEXT:    addi sp, sp, -48
+; RV32-VLEN64-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+; RV32-VLEN64-NEXT:    csrr a0, vlenb
+; RV32-VLEN64-NEXT:    slli a0, a0, 1
+; RV32-VLEN64-NEXT:    sub sp, sp, a0
+; RV32-VLEN64-NEXT:    addi a0, sp, 32
+; RV32-VLEN64-NEXT:    call extern@plt
+; RV32-VLEN64-NEXT:    addi a0, sp, 16
+; RV32-VLEN64-NEXT:    csrr a1, vlenb
+; RV32-VLEN64-NEXT:    slli a1, a1, 1
+; RV32-VLEN64-NEXT:    add sp, sp, a1
+; RV32-VLEN64-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+; RV32-VLEN64-NEXT:    addi sp, sp, 48
+; RV32-VLEN64-NEXT:    ret
+;
+; RV64-VLEN64-LABEL: scalar_stack_align16:
+; RV64-VLEN64:       # %bb.0:
+; RV64-VLEN64-NEXT:    addi sp, sp, -48
+; RV64-VLEN64-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
+; RV64-VLEN64-NEXT:    csrr a0, vlenb
+; RV64-VLEN64-NEXT:    slli a0, a0, 1
+; RV64-VLEN64-NEXT:    sub sp, sp, a0
+; RV64-VLEN64-NEXT:    addi a0, sp, 32
+; RV64-VLEN64-NEXT:    call extern@plt
+; RV64-VLEN64-NEXT:    addi a0, sp, 16
+; RV64-VLEN64-NEXT:    csrr a1, vlenb
+; RV64-VLEN64-NEXT:    slli a1, a1, 1
+; RV64-VLEN64-NEXT:    add sp, sp, a1
+; RV64-VLEN64-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
+; RV64-VLEN64-NEXT:    addi sp, sp, 48
+; RV64-VLEN64-NEXT:    ret
+;
+; RV32-VLEN128-LABEL: scalar_stack_align16:
+; RV32-VLEN128:       # %bb.0:
+; RV32-VLEN128-NEXT:    addi sp, sp, -48
+; RV32-VLEN128-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+; RV32-VLEN128-NEXT:    csrr a0, vlenb
+; RV32-VLEN128-NEXT:    sub sp, sp, a0
+; RV32-VLEN128-NEXT:    addi a0, sp, 32
+; RV32-VLEN128-NEXT:    call extern@plt
+; RV32-VLEN128-NEXT:    addi a0, sp, 16
+; RV32-VLEN128-NEXT:    csrr a1, vlenb
+; RV32-VLEN128-NEXT:    add sp, sp, a1
+; RV32-VLEN128-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+; RV32-VLEN128-NEXT:    addi sp, sp, 48
+; RV32-VLEN128-NEXT:    ret
 ;
-; RV64-LABEL: scalar_stack_align16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    addi sp, sp, -48
-; RV64-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
-; RV64-NEXT:    csrr a0, vlenb
-; RV64-NEXT:    slli a0, a0, 1
-; RV64-NEXT:    sub sp, sp, a0
-; RV64-NEXT:    addi a0, sp, 32
-; RV64-NEXT:    call extern@plt
-; RV64-NEXT:    addi a0, sp, 16
-; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    slli a1, a1, 1
-; RV64-NEXT:    add sp, sp, a1
-; RV64-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
-; RV64-NEXT:    addi sp, sp, 48
-; RV64-NEXT:    ret
+; RV64-VLEN128-LABEL: scalar_stack_align16:
+; RV64-VLEN128:       # %bb.0:
+; RV64-VLEN128-NEXT:    addi sp, sp, -48
+; RV64-VLEN128-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
+; RV64-VLEN128-NEXT:    csrr a0, vlenb
+; RV64-VLEN128-NEXT:    sub sp, sp, a0
+; RV64-VLEN128-NEXT:    addi a0, sp, 32
+; RV64-VLEN128-NEXT:    call extern@plt
+; RV64-VLEN128-NEXT:    addi a0, sp, 16
+; RV64-VLEN128-NEXT:    csrr a1, vlenb
+; RV64-VLEN128-NEXT:    add sp, sp, a1
+; RV64-VLEN128-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
+; RV64-VLEN128-NEXT:    addi sp, sp, 48
+; RV64-VLEN128-NEXT:    ret
   %a = alloca <vscale x 2 x i32>
   %c = alloca i64, align 16
   call void @extern(<vscale x 2 x i32>* %a)
   ret i64* %c
 }
 
 declare void @extern(<vscale x 2 x i32>*)

llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir

machineFunctionInfo:
   varArgsFrameIndex: -1
   varArgsSaveSize: 16
 body:             |
   ; CHECK-LABEL: name: asm_fprintf
   ; CHECK: stack:
   ; CHECK-NEXT:  - { id: 0, name: buf1, type: default, offset: -48, size: 1, alignment: 8,
   ; CHECK-NEXT:      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
   ; CHECK-NEXT:      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-  ; CHECK-NEXT:  - { id: 1, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,
+  ; CHECK-NEXT:  - { id: 1, name: '', type: spill-slot, offset: -8, size: 8, alignment: 8,
   ; CHECK-NEXT:      stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true,
   ; CHECK-NEXT:      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
   ; CHECK-NEXT:  - { id: 2, name: '', type: spill-slot, offset: -24, size: 8, alignment: 8,
   ; CHECK-NEXT:      stack-id: default, callee-saved-register: '$x1', callee-saved-restored: true,
   ; CHECK-NEXT:      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
   ; CHECK-NEXT:  - { id: 3, name: '', type: spill-slot, offset: -32, size: 8, alignment: 8,
   ; CHECK-NEXT:      stack-id: default, callee-saved-register: '$x8', callee-saved-restored: true,
   ; CHECK-NEXT:      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body:             |
   ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_offset 80
   ; CHECK-NEXT:   SD killed $x1, $x2, 56 :: (store (s64) into %stack.2)
   ; CHECK-NEXT:   SD killed $x8, $x2, 48 :: (store (s64) into %stack.3)
   ; CHECK-NEXT:   SD killed $x9, $x2, 40 :: (store (s64) into %stack.4)
   ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $x1, -24
   ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $x8, -32
   ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $x9, -40
   ; CHECK-NEXT:   $x10 = frame-setup PseudoReadVLENB
-  ; CHECK-NEXT:   $x10 = frame-setup SLLI killed $x10, 1
   ; CHECK-NEXT:   $x2 = frame-setup SUB $x2, killed $x10
   ; CHECK-NEXT:   renamable $x8 = COPY $x14
   ; CHECK-NEXT:   renamable $x9 = COPY $x11
   ; CHECK-NEXT:   $x10 = PseudoReadVLENB
-  ; CHECK-NEXT:   $x10 = SLLI killed $x10, 1
   ; CHECK-NEXT:   $x10 = ADD $x2, killed $x10
   ; CHECK-NEXT:   SD killed renamable $x17, killed $x10, 72 :: (store (s64))
   ; CHECK-NEXT:   $x10 = PseudoReadVLENB
-  ; CHECK-NEXT:   $x10 = SLLI killed $x10, 1
   ; CHECK-NEXT:   $x10 = ADD $x2, killed $x10
   ; CHECK-NEXT:   SD killed renamable $x16, killed $x10, 64 :: (store (s64) into %fixed-stack.1, align 16)
   ; CHECK-NEXT:   dead $x0 = PseudoVSETIVLI 2, 69 /* e8, mf8, ta, mu */, implicit-def $vl, implicit-def $vtype
   ; CHECK-NEXT:   renamable $v8 = PseudoVMV_V_I_MF8 0, 2, 3 /* e8 */, implicit $vl, implicit $vtype
   ; CHECK-NEXT:   $x10 = ADDI $x2, 32
   ; CHECK-NEXT:   PseudoVSPILL_M1 killed renamable $v8, killed $x10 :: (store unknown-size into %stack.1, align 8)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1.while.cond: