[RISCV] Add DAGCombine to fold base operation and reduction.

[fakepaper56]

Summary

Transform (<bop> x, (reduce.<bop> vec, splat(neutral_element))) to
(reduce.<bop> vec, splat (x)).

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

7434

Why int instead of unsigned?

7435

Capitalize

7442

reassocation->reassociation

7447

Why getNode()?

7461

Pass Opc by value not by reference

7463

auto C -> auto *C We always want to be able to see if something is a pointer.

7470

netrual -> neutral

7479

Capitalize anotherOpIdx

Use (1 - ReduceIdx) instead of !reduceIdx.

7483

auto C -> auto *C

7490

Use ScalarV.getOperand(0) instead of ScalarV->getOperand(0)

7492

Don't use UpdateNodeOperands it scares me because it can trigger surprising DAG changes that can invalidate the SDValues you're holding.. Use getNode to create new nodes.

[fakepaper56]

Fix those issues Craig raised. And I also removed anotherOpIdx since I think (1 - ReduceIdx) is enough clear.

[fakepaper56]

Use auto *C for C is pointer

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

7429

I think you also need isNullConstant(V.getOperand(1) to make sure we're extracting the lowest element.

7442

disallow->disallows

7448

Extract.getOperand(0)

7452

Reduce.getOperand(2)

7463

I think you can use isNullFPConstant

8632

Can we just lump all these together calling combineBinOpToReduce directly until we need specific combines for them?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

7444

The ReduceIdx is relevant here. The order of the fadd operands doesn't matter. The reduce operation is before the fadd, we need to know if the fadd can be moved before the reduce.

[fakepaper56]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

7444

VECREDUCE_FADD_VL always has reassociation, so I think I only need to check N->getFlags().hasAllowReassociation() to make sure fadd can be moved before the reduce.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

7444

I meant to say “ReduceIdx ISN’T relevant”

[fakepaper56]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

7444

Yeah. I understand I should remove the condition.

[fakepaper56]

Fix the issues Craig raised.

[fakepaper56]

disallow -> disallows

[fakepaper56]

Update missing issues needed to solve.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

7455

I missed it before, but I believe you need to be able to prove that the VL parameter for the splat isn't 0. In the usual case it's a constant 1 right? S o you can probably just check that it's a constant that isn't 0.

7463

I think you want the isNullFPConstant in the if and a return true here. Just because hasNoSignedZeros is true doesn't mean that -0.0 can't appear.

[frasercrmck]

Taking a step back a bit, this is also a target-independent combine we'd want to perform on vp.reduce operations, right? Is it possible that we may want to lower/combine vector.reduce to vp.reduce and let this sort of combine happen in a target-independent combine?

[fakepaper56]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

7463

When hasNoSignedZeros enabling, compiler insert +0.0 into VECREDUCE_FADD_VL. I think the only way to replace the start value is this combiner combineBinOpToReduce, so the start value is -0.0 is caused by FADD with -0.0. But I think DAGCombiner could fix it.

[fakepaper56]

In D122563#3415868, @frasercrmck wrote:

Taking a step back a bit, this is also a target-independent combine we'd want to perform on vp.reduce operations, right? Is it possible that we may want to lower/combine vector.reduce to vp.reduce and let this sort of combine happen in a target-independent combine?

I think it may be a good idea to do the combine when before-legalized DAG.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

7463

If we use vp.reduce.fadd.nxv2f16 the compiler doesn't insert +0.0 if the user provided -0.0.

declare half @llvm.vp.reduce.fadd.nxv2f16(half, <vscale x 2 x half>, <vscale x 2 x i1>, i32)
                                                                                 
define half @vpreduce_fadd_nxv2f16(half %s, <vscale x 2 x half> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
  %r = call reassoc half @llvm.vp.reduce.fadd.nxv2f16(half -0.0, <vscale x 2 x half> %v, <vscale x 2 x i1> %m, i32 %evl)
  %t = fadd reassoc half %r, %s                                                  
  ret half %t                                                                    
}

[fakepaper56]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

7463

Thank you. I understand it.

[fakepaper56]

Fix the issue raised by reviewers.

[craig.topper]

In D122563#3415868, @frasercrmck wrote:

Taking a step back a bit, this is also a target-independent combine we'd want to perform on vp.reduce operations, right? Is it possible that we may want to lower/combine vector.reduce to vp.reduce and let this sort of combine happen in a target-independent combine?

I think that makes sense, but I have a few questions.

-Do we currently mark VP_REDUCE nodes as Expand on targets that don't support it? I don't see anything in TargetLoweringBase::initActions, but maybe I missed it. I think we would need that fixed to know if we could do the combine so that we only do it on targets that support it.
-What would we use for VL for the VP_REDUCE from a generic combine? vscale * known minimum element count? Then we'd need to detect that and replace it with RISCV::X0 for RISCV?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8632

This wasn't addressed. I don't think we want individual performUMAXCombine, performUMINCombine, etc. functions.

[fakepaper56]

In D122563#3438080, @craig.topper wrote:

-Do we currently mark VP_REDUCE nodes as Expand on targets that don't support it? I don't see anything in TargetLoweringBase::initActions, but maybe I missed it. I think we would need that fixed to know if we could do the combine so that we only do it on targets that support it.

VP_REDUCE nodes are marked as Custom. VP_REDUCE opcodes are elements of IntegerVPOps and FloatingPointVPOps whose elements would be marked as Custom.

-What would we use for VL for the VP_REDUCE from a generic combine? vscale * known minimum element count? Then we'd need to detect that and replace it with RISCV::X0 for RISCV?

I have another question. If we want to transform VECREDUCE to VP_REDUCE before legalization, what is the VL of vectors needed split like <vscale x 16 x i64>?

[fakepaper56]

Since we need to transform VECREDUCE to VP_REDUCE before legalization for Fraser's method, we need to deal with illegal type of VECREDUCE. If we don't have idea to deal with illegal type nodes of VECREDUCE, how about we just use my original combine?

[craig.topper]

In D122563#3451221, @fakepaper56 wrote:

In D122563#3438080, @craig.topper wrote:

-Do we currently mark VP_REDUCE nodes as Expand on targets that don't support it? I don't see anything in TargetLoweringBase::initActions, but maybe I missed it. I think we would need that fixed to know if we could do the combine so that we only do it on targets that support it.

VP_REDUCE nodes are marked as Custom. VP_REDUCE opcodes are elements of IntegerVPOps and FloatingPointVPOps whose elements would be marked as Custom.

They aren't marked Custom or Expand on other targets like X86. They are marked Legal because that is the default. So we can't write a generic DAGCombine until we fix every other target to mark them as Expand. Otherwise the DAGCombine will start creating VP_REDUCE on other targets that don't really support it.

-What would we use for VL for the VP_REDUCE from a generic combine? vscale * known minimum element count? Then we'd need to detect that and replace it with RISCV::X0 for RISCV?

I have another question. If we want to transform VECREDUCE to VP_REDUCE before legalization, what is the VL of vectors needed split like <vscale x 16 x i64>?

The VL would be 16 * ISD::VSCALE. Then we need more DAGCombine's to make sure that gets split nicely into 8*VSCALE after the split. Then we need to teach RISC-V lowering to detect VSCALE based VL to map to X0 for vsetvli.

This all seems like more work than this patch right now.

[craig.topper]

In D122563#3469797, @fakepaper56 wrote:

Since we need to transform VECREDUCE to VP_REDUCE before legalization for Fraser's method, we need to deal with illegal type of VECREDUCE. If we don't have idea to deal with illegal type nodes of VECREDUCE, how about we just use my original combine?

I'm fine with this patch. It makes the most sense with the way things currently are.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8632

Please address this comment and I will approve this patch.

[frasercrmck]

In D122563#3469797, @fakepaper56 wrote:

Since we need to transform VECREDUCE to VP_REDUCE before legalization for Fraser's method, we need to deal with illegal type of VECREDUCE. If we don't have idea to deal with illegal type nodes of VECREDUCE, how about we just use my original combine?

Yeah, this patch is good as it is Thanks for going along with my suggestion and finding out what still needs to be done! Sorry for not getting back to you promptly.

As Craig says, LGTM with his request.

[fakepaper56]

The update replaces specefic function only calling combineBinOpToReduce with combineBinOpToReduce and uses array input version setTargetDAGCombine.

[fakepaper56]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8632

I had lumped them together and call combineBinOpToReduce directly in the latest update.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   setMinimumJumpTableEntries(5);
 
   // Jumps are expensive, compared to logic
   setJumpIsExpensive();
 
   setTargetDAGCombine({ISD::INTRINSIC_WO_CHAIN, ISD::ADD, ISD::SUB, ISD::AND,
                        ISD::OR, ISD::XOR});
 
+  if (Subtarget.hasStdExtF())
+    setTargetDAGCombine({ISD::FADD, ISD::FMAXNUM, ISD::FMINNUM});
+
   if (Subtarget.hasStdExtZbp())
     setTargetDAGCombine({ISD::ROTL, ISD::ROTR});
+
+  if (Subtarget.hasStdExtZbb())
+    setTargetDAGCombine({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN});
+
   if (Subtarget.hasStdExtZbkb())
     setTargetDAGCombine(ISD::BITREVERSE);
   if (Subtarget.hasStdExtZfh() || Subtarget.hasStdExtZbb())
     setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
   if (Subtarget.hasStdExtF())
     setTargetDAGCombine({ISD::ZERO_EXTEND, ISD::FP_TO_SINT, ISD::FP_TO_UINT,
                          ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT});
   if (Subtarget.hasVInstructions())
static Optional<RISCVBitmanipPat> matchGREVIPat(SDValue Op) {
   // patterns. They may be shifted left in certain circumstances.
   static const uint64_t BitmanipMasks[] = {
       0x5555555555555555ULL, 0x3333333333333333ULL, 0x0F0F0F0F0F0F0F0FULL,
       0x00FF00FF00FF00FFULL, 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL};
 
   return matchRISCVBitmanipPat(Op, BitmanipMasks);
 }
 
+// Try to fold (<bop> x, (reduction.<bop> vec, start))
+static SDValue combineBinOpToReduce(SDNode *N, SelectionDAG &DAG) {
+  auto BinOpToRVVReduce = [](unsigned Opc) {
+    switch (Opc) {
+    default:
+      llvm_unreachable("Unhandled binary to transfrom reduction");
+    case ISD::ADD:
+      return RISCVISD::VECREDUCE_ADD_VL;
+    case ISD::UMAX:
+      return RISCVISD::VECREDUCE_UMAX_VL;
+    case ISD::SMAX:
+      return RISCVISD::VECREDUCE_SMAX_VL;
+    case ISD::UMIN:
+      return RISCVISD::VECREDUCE_UMIN_VL;
+    case ISD::SMIN:
+      return RISCVISD::VECREDUCE_SMIN_VL;
+    case ISD::AND:
+      return RISCVISD::VECREDUCE_AND_VL;
+    case ISD::OR:
+      return RISCVISD::VECREDUCE_OR_VL;
+    case ISD::XOR:
+      return RISCVISD::VECREDUCE_XOR_VL;
+    case ISD::FADD:
+      return RISCVISD::VECREDUCE_FADD_VL;
+    case ISD::FMAXNUM:
+      return RISCVISD::VECREDUCE_FMAX_VL;
+    case ISD::FMINNUM:
+      return RISCVISD::VECREDUCE_FMIN_VL;
+    }
+  };
+
+  auto IsReduction = [&BinOpToRVVReduce](SDValue V, unsigned Opc) {
+    return V.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
+           isNullConstant(V.getOperand(1)) &&
+           V.getOperand(0).getOpcode() == BinOpToRVVReduce(Opc);
+  };
+
+  unsigned Opc = N->getOpcode();
+  unsigned ReduceIdx;
+  if (IsReduction(N->getOperand(0), Opc))
+    ReduceIdx = 0;
+  else if (IsReduction(N->getOperand(1), Opc))
+    ReduceIdx = 1;
+  else
+    return SDValue();
+
+  // Skip if FADD disallows reassociation but the combiner needs.
+  if (Opc == ISD::FADD && !N->getFlags().hasAllowReassociation())
+    return SDValue();
+
+  SDValue Extract = N->getOperand(ReduceIdx);
+  SDValue Reduce = Extract.getOperand(0);
+  if (!Reduce.hasOneUse())
+    return SDValue();
+
+  SDValue ScalarV = Reduce.getOperand(2);
+
+  // Make sure that ScalarV is a splat with VL=1.
+  if (ScalarV.getOpcode() != RISCVISD::VFMV_S_F_VL &&
+      ScalarV.getOpcode() != RISCVISD::VMV_S_X_VL &&
+      ScalarV.getOpcode() != RISCVISD::VMV_V_X_VL)
+    return SDValue();
+
+  if (!isOneConstant(ScalarV.getOperand(2)))
+    return SDValue();
+
+  // TODO: Deal with value other than neutral element.
+  auto IsRVVNeutralElement = [Opc, &DAG](SDNode *N, SDValue V) {
+    if (Opc == ISD::FADD && N->getFlags().hasNoSignedZeros() &&
+        isNullFPConstant(V))
+      return true;
+    return DAG.getNeutralElement(Opc, SDLoc(V), V.getSimpleValueType(),
+                                 N->getFlags()) == V;
+  };
+
+  // Check the scalar of ScalarV is neutral element
+  if (!IsRVVNeutralElement(N, ScalarV.getOperand(1)))
+    return SDValue();
+
+  if (!ScalarV.hasOneUse())
+    return SDValue();
+
+  EVT SplatVT = ScalarV.getValueType();
+  SDValue NewStart = N->getOperand(1 - ReduceIdx);
+  unsigned SplatOpc = RISCVISD::VFMV_S_F_VL;
+  if (SplatVT.isInteger()) {
+    auto *C = dyn_cast<ConstantSDNode>(NewStart.getNode());
+    if (!C || C->isZero() || !isInt<5>(C->getSExtValue()))
+      SplatOpc = RISCVISD::VMV_S_X_VL;
+    else
+      SplatOpc = RISCVISD::VMV_V_X_VL;
+  }
+
+  SDValue NewScalarV =
+      DAG.getNode(SplatOpc, SDLoc(N), SplatVT, ScalarV.getOperand(0), NewStart,
+                  ScalarV.getOperand(2));
+  SDValue NewReduce =
+      DAG.getNode(Reduce.getOpcode(), SDLoc(Reduce), Reduce.getValueType(),
+                  Reduce.getOperand(0), Reduce.getOperand(1), NewScalarV,
+                  Reduce.getOperand(3), Reduce.getOperand(4));
+  return DAG.getNode(Extract.getOpcode(), SDLoc(Extract),
+                     Extract.getValueType(), NewReduce, Extract.getOperand(1));
+}
+
 // Match the following pattern as a GREVI(W) operation
 //   (or (BITMANIP_SHL x), (BITMANIP_SRL x))
 static SDValue combineORToGREV(SDValue Op, SelectionDAG &DAG,
                                const RISCVSubtarget &Subtarget) {
   assert(Subtarget.hasStdExtZbp() && "Expected Zbp extenson");
   EVT VT = Op.getValueType();
 
   if (VT == Subtarget.getXLenVT() || (Subtarget.is64Bit() && VT == MVT::i32)) {

 }
 
 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
                                  const RISCVSubtarget &Subtarget) {
   if (SDValue V = transformAddImmMulImm(N, DAG, Subtarget))
     return V;
   if (SDValue V = transformAddShlImm(N, DAG, Subtarget))
     return V;
+  if (SDValue V = combineBinOpToReduce(N, DAG))
+    return V;
   // fold (add (select lhs, rhs, cc, 0, y), x) ->
   //      (select lhs, rhs, cc, x, (add x, y))
   return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false);
 }
 
 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG) {
   // fold (sub x, (select lhs, rhs, cc, 0, y)) ->
   //      (select lhs, rhs, cc, x, (sub x, y))
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
   return combineSelectAndUse(N, N1, N0, DAG, /*AllOnes*/ false);
 }
 
 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG) {
+  if (SDValue V = combineBinOpToReduce(N, DAG))
+    return V;
   // fold (and (select lhs, rhs, cc, -1, y), x) ->
   //      (select lhs, rhs, cc, x, (and x, y))
   return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ true);
 }
 
 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
                                 const RISCVSubtarget &Subtarget) {
   if (Subtarget.hasStdExtZbp()) {
     if (auto GREV = combineORToGREV(SDValue(N, 0), DAG, Subtarget))
       return GREV;
     if (auto GORC = combineORToGORC(SDValue(N, 0), DAG, Subtarget))
       return GORC;
     if (auto SHFL = combineORToSHFL(SDValue(N, 0), DAG, Subtarget))
       return SHFL;
   }
 
+  if (SDValue V = combineBinOpToReduce(N, DAG))
+    return V;
   // fold (or (select cond, 0, y), x) ->
   //      (select cond, x, (or x, y))
   return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false);
 }
 
 static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
 
   // fold (xor (sllw 1, x), -1) -> (rolw ~1, x)
   // NOTE: Assumes ROL being legal means ROLW is legal.
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   if (N0.getOpcode() == RISCVISD::SLLW &&
       isAllOnesConstant(N1) && isOneConstant(N0.getOperand(0)) &&
       TLI.isOperationLegal(ISD::ROTL, MVT::i64)) {
     SDLoc DL(N);
     return DAG.getNode(RISCVISD::ROLW, DL, MVT::i64,
                        DAG.getConstant(~1, DL, MVT::i64), N0.getOperand(1));
   }
 
+  if (SDValue V = combineBinOpToReduce(N, DAG))
+    return V;
   // fold (xor (select cond, 0, y), x) ->
   //      (select cond, x, (xor x, y))
   return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false);
 }
 
 static SDValue
 performSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
                                 const RISCVSubtarget &Subtarget) {
SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
   case ISD::SUB:
     return performSUBCombine(N, DAG);
   case ISD::AND:
     return performANDCombine(N, DAG);
   case ISD::OR:
     return performORCombine(N, DAG, Subtarget);
   case ISD::XOR:
     return performXORCombine(N, DAG);
+  case ISD::FADD:
+  case ISD::UMAX:
+  case ISD::UMIN:
+  case ISD::SMAX:
+  case ISD::SMIN:
+  case ISD::FMAXNUM:
+  case ISD::FMINNUM:
+    return combineBinOpToReduce(N, DAG);
   case ISD::SIGN_EXTEND_INREG:
     return performSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
   case ISD::ZERO_EXTEND:
     // Fold (zero_extend (fp_to_uint X)) to prevent forming fcvt+zexti32 during
     // type legalization. This is safe because fp_to_uint produces poison if
     // it overflows.
     if (N->getValueType(0) == MVT::i64 && Subtarget.is64Bit()) {
       SDValue Src = N->getOperand(0);

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128  -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128  -verify-machineinstrs < %s | FileCheck %s
 
 declare half @llvm.vector.reduce.fadd.v1f16(half, <1 x half>)
 
 define half @vreduce_fadd_v1f16(<1 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_fadd_v1f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e16, mf4, ta, mu
 ; CHECK-NEXT:    vle16.v v8, (a0)

 
 declare half @llvm.vector.reduce.fadd.v2f16(half, <2 x half>)
 
 define half @vreduce_fadd_v2f16(<2 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_fadd_v2f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    fmv.h.x ft0, zero
-; CHECK-NEXT:    fneg.h ft0, ft0
-; CHECK-NEXT:    vfmv.s.f v9, ft0
+; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v9
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.h fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <2 x half>, <2 x half>* %x
   %red = call reassoc half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v)
   ret half %red
 }
 
 define half @vreduce_ord_fadd_v2f16(<2 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v2f16:

 
 declare half @llvm.vector.reduce.fadd.v4f16(half, <4 x half>)
 
 define half @vreduce_fadd_v4f16(<4 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_fadd_v4f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    fmv.h.x ft0, zero
-; CHECK-NEXT:    fneg.h ft0, ft0
-; CHECK-NEXT:    vfmv.s.f v9, ft0
+; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v9
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.h fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <4 x half>, <4 x half>* %x
   %red = call reassoc half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v)
   ret half %red
 }
 
 define half @vreduce_ord_fadd_v4f16(<4 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v4f16:

 
 declare half @llvm.vector.reduce.fadd.v8f16(half, <8 x half>)
 
 define half @vreduce_fadd_v8f16(<8 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_fadd_v8f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    fmv.h.x ft0, zero
-; CHECK-NEXT:    fneg.h ft0, ft0
-; CHECK-NEXT:    vfmv.s.f v9, ft0
+; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v9
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.h fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <8 x half>, <8 x half>* %x
   %red = call reassoc half @llvm.vector.reduce.fadd.v8f16(half %s, <8 x half> %v)
   ret half %red
 }
 
 define half @vreduce_ord_fadd_v8f16(<8 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v8f16:

 
 declare half @llvm.vector.reduce.fadd.v16f16(half, <16 x half>)
 
 define half @vreduce_fadd_v16f16(<16 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_fadd_v16f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    fmv.h.x ft0, zero
-; CHECK-NEXT:    fneg.h ft0, ft0
-; CHECK-NEXT:    vfmv.s.f v10, ft0
+; CHECK-NEXT:    vfmv.s.f v10, fa0
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v10
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.h fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <16 x half>, <16 x half>* %x
   %red = call reassoc half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v)
   ret half %red
 }
 
 define half @vreduce_ord_fadd_v16f16(<16 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v16f16:

 declare half @llvm.vector.reduce.fadd.v32f16(half, <32 x half>)
 
 define half @vreduce_fadd_v32f16(<32 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_fadd_v32f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a1, 32
 ; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    fmv.h.x ft0, zero
-; CHECK-NEXT:    fneg.h ft0, ft0
 ; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT:    vfmv.s.f v12, ft0
+; CHECK-NEXT:    vfmv.s.f v12, fa0
 ; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v12
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.h fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <32 x half>, <32 x half>* %x
   %red = call reassoc half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v)
   ret half %red
 }
 
 define half @vreduce_ord_fadd_v32f16(<32 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v32f16:

 declare half @llvm.vector.reduce.fadd.v64f16(half, <64 x half>)
 
 define half @vreduce_fadd_v64f16(<64 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_fadd_v64f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a1, 64
 ; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    fmv.h.x ft0, zero
-; CHECK-NEXT:    fneg.h ft0, ft0
 ; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT:    vfmv.s.f v16, ft0
+; CHECK-NEXT:    vfmv.s.f v16, fa0
 ; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v16
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.h fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <64 x half>, <64 x half>* %x
   %red = call reassoc half @llvm.vector.reduce.fadd.v64f16(half %s, <64 x half> %v)
   ret half %red
 }
 
 define half @vreduce_ord_fadd_v64f16(<64 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v64f16:

 ; CHECK-LABEL: vreduce_fadd_v128f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a1, 64
 ; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle16.v v16, (a0)
 ; CHECK-NEXT:    vfadd.vv v8, v8, v16
-; CHECK-NEXT:    fmv.h.x ft0, zero
-; CHECK-NEXT:    fneg.h ft0, ft0
 ; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT:    vfmv.s.f v16, ft0
+; CHECK-NEXT:    vfmv.s.f v16, fa0
 ; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v16
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.h fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <128 x half>, <128 x half>* %x
   %red = call reassoc half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v)
   ret half %red
 }
 
 define half @vreduce_ord_fadd_v128f16(<128 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v128f16:

 
 declare float @llvm.vector.reduce.fadd.v2f32(float, <2 x float>)
 
 define float @vreduce_fadd_v2f32(<2 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_fadd_v2f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
-; CHECK-NEXT:    fmv.w.x ft0, zero
-; CHECK-NEXT:    fneg.s ft0, ft0
-; CHECK-NEXT:    vfmv.s.f v9, ft0
+; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v9
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <2 x float>, <2 x float>* %x
   %red = call reassoc float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %v)
   ret float %red
 }
 
 define float @vreduce_ord_fadd_v2f32(<2 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v2f32:
; CHECK-NEXT:    ret
   ret float %red
 }
 
 define float @vreduce_fwadd_v2f32(<2 x half>* %x, float %s) {
 ; CHECK-LABEL: vreduce_fwadd_v2f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    fmv.w.x ft0, zero
-; CHECK-NEXT:    fneg.s ft0, ft0
 ; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.s.f v9, ft0
+; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, mu
 ; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
 ; CHECK-NEXT:    vsetivli zero, 0, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <2 x half>, <2 x half>* %x
   %e = fpext <2 x half> %v to <2 x float>
   %red = call reassoc float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %e)
   ret float %red
 }
 
 define float @vreduce_ord_fwadd_v2f32(<2 x half>* %x, float %s) {

 
 declare float @llvm.vector.reduce.fadd.v4f32(float, <4 x float>)
 
 define float @vreduce_fadd_v4f32(<4 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_fadd_v4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
-; CHECK-NEXT:    fmv.w.x ft0, zero
-; CHECK-NEXT:    fneg.s ft0, ft0
-; CHECK-NEXT:    vfmv.s.f v9, ft0
+; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v9
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <4 x float>, <4 x float>* %x
   %red = call reassoc float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v)
   ret float %red
 }
 
 define float @vreduce_ord_fadd_v4f32(<4 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v4f32:
; CHECK-NEXT:    ret
   ret float %red
 }
 
 define float @vreduce_fwadd_v4f32(<4 x half>* %x, float %s) {
 ; CHECK-LABEL: vreduce_fwadd_v4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    fmv.w.x ft0, zero
-; CHECK-NEXT:    fneg.s ft0, ft0
 ; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.s.f v9, ft0
+; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, mu
 ; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
 ; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <4 x half>, <4 x half>* %x
   %e = fpext <4 x half> %v to <4 x float>
   %red = call reassoc float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %e)
   ret float %red
 }
 
 define float @vreduce_ord_fwadd_v4f32(<4 x half>* %x, float %s) {

 
 declare float @llvm.vector.reduce.fadd.v8f32(float, <8 x float>)
 
 define float @vreduce_fadd_v8f32(<8 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_fadd_v8f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
-; CHECK-NEXT:    fmv.w.x ft0, zero
-; CHECK-NEXT:    fneg.s ft0, ft0
-; CHECK-NEXT:    vfmv.s.f v10, ft0
+; CHECK-NEXT:    vfmv.s.f v10, fa0
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v10
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <8 x float>, <8 x float>* %x
   %red = call reassoc float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %v)
   ret float %red
 }
 
 define float @vreduce_ord_fadd_v8f32(<8 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v8f32:
; CHECK-NEXT:    ret
   ret float %red
 }
 
 define float @vreduce_fwadd_v8f32(<8 x half>* %x, float %s) {
 ; CHECK-LABEL: vreduce_fwadd_v8f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    fmv.w.x ft0, zero
-; CHECK-NEXT:    fneg.s ft0, ft0
 ; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.s.f v9, ft0
+; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, mu
 ; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
 ; CHECK-NEXT:    vsetivli zero, 0, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <8 x half>, <8 x half>* %x
   %e = fpext <8 x half> %v to <8 x float>
   %red = call reassoc float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %e)
   ret float %red
 }
 
 define float @vreduce_ord_fwadd_v8f32(<8 x half>* %x, float %s) {

 
 declare float @llvm.vector.reduce.fadd.v16f32(float, <16 x float>)
 
 define float @vreduce_fadd_v16f32(<16 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_fadd_v16f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
-; CHECK-NEXT:    fmv.w.x ft0, zero
-; CHECK-NEXT:    fneg.s ft0, ft0
-; CHECK-NEXT:    vfmv.s.f v12, ft0
+; CHECK-NEXT:    vfmv.s.f v12, fa0
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v12
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <16 x float>, <16 x float>* %x
   %red = call reassoc float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %v)
   ret float %red
 }
 
 define float @vreduce_ord_fadd_v16f32(<16 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v16f32:
; CHECK-NEXT:    ret
   ret float %red
 }
 
 define float @vreduce_fwadd_v16f32(<16 x half>* %x, float %s) {
 ; CHECK-LABEL: vreduce_fwadd_v16f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    fmv.w.x ft0, zero
-; CHECK-NEXT:    fneg.s ft0, ft0
 ; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.s.f v10, ft0
+; CHECK-NEXT:    vfmv.s.f v10, fa0
 ; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, mu
 ; CHECK-NEXT:    vfwredusum.vs v8, v8, v10
 ; CHECK-NEXT:    vsetivli zero, 0, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <16 x half>, <16 x half>* %x
   %e = fpext <16 x half> %v to <16 x float>
   %red = call reassoc float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %e)
   ret float %red
 }
 
 define float @vreduce_ord_fwadd_v16f32(<16 x half>* %x, float %s) {

 declare float @llvm.vector.reduce.fadd.v32f32(float, <32 x float>)
 
 define float @vreduce_fadd_v32f32(<32 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_fadd_v32f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a1, 32
 ; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
-; CHECK-NEXT:    fmv.w.x ft0, zero
-; CHECK-NEXT:    fneg.s ft0, ft0
 ; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.s.f v16, ft0
+; CHECK-NEXT:    vfmv.s.f v16, fa0
 ; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v16
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <32 x float>, <32 x float>* %x
   %red = call reassoc float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %v)
   ret float %red
 }
 
 define float @vreduce_ord_fadd_v32f32(<32 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v32f32:

 }
 
 define float @vreduce_fwadd_v32f32(<32 x half>* %x, float %s) {
 ; CHECK-LABEL: vreduce_fwadd_v32f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a1, 32
 ; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    fmv.w.x ft0, zero
-; CHECK-NEXT:    fneg.s ft0, ft0
 ; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.s.f v12, ft0
+; CHECK-NEXT:    vfmv.s.f v12, fa0
 ; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu
 ; CHECK-NEXT:    vfwredusum.vs v8, v8, v12
 ; CHECK-NEXT:    vsetivli zero, 0, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <32 x half>, <32 x half>* %x
   %e = fpext <32 x half> %v to <32 x float>
   %red = call reassoc float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %e)
   ret float %red
 }
 
 define float @vreduce_ord_fwadd_v32f32(<32 x half>* %x, float %s) {

 ; CHECK-LABEL: vreduce_fadd_v64f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a1, 32
 ; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle32.v v16, (a0)
 ; CHECK-NEXT:    vfadd.vv v8, v8, v16
-; CHECK-NEXT:    fmv.w.x ft0, zero
-; CHECK-NEXT:    fneg.s ft0, ft0
 ; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.s.f v16, ft0
+; CHECK-NEXT:    vfmv.s.f v16, fa0
 ; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v16
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <64 x float>, <64 x float>* %x
   %red = call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v)
   ret float %red
 }
 
 define float @vreduce_ord_fadd_v64f32(<64 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v64f32:

 ; CHECK-NEXT:    li a1, 64
 ; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    li a0, 32
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, mu
 ; CHECK-NEXT:    vslidedown.vx v16, v8, a0
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu
 ; CHECK-NEXT:    vfwadd.vv v24, v8, v16
-; CHECK-NEXT:    fmv.w.x ft0, zero
-; CHECK-NEXT:    fneg.s ft0, ft0
 ; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.s.f v8, ft0
+; CHECK-NEXT:    vfmv.s.f v8, fa0
 ; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, mu
 ; CHECK-NEXT:    vfredusum.vs v8, v24, v8
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <64 x half>, <64 x half>* %x
   %e = fpext <64 x half> %v to <64 x float>
   %red = call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %e)
   ret float %red
 }
 
 define float @vreduce_ord_fwadd_v64f32(<64 x half>* %x, float %s) {
; CHECK-NEXT:    ret
   %e = fpext <1 x float> %v to <1 x double>
   %red = call double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %e)
   ret double %red
 }
 
 declare double @llvm.vector.reduce.fadd.v2f64(double, <2 x double>)
 
 define double @vreduce_fadd_v2f64(<2 x double>* %x, double %s) {
-; RV32-LABEL: vreduce_fadd_v2f64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT:    vle64.v v8, (a0)
-; RV32-NEXT:    fcvt.d.w ft0, zero
-; RV32-NEXT:    fneg.d ft0, ft0
-; RV32-NEXT:    vfmv.s.f v9, ft0
-; RV32-NEXT:    vfredusum.vs v8, v8, v9
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    fadd.d fa0, fa0, ft0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vreduce_fadd_v2f64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT:    vle64.v v8, (a0)
-; RV64-NEXT:    fmv.d.x ft0, zero
-; RV64-NEXT:    fneg.d ft0, ft0
-; RV64-NEXT:    vfmv.s.f v9, ft0
-; RV64-NEXT:    vfredusum.vs v8, v8, v9
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    fadd.d fa0, fa0, ft0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_fadd_v2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vfmv.s.f v9, fa0
+; CHECK-NEXT:    vfredusum.vs v8, v8, v9
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
   %v = load <2 x double>, <2 x double>* %x
   %red = call reassoc double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %v)
   ret double %red
 }
 
 define double @vreduce_ord_fadd_v2f64(<2 x double>* %x, double %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vfredosum.vs v8, v8, v9
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <2 x double>, <2 x double>* %x
   %red = call double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %v)
   ret double %red
 }
 
 define double @vreduce_fwadd_v2f64(<2 x float>* %x, double %s) {
-; RV32-LABEL: vreduce_fwadd_v2f64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-NEXT:    vle32.v v8, (a0)
-; RV32-NEXT:    fcvt.d.w ft0, zero
-; RV32-NEXT:    fneg.d ft0, ft0
-; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT:    vfmv.s.f v9, ft0
-; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-NEXT:    vfwredusum.vs v8, v8, v9
-; RV32-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    fadd.d fa0, fa0, ft0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vreduce_fwadd_v2f64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT:    vle32.v v8, (a0)
-; RV64-NEXT:    fmv.d.x ft0, zero
-; RV64-NEXT:    fneg.d ft0, ft0
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT:    vfmv.s.f v9, ft0
-; RV64-NEXT:    vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT:    vfwredusum.vs v8, v8, v9
-; RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    fadd.d fa0, fa0, ft0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_fwadd_v2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vfmv.s.f v9, fa0
+; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, mu
+; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
+; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
   %v = load <2 x float>, <2 x float>* %x
   %e = fpext <2 x float> %v to <2 x double>
   %red = call reassoc double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %e)
   ret double %red
 }
 
 define double @vreduce_ord_fwadd_v2f64(<2 x float>* %x, double %s) {
 ; CHECK-LABEL: vreduce_ord_fwadd_v2f64:
; CHECK-NEXT:    ret
   %e = fpext <2 x float> %v to <2 x double>
   %red = call double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %e)
   ret double %red
 }
 
 declare double @llvm.vector.reduce.fadd.v4f64(double, <4 x double>)
 
 define double @vreduce_fadd_v4f64(<4 x double>* %x, double %s) {
-; RV32-LABEL: vreduce_fadd_v4f64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT:    vle64.v v8, (a0)
-; RV32-NEXT:    fcvt.d.w ft0, zero
-; RV32-NEXT:    fneg.d ft0, ft0
-; RV32-NEXT:    vfmv.s.f v10, ft0
-; RV32-NEXT:    vfredusum.vs v8, v8, v10
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    fadd.d fa0, fa0, ft0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vreduce_fadd_v4f64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT:    vle64.v v8, (a0)
-; RV64-NEXT:    fmv.d.x ft0, zero
-; RV64-NEXT:    fneg.d ft0, ft0
-; RV64-NEXT:    vfmv.s.f v10, ft0
-; RV64-NEXT:    vfredusum.vs v8, v8, v10
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    fadd.d fa0, fa0, ft0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_fadd_v4f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vfmv.s.f v10, fa0
+; CHECK-NEXT:    vfredusum.vs v8, v8, v10
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
   %v = load <4 x double>, <4 x double>* %x
   %red = call reassoc double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %v)
   ret double %red
 }
 
 define double @vreduce_ord_fadd_v4f64(<4 x double>* %x, double %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    vfmv.s.f v10, fa0
 ; CHECK-NEXT:    vfredosum.vs v8, v8, v10
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <4 x double>, <4 x double>* %x
   %red = call double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %v)
   ret double %red
 }
 
 define double @vreduce_fwadd_v4f64(<4 x float>* %x, double %s) {
-; RV32-LABEL: vreduce_fwadd_v4f64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
-; RV32-NEXT:    vle32.v v8, (a0)
-; RV32-NEXT:    fcvt.d.w ft0, zero
-; RV32-NEXT:    fneg.d ft0, ft0
-; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT:    vfmv.s.f v9, ft0
-; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
-; RV32-NEXT:    vfwredusum.vs v8, v8, v9
-; RV32-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    fadd.d fa0, fa0, ft0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vreduce_fwadd_v4f64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
-; RV64-NEXT:    vle32.v v8, (a0)
-; RV64-NEXT:    fmv.d.x ft0, zero
-; RV64-NEXT:    fneg.d ft0, ft0
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT:    vfmv.s.f v9, ft0
-; RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
-; RV64-NEXT:    vfwredusum.vs v8, v8, v9
-; RV64-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    fadd.d fa0, fa0, ft0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_fwadd_v4f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vfmv.s.f v9, fa0
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
   %v = load <4 x float>, <4 x float>* %x
   %e = fpext <4 x float> %v to <4 x double>
   %red = call reassoc double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %e)
   ret double %red
 }
 
 define double @vreduce_ord_fwadd_v4f64(<4 x float>* %x, double %s) {
 ; CHECK-LABEL: vreduce_ord_fwadd_v4f64:
; CHECK-NEXT:    ret
   %e = fpext <4 x float> %v to <4 x double>
   %red = call double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %e)
   ret double %red
 }
 
 declare double @llvm.vector.reduce.fadd.v8f64(double, <8 x double>)
 
 define double @vreduce_fadd_v8f64(<8 x double>* %x, double %s) {
-; RV32-LABEL: vreduce_fadd_v8f64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT:    vle64.v v8, (a0)
-; RV32-NEXT:    fcvt.d.w ft0, zero
-; RV32-NEXT:    fneg.d ft0, ft0
-; RV32-NEXT:    vfmv.s.f v12, ft0
-; RV32-NEXT:    vfredusum.vs v8, v8, v12
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    fadd.d fa0, fa0, ft0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vreduce_fadd_v8f64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT:    vle64.v v8, (a0)
-; RV64-NEXT:    fmv.d.x ft0, zero
-; RV64-NEXT:    fneg.d ft0, ft0
-; RV64-NEXT:    vfmv.s.f v12, ft0
-; RV64-NEXT:    vfredusum.vs v8, v8, v12
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    fadd.d fa0, fa0, ft0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_fadd_v8f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vfmv.s.f v12, fa0
+; CHECK-NEXT:    vfredusum.vs v8, v8, v12
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
   %v = load <8 x double>, <8 x double>* %x
   %red = call reassoc double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %v)
   ret double %red
 }
 
 define double @vreduce_ord_fadd_v8f64(<8 x double>* %x, double %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v8f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    vfmv.s.f v12, fa0
 ; CHECK-NEXT:    vfredosum.vs v8, v8, v12
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <8 x double>, <8 x double>* %x
   %red = call double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %v)
   ret double %red
 }
 
 define double @vreduce_fwadd_v8f64(<8 x float>* %x, double %s) {
-; RV32-LABEL: vreduce_fwadd_v8f64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT:    vle32.v v8, (a0)
-; RV32-NEXT:    fcvt.d.w ft0, zero
-; RV32-NEXT:    fneg.d ft0, ft0
-; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT:    vfmv.s.f v10, ft0
-; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT:    vfwredusum.vs v8, v8, v10
-; RV32-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    fadd.d fa0, fa0, ft0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vreduce_fwadd_v8f64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
-; RV64-NEXT:    vle32.v v8, (a0)
-; RV64-NEXT:    fmv.d.x ft0, zero
-; RV64-NEXT:    fneg.d ft0, ft0
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT:    vfmv.s.f v10, ft0
-; RV64-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
-; RV64-NEXT:    vfwredusum.vs v8, v8, v10
-; RV64-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    fadd.d fa0, fa0, ft0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_fwadd_v8f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vfmv.s.f v10, fa0
+; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
+; CHECK-NEXT:    vfwredusum.vs v8, v8, v10
+; CHECK-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
   %v = load <8 x float>, <8 x float>* %x
   %e = fpext <8 x float> %v to <8 x double>
   %red = call reassoc double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %e)
   ret double %red
 }
 
 define double @vreduce_ord_fwadd_v8f64(<8 x float>* %x, double %s) {
 ; CHECK-LABEL: vreduce_ord_fwadd_v8f64:
; CHECK-NEXT:    ret
   %e = fpext <8 x float> %v to <8 x double>
   %red = call double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %e)
   ret double %red
 }
 
 declare double @llvm.vector.reduce.fadd.v16f64(double, <16 x double>)
 
 define double @vreduce_fadd_v16f64(<16 x double>* %x, double %s) {
-; RV32-LABEL: vreduce_fadd_v16f64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT:    vle64.v v8, (a0)
-; RV32-NEXT:    fcvt.d.w ft0, zero
-; RV32-NEXT:    fneg.d ft0, ft0
-; RV32-NEXT:    vfmv.s.f v16, ft0
-; RV32-NEXT:    vfredusum.vs v8, v8, v16
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    fadd.d fa0, fa0, ft0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vreduce_fadd_v16f64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT:    vle64.v v8, (a0)
-; RV64-NEXT:    fmv.d.x ft0, zero
-; RV64-NEXT:    fneg.d ft0, ft0
-; RV64-NEXT:    vfmv.s.f v16, ft0
-; RV64-NEXT:    vfredusum.vs v8, v8, v16
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    fadd.d fa0, fa0, ft0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_fadd_v16f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vfmv.s.f v16, fa0
+; CHECK-NEXT:    vfredusum.vs v8, v8, v16
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
   %v = load <16 x double>, <16 x double>* %x
   %red = call reassoc double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %v)
   ret double %red
 }
 
 define double @vreduce_ord_fadd_v16f64(<16 x double>* %x, double %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v16f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    vfmv.s.f v16, fa0
 ; CHECK-NEXT:    vfredosum.vs v8, v8, v16
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <16 x double>, <16 x double>* %x
   %red = call double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %v)
   ret double %red
 }
 
 define double @vreduce_fwadd_v16f64(<16 x float>* %x, double %s) {
-; RV32-LABEL: vreduce_fwadd_v16f64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 16, e32, m4, ta, mu
-; RV32-NEXT:    vle32.v v8, (a0)
-; RV32-NEXT:    fcvt.d.w ft0, zero
-; RV32-NEXT:    fneg.d ft0, ft0
-; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT:    vfmv.s.f v12, ft0
-; RV32-NEXT:    vsetivli zero, 16, e32, m4, ta, mu
-; RV32-NEXT:    vfwredusum.vs v8, v8, v12
-; RV32-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    fadd.d fa0, fa0, ft0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vreduce_fwadd_v16f64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 16, e32, m4, ta, mu
-; RV64-NEXT:    vle32.v v8, (a0)
-; RV64-NEXT:    fmv.d.x ft0, zero
-; RV64-NEXT:    fneg.d ft0, ft0
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT:    vfmv.s.f v12, ft0
-; RV64-NEXT:    vsetivli zero, 16, e32, m4, ta, mu
-; RV64-NEXT:    vfwredusum.vs v8, v8, v12
-; RV64-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    fadd.d fa0, fa0, ft0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_fwadd_v16f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vfmv.s.f v12, fa0
+; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, mu
+; CHECK-NEXT:    vfwredusum.vs v8, v8, v12
+; CHECK-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
   %v = load <16 x float>, <16 x float>* %x
   %e = fpext <16 x float> %v to <16 x double>
   %red = call reassoc double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %e)
   ret double %red
 }
 
 define double @vreduce_ord_fwadd_v16f64(<16 x float>* %x, double %s) {
 ; CHECK-LABEL: vreduce_ord_fwadd_v16f64:
; CHECK-NEXT:    ret
   %e = fpext <16 x float> %v to <16 x double>
   %red = call double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %e)
   ret double %red
 }
 
 declare double @llvm.vector.reduce.fadd.v32f64(double, <32 x double>)
 
 define double @vreduce_fadd_v32f64(<32 x double>* %x, double %s) {
-; RV32-LABEL: vreduce_fadd_v32f64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT:    vle64.v v8, (a0)
-; RV32-NEXT:    addi a0, a0, 128
-; RV32-NEXT:    vle64.v v16, (a0)
-; RV32-NEXT:    fcvt.d.w ft0, zero
-; RV32-NEXT:    fneg.d ft0, ft0
-; RV32-NEXT:    vfmv.s.f v24, ft0
-; RV32-NEXT:    vfadd.vv v8, v8, v16
-; RV32-NEXT:    vfredusum.vs v8, v8, v24
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    fadd.d fa0, fa0, ft0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vreduce_fadd_v32f64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT:    vle64.v v8, (a0)
-; RV64-NEXT:    addi a0, a0, 128
-; RV64-NEXT:    vle64.v v16, (a0)
-; RV64-NEXT:    fmv.d.x ft0, zero
-; RV64-NEXT:    fneg.d ft0, ft0
-; RV64-NEXT:    vfmv.s.f v24, ft0
-; RV64-NEXT:    vfadd.vv v8, v8, v16
-; RV64-NEXT:    vfredusum.vs v8, v8, v24
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    fadd.d fa0, fa0, ft0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_fadd_v32f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    addi a0, a0, 128
+; CHECK-NEXT:    vle64.v v16, (a0)
+; CHECK-NEXT:    vfmv.s.f v24, fa0
+; CHECK-NEXT:    vfadd.vv v8, v8, v16
+; CHECK-NEXT:    vfredusum.vs v8, v8, v24
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
   %v = load <32 x double>, <32 x double>* %x
   %red = call reassoc double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v)
   ret double %red
 }
 
 define double @vreduce_ord_fadd_v32f64(<32 x double>* %x, double %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v32f64:
 ; CHECK:       # %bb.0:

 ; RV64-NEXT:    fneg.d ft0, ft0
 ; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; RV64-NEXT:    vfmv.s.f v8, ft0
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vfredusum.vs v8, v24, v8
 ; RV64-NEXT:    vfmv.f.s ft0, v8
 ; RV64-NEXT:    fadd.d fa0, fa0, ft0
 ; RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_fwadd_v32f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a1, 32
+; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 16, e32, m8, ta, mu
+; CHECK-NEXT:    vslidedown.vi v16, v8, 16
+; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, mu
+; CHECK-NEXT:    vfwadd.vv v24, v8, v16
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
+; CHECK-NEXT:    vfredusum.vs v8, v24, v8
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
   %v = load <32 x float>, <32 x float>* %x
   %e = fpext <32 x float> %v to <32 x double>
   %red = call reassoc double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %e)
   ret double %red
 }
 
 define double @vreduce_ord_fwadd_v32f64(<32 x float>* %x, double %s) {
 ; CHECK-LABEL: vreduce_ord_fwadd_v32f64:
; CHECK-NEXT:    ret
   ret double %red
 }
 
 define float @vreduce_nsz_fadd_v4f32(<4 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_nsz_fadd_v4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
-; CHECK-NEXT:    vmv.s.x v9, zero
+; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v9
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <4 x float>, <4 x float>* %x
   %red = call reassoc nsz float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v)
   ret float %red
 }

llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+zbb -riscv-v-vector-bits-min=128 -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s
+
+define i64 @reduce_add(i64 %x, <4 x i64> %v) {
+; CHECK-LABEL: reduce_add:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vmv.s.x v10, a0
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
+; CHECK-NEXT:    vredsum.vs v8, v8, v10
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+entry:
+  %rdx = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %v)
+  %res = add i64 %rdx, %x
+  ret i64 %res
+}
+
+define i64 @reduce_add2(<4 x i64> %v) {
+; CHECK-LABEL: reduce_add2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vmv.v.i v10, 8
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
+; CHECK-NEXT:    vredsum.vs v8, v8, v10
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+entry:
+  %rdx = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %v)
+  %res = add i64 %rdx, 8
+  ret i64 %res
+}
+
+define i64 @reduce_and(i64 %x, <4 x i64> %v) {
+; CHECK-LABEL: reduce_and:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vmv.s.x v10, a0
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
+; CHECK-NEXT:    vredand.vs v8, v8, v10
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+entry:
+  %rdx = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %v)
+  %res = and i64 %rdx, %x
+  ret i64 %res
+}
+
+define i64 @reduce_and2(<4 x i64> %v) {
+; CHECK-LABEL: reduce_and2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vmv.v.i v10, 8
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
+; CHECK-NEXT:    vredand.vs v8, v8, v10
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+entry:
+  %rdx = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %v)
+  %res = and i64 %rdx, 8
+  ret i64 %res
+}
+
+define i64 @reduce_or(i64 %x, <4 x i64> %v) {
+; CHECK-LABEL: reduce_or:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vmv.s.x v10, a0
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
+; CHECK-NEXT:    vredor.vs v8, v8, v10
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+entry:
+  %rdx = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %v)
+  %res = or i64 %rdx, %x
+  ret i64 %res
+}
+
+define i64 @reduce_or2(<4 x i64> %v) {
+; CHECK-LABEL: reduce_or2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vmv.v.i v10, 8
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
+; CHECK-NEXT:    vredor.vs v8, v8, v10
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+entry:
+  %rdx = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %v)
+  %res = or i64 %rdx, 8
+  ret i64 %res
+}
+
+define i64 @reduce_xor(i64 %x, <4 x i64> %v) {
+; CHECK-LABEL: reduce_xor:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vmv.s.x v10, a0
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
+; CHECK-NEXT:    vredxor.vs v8, v8, v10
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+entry:
+  %rdx = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %v)
+  %res = xor i64 %rdx, %x
+  ret i64 %res
+}
+
+define i64 @reduce_xor2(<4 x i64> %v) {
+; CHECK-LABEL: reduce_xor2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vmv.s.x v10, zero
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
+; CHECK-NEXT:    vredxor.vs v8, v8, v10
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    andi a0, a0, 8
+; CHECK-NEXT:    ret
+entry:
+  %rdx = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %v)
+  %res = and i64 %rdx, 8
+  ret i64 %res
+}
+
+define i64 @reduce_umax(i64 %x, <4 x i64> %v) {
+; CHECK-LABEL: reduce_umax:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vmv.s.x v10, a0
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
+; CHECK-NEXT:    vredmaxu.vs v8, v8, v10
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+entry:
+  %rdx = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> %v)
+  %res = call i64 @llvm.umax.i64(i64 %rdx, i64 %x)
+  ret i64 %res
+}
+
+define i64 @reduce_umax2(<4 x i64> %v) {
+; CHECK-LABEL: reduce_umax2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vmv.v.i v10, 8
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
+; CHECK-NEXT:    vredmaxu.vs v8, v8, v10
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+entry:
+  %rdx = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> %v)
+  %res = call i64 @llvm.umax.i64(i64 %rdx, i64 8)
+  ret i64 %res
+}
+
+define i64 @reduce_umin(i64 %x, <4 x i64> %v) {
+; CHECK-LABEL: reduce_umin:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vmv.s.x v10, a0
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
+; CHECK-NEXT:    vredminu.vs v8, v8, v10
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+entry:
+  %rdx = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> %v)
+  %res = call i64 @llvm.umin.i64(i64 %rdx, i64 %x)
+  ret i64 %res
+}
+
+define i64 @reduce_umin2(<4 x i64> %v) {
+; CHECK-LABEL: reduce_umin2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vmv.v.i v10, 8
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
+; CHECK-NEXT:    vredminu.vs v8, v8, v10
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+entry:
+  %rdx = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> %v)
+  %res = call i64 @llvm.umin.i64(i64 %rdx, i64 8)
+  ret i64 %res
+}
+
+define i64 @reduce_smax(i64 %x, <4 x i64> %v) {
+; CHECK-LABEL: reduce_smax:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vmv.s.x v10, a0
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
+; CHECK-NEXT:    vredmax.vs v8, v8, v10
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+entry:
+  %rdx = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %v)
+  %res = call i64 @llvm.smax.i64(i64 %rdx, i64 %x)
+  ret i64 %res
+}
+
+define i64 @reduce_smax2(<4 x i64> %v) {
+; CHECK-LABEL: reduce_smax2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vmv.v.i v10, 8
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
+; CHECK-NEXT:    vredmax.vs v8, v8, v10
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+entry:
+  %rdx = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %v)
+  %res = call i64 @llvm.smax.i64(i64 %rdx, i64 8)
+  ret i64 %res
+}
+
+define i64 @reduce_smin(i64 %x, <4 x i64> %v) {
+; CHECK-LABEL: reduce_smin:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vmv.s.x v10, a0
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
+; CHECK-NEXT:    vredmin.vs v8, v8, v10
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+entry:
+  %rdx = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> %v)
+  %res = call i64 @llvm.smin.i64(i64 %rdx, i64 %x)
+  ret i64 %res
+}
+
+define i64 @reduce_smin2(<4 x i64> %v) {
+; CHECK-LABEL: reduce_smin2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vmv.v.i v10, 8
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
+; CHECK-NEXT:    vredmin.vs v8, v8, v10
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+entry:
+  %rdx = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> %v)
+  %res = call i64 @llvm.smin.i64(i64 %rdx, i64 8)
+  ret i64 %res
+}
+
+define float @reduce_fadd(float %x, <4 x float> %v) {
+; CHECK-LABEL: reduce_fadd:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
+; CHECK-NEXT:    vfmv.s.f v9, fa0
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT:    vfredusum.vs v8, v8, v9
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+entry:
+  %rdx = call fast float @llvm.vector.reduce.fadd.v4f32(float %x, <4 x float> %v)
+  ret float %rdx
+}
+
+define float @reduce_fmax(float %x, <4 x float> %v) {
+; CHECK-LABEL: reduce_fmax:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
+; CHECK-NEXT:    vfmv.s.f v9, fa0
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT:    vfredmax.vs v8, v8, v9
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+entry:
+  %rdx = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v)
+  %res = call float @llvm.maxnum.f32(float %x, float %rdx)
+  ret float %res
+}
+
+define float @reduce_fmin(float %x, <4 x float> %v) {
+; CHECK-LABEL: reduce_fmin:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
+; CHECK-NEXT:    vfmv.s.f v9, fa0
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT:    vfredmin.vs v8, v8, v9
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+entry:
+  %rdx = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v)
+  %res = call float @llvm.minnum.f32(float %x, float %rdx)
+  ret float %res
+}
+
+; Function Attrs: nofree nosync nounwind readnone willreturn
+declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)
+declare i64 @llvm.vector.reduce.and.v4i64(<4 x i64>)
+declare i64 @llvm.vector.reduce.or.v4i64(<4 x i64>)
+declare i64 @llvm.vector.reduce.xor.v4i64(<4 x i64>)
+declare i64 @llvm.vector.reduce.umax.v4i64(<4 x i64>)
+declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
+declare i64 @llvm.vector.reduce.smax.v4i64(<4 x i64>)
+declare i64 @llvm.vector.reduce.smin.v4i64(<4 x i64>)
+declare float @llvm.vector.reduce.fadd.v4f32(float, <4 x float>)
+declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)
+declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
+declare i64 @llvm.umax.i64(i64, i64)
+declare i64 @llvm.umin.i64(i64, i64)
+declare i64 @llvm.smax.i64(i64, i64)
+declare i64 @llvm.smin.i64(i64, i64)
+declare float @llvm.maxnum.f32(float ,float)
+declare float @llvm.minnum.f32(float ,float)

llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
-; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
-; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
 
 declare half @llvm.vector.reduce.fadd.nxv1f16(half, <vscale x 1 x half>)
 
 define half @vreduce_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) {
 ; CHECK-LABEL: vreduce_fadd_nxv1f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fmv.h.x ft0, zero
-; CHECK-NEXT:    fneg.h ft0, ft0
 ; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT:    vfmv.s.f v9, ft0
+; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v9
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.h fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %red = call reassoc half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v)
   ret half %red
 }
 
 define half @vreduce_ord_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_nxv1f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
 ; CHECK-NEXT:    vfredosum.vs v8, v8, v9
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %red = call half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fadd.nxv2f16(half, <vscale x 2 x half>)
 
 define half @vreduce_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) {
 ; CHECK-LABEL: vreduce_fadd_nxv2f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fmv.h.x ft0, zero
-; CHECK-NEXT:    fneg.h ft0, ft0
 ; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT:    vfmv.s.f v9, ft0
+; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v9
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.h fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %red = call reassoc half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v)
   ret half %red
 }
 
 define half @vreduce_ord_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_nxv2f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
 ; CHECK-NEXT:    vfredosum.vs v8, v8, v9
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %red = call half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fadd.nxv4f16(half, <vscale x 4 x half>)
 
 define half @vreduce_fadd_nxv4f16(<vscale x 4 x half> %v, half %s) {
 ; CHECK-LABEL: vreduce_fadd_nxv4f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fmv.h.x ft0, zero
-; CHECK-NEXT:    fneg.h ft0, ft0
 ; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT:    vfmv.s.f v9, ft0
+; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v9
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.h fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %red = call reassoc half @llvm.vector.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v)
   ret half %red
 }
 
 define half @vreduce_ord_fadd_nxv4f16(<vscale x 4 x half> %v, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_nxv4f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
 ; CHECK-NEXT:    vfredosum.vs v8, v8, v9
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %red = call half @llvm.vector.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v)
   ret half %red
 }
 
 declare float @llvm.vector.reduce.fadd.nxv1f32(float, <vscale x 1 x float>)
 
 define float @vreduce_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {
 ; CHECK-LABEL: vreduce_fadd_nxv1f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fmv.w.x ft0, zero
-; CHECK-NEXT:    fneg.s ft0, ft0
 ; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.s.f v9, ft0
+; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v9
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %red = call reassoc float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
   ret float %red
 }
 
 define float @vreduce_ord_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_nxv1f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
 ; CHECK-NEXT:    vfredosum.vs v8, v8, v9
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %red = call float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
   ret float %red
 }
 
 define float @vreduce_fwadd_nxv1f32(<vscale x 1 x half> %v, float %s) {
 ; CHECK-LABEL: vreduce_fwadd_nxv1f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fmv.w.x ft0, zero
-; CHECK-NEXT:    fneg.s ft0, ft0
 ; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.s.f v9, ft0
+; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
 ; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
 ; CHECK-NEXT:    vsetivli zero, 0, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %e = fpext <vscale x 1 x half> %v to <vscale x 1 x float>
   %red = call reassoc float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %e)
   ret float %red
 }
 
 define float @vreduce_ord_fwadd_nxv1f32(<vscale x 1 x half> %v, float %s) {
 ; CHECK-LABEL: vreduce_ord_fwadd_nxv1f32:
; CHECK-NEXT:    ret
   ret float %red
 }
 
 declare float @llvm.vector.reduce.fadd.nxv2f32(float, <vscale x 2 x float>)
 
 define float @vreduce_fadd_nxv2f32(<vscale x 2 x float> %v, float %s) {
 ; CHECK-LABEL: vreduce_fadd_nxv2f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fmv.w.x ft0, zero
-; CHECK-NEXT:    fneg.s ft0, ft0
 ; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.s.f v9, ft0
+; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v9
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %red = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v)
   ret float %red
 }
 
 define float @vreduce_ord_fadd_nxv2f32(<vscale x 2 x float> %v, float %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_nxv2f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
 ; CHECK-NEXT:    vfredosum.vs v8, v8, v9
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %red = call float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v)
   ret float %red
 }
 
 define float @vreduce_fwadd_nxv2f32(<vscale x 2 x half> %v, float %s) {
 ; CHECK-LABEL: vreduce_fwadd_nxv2f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fmv.w.x ft0, zero
-; CHECK-NEXT:    fneg.s ft0, ft0
 ; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.s.f v9, ft0
+; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
 ; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
 ; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %e = fpext <vscale x 2 x half> %v to <vscale x 2 x float>
   %red = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %e)
   ret float %red
 }
 
 define float @vreduce_ord_fwadd_nxv2f32(<vscale x 2 x half> %v, float %s) {
 ; CHECK-LABEL: vreduce_ord_fwadd_nxv2f32:
; CHECK-NEXT:    ret
   ret float %red
 }
 
 declare float @llvm.vector.reduce.fadd.nxv4f32(float, <vscale x 4 x float>)
 
 define float @vreduce_fadd_nxv4f32(<vscale x 4 x float> %v, float %s) {
 ; CHECK-LABEL: vreduce_fadd_nxv4f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fmv.w.x ft0, zero
-; CHECK-NEXT:    fneg.s ft0, ft0
 ; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.s.f v10, ft0
+; CHECK-NEXT:    vfmv.s.f v10, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v10
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %red = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v)
   ret float %red
 }
 
 define float @vreduce_ord_fadd_nxv4f32(<vscale x 4 x float> %v, float %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_nxv4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
 ; CHECK-NEXT:    vfmv.s.f v10, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
 ; CHECK-NEXT:    vfredosum.vs v8, v8, v10
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %red = call float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v)
   ret float %red
 }
 
 define float @vreduce_fwadd_nxv4f32(<vscale x 4 x half> %v, float %s) {
 ; CHECK-LABEL: vreduce_fwadd_nxv4f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fmv.w.x ft0, zero
-; CHECK-NEXT:    fneg.s ft0, ft0
 ; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.s.f v9, ft0
+; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
 ; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
 ; CHECK-NEXT:    vsetivli zero, 0, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %e = fpext <vscale x 4 x half> %v to <vscale x 4 x float>
   %red = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %e)
   ret float %red
 }
 
 define float @vreduce_ord_fwadd_nxv4f32(<vscale x 4 x half> %v, float %s) {
 ; CHECK-LABEL: vreduce_ord_fwadd_nxv4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
 ; CHECK-NEXT:    vfwredosum.vs v8, v8, v9
 ; CHECK-NEXT:    vsetivli zero, 0, e32, m1, ta, mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %e = fpext <vscale x 4 x half> %v to <vscale x 4 x float>
   %red = call float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %e)
   ret float %red
 }
 
 declare double @llvm.vector.reduce.fadd.nxv1f64(double, <vscale x 1 x double>)
 
 define double @vreduce_fadd_nxv1f64(<vscale x 1 x double> %v, double %s) {
-; RV32-LABEL: vreduce_fadd_nxv1f64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    fcvt.d.w ft0, zero
-; RV32-NEXT:    fneg.d ft0, ft0
-; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT:    vfmv.s.f v9, ft0
-; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT:    vfredusum.vs v8, v8, v9
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    fadd.d fa0, fa0, ft0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vreduce_fadd_nxv1f64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    fmv.d.x ft0, zero
-; RV64-NEXT:    fneg.d ft0, ft0
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT:    vfmv.s.f v9, ft0
-; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT:    vfredusum.vs v8, v8, v9
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    fadd.d fa0, fa0, ft0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_fadd_nxv1f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vfmv.s.f v9, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT:    vfredusum.vs v8, v8, v9
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
   %red = call reassoc double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v)
   ret double %red
 }
 
 define double @vreduce_ord_fadd_nxv1f64(<vscale x 1 x double> %v, double %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_nxv1f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
 ; CHECK-NEXT:    vfredosum.vs v8, v8, v9
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %red = call double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v)
   ret double %red
 }
 
 define double @vreduce_fwadd_nxv1f64(<vscale x 1 x float> %v, double %s) {
-; RV32-LABEL: vreduce_fwadd_nxv1f64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    fcvt.d.w ft0, zero
-; RV32-NEXT:    fneg.d ft0, ft0
-; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT:    vfmv.s.f v9, ft0
-; RV32-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
-; RV32-NEXT:    vfwredusum.vs v8, v8, v9
-; RV32-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    fadd.d fa0, fa0, ft0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vreduce_fwadd_nxv1f64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    fmv.d.x ft0, zero
-; RV64-NEXT:    fneg.d ft0, ft0
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT:    vfmv.s.f v9, ft0
-; RV64-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
-; RV64-NEXT:    vfwredusum.vs v8, v8, v9
-; RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    fadd.d fa0, fa0, ft0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_fwadd_nxv1f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vfmv.s.f v9, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
+; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
   %e = fpext <vscale x 1 x float> %v to <vscale x 1 x double>
   %red = call reassoc double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %e)
   ret double %red
 }
 
 define double @vreduce_ord_fwadd_nxv1f64(<vscale x 1 x float> %v, double %s) {
 ; CHECK-LABEL: vreduce_ord_fwadd_nxv1f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
 ; CHECK-NEXT:    vfwredosum.vs v8, v8, v9
 ; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %e = fpext <vscale x 1 x float> %v to <vscale x 1 x double>
   %red = call double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %e)
   ret double %red
 }
 
 declare double @llvm.vector.reduce.fadd.nxv2f64(double, <vscale x 2 x double>)
 
 define double @vreduce_fadd_nxv2f64(<vscale x 2 x double> %v, double %s) {
-; RV32-LABEL: vreduce_fadd_nxv2f64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    fcvt.d.w ft0, zero
-; RV32-NEXT:    fneg.d ft0, ft0
-; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT:    vfmv.s.f v10, ft0
-; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT:    vfredusum.vs v8, v8, v10
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    fadd.d fa0, fa0, ft0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vreduce_fadd_nxv2f64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    fmv.d.x ft0, zero
-; RV64-NEXT:    fneg.d ft0, ft0
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT:    vfmv.s.f v10, ft0
-; RV64-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; RV64-NEXT:    vfredusum.vs v8, v8, v10
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    fadd.d fa0, fa0, ft0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_fadd_nxv2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vfmv.s.f v10, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT:    vfredusum.vs v8, v8, v10
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
   %red = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v)
   ret double %red
 }
 
 define double @vreduce_ord_fadd_nxv2f64(<vscale x 2 x double> %v, double %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_nxv2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; CHECK-NEXT:    vfmv.s.f v10, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
 ; CHECK-NEXT:    vfredosum.vs v8, v8, v10
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %red = call double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v)
   ret double %red
 }
 
 define double @vreduce_fwadd_nxv2f64(<vscale x 2 x float> %v, double %s) {
-; RV32-LABEL: vreduce_fwadd_nxv2f64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    fcvt.d.w ft0, zero
-; RV32-NEXT:    fneg.d ft0, ft0
-; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT:    vfmv.s.f v9, ft0
-; RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
-; RV32-NEXT:    vfwredusum.vs v8, v8, v9
-; RV32-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    fadd.d fa0, fa0, ft0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vreduce_fwadd_nxv2f64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    fmv.d.x ft0, zero
-; RV64-NEXT:    fneg.d ft0, ft0
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT:    vfmv.s.f v9, ft0
-; RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
-; RV64-NEXT:    vfwredusum.vs v8, v8, v9
-; RV64-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    fadd.d fa0, fa0, ft0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_fwadd_nxv2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vfmv.s.f v9, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
   %e = fpext <vscale x 2 x float> %v to <vscale x 2 x double>
   %red = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %e)
   ret double %red
 }
 
 define double @vreduce_ord_fwadd_nxv2f64(<vscale x 2 x float> %v, double %s) {
 ; CHECK-LABEL: vreduce_ord_fwadd_nxv2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
 ; CHECK-NEXT:    vfwredosum.vs v8, v8, v9
 ; CHECK-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %e = fpext <vscale x 2 x float> %v to <vscale x 2 x double>
   %red = call double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %e)
   ret double %red
 }
 
 declare double @llvm.vector.reduce.fadd.nxv4f64(double, <vscale x 4 x double>)
 
 define double @vreduce_fadd_nxv4f64(<vscale x 4 x double> %v, double %s) {
-; RV32-LABEL: vreduce_fadd_nxv4f64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    fcvt.d.w ft0, zero
-; RV32-NEXT:    fneg.d ft0, ft0
-; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT:    vfmv.s.f v12, ft0
-; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT:    vfredusum.vs v8, v8, v12
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    fadd.d fa0, fa0, ft0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vreduce_fadd_nxv4f64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    fmv.d.x ft0, zero
-; RV64-NEXT:    fneg.d ft0, ft0
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT:    vfmv.s.f v12, ft0
-; RV64-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; RV64-NEXT:    vfredusum.vs v8, v8, v12
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    fadd.d fa0, fa0, ft0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_fadd_nxv4f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vfmv.s.f v12, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT:    vfredusum.vs v8, v8, v12
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
   %red = call reassoc double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v)
   ret double %red
 }
 
 define double @vreduce_ord_fadd_nxv4f64(<vscale x 4 x double> %v, double %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_nxv4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; CHECK-NEXT:    vfmv.s.f v12, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
 ; CHECK-NEXT:    vfredosum.vs v8, v8, v12
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %red = call double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v)
   ret double %red
 }
 
 define double @vreduce_fwadd_nxv4f64(<vscale x 4 x float> %v, double %s) {
-; RV32-LABEL: vreduce_fwadd_nxv4f64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    fcvt.d.w ft0, zero
-; RV32-NEXT:    fneg.d ft0, ft0
-; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT:    vfmv.s.f v10, ft0
-; RV32-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
-; RV32-NEXT:    vfwredusum.vs v8, v8, v10
-; RV32-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    fadd.d fa0, fa0, ft0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vreduce_fwadd_nxv4f64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    fmv.d.x ft0, zero
-; RV64-NEXT:    fneg.d ft0, ft0
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT:    vfmv.s.f v10, ft0
-; RV64-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
-; RV64-NEXT:    vfwredusum.vs v8, v8, v10
-; RV64-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    fadd.d fa0, fa0, ft0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vreduce_fwadd_nxv4f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
+; CHECK-NEXT:    vfmv.s.f v10, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vfwredusum.vs v8, v8, v10
+; CHECK-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
   %e = fpext <vscale x 4 x float> %v to <vscale x 4 x double>
   %red = call reassoc double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %e)
   ret double %red
 }
 
 define double @vreduce_ord_fwadd_nxv4f64(<vscale x 4 x float> %v, double %s) {
 ; CHECK-LABEL: vreduce_ord_fwadd_nxv4f64:
 ; CHECK:       # %bb.0:
; CHECK-NEXT:    ret
   %red = call double @llvm.vector.reduce.fmax.nxv16f64(<vscale x 16 x double> %v)
   ret double %red
 }
 
 define float @vreduce_nsz_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {
 ; CHECK-LABEL: vreduce_nsz_fadd_nxv1f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT:    vmv.s.x v9, zero
+; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v9
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %red = call reassoc nsz float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
   ret float %red
 }