[RISCV] Update Zba, Zbb, Zbc, and Zbs version from 0.93 to 1.0.

[craig.topper]

Summary

I've removed the Zbs W instructions that are not part of the frozen spec.

References to B as an extension name have been removed. Tests are updated or split accordingly.

[kito-cheng]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

504

Those instruction are gone since 0.94 draft, and not add back on 1.0, so I think that should removed once we upgrade to 1.0.

528

Same here.

[craig.topper]

Remove Zbs W instructions.

[kito-cheng]

We might need to update the version output for ELF attribute too, but I would prefer waiting https://reviews.llvm.org/D105168 instead of bump version in many place every time...

[craig.topper]

Update attributes as well

[craig.topper]

In D110669#3029140, @kito-cheng wrote:

We might need to update the version output for ELF attribute too, but I would prefer waiting https://reviews.llvm.org/D105168 instead of bump version in many place every time...

Done. Waiting for D105168 wouldn't prevent needing to update the tests so I went ahead and did it.

[asb]

Should we rename RISCVInstrInfoB.td? Should we remove b0p93 from march parsing?

I think so.

[craig.topper]

Drop experimental-b. Update tests accordingly.
Rename RISCVInstrInfoB.td RISCVInstrInfoZb.td

[craig.topper]

Remove hasStdExtB from RISCVSubtarget.h

[craig.topper]

Rebase after removal of Zbproposedc

[craig.topper]

Would it be better to break this patch down into smaller parts. Maybe removing +experimental-b and the associated test changes first?

[craig.topper]

Split the removal of B to a separate patch D111338

[craig.topper]

Rebase

[craig.topper]

Add back dropped changes to RISCV.td

[achieveartificialintelligence]

clang/lib/Driver/ToolChains/Arch/RISCV.cpp

62–64

Need format here?

[craig.topper]

clang-format

[luismarques]

LGTM.

clang/lib/Basic/Targets/RISCV.h

 class RISCVTargetInfo : public TargetInfo {
 protected:
   std::string ABI, CPU;
   bool HasM = false;
   bool HasA = false;
   bool HasF = false;
   bool HasD = false;
   bool HasC = false;
-  bool HasB = false;
   bool HasV = false;
   bool HasZba = false;
   bool HasZbb = false;
   bool HasZbc = false;
   bool HasZbe = false;
   bool HasZbf = false;
   bool HasZbm = false;
   bool HasZbp = false;

clang/lib/Basic/Targets/RISCV.cpp

void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
   if (HasD)
     Builder.defineMacro("__riscv_d", "2000000");
 
   if (HasC) {
     Builder.defineMacro("__riscv_c", "2000000");
     Builder.defineMacro("__riscv_compressed");
   }
 
-  if (HasB) {
-    Builder.defineMacro("__riscv_b", "93000");
-    Builder.defineMacro("__riscv_bitmanip");
-  }
-
   if (HasV) {
     Builder.defineMacro("__riscv_v", "10000");
     Builder.defineMacro("__riscv_vector");
   }
 
   if (HasZba)
-    Builder.defineMacro("__riscv_zba", "93000");
+    Builder.defineMacro("__riscv_zba", "1000000");
 
   if (HasZbb)
-    Builder.defineMacro("__riscv_zbb", "93000");
+    Builder.defineMacro("__riscv_zbb", "1000000");
 
   if (HasZbc)
-    Builder.defineMacro("__riscv_zbc", "93000");
+    Builder.defineMacro("__riscv_zbc", "1000000");
 
   if (HasZbe)
     Builder.defineMacro("__riscv_zbe", "93000");
 
   if (HasZbf)
     Builder.defineMacro("__riscv_zbf", "93000");
 
   if (HasZbm)
     Builder.defineMacro("__riscv_zbm", "93000");
 
   if (HasZbp)
     Builder.defineMacro("__riscv_zbp", "93000");
 
   if (HasZbproposedc)
     Builder.defineMacro("__riscv_zbproposedc", "93000");
 
   if (HasZbr)
     Builder.defineMacro("__riscv_zbr", "93000");
 
   if (HasZbs)
-    Builder.defineMacro("__riscv_zbs", "93000");
+    Builder.defineMacro("__riscv_zbs", "1000000");
 
   if (HasZbt)
     Builder.defineMacro("__riscv_zbt", "93000");
 
   if (HasZfh)
     Builder.defineMacro("__riscv_zfh", "1000");
 
   if (HasZvamo)
return llvm::StringSwitch<bool>(Feature)
       .Case("riscv32", !Is64Bit)
       .Case("riscv64", Is64Bit)
       .Case("64bit", Is64Bit)
       .Case("m", HasM)
       .Case("a", HasA)
       .Case("f", HasF)
       .Case("d", HasD)
       .Case("c", HasC)
-      .Case("experimental-b", HasB)
       .Case("experimental-v", HasV)
       .Case("experimental-zba", HasZba)
       .Case("experimental-zbb", HasZbb)
       .Case("experimental-zbc", HasZbc)
       .Case("experimental-zbe", HasZbe)
       .Case("experimental-zbf", HasZbf)
       .Case("experimental-zbm", HasZbm)
       .Case("experimental-zbp", HasZbp)
for (const auto &Feature : Features) {
     else if (Feature == "+a")
       HasA = true;
     else if (Feature == "+f")
       HasF = true;
     else if (Feature == "+d")
       HasD = true;
     else if (Feature == "+c")
       HasC = true;
-    else if (Feature == "+experimental-b")
-      HasB = true;
     else if (Feature == "+experimental-v")
       HasV = true;
     else if (Feature == "+experimental-zba")
       HasZba = true;
     else if (Feature == "+experimental-zbb")
       HasZbb = true;
     else if (Feature == "+experimental-zbc")
       HasZbc = true;

clang/lib/Driver/ToolChains/Arch/RISCV.cpp

if (Ext.startswith("z"))
     return "z";
   return StringRef();
 }
 
 // If the extension is supported as experimental, return the version of that
 // extension that the compiler currently supports.
 static Optional<RISCVExtensionVersion>
 isExperimentalExtension(StringRef Ext) {
-  if (Ext == "b" || Ext == "zba" || Ext == "zbb" || Ext == "zbc" ||
-      Ext == "zbe" || Ext == "zbf" || Ext == "zbm" || Ext == "zbp" ||
-      Ext == "zbr" || Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
+  if (Ext == "zba" || Ext == "zbb" || Ext == "zbc" || Ext == "zbs")
+    return RISCVExtensionVersion{"1", "0"};
+  if (Ext == "zbe" || Ext == "zbf" || Ext == "zbm" || Ext == "zbp" ||
+      Ext == "zbr" || Ext == "zbt" || Ext == "zbproposedc")
     return RISCVExtensionVersion{"0", "93"};
   if (Ext == "v" || Ext == "zvamo" || Ext == "zvlsseg")
     return RISCVExtensionVersion{"0", "10"};
   if (Ext == "zfh")
     return RISCVExtensionVersion{"0", "1"};
   return None;
 }
 
case 'f':
       break;
     case 'd':
       Features.push_back("+d");
       HasD = true;
       break;
     case 'c':
       Features.push_back("+c");
       break;
-    case 'b':
-      Features.push_back("+experimental-b");
-      Features.push_back("+experimental-zba");
-      Features.push_back("+experimental-zbb");
-      Features.push_back("+experimental-zbc");
-      Features.push_back("+experimental-zbe");
-      Features.push_back("+experimental-zbf");
-      Features.push_back("+experimental-zbm");
-      Features.push_back("+experimental-zbp");
-      Features.push_back("+experimental-zbr");
-      Features.push_back("+experimental-zbs");
-      Features.push_back("+experimental-zbt");
-      break;
     case 'v':
       Features.push_back("+experimental-v");
       Features.push_back("+experimental-zvlsseg");
       break;
     }
 
     // Consume full extension name and version, including any optional '_'
     // between this extension and the next

clang/test/Driver/riscv-arch.c

 // RV32-TARGET: "-triple" "riscv32-unknown-unknown-elf"
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv64i -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
 // RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
 // RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s
-// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32ib'
-// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
-
-// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -menable-experimental-extensions -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s
-// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32ib'
-// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number
-
-// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p1 -menable-experimental-extensions -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s
-// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32ib0p1'
-// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension
-
-// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p93 -menable-experimental-extensions -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
-// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-b"
-
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-NOFLAG %s
 // RV32-EXPERIMENTAL-ZBB-NOFLAG: error: invalid arch name 'rv32izbb'
 // RV32-EXPERIMENTAL-ZBB-NOFLAG: requires '-menable-experimental-extensions'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p93 -menable-experimental-extensions -### %s \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0 -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB %s
 // RV32-EXPERIMENTAL-ZBB: "-target-feature" "+experimental-zbb"
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p93_zbp0p93 -menable-experimental-extensions -### %s \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0_zbp0p93 -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP %s
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbb"
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbp"
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p93zbp0p93 -menable-experimental-extensions -### %s \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0zbp0p93 -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
-// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb0p93zbp0p93', multi-character extensions must be separated by underscores
+// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb1p0zbp0p93', multi-character extensions must be separated by underscores
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32izba0p93 -menable-experimental-extensions -### %s \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izba1p0 -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s
 // RV32-EXPERIMENTAL-ZBA: "-target-feature" "+experimental-zba"
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOFLAG %s
 // RV32-EXPERIMENTAL-V-NOFLAG: error: invalid arch name 'rv32iv'
 // RV32-EXPERIMENTAL-V-NOFLAG: requires '-menable-experimental-extensions'
 

clang/test/Preprocessor/riscv-target-features.c

 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ic -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // CHECK-C-EXT: __riscv_c 2000000
 // CHECK-C-EXT: __riscv_compressed 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv32ib0p93 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
-// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv64ib0p93 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
-// CHECK-B-EXT: __riscv_b 93000
-// CHECK-B-EXT: __riscv_bitmanip 1
-// CHECK-B-EXT: __riscv_zba 93000
-// CHECK-B-EXT: __riscv_zbb 93000
-// CHECK-B-EXT: __riscv_zbc 93000
-// CHECK-B-EXT: __riscv_zbe 93000
-// CHECK-B-EXT: __riscv_zbf 93000
-// CHECK-B-EXT: __riscv_zbm 93000
-// CHECK-B-EXT: __riscv_zbp 93000
-// CHECK-B-EXT: __riscv_zbr 93000
-// CHECK-B-EXT: __riscv_zbs 93000
-// CHECK-B-EXT: __riscv_zbt 93000
-
-// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv32izba0p93 -x c -E -dM %s \
+// RUN: -march=rv32izba1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv64izba0p93 -x c -E -dM %s \
+// RUN: -march=rv64izba1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s
 // CHECK-ZBA-NOT: __riscv_b
-// CHECK-ZBA-EXT: __riscv_zba 93000
+// CHECK-ZBA-EXT: __riscv_zba 1000000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv32izbb0p93 -x c -E -dM %s \
+// RUN: -march=rv32izbb1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBB-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv64izbb0p93 -x c -E -dM %s \
+// RUN: -march=rv64izbb1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBB-EXT %s
 // CHECK-ZBB-NOT: __riscv_b
-// CHECK-ZBB-EXT: __riscv_zbb 93000
+// CHECK-ZBB-EXT: __riscv_zbb 1000000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv32izbc0p93 -x c -E -dM %s \
+// RUN: -march=rv32izbc1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBC-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv64izbc0p93 -x c -E -dM %s \
+// RUN: -march=rv64izbc1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBC-EXT %s
 // CHECK-ZBC-NOT: __riscv_b
-// CHECK-ZBC-EXT: __riscv_zbc 93000
+// CHECK-ZBC-EXT: __riscv_zbc 1000000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32izbe0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBE-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv64izbe0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBE-EXT %s
 // CHECK-ZBE-NOT: __riscv_b

 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBR-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv64izbr0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBR-EXT %s
 // CHECK-ZBR-NOT: __riscv_b
 // CHECK-ZBR-EXT: __riscv_zbr 93000
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv32izbs0p93 -x c -E -dM %s \
+// RUN: -march=rv32izbs1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBS-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv64izbs0p93 -x c -E -dM %s \
+// RUN: -march=rv64izbs1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBS-EXT %s
 // CHECK-ZBS-NOT: __riscv_b
-// CHECK-ZBS-EXT: __riscv_zbs 93000
+// CHECK-ZBS-EXT: __riscv_zbs 1000000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32izbt0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBT-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv64izbt0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBT-EXT %s
 // CHECK-ZBT-NOT: __riscv_b

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

if (Tag == RISCVAttrs::ARCH) {
     // .attribute arch overrides the current architecture, so unset all
     // currently enabled extensions
     clearFeatureBits(RISCV::FeatureRV32E, "e");
     clearFeatureBits(RISCV::FeatureStdExtM, "m");
     clearFeatureBits(RISCV::FeatureStdExtA, "a");
     clearFeatureBits(RISCV::FeatureStdExtF, "f");
     clearFeatureBits(RISCV::FeatureStdExtD, "d");
     clearFeatureBits(RISCV::FeatureStdExtC, "c");
-    clearFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
     clearFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
     clearFeatureBits(RISCV::FeatureStdExtZfh, "experimental-zfh");
     clearFeatureBits(RISCV::FeatureStdExtZba, "experimental-zba");
     clearFeatureBits(RISCV::FeatureStdExtZbb, "experimental-zbb");
     clearFeatureBits(RISCV::FeatureStdExtZbc, "experimental-zbc");
     clearFeatureBits(RISCV::FeatureStdExtZbe, "experimental-zbe");
     clearFeatureBits(RISCV::FeatureStdExtZbf, "experimental-zbf");
     clearFeatureBits(RISCV::FeatureStdExtZbm, "experimental-zbm");
while (!Arch.empty()) {
         setFeatureBits(RISCV::FeatureStdExtA, "a");
       else if (Arch[0] == 'f')
         setFeatureBits(RISCV::FeatureStdExtF, "f");
       else if (Arch[0] == 'd') {
         setFeatureBits(RISCV::FeatureStdExtF, "f");
         setFeatureBits(RISCV::FeatureStdExtD, "d");
       } else if (Arch[0] == 'c') {
         setFeatureBits(RISCV::FeatureStdExtC, "c");
-      } else if (Arch[0] == 'b') {
-        setFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
       } else if (Arch[0] == 'v') {
         setFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
       } else if (Arch[0] == 's' || Arch[0] == 'x' || Arch[0] == 'z') {
         StringRef Ext =
             Arch.take_until([](char c) { return ::isdigit(c) || c == '_'; });
         if (Ext == "zba")
           setFeatureBits(RISCV::FeatureStdExtZba, "experimental-zba");
         else if (Ext == "zbb")
if (Tag != RISCVAttrs::ARCH) {
       if (getFeatureBits(RISCV::FeatureStdExtA))
         formalArchStr = (Twine(formalArchStr) + "_a2p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtF))
         formalArchStr = (Twine(formalArchStr) + "_f2p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtD))
         formalArchStr = (Twine(formalArchStr) + "_d2p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtC))
         formalArchStr = (Twine(formalArchStr) + "_c2p0").str();
-      if (getFeatureBits(RISCV::FeatureStdExtB))
-        formalArchStr = (Twine(formalArchStr) + "_b0p93").str();
       if (getFeatureBits(RISCV::FeatureStdExtV))
         formalArchStr = (Twine(formalArchStr) + "_v0p10").str();
       if (getFeatureBits(RISCV::FeatureStdExtZfh))
         formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str();
       if (getFeatureBits(RISCV::FeatureStdExtZba))
-        formalArchStr = (Twine(formalArchStr) + "_zba0p93").str();
+        formalArchStr = (Twine(formalArchStr) + "_zba1p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtZbb))
-        formalArchStr = (Twine(formalArchStr) + "_zbb0p93").str();
+        formalArchStr = (Twine(formalArchStr) + "_zbb1p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtZbc))
-        formalArchStr = (Twine(formalArchStr) + "_zbc0p93").str();
+        formalArchStr = (Twine(formalArchStr) + "_zbc1p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtZbe))
         formalArchStr = (Twine(formalArchStr) + "_zbe0p93").str();
       if (getFeatureBits(RISCV::FeatureStdExtZbf))
         formalArchStr = (Twine(formalArchStr) + "_zbf0p93").str();
       if (getFeatureBits(RISCV::FeatureStdExtZbm))
         formalArchStr = (Twine(formalArchStr) + "_zbm0p93").str();
       if (getFeatureBits(RISCV::FeatureStdExtZbp))
         formalArchStr = (Twine(formalArchStr) + "_zbp0p93").str();
       if (getFeatureBits(RISCV::FeatureStdExtZbproposedc))
         formalArchStr = (Twine(formalArchStr) + "_zbproposedc0p93").str();
       if (getFeatureBits(RISCV::FeatureStdExtZbr))
         formalArchStr = (Twine(formalArchStr) + "_zbr0p93").str();
       if (getFeatureBits(RISCV::FeatureStdExtZbs))
-        formalArchStr = (Twine(formalArchStr) + "_zbs0p93").str();
+        formalArchStr = (Twine(formalArchStr) + "_zbs1p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtZbt))
         formalArchStr = (Twine(formalArchStr) + "_zbt0p93").str();
       if (getFeatureBits(RISCV::FeatureStdExtZvamo))
         formalArchStr = (Twine(formalArchStr) + "_zvamo0p10").str();
       if (getFeatureBits(RISCV::FeatureStdExtZvlsseg))
         formalArchStr = (Twine(formalArchStr) + "_zvlsseg0p10").str();
 
       getTargetStreamer().emitTextAttribute(Tag, formalArchStr);

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
   if (STI.hasFeature(RISCV::FeatureStdExtA))
     Arch += "_a2p0";
   if (STI.hasFeature(RISCV::FeatureStdExtF))
     Arch += "_f2p0";
   if (STI.hasFeature(RISCV::FeatureStdExtD))
     Arch += "_d2p0";
   if (STI.hasFeature(RISCV::FeatureStdExtC))
     Arch += "_c2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtB))
-    Arch += "_b0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtV))
     Arch += "_v0p10";
   if (STI.hasFeature(RISCV::FeatureStdExtZfh))
     Arch += "_zfh0p1";
   if (STI.hasFeature(RISCV::FeatureStdExtZba))
-    Arch += "_zba0p93";
+    Arch += "_zba1p0";
   if (STI.hasFeature(RISCV::FeatureStdExtZbb))
-    Arch += "_zbb0p93";
+    Arch += "_zbb1p0";
   if (STI.hasFeature(RISCV::FeatureStdExtZbc))
-    Arch += "_zbc0p93";
+    Arch += "_zbc1p0";
   if (STI.hasFeature(RISCV::FeatureStdExtZbe))
     Arch += "_zbe0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtZbf))
     Arch += "_zbf0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtZbm))
     Arch += "_zbm0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtZbp))
     Arch += "_zbp0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtZbproposedc))
     Arch += "_zbproposedc0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtZbr))
     Arch += "_zbr0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtZbs))
-    Arch += "_zbs0p93";
+    Arch += "_zbs1p0";
   if (STI.hasFeature(RISCV::FeatureStdExtZbt))
     Arch += "_zbt0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtZvamo))
     Arch += "_zvamo0p10";
   if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
     Arch += "_zvlsseg0p10";
 
   emitTextAttribute(RISCVAttrs::ARCH, Arch);

llvm/lib/Target/RISCV/RISCV.td

 
 def FeatureStdExtZbproposedc
     : SubtargetFeature<"experimental-zbproposedc", "HasStdExtZbproposedc", "true",
                        "'Zbproposedc' (Proposed Compressed 'B' Instructions)">;
 def HasStdExtZbproposedc : Predicate<"Subtarget->hasStdExtZbproposedc()">,
                            AssemblerPredicate<(all_of FeatureStdExtZbproposedc),
                            "'Zbproposedc' (Proposed Compressed 'B' Instructions)">;
 
-def FeatureStdExtB
-    : SubtargetFeature<"experimental-b", "HasStdExtB", "true",
-                       "'B' (Bit Manipulation Instructions)",
-                       [FeatureStdExtZba,
-                        FeatureStdExtZbb,
-                        FeatureStdExtZbc,
-                        FeatureStdExtZbe,
-                        FeatureStdExtZbf,
-                        FeatureStdExtZbm,
-                        FeatureStdExtZbp,
-                        FeatureStdExtZbr,
-                        FeatureStdExtZbs,
-                        FeatureStdExtZbt]>;
-def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
-                           AssemblerPredicate<(all_of FeatureStdExtB),
-                           "'B' (Bit Manipulation Instructions)">;
-
 def FeatureNoRVCHints
     : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
                        "Disable RVC Hint Instructions.">;
 def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
                   AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
                                       "RVC Hint Instructions">;
 
 def FeatureStdExtV

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 // Standard extensions
 //===----------------------------------------------------------------------===//
 
 include "RISCVInstrInfoM.td"
 include "RISCVInstrInfoA.td"
 include "RISCVInstrInfoF.td"
 include "RISCVInstrInfoD.td"
 include "RISCVInstrInfoC.td"
-include "RISCVInstrInfoB.td"
+include "RISCVInstrInfoZb.td"
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZfh.td"

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

-//===-- RISCVInstrInfoB.td - RISC-V 'B' instructions -------*- tablegen -*-===//
+//===-- RISCVInstrInfoZb.td - RISC-V Bitmanip instructions -*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
-// This file describes the RISC-V instructions from the standard 'B' Bitmanip
-// extension, version 0.93.
-// This version is still experimental as the 'B' extension hasn't been
+// This file describes the RISC-V instructions from the standard Bitmanip
+// extensions, versions:
+//   Zba - 1.0
+//   Zbb - 1.0
+//   Zbc - 1.0
+//   Zbs - 1.0
+//   Zbe - 0.93
+//   Zbf - 0.93
+//   Zbm - 0.93
+//   Zbp - 0.93
+//   Zbr - 0.93
+//   Zbt - 0.93
+// This version is still experimental as the Bitmanip extensions haven't been
 // ratified yet.
 //
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // Operand and SDNode transformation definitions.
 //===----------------------------------------------------------------------===//
 

 } // Predicates = [HasStdExtZbb, IsRV64]
 
 let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
 def ROLW  : ALUW_rr<0b0110000, 0b001, "rolw">,
             Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>;
 def RORW  : ALUW_rr<0b0110000, 0b101, "rorw">,
             Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>;
 } // Predicates = [HasStdExtZbbOrZbp, IsRV64]
 
-let Predicates = [HasStdExtZbs, IsRV64] in {
-// NOTE: These instructions have been removed from the 0.94 spec. As a result
-// we have no isel patterns for them.
-def BCLRW : ALUW_rr<0b0100100, 0b001, "bclrw">, Sched<[]>;
-def BSETW : ALUW_rr<0b0010100, 0b001, "bsetw">, Sched<[]>;
-def BINVW : ALUW_rr<0b0110100, 0b001, "binvw">, Sched<[]>;
-def BEXTW : ALUW_rr<0b0100100, 0b101, "bextw">, Sched<[]>;
-} // Predicates = [HasStdExtZbs, IsRV64]
-
 let Predicates = [HasStdExtZbp, IsRV64] in {
 def GORCW  : ALUW_rr<0b0010100, 0b101, "gorcw">, Sched<[]>;
 def GREVW  : ALUW_rr<0b0110100, 0b101, "grevw">, Sched<[]>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbp, IsRV64] in {
 def XPERMW : ALU_rr<0b0010100, 0b000, "xperm.w">, Sched<[]>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbbOrZbp, IsRV64] in
 def RORIW : RVBShiftW_ri<0b0110000, 0b101, OPC_OP_IMM_32, "roriw">,
             Sched<[WriteRotateImm32, ReadRotateImm32]>;
 
-let Predicates = [HasStdExtZbs, IsRV64] in {
-// NOTE: These instructions have been removed from the 0.94 spec. As a result
-// we have no isel patterns for them.
-def BCLRIW : RVBShiftW_ri<0b0100100, 0b001, OPC_OP_IMM_32, "bclriw">,
-              Sched<[]>;
-def BSETIW : RVBShiftW_ri<0b0010100, 0b001, OPC_OP_IMM_32, "bsetiw">,
-              Sched<[]>;
-def BINVIW : RVBShiftW_ri<0b0110100, 0b001, OPC_OP_IMM_32, "binviw">,
-              Sched<[]>;
-} // Predicates = [HasStdExtZbs, IsRV64]
-
 let Predicates = [HasStdExtZbp, IsRV64] in {
 def GORCIW : RVBShiftW_ri<0b0010100, 0b101, OPC_OP_IMM_32, "gorciw">, Sched<[]>;
 def GREVIW : RVBShiftW_ri<0b0110100, 0b101, OPC_OP_IMM_32, "greviw">, Sched<[]>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbt, IsRV64] in {
 def FSLW  : RVBTernaryR<0b10, 0b001, OPC_OP_32,
                         "fslw", "$rd, $rs1, $rs3, $rs2">, Sched<[]>;
 def FSRW  : RVBTernaryR<0b10, 0b101, OPC_OP_32, "fsrw",

 let DecoderNamespace = "RVBC", Predicates = [HasStdExtZbproposedc, HasStdExtZba, HasStdExtC, IsRV64] in
 def C_ZEXTW : RVBInstC<0b10, "c.zext.w">, Sched<[]>;
 
 //===----------------------------------------------------------------------===//
 // Pseudo Instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtZba, IsRV64] in {
-// NOTE: The 0.93 spec shows zext.w as an alias of pack/packw. It has been
-// changed to add.uw in a draft after 0.94.
 def : InstAlias<"zext.w $rd, $rs", (ADDUW GPR:$rd, GPR:$rs, X0)>;
 }
 
 let Predicates = [HasStdExtZbp] in {
 def : InstAlias<"rev.p $rd, $rs",  (GREVI GPR:$rd, GPR:$rs, 0b00001)>;
 def : InstAlias<"rev2.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00010)>;
 def : InstAlias<"rev.n $rd, $rs",  (GREVI GPR:$rd, GPR:$rs, 0b00011)>;
 def : InstAlias<"rev4.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00100)>;

llvm/lib/Target/RISCV/RISCVSubtarget.h

 
 class RISCVSubtarget : public RISCVGenSubtargetInfo {
   virtual void anchor();
   bool HasStdExtM = false;
   bool HasStdExtA = false;
   bool HasStdExtF = false;
   bool HasStdExtD = false;
   bool HasStdExtC = false;
-  bool HasStdExtB = false;
   bool HasStdExtZba = false;
   bool HasStdExtZbb = false;
   bool HasStdExtZbc = false;
   bool HasStdExtZbe = false;
   bool HasStdExtZbf = false;
   bool HasStdExtZbm = false;
   bool HasStdExtZbp = false;
   bool HasStdExtZbr = false;
const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
     return &TSInfo;
   }
   bool enableMachineScheduler() const override { return true; }
   bool hasStdExtM() const { return HasStdExtM; }
   bool hasStdExtA() const { return HasStdExtA; }
   bool hasStdExtF() const { return HasStdExtF; }
   bool hasStdExtD() const { return HasStdExtD; }
   bool hasStdExtC() const { return HasStdExtC; }
-  bool hasStdExtB() const { return HasStdExtB; }
   bool hasStdExtZba() const { return HasStdExtZba; }
   bool hasStdExtZbb() const { return HasStdExtZbb; }
   bool hasStdExtZbc() const { return HasStdExtZbc; }
   bool hasStdExtZbe() const { return HasStdExtZbe; }
   bool hasStdExtZbf() const { return HasStdExtZbf; }
   bool hasStdExtZbm() const { return HasStdExtZbm; }
   bool hasStdExtZbp() const { return HasStdExtZbp; }
   bool hasStdExtZbr() const { return HasStdExtZbr; }

llvm/test/CodeGen/RISCV/attributes.ll

 ;; Generate ELF attributes from llc.
 
 ; RUN: llc -mtriple=riscv32 -mattr=+m %s -o - | FileCheck --check-prefix=RV32M %s
 ; RUN: llc -mtriple=riscv32 -mattr=+a %s -o - | FileCheck --check-prefix=RV32A %s
 ; RUN: llc -mtriple=riscv32 -mattr=+f %s -o - | FileCheck --check-prefix=RV32F %s
 ; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefix=RV32D %s
 ; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefix=RV32C %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-b %s -o - | FileCheck --check-prefix=RV32B %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-zvamo,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32V %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh %s -o - | FileCheck --check-prefix=RV32ZFH %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zba %s -o - | FileCheck --check-prefix=RV32ZBA %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb %s -o - | FileCheck --check-prefix=RV32ZBB %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbc %s -o - | FileCheck --check-prefix=RV32ZBC %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe %s -o - | FileCheck --check-prefix=RV32ZBE %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV32ZBF %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV32ZBM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV32ZBP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbproposedc %s -o - | FileCheck --check-prefix=RV32ZBPROPOSEDC %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s
 ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-b %s -o - | FileCheck --check-prefix=RV64B %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zvamo,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64V %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh %s -o - | FileCheck --check-prefix=RV64ZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zba %s -o - | FileCheck --check-prefix=RV64ZBA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb %s -o - | FileCheck --check-prefix=RV64ZBB %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbc %s -o - | FileCheck --check-prefix=RV64ZBC %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe %s -o - | FileCheck --check-prefix=RV64ZBE %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV64ZBF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV64ZBM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV64ZBP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbproposedc %s -o - | FileCheck --check-prefix=RV64ZBPROPOSEDC %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64COMBINED %s
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
 ; RV32A: .attribute 5, "rv32i2p0_a2p0"
 ; RV32F: .attribute 5, "rv32i2p0_f2p0"
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
-; RV32B: .attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 ; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
-; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93"
-; RV32ZBB: .attribute 5, "rv32i2p0_zbb0p93"
-; RV32ZBC: .attribute 5, "rv32i2p0_zbc0p93"
+; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0"
+; RV32ZBB: .attribute 5, "rv32i2p0_zbb1p0"
+; RV32ZBC: .attribute 5, "rv32i2p0_zbc1p0"
 ; RV32ZBE: .attribute 5, "rv32i2p0_zbe0p93"
 ; RV32ZBF: .attribute 5, "rv32i2p0_zbf0p93"
 ; RV32ZBM: .attribute 5, "rv32i2p0_zbm0p93"
 ; RV32ZBP: .attribute 5, "rv32i2p0_zbp0p93"
 ; RV32ZBPROPOSEDC: .attribute 5, "rv32i2p0_zbproposedc0p93"
 ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
-; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93"
+; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
-; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10"
+; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb1p0_zvamo0p10_zvlsseg0p10"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
 ; RV64F: .attribute 5, "rv64i2p0_f2p0"
 ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
 ; RV64C: .attribute 5, "rv64i2p0_c2p0"
-; RV64B: .attribute 5, "rv64i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 ; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh0p1"
-; RV64ZBA: .attribute 5, "rv64i2p0_zba0p93"
-; RV64ZBB: .attribute 5, "rv64i2p0_zbb0p93"
-; RV64ZBC: .attribute 5, "rv64i2p0_zbc0p93"
+; RV64ZBA: .attribute 5, "rv64i2p0_zba1p0"
+; RV64ZBB: .attribute 5, "rv64i2p0_zbb1p0"
+; RV64ZBC: .attribute 5, "rv64i2p0_zbc1p0"
 ; RV64ZBE: .attribute 5, "rv64i2p0_zbe0p93"
 ; RV64ZBF: .attribute 5, "rv64i2p0_zbf0p93"
 ; RV64ZBM: .attribute 5, "rv64i2p0_zbm0p93"
 ; RV64ZBP: .attribute 5, "rv64i2p0_zbp0p93"
 ; RV64ZBPROPOSEDC: .attribute 5, "rv64i2p0_zbproposedc0p93"
 ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
-; RV64ZBS: .attribute 5, "rv64i2p0_zbs0p93"
+; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0"
 ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
 ; RV64V: .attribute 5, "rv64i2p0_v0p10_zvamo0p10_zvlsseg0p10"
-; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10"
+; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh0p1_zbb1p0_zvamo0p10_zvlsseg0p10"
 
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
   ret i32 %1
 }

llvm/test/CodeGen/RISCV/rv32zba.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
-; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-b -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32B
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-zba -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32ZBA
 
 define signext i16 @sh1add(i64 %0, i16* %1) {
 ; RV32I-LABEL: sh1add:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 1
 ; RV32I-NEXT:    add a0, a2, a0
 ; RV32I-NEXT:    lh a0, 0(a0)
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: sh1add:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh1add a0, a0, a2
-; RV32B-NEXT:    lh a0, 0(a0)
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: sh1add:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh1add a0, a0, a2
 ; RV32ZBA-NEXT:    lh a0, 0(a0)
 ; RV32ZBA-NEXT:    ret
   %3 = getelementptr inbounds i16, i16* %1, i64 %0
   %4 = load i16, i16* %3
   ret i16 %4
 }
 
 define i32 @sh2add(i64 %0, i32* %1) {
 ; RV32I-LABEL: sh2add:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 2
 ; RV32I-NEXT:    add a0, a2, a0
 ; RV32I-NEXT:    lw a0, 0(a0)
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: sh2add:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh2add a0, a0, a2
-; RV32B-NEXT:    lw a0, 0(a0)
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: sh2add:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh2add a0, a0, a2
 ; RV32ZBA-NEXT:    lw a0, 0(a0)
 ; RV32ZBA-NEXT:    ret
   %3 = getelementptr inbounds i32, i32* %1, i64 %0
   %4 = load i32, i32* %3
   ret i32 %4
 }
 
 define i64 @sh3add(i64 %0, i64* %1) {
 ; RV32I-LABEL: sh3add:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 3
 ; RV32I-NEXT:    add a1, a2, a0
 ; RV32I-NEXT:    lw a0, 0(a1)
 ; RV32I-NEXT:    lw a1, 4(a1)
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: sh3add:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh3add a1, a0, a2
-; RV32B-NEXT:    lw a0, 0(a1)
-; RV32B-NEXT:    lw a1, 4(a1)
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: sh3add:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a1, a0, a2
 ; RV32ZBA-NEXT:    lw a0, 0(a1)
 ; RV32ZBA-NEXT:    lw a1, 4(a1)
 ; RV32ZBA-NEXT:    ret
   %3 = getelementptr inbounds i64, i64* %1, i64 %0
   %4 = load i64, i64* %3
   ret i64 %4
 }
 
 define i32 @addmul6(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul6:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 6
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: addmul6:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh1add a0, a0, a0
-; RV32B-NEXT:    sh1add a0, a0, a1
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: addmul6:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh1add a0, a0, a0
 ; RV32ZBA-NEXT:    sh1add a0, a0, a1
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 6
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul10(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul10:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 10
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: addmul10:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh2add a0, a0, a0
-; RV32B-NEXT:    sh1add a0, a0, a1
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: addmul10:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh2add a0, a0, a0
 ; RV32ZBA-NEXT:    sh1add a0, a0, a1
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 10
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul12(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul12:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 12
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: addmul12:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh1add a0, a0, a0
-; RV32B-NEXT:    sh2add a0, a0, a1
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: addmul12:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh1add a0, a0, a0
 ; RV32ZBA-NEXT:    sh2add a0, a0, a1
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 12
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul18(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul18:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 18
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: addmul18:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh3add a0, a0, a0
-; RV32B-NEXT:    sh1add a0, a0, a1
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: addmul18:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a0, a0, a0
 ; RV32ZBA-NEXT:    sh1add a0, a0, a1
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 18
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul20(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul20:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 20
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: addmul20:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh2add a0, a0, a0
-; RV32B-NEXT:    sh2add a0, a0, a1
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: addmul20:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh2add a0, a0, a0
 ; RV32ZBA-NEXT:    sh2add a0, a0, a1
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 20
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul24(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul24:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 24
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: addmul24:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh1add a0, a0, a0
-; RV32B-NEXT:    sh3add a0, a0, a1
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: addmul24:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh1add a0, a0, a0
 ; RV32ZBA-NEXT:    sh3add a0, a0, a1
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 24
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul36(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul36:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 36
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: addmul36:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh3add a0, a0, a0
-; RV32B-NEXT:    sh2add a0, a0, a1
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: addmul36:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a0, a0, a0
 ; RV32ZBA-NEXT:    sh2add a0, a0, a1
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 36
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul40(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul40:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 40
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: addmul40:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh2add a0, a0, a0
-; RV32B-NEXT:    sh3add a0, a0, a1
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: addmul40:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh2add a0, a0, a0
 ; RV32ZBA-NEXT:    sh3add a0, a0, a1
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 40
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul72(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul72:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 72
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: addmul72:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh3add a0, a0, a0
-; RV32B-NEXT:    sh3add a0, a0, a1
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: addmul72:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a0, a0, a0
 ; RV32ZBA-NEXT:    sh3add a0, a0, a1
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 72
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @mul96(i32 %a) {
 ; RV32I-LABEL: mul96:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 96
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: mul96:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh1add a0, a0, a0
-; RV32B-NEXT:    slli a0, a0, 5
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: mul96:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh1add a0, a0, a0
 ; RV32ZBA-NEXT:    slli a0, a0, 5
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 96
   ret i32 %c
 }
 
 define i32 @mul160(i32 %a) {
 ; RV32I-LABEL: mul160:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 160
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: mul160:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh2add a0, a0, a0
-; RV32B-NEXT:    slli a0, a0, 5
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: mul160:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh2add a0, a0, a0
 ; RV32ZBA-NEXT:    slli a0, a0, 5
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 160
   ret i32 %c
 }
 
 define i32 @mul288(i32 %a) {
 ; RV32I-LABEL: mul288:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 288
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: mul288:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh3add a0, a0, a0
-; RV32B-NEXT:    slli a0, a0, 5
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: mul288:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a0, a0, a0
 ; RV32ZBA-NEXT:    slli a0, a0, 5
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 288
   ret i32 %c
 }
 
 define i32 @mul258(i32 %a) {
 ; RV32I-LABEL: mul258:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 258
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: mul258:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    addi a1, zero, 258
-; RV32B-NEXT:    mul a0, a0, a1
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: mul258:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    addi a1, zero, 258
 ; RV32ZBA-NEXT:    mul a0, a0, a1
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 258
   ret i32 %c
 }
 
 define i32 @mul260(i32 %a) {
 ; RV32I-LABEL: mul260:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 260
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: mul260:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    addi a1, zero, 260
-; RV32B-NEXT:    mul a0, a0, a1
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: mul260:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    addi a1, zero, 260
 ; RV32ZBA-NEXT:    mul a0, a0, a1
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 260
   ret i32 %c
 }
 
 define i32 @mul264(i32 %a) {
 ; RV32I-LABEL: mul264:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 264
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: mul264:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    addi a1, zero, 264
-; RV32B-NEXT:    mul a0, a0, a1
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: mul264:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    addi a1, zero, 264
 ; RV32ZBA-NEXT:    mul a0, a0, a1
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 264
   ret i32 %c
 }
 
 define i32 @mul11(i32 %a) {
 ; RV32I-LABEL: mul11:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 11
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: mul11:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh2add a1, a0, a0
-; RV32B-NEXT:    sh1add a0, a1, a0
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: mul11:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh2add a1, a0, a0
 ; RV32ZBA-NEXT:    sh1add a0, a1, a0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 11
   ret i32 %c
 }
 
 define i32 @mul19(i32 %a) {
 ; RV32I-LABEL: mul19:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 19
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: mul19:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh3add a1, a0, a0
-; RV32B-NEXT:    sh1add a0, a1, a0
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: mul19:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a1, a0, a0
 ; RV32ZBA-NEXT:    sh1add a0, a1, a0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 19
   ret i32 %c
 }
 
 define i32 @mul13(i32 %a) {
 ; RV32I-LABEL: mul13:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 13
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: mul13:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh1add a1, a0, a0
-; RV32B-NEXT:    sh2add a0, a1, a0
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: mul13:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh1add a1, a0, a0
 ; RV32ZBA-NEXT:    sh2add a0, a1, a0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 13
   ret i32 %c
 }
 
 define i32 @mul21(i32 %a) {
 ; RV32I-LABEL: mul21:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 21
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: mul21:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh2add a1, a0, a0
-; RV32B-NEXT:    sh2add a0, a1, a0
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: mul21:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh2add a1, a0, a0
 ; RV32ZBA-NEXT:    sh2add a0, a1, a0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 21
   ret i32 %c
 }
 
 define i32 @mul37(i32 %a) {
 ; RV32I-LABEL: mul37:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 37
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: mul37:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh3add a1, a0, a0
-; RV32B-NEXT:    sh2add a0, a1, a0
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: mul37:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a1, a0, a0
 ; RV32ZBA-NEXT:    sh2add a0, a1, a0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 37
   ret i32 %c
 }
 
 define i32 @mul25(i32 %a) {
 ; RV32I-LABEL: mul25:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 25
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: mul25:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh1add a1, a0, a0
-; RV32B-NEXT:    sh3add a0, a1, a0
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: mul25:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh1add a1, a0, a0
 ; RV32ZBA-NEXT:    sh3add a0, a1, a0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 25
   ret i32 %c
 }
 
 define i32 @mul41(i32 %a) {
 ; RV32I-LABEL: mul41:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 41
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: mul41:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh2add a1, a0, a0
-; RV32B-NEXT:    sh3add a0, a1, a0
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: mul41:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh2add a1, a0, a0
 ; RV32ZBA-NEXT:    sh3add a0, a1, a0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 41
   ret i32 %c
 }
 
 define i32 @mul73(i32 %a) {
 ; RV32I-LABEL: mul73:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 73
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: mul73:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh3add a1, a0, a0
-; RV32B-NEXT:    sh3add a0, a1, a0
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: mul73:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a1, a0, a0
 ; RV32ZBA-NEXT:    sh3add a0, a1, a0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 73
   ret i32 %c
 }
 
 define i32 @mul27(i32 %a) {
 ; RV32I-LABEL: mul27:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 27
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: mul27:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh3add a0, a0, a0
-; RV32B-NEXT:    sh1add a0, a0, a0
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: mul27:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a0, a0, a0
 ; RV32ZBA-NEXT:    sh1add a0, a0, a0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 27
   ret i32 %c
 }
 
 define i32 @mul45(i32 %a) {
 ; RV32I-LABEL: mul45:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 45
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: mul45:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh3add a0, a0, a0
-; RV32B-NEXT:    sh2add a0, a0, a0
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: mul45:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a0, a0, a0
 ; RV32ZBA-NEXT:    sh2add a0, a0, a0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 45
   ret i32 %c
 }
 
 define i32 @mul81(i32 %a) {
 ; RV32I-LABEL: mul81:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 81
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: mul81:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh3add a0, a0, a0
-; RV32B-NEXT:    sh3add a0, a0, a0
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: mul81:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a0, a0, a0
 ; RV32ZBA-NEXT:    sh3add a0, a0, a0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 81
   ret i32 %c
 }
 
 define i32 @mul4098(i32 %a) {
 ; RV32I-LABEL: mul4098:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1
 ; RV32I-NEXT:    addi a1, a1, 2
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: mul4098:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    slli a1, a0, 12
-; RV32B-NEXT:    sh1add a0, a0, a1
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: mul4098:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    slli a1, a0, 12
 ; RV32ZBA-NEXT:    sh1add a0, a0, a1
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 4098
   ret i32 %c
 }
 
 define i32 @mul4100(i32 %a) {
 ; RV32I-LABEL: mul4100:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1
 ; RV32I-NEXT:    addi a1, a1, 4
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: mul4100:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    slli a1, a0, 12
-; RV32B-NEXT:    sh2add a0, a0, a1
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: mul4100:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    slli a1, a0, 12
 ; RV32ZBA-NEXT:    sh2add a0, a0, a1
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 4100
   ret i32 %c
 }
 
 define i32 @mul4104(i32 %a) {
 ; RV32I-LABEL: mul4104:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1
 ; RV32I-NEXT:    addi a1, a1, 8
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: mul4104:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    slli a1, a0, 12
-; RV32B-NEXT:    sh3add a0, a0, a1
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: mul4104:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    slli a1, a0, 12
 ; RV32ZBA-NEXT:    sh3add a0, a0, a1
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 4104
   ret i32 %c
 }
 
 define i32 @add4104(i32 %a) {
 ; RV32I-LABEL: add4104:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1
 ; RV32I-NEXT:    addi a1, a1, 8
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: add4104:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    addi a1, zero, 1026
-; RV32B-NEXT:    sh2add a0, a1, a0
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: add4104:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    addi a1, zero, 1026
 ; RV32ZBA-NEXT:    sh2add a0, a1, a0
 ; RV32ZBA-NEXT:    ret
   %c = add i32 %a, 4104
   ret i32 %c
 }
 
 define i32 @add8208(i32 %a) {
 ; RV32I-LABEL: add8208:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 2
 ; RV32I-NEXT:    addi a1, a1, 16
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: add8208:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    addi a1, zero, 1026
-; RV32B-NEXT:    sh3add a0, a1, a0
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: add8208:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    addi a1, zero, 1026
 ; RV32ZBA-NEXT:    sh3add a0, a1, a0
 ; RV32ZBA-NEXT:    ret
   %c = add i32 %a, 8208
   ret i32 %c
 }
 
 define i32 @addshl_5_6(i32 %a, i32 %b) {
 ; RV32I-LABEL: addshl_5_6:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 5
 ; RV32I-NEXT:    slli a1, a1, 6
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: addshl_5_6:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh1add a0, a1, a0
-; RV32B-NEXT:    slli a0, a0, 5
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: addshl_5_6:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh1add a0, a1, a0
 ; RV32ZBA-NEXT:    slli a0, a0, 5
 ; RV32ZBA-NEXT:    ret
   %c = shl i32 %a, 5
   %d = shl i32 %b, 6
   %e = add i32 %c, %d
   ret i32 %e
 }
 
 define i32 @addshl_5_7(i32 %a, i32 %b) {
 ; RV32I-LABEL: addshl_5_7:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 5
 ; RV32I-NEXT:    slli a1, a1, 7
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: addshl_5_7:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh2add a0, a1, a0
-; RV32B-NEXT:    slli a0, a0, 5
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: addshl_5_7:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh2add a0, a1, a0
 ; RV32ZBA-NEXT:    slli a0, a0, 5
 ; RV32ZBA-NEXT:    ret
   %c = shl i32 %a, 5
   %d = shl i32 %b, 7
   %e = add i32 %c, %d
   ret i32 %e
 }
 
 define i32 @addshl_5_8(i32 %a, i32 %b) {
 ; RV32I-LABEL: addshl_5_8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 5
 ; RV32I-NEXT:    slli a1, a1, 8
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: addshl_5_8:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sh3add a0, a1, a0
-; RV32B-NEXT:    slli a0, a0, 5
-; RV32B-NEXT:    ret
-;
 ; RV32ZBA-LABEL: addshl_5_8:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a0, a1, a0
 ; RV32ZBA-NEXT:    slli a0, a0, 5
 ; RV32ZBA-NEXT:    ret
   %c = shl i32 %a, 5
   %d = shl i32 %b, 8
   %e = add i32 %c, %d
   ret i32 %e
 }

llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32B
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32ZBB
 
 declare i32 @llvm.riscv.orc.b.i32(i32)
 
 define i32 @orcb(i32 %a) nounwind {
-; RV32B-LABEL: orcb:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    orc.b a0, a0
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: orcb:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    orc.b a0, a0
 ; RV32ZBB-NEXT:    ret
   %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
  ret i32 %tmp
 }

llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32B
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32ZBB
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32ZBP
 
 define i32 @andn_i32(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: andn_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    not a1, a1
 ; RV32I-NEXT:    and a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: andn_i32:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    andn a0, a0, a1
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: andn_i32:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    andn a0, a0, a1
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV32ZBP-LABEL: andn_i32:
 ; RV32ZBP:       # %bb.0:
 ; RV32ZBP-NEXT:    andn a0, a0, a1
 ; RV32ZBP-NEXT:    ret
   %neg = xor i32 %b, -1
   %and = and i32 %neg, %a
   ret i32 %and
 }
 
 define i64 @andn_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: andn_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    not a3, a3
 ; RV32I-NEXT:    not a2, a2
 ; RV32I-NEXT:    and a0, a2, a0
 ; RV32I-NEXT:    and a1, a3, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: andn_i64:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    andn a0, a0, a2
-; RV32B-NEXT:    andn a1, a1, a3
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: andn_i64:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    andn a0, a0, a2
 ; RV32ZBB-NEXT:    andn a1, a1, a3
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV32ZBP-LABEL: andn_i64:
 ; RV32ZBP:       # %bb.0:
 ; RV32ZBP-NEXT:    andn a0, a0, a2
 ; RV32ZBP-NEXT:    andn a1, a1, a3
 ; RV32ZBP-NEXT:    ret
   %neg = xor i64 %b, -1
   %and = and i64 %neg, %a
   ret i64 %and
 }
 
 define i32 @orn_i32(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: orn_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    not a1, a1
 ; RV32I-NEXT:    or a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: orn_i32:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    orn a0, a0, a1
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: orn_i32:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    orn a0, a0, a1
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV32ZBP-LABEL: orn_i32:
 ; RV32ZBP:       # %bb.0:
 ; RV32ZBP-NEXT:    orn a0, a0, a1
 ; RV32ZBP-NEXT:    ret
   %neg = xor i32 %b, -1
   %or = or i32 %neg, %a
   ret i32 %or
 }
 
 define i64 @orn_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: orn_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    not a3, a3
 ; RV32I-NEXT:    not a2, a2
 ; RV32I-NEXT:    or a0, a2, a0
 ; RV32I-NEXT:    or a1, a3, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: orn_i64:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    orn a0, a0, a2
-; RV32B-NEXT:    orn a1, a1, a3
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: orn_i64:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    orn a0, a0, a2
 ; RV32ZBB-NEXT:    orn a1, a1, a3
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV32ZBP-LABEL: orn_i64:
 ; RV32ZBP:       # %bb.0:
 ; RV32ZBP-NEXT:    orn a0, a0, a2
 ; RV32ZBP-NEXT:    orn a1, a1, a3
 ; RV32ZBP-NEXT:    ret
   %neg = xor i64 %b, -1
   %or = or i64 %neg, %a
   ret i64 %or
 }
 
 define i32 @xnor_i32(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: xnor_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: xnor_i32:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    xnor a0, a0, a1
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: xnor_i32:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    xnor a0, a0, a1
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV32ZBP-LABEL: xnor_i32:
 ; RV32ZBP:       # %bb.0:
 ; RV32ZBP-NEXT:    xnor a0, a0, a1
 ; RV32ZBP-NEXT:    ret
   %neg = xor i32 %a, -1
   %xor = xor i32 %neg, %b
   ret i32 %xor
 }
 
 define i64 @xnor_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: xnor_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    xor a1, a1, a3
 ; RV32I-NEXT:    xor a0, a0, a2
 ; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    not a1, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: xnor_i64:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    xnor a0, a0, a2
-; RV32B-NEXT:    xnor a1, a1, a3
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: xnor_i64:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    xnor a0, a0, a2
 ; RV32ZBB-NEXT:    xnor a1, a1, a3
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV32ZBP-LABEL: xnor_i64:
 ; RV32ZBP:       # %bb.0:

 ; RV32I-LABEL: rol_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sll a2, a0, a1
 ; RV32I-NEXT:    neg a1, a1
 ; RV32I-NEXT:    srl a0, a0, a1
 ; RV32I-NEXT:    or a0, a2, a0
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: rol_i32:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    rol a0, a0, a1
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: rol_i32:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    rol a0, a0, a1
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV32ZBP-LABEL: rol_i32:
 ; RV32ZBP:       # %bb.0:
 ; RV32ZBP-NEXT:    rol a0, a0, a1
 ; RV32ZBP-NEXT:    ret
   %or = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %b)
   ret i32 %or
 }
 
-; As we are not matching directly i64 code patterns on RV32 some i64 patterns
-; don't have yet any matching bit manipulation instructions on RV32.
 ; This test is presented here in case future expansions of the experimental-b
 ; extension introduce instructions suitable for this pattern.
 
 declare i64 @llvm.fshl.i64(i64, i64, i64)
 
 define i64 @rol_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: rol_i64:
 ; RV32I:       # %bb.0:

 ; RV32I-NEXT:    bgez t0, .LBB7_7
 ; RV32I-NEXT:  .LBB7_6:
 ; RV32I-NEXT:    sll a0, a0, a2
 ; RV32I-NEXT:    or a3, a3, a0
 ; RV32I-NEXT:  .LBB7_7:
 ; RV32I-NEXT:    mv a0, a3
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: rol_i64:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sll a7, a1, a2
-; RV32B-NEXT:    andi a4, a2, 63
-; RV32B-NEXT:    addi a6, zero, 31
-; RV32B-NEXT:    sub a5, a6, a4
-; RV32B-NEXT:    srli a3, a0, 1
-; RV32B-NEXT:    srl a3, a3, a5
-; RV32B-NEXT:    or a7, a7, a3
-; RV32B-NEXT:    addi t1, a4, -32
-; RV32B-NEXT:    sll a5, a0, t1
-; RV32B-NEXT:    slti a3, t1, 0
-; RV32B-NEXT:    cmov a7, a3, a7, a5
-; RV32B-NEXT:    neg a5, a2
-; RV32B-NEXT:    srl t0, a1, a5
-; RV32B-NEXT:    andi t2, a5, 63
-; RV32B-NEXT:    addi a4, t2, -32
-; RV32B-NEXT:    srai a3, a4, 31
-; RV32B-NEXT:    and a3, a3, t0
-; RV32B-NEXT:    or a7, a7, a3
-; RV32B-NEXT:    srl t0, a0, a5
-; RV32B-NEXT:    sub a5, a6, t2
-; RV32B-NEXT:    slli a3, a1, 1
-; RV32B-NEXT:    sll a3, a3, a5
-; RV32B-NEXT:    or a3, t0, a3
-; RV32B-NEXT:    srl a1, a1, a4
-; RV32B-NEXT:    slti a4, a4, 0
-; RV32B-NEXT:    cmov a1, a4, a3, a1
-; RV32B-NEXT:    sll a0, a0, a2
-; RV32B-NEXT:    srai a2, t1, 31
-; RV32B-NEXT:    and a0, a2, a0
-; RV32B-NEXT:    or a0, a0, a1
-; RV32B-NEXT:    mv a1, a7
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: rol_i64:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    mv a7, a1
 ; RV32ZBB-NEXT:    andi a1, a2, 63
 ; RV32ZBB-NEXT:    addi t0, a1, -32
 ; RV32ZBB-NEXT:    addi a6, zero, 31
 ; RV32ZBB-NEXT:    bltz t0, .LBB7_2
 ; RV32ZBB-NEXT:  # %bb.1:

 ; RV32I-LABEL: ror_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srl a2, a0, a1
 ; RV32I-NEXT:    neg a1, a1
 ; RV32I-NEXT:    sll a0, a0, a1
 ; RV32I-NEXT:    or a0, a2, a0
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: ror_i32:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    ror a0, a0, a1
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: ror_i32:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    ror a0, a0, a1
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV32ZBP-LABEL: ror_i32:
 ; RV32ZBP:       # %bb.0:
 ; RV32ZBP-NEXT:    ror a0, a0, a1
 ; RV32ZBP-NEXT:    ret
   %or = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %b)
   ret i32 %or
 }
 
-; As we are not matching directly i64 code patterns on RV32 some i64 patterns
-; don't have yet any matching bit manipulation instructions on RV32.
 ; This test is presented here in case future expansions of the experimental-b
 ; extension introduce instructions suitable for this pattern.
 
 declare i64 @llvm.fshr.i64(i64, i64, i64)
 
 define i64 @ror_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: ror_i64:
 ; RV32I:       # %bb.0:

 ; RV32I-NEXT:    bgez a7, .LBB9_7
 ; RV32I-NEXT:  .LBB9_6:
 ; RV32I-NEXT:    srl a1, a1, a2
 ; RV32I-NEXT:    or a3, a3, a1
 ; RV32I-NEXT:  .LBB9_7:
 ; RV32I-NEXT:    mv a1, a3
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: ror_i64:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    srl a7, a0, a2
-; RV32B-NEXT:    andi a4, a2, 63
-; RV32B-NEXT:    addi a6, zero, 31
-; RV32B-NEXT:    sub a5, a6, a4
-; RV32B-NEXT:    slli a3, a1, 1
-; RV32B-NEXT:    sll a3, a3, a5
-; RV32B-NEXT:    or a7, a7, a3
-; RV32B-NEXT:    addi t1, a4, -32
-; RV32B-NEXT:    srl a5, a1, t1
-; RV32B-NEXT:    slti a3, t1, 0
-; RV32B-NEXT:    cmov a7, a3, a7, a5
-; RV32B-NEXT:    neg a5, a2
-; RV32B-NEXT:    sll t0, a0, a5
-; RV32B-NEXT:    andi t2, a5, 63
-; RV32B-NEXT:    addi a4, t2, -32
-; RV32B-NEXT:    srai a3, a4, 31
-; RV32B-NEXT:    and a3, a3, t0
-; RV32B-NEXT:    or a7, a7, a3
-; RV32B-NEXT:    sll t0, a1, a5
-; RV32B-NEXT:    sub a5, a6, t2
-; RV32B-NEXT:    srli a3, a0, 1
-; RV32B-NEXT:    srl a3, a3, a5
-; RV32B-NEXT:    or a3, t0, a3
-; RV32B-NEXT:    sll a0, a0, a4
-; RV32B-NEXT:    slti a4, a4, 0
-; RV32B-NEXT:    cmov a0, a4, a3, a0
-; RV32B-NEXT:    srl a1, a1, a2
-; RV32B-NEXT:    srai a2, t1, 31
-; RV32B-NEXT:    and a1, a2, a1
-; RV32B-NEXT:    or a1, a1, a0
-; RV32B-NEXT:    mv a0, a7
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: ror_i64:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    mv t0, a0
 ; RV32ZBB-NEXT:    andi a0, a2, 63
 ; RV32ZBB-NEXT:    addi a7, a0, -32
 ; RV32ZBB-NEXT:    addi a6, zero, 31
 ; RV32ZBB-NEXT:    bltz a7, .LBB9_2
 ; RV32ZBB-NEXT:  # %bb.1:

 define i32 @rori_i32_fshl(i32 %a) nounwind {
 ; RV32I-LABEL: rori_i32_fshl:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a1, a0, 1
 ; RV32I-NEXT:    slli a0, a0, 31
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: rori_i32_fshl:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    rori a0, a0, 1
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: rori_i32_fshl:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    rori a0, a0, 1
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV32ZBP-LABEL: rori_i32_fshl:
 ; RV32ZBP:       # %bb.0:
 ; RV32ZBP-NEXT:    rori a0, a0, 1
 ; RV32ZBP-NEXT:    ret
   %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 31)
   ret i32 %1
 }
 
 define i32 @rori_i32_fshr(i32 %a) nounwind {
 ; RV32I-LABEL: rori_i32_fshr:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a1, a0, 1
 ; RV32I-NEXT:    srli a0, a0, 31
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: rori_i32_fshr:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    rori a0, a0, 31
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: rori_i32_fshr:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    rori a0, a0, 31
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV32ZBP-LABEL: rori_i32_fshr:
 ; RV32ZBP:       # %bb.0:
 ; RV32ZBP-NEXT:    rori a0, a0, 31

 ; RV32I-NEXT:    srli a3, a0, 1
 ; RV32I-NEXT:    or a2, a3, a2
 ; RV32I-NEXT:    srli a1, a1, 1
 ; RV32I-NEXT:    slli a0, a0, 31
 ; RV32I-NEXT:    or a1, a0, a1
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: rori_i64:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    fsri a2, a0, a1, 1
-; RV32B-NEXT:    fsri a1, a1, a0, 1
-; RV32B-NEXT:    mv a0, a2
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: rori_i64:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    slli a2, a1, 31
 ; RV32ZBB-NEXT:    srli a3, a0, 1
 ; RV32ZBB-NEXT:    or a2, a3, a2
 ; RV32ZBB-NEXT:    srli a1, a1, 1
 ; RV32ZBB-NEXT:    slli a0, a0, 31
 ; RV32ZBB-NEXT:    or a1, a0, a1

 ; RV32I-NEXT:    srli a3, a1, 31
 ; RV32I-NEXT:    or a2, a3, a2
 ; RV32I-NEXT:    srli a0, a0, 31
 ; RV32I-NEXT:    slli a1, a1, 1
 ; RV32I-NEXT:    or a1, a1, a0
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: rori_i64_fshr:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    fsri a2, a1, a0, 31
-; RV32B-NEXT:    fsri a1, a0, a1, 31
-; RV32B-NEXT:    mv a0, a2
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: rori_i64_fshr:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    slli a2, a0, 1
 ; RV32ZBB-NEXT:    srli a3, a1, 31
 ; RV32ZBB-NEXT:    or a2, a3, a2
 ; RV32ZBB-NEXT:    srli a0, a0, 31
 ; RV32ZBB-NEXT:    slli a1, a1, 1
 ; RV32ZBB-NEXT:    or a1, a1, a0

 
 define i8 @srli_i8(i8 %a) nounwind {
 ; RV32I-LABEL: srli_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    andi a0, a0, 192
 ; RV32I-NEXT:    srli a0, a0, 6
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: srli_i8:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    andi a0, a0, 192
-; RV32B-NEXT:    srli a0, a0, 6
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: srli_i8:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    andi a0, a0, 192
 ; RV32ZBB-NEXT:    srli a0, a0, 6
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV32ZBP-LABEL: srli_i8:
 ; RV32ZBP:       # %bb.0:
 ; RV32ZBP-NEXT:    andi a0, a0, 192
 ; RV32ZBP-NEXT:    srli a0, a0, 6
 ; RV32ZBP-NEXT:    ret
   %1 = lshr i8 %a, 6
   ret i8 %1
 }
 
 define i8 @srai_i8(i8 %a) nounwind {
 ; RV32I-LABEL: srai_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 24
 ; RV32I-NEXT:    srai a0, a0, 29
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: srai_i8:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sext.b a0, a0
-; RV32B-NEXT:    srai a0, a0, 5
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: srai_i8:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    sext.b a0, a0
 ; RV32ZBB-NEXT:    srai a0, a0, 5
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV32ZBP-LABEL: srai_i8:
 ; RV32ZBP:       # %bb.0:
 ; RV32ZBP-NEXT:    slli a0, a0, 24
 ; RV32ZBP-NEXT:    srai a0, a0, 29
 ; RV32ZBP-NEXT:    ret
   %1 = ashr i8 %a, 5
   ret i8 %1
 }
 
 define i16 @srli_i16(i16 %a) nounwind {
 ; RV32I-LABEL: srli_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 22
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: srli_i16:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    zext.h a0, a0
-; RV32B-NEXT:    srli a0, a0, 6
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: srli_i16:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    zext.h a0, a0
 ; RV32ZBB-NEXT:    srli a0, a0, 6
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV32ZBP-LABEL: srli_i16:
 ; RV32ZBP:       # %bb.0:
 ; RV32ZBP-NEXT:    zext.h a0, a0
 ; RV32ZBP-NEXT:    srli a0, a0, 6
 ; RV32ZBP-NEXT:    ret
   %1 = lshr i16 %a, 6
   ret i16 %1
 }
 
 define i16 @srai_i16(i16 %a) nounwind {
 ; RV32I-LABEL: srai_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srai a0, a0, 25
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: srai_i16:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    sext.h a0, a0
-; RV32B-NEXT:    srai a0, a0, 9
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: srai_i16:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    sext.h a0, a0
 ; RV32ZBB-NEXT:    srai a0, a0, 9
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV32ZBP-LABEL: srai_i16:
 ; RV32ZBP:       # %bb.0:
 ; RV32ZBP-NEXT:    slli a0, a0, 16
 ; RV32ZBP-NEXT:    srai a0, a0, 25
 ; RV32ZBP-NEXT:    ret
   %1 = ashr i16 %a, 9
   ret i16 %1
 }

llvm/test/CodeGen/RISCV/rv32zbb.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32B
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32ZBB
 
 declare i32 @llvm.ctlz.i32(i32, i1)
 
 define i32 @ctlz_i32(i32 %a) nounwind {
 ; RV32I-LABEL: ctlz_i32:
 ; RV32I:       # %bb.0:

 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB0_2:
 ; RV32I-NEXT:    addi a0, zero, 32
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: ctlz_i32:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    clz a0, a0
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: ctlz_i32:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    clz a0, a0
 ; RV32ZBB-NEXT:    ret
   %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
   ret i32 %1
 }
 

 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: ctlz_i64:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    clz a2, a1
-; RV32B-NEXT:    clz a0, a0
-; RV32B-NEXT:    addi a0, a0, 32
-; RV32B-NEXT:    cmov a0, a1, a2, a0
-; RV32B-NEXT:    mv a1, zero
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: ctlz_i64:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    bnez a1, .LBB1_2
 ; RV32ZBB-NEXT:  # %bb.1:
 ; RV32ZBB-NEXT:    clz a0, a0
 ; RV32ZBB-NEXT:    addi a0, a0, 32
 ; RV32ZBB-NEXT:    mv a1, zero
 ; RV32ZBB-NEXT:    ret

 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB2_2:
 ; RV32I-NEXT:    addi a0, zero, 32
 ; RV32I-NEXT:    ret
 ;
-; RV32B-LABEL: cttz_i32:
-; RV32B:       # %bb.0:
-; RV32B-NEXT:    ctz a0, a0
-; RV32B-NEXT:    ret
-;
 ; RV32ZBB-LABEL: cttz_i32:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    ctz a0, a0
 ; RV32ZBB-NEXT:    ret