This is an archive of the discontinued LLVM Phabricator instance.

Differential D111338

[RISCV] Remove experimental-b extension that includes all Zb* extensions
ClosedPublic

Authored by craig.topper on Oct 7 2021, 12:09 PM.

Details

Reviewers
asb
luismarques
frasercrmck
kito-cheng
jrtc27
Commits
rGf2ad8c9dc6d8: [RISCV] Remove experimental-b extension that includes all Zb* extensions
Summary

At this point it looks like a B extension will never exist. Instead Zba, Zbb, Zbc, and Zbs are individual extensions being ratified together as package. Unclear what will happen with the other Zb* extensions from the 0.93 spec.

This patch removes references to the B extension. I've updated and split tests accordingly.

This has been split from D110669 to make review a little easier.

Diff Detail

Event Timeline

craig.topper created this revision.Oct 7 2021, 12:09 PM
Herald added subscribers: achieveartificialintelligence, StephenFan, vkmr and 23 others. · View Herald TranscriptOct 7 2021, 12:09 PM
craig.topper requested review of this revision.Oct 7 2021, 12:09 PM
Herald added a project: Restricted Project. · View Herald TranscriptOct 7 2021, 12:09 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
jrtc27 added a comment.Oct 7 2021, 12:17 PM

Technically they're individual extensions being ratified together as part of a Zb[abcs] "package"

craig.topper edited the summary of this revision. (Show Details)Oct 7 2021, 12:21 PM
craig.topper mentioned this in D110669: [RISCV] Update Zba, Zbb, Zbc, and Zbs version from 0.93 to 1.0..Oct 7 2021, 12:49 PM
Harbormaster completed remote builds in B127592: Diff 377955.Oct 7 2021, 1:02 PM
kito-cheng accepted this revision.Oct 7 2021, 7:44 PM

LGTM.

Of cause we can still keep this as 0.93 but it's weird since it included zba, zbb, zbc and zbs, which is 1.0 not 0.93, and might cause confusion...so remove that is make more sense to me .

This revision is now accepted and ready to land.Oct 7 2021, 7:44 PM
This revision was landed with ongoing or failed builds.Oct 7 2021, 8:50 PM
Closed by commit rGf2ad8c9dc6d8: [RISCV] Remove experimental-b extension that includes all Zb* extensions (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGf2ad8c9dc6d8: [RISCV] Remove experimental-b extension that includes all Zb* extensions.
Herald added a project: Restricted Project. · View Herald TranscriptOct 7 2021, 8:50 PM
Herald added a subscriber: cfe-commits. · View Herald Transcript

Revision Contents

PathSize
clang/
lib/
Basic/
Targets/
1 line
8 lines
Driver/
ToolChains/
Arch/
19 lines
test/
Driver/
19 lines
Preprocessor/
19 lines
llvm/
lib/
Target/
RISCV/
AsmParser/
5 lines
MCTargetDesc/
2 lines
17 lines
2 lines
RISCVInstrInfoZb.td
RISCVInstrInfoB.td
8 lines
2 lines
test/
CodeGen/
RISCV/
4 lines
225 lines
7 lines
167 lines
166 lines
17 lines
12 lines
77 lines
419 lines
240 lines
208 lines
391 lines
12 lines
149 lines
185 lines
17 lines
36 lines
146 lines
432 lines
356 lines
140 lines
MC/
RISCV/
3 lines
12 lines
32 lines
12 lines
7 lines
12 lines
12 lines
12 lines
12 lines
rv32zbp-aliases-valid.s
rv32b-aliases-valid.s
32 lines
7 lines
12 lines
7 lines
32 lines
7 lines
12 lines
12 lines
34 lines
7 lines
36 lines
7 lines
7 lines
7 lines
7 lines
7 lines
rv64zbp-aliases-valid.s
rv64b-aliases-valid.s
50 lines
7 lines
7 lines
32 lines
7 lines
Transforms/
LoopIdiom/
RISCV/
2 lines

Diff 378083

clang/lib/Basic/Targets/RISCV.h

Show All 24 Lines
class RISCVTargetInfo : public TargetInfo { class RISCVTargetInfo : public TargetInfo {
protected: protected:
std::string ABI, CPU; std::string ABI, CPU;
bool HasM = false; bool HasM = false;
bool HasA = false; bool HasA = false;
bool HasF = false; bool HasF = false;
bool HasD = false; bool HasD = false;
bool HasC = false; bool HasC = false;
bool HasB = false;
bool HasV = false; bool HasV = false;
bool HasZba = false; bool HasZba = false;
bool HasZbb = false; bool HasZbb = false;
bool HasZbc = false; bool HasZbc = false;
bool HasZbe = false; bool HasZbe = false;
bool HasZbf = false; bool HasZbf = false;
bool HasZbm = false; bool HasZbm = false;
bool HasZbp = false; bool HasZbp = false;
▲ Show 20 Lines • Show All 140 Lines • Show Last 20 Lines

clang/lib/Basic/Targets/RISCV.cpp

Show First 20 Lines • Show All 170 Lines • ▼ Show 20 Linesvoid RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
if (HasD) if (HasD)
Builder.defineMacro("__riscv_d", "2000000"); Builder.defineMacro("__riscv_d", "2000000");
if (HasC) { if (HasC) {
Builder.defineMacro("__riscv_c", "2000000"); Builder.defineMacro("__riscv_c", "2000000");
Builder.defineMacro("__riscv_compressed"); Builder.defineMacro("__riscv_compressed");
} }
if (HasB) {
Builder.defineMacro("__riscv_b", "93000");
Builder.defineMacro("__riscv_bitmanip");
}
if (HasV) { if (HasV) {
Builder.defineMacro("__riscv_v", "10000"); Builder.defineMacro("__riscv_v", "10000");
Builder.defineMacro("__riscv_vector"); Builder.defineMacro("__riscv_vector");
} }
if (HasZba) if (HasZba)
Builder.defineMacro("__riscv_zba", "93000"); Builder.defineMacro("__riscv_zba", "93000");
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines return llvm::StringSwitch<bool>(Feature)
.Case("riscv32", !Is64Bit) .Case("riscv32", !Is64Bit)
.Case("riscv64", Is64Bit) .Case("riscv64", Is64Bit)
.Case("64bit", Is64Bit) .Case("64bit", Is64Bit)
.Case("m", HasM) .Case("m", HasM)
.Case("a", HasA) .Case("a", HasA)
.Case("f", HasF) .Case("f", HasF)
.Case("d", HasD) .Case("d", HasD)
.Case("c", HasC) .Case("c", HasC)
.Case("experimental-b", HasB)
.Case("experimental-v", HasV) .Case("experimental-v", HasV)
.Case("experimental-zba", HasZba) .Case("experimental-zba", HasZba)
.Case("experimental-zbb", HasZbb) .Case("experimental-zbb", HasZbb)
.Case("experimental-zbc", HasZbc) .Case("experimental-zbc", HasZbc)
.Case("experimental-zbe", HasZbe) .Case("experimental-zbe", HasZbe)
.Case("experimental-zbf", HasZbf) .Case("experimental-zbf", HasZbf)
.Case("experimental-zbm", HasZbm) .Case("experimental-zbm", HasZbm)
.Case("experimental-zbp", HasZbp) .Case("experimental-zbp", HasZbp)
Show All 15 Lines for (const auto &Feature : Features) {
else if (Feature == "+a") else if (Feature == "+a")
HasA = true; HasA = true;
else if (Feature == "+f") else if (Feature == "+f")
HasF = true; HasF = true;
else if (Feature == "+d") else if (Feature == "+d")
HasD = true; HasD = true;
else if (Feature == "+c") else if (Feature == "+c")
HasC = true; HasC = true;
else if (Feature == "+experimental-b")
HasB = true;
else if (Feature == "+experimental-v") else if (Feature == "+experimental-v")
HasV = true; HasV = true;
else if (Feature == "+experimental-zba") else if (Feature == "+experimental-zba")
HasZba = true; HasZba = true;
else if (Feature == "+experimental-zbb") else if (Feature == "+experimental-zbb")
HasZbb = true; HasZbb = true;
else if (Feature == "+experimental-zbc") else if (Feature == "+experimental-zbc")
HasZbc = true; HasZbc = true;
▲ Show 20 Lines • Show All 66 Lines • Show Last 20 Lines

clang/lib/Driver/ToolChains/Arch/RISCV.cpp

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines if (Ext.startswith("z"))
return "z"; return "z";
return StringRef(); return StringRef();
} }
// If the extension is supported as experimental, return the version of that // If the extension is supported as experimental, return the version of that
// extension that the compiler currently supports. // extension that the compiler currently supports.
static Optional<RISCVExtensionVersion> static Optional<RISCVExtensionVersion>
isExperimentalExtension(StringRef Ext) { isExperimentalExtension(StringRef Ext) {
if (Ext == "b" || Ext == "zba" || Ext == "zbb" || Ext == "zbc" || if (Ext == "zba" || Ext == "zbb" || Ext == "zbc" || Ext == "zbe" ||
Ext == "zbe" || Ext == "zbf" || Ext == "zbm" || Ext == "zbp" || Ext == "zbf" || Ext == "zbm" || Ext == "zbp" || Ext == "zbr" ||
Ext == "zbr" || Ext == "zbs" || Ext == "zbt") Ext == "zbs" || Ext == "zbt")
return RISCVExtensionVersion{"0", "93"}; return RISCVExtensionVersion{"0", "93"};
if (Ext == "v" || Ext == "zvamo" || Ext == "zvlsseg") if (Ext == "v" || Ext == "zvamo" || Ext == "zvlsseg")
return RISCVExtensionVersion{"0", "10"}; return RISCVExtensionVersion{"0", "10"};
if (Ext == "zfh") if (Ext == "zfh")
return RISCVExtensionVersion{"0", "1"}; return RISCVExtensionVersion{"0", "1"};
return None; return None;
} }
▲ Show 20 Lines • Show All 340 Lines • ▼ Show 20 Lines case 'f':
break; break;
case 'd': case 'd':
Features.push_back("+d"); Features.push_back("+d");
HasD = true; HasD = true;
break; break;
case 'c': case 'c':
Features.push_back("+c"); Features.push_back("+c");
break; break;
case 'b':
Features.push_back("+experimental-b");
Features.push_back("+experimental-zba");
Features.push_back("+experimental-zbb");
Features.push_back("+experimental-zbc");
Features.push_back("+experimental-zbe");
Features.push_back("+experimental-zbf");
Features.push_back("+experimental-zbm");
Features.push_back("+experimental-zbp");
Features.push_back("+experimental-zbr");
Features.push_back("+experimental-zbs");
Features.push_back("+experimental-zbt");
break;
case 'v': case 'v':
Features.push_back("+experimental-v"); Features.push_back("+experimental-v");
Features.push_back("+experimental-zvlsseg"); Features.push_back("+experimental-zvlsseg");
break; break;
} }
// Consume full extension name and version, including any optional '_' // Consume full extension name and version, including any optional '_'
// between this extension and the next // between this extension and the next
▲ Show 20 Lines • Show All 287 Lines • Show Last 20 Lines

clang/test/Driver/riscv-arch.c

Show First 20 Lines • Show All 376 Lines • ▼ Show 20 Lines
// RV32-TARGET: "-triple" "riscv32-unknown-unknown-elf" // RV32-TARGET: "-triple" "riscv32-unknown-unknown-elf"
// RUN: %clang -target riscv32-unknown-elf -march=rv64i -### %s \ // RUN: %clang -target riscv32-unknown-elf -march=rv64i -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
// RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \ // RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
// RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf" // RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s
// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32ib'
// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s
// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32ib'
// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number
// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p1 -menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s
// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32ib0p1'
// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension
// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p93 -menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-b"
// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb -### %s \ // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-NOFLAG %s // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-NOFLAG %s
// RV32-EXPERIMENTAL-ZBB-NOFLAG: error: invalid arch name 'rv32izbb' // RV32-EXPERIMENTAL-ZBB-NOFLAG: error: invalid arch name 'rv32izbb'
// RV32-EXPERIMENTAL-ZBB-NOFLAG: requires '-menable-experimental-extensions' // RV32-EXPERIMENTAL-ZBB-NOFLAG: requires '-menable-experimental-extensions'
// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p93 -menable-experimental-extensions -### %s \ // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p93 -menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB %s // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB %s
// RV32-EXPERIMENTAL-ZBB: "-target-feature" "+experimental-zbb" // RV32-EXPERIMENTAL-ZBB: "-target-feature" "+experimental-zbb"
▲ Show 20 Lines • Show All 79 Lines • Show Last 20 Lines

clang/test/Preprocessor/riscv-target-features.c

Show First 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ic -x c -E -dM %s \ // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ic -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \ // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
// CHECK-C-EXT: __riscv_c 2000000 // CHECK-C-EXT: __riscv_c 2000000
// CHECK-C-EXT: __riscv_compressed 1 // CHECK-C-EXT: __riscv_compressed 1
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv32ib0p93 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv64ib0p93 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
// CHECK-B-EXT: __riscv_b 93000
// CHECK-B-EXT: __riscv_bitmanip 1
// CHECK-B-EXT: __riscv_zba 93000
// CHECK-B-EXT: __riscv_zbb 93000
// CHECK-B-EXT: __riscv_zbc 93000
// CHECK-B-EXT: __riscv_zbe 93000
// CHECK-B-EXT: __riscv_zbf 93000
// CHECK-B-EXT: __riscv_zbm 93000
// CHECK-B-EXT: __riscv_zbp 93000
// CHECK-B-EXT: __riscv_zbr 93000
// CHECK-B-EXT: __riscv_zbs 93000
// CHECK-B-EXT: __riscv_zbt 93000
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv32izba0p93 -x c -E -dM %s \ // RUN: -march=rv32izba0p93 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv64izba0p93 -x c -E -dM %s \ // RUN: -march=rv64izba0p93 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s
// CHECK-ZBA-NOT: __riscv_b // CHECK-ZBA-NOT: __riscv_b
// CHECK-ZBA-EXT: __riscv_zba 93000 // CHECK-ZBA-EXT: __riscv_zba 93000
▲ Show 20 Lines • Show All 115 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Show First 20 Lines • Show All 2,062 Lines • ▼ Show 20 Lines if (Tag == RISCVAttrs::ARCH) {
// .attribute arch overrides the current architecture, so unset all // .attribute arch overrides the current architecture, so unset all
// currently enabled extensions // currently enabled extensions
clearFeatureBits(RISCV::FeatureRV32E, "e"); clearFeatureBits(RISCV::FeatureRV32E, "e");
clearFeatureBits(RISCV::FeatureStdExtM, "m"); clearFeatureBits(RISCV::FeatureStdExtM, "m");
clearFeatureBits(RISCV::FeatureStdExtA, "a"); clearFeatureBits(RISCV::FeatureStdExtA, "a");
clearFeatureBits(RISCV::FeatureStdExtF, "f"); clearFeatureBits(RISCV::FeatureStdExtF, "f");
clearFeatureBits(RISCV::FeatureStdExtD, "d"); clearFeatureBits(RISCV::FeatureStdExtD, "d");
clearFeatureBits(RISCV::FeatureStdExtC, "c"); clearFeatureBits(RISCV::FeatureStdExtC, "c");
clearFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
clearFeatureBits(RISCV::FeatureStdExtV, "experimental-v"); clearFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
clearFeatureBits(RISCV::FeatureStdExtZfh, "experimental-zfh"); clearFeatureBits(RISCV::FeatureStdExtZfh, "experimental-zfh");
clearFeatureBits(RISCV::FeatureStdExtZba, "experimental-zba"); clearFeatureBits(RISCV::FeatureStdExtZba, "experimental-zba");
clearFeatureBits(RISCV::FeatureStdExtZbb, "experimental-zbb"); clearFeatureBits(RISCV::FeatureStdExtZbb, "experimental-zbb");
clearFeatureBits(RISCV::FeatureStdExtZbc, "experimental-zbc"); clearFeatureBits(RISCV::FeatureStdExtZbc, "experimental-zbc");
clearFeatureBits(RISCV::FeatureStdExtZbe, "experimental-zbe"); clearFeatureBits(RISCV::FeatureStdExtZbe, "experimental-zbe");
clearFeatureBits(RISCV::FeatureStdExtZbf, "experimental-zbf"); clearFeatureBits(RISCV::FeatureStdExtZbf, "experimental-zbf");
clearFeatureBits(RISCV::FeatureStdExtZbm, "experimental-zbm"); clearFeatureBits(RISCV::FeatureStdExtZbm, "experimental-zbm");
Show All 22 Lines while (!Arch.empty()) {
setFeatureBits(RISCV::FeatureStdExtA, "a"); setFeatureBits(RISCV::FeatureStdExtA, "a");
else if (Arch[0] == 'f') else if (Arch[0] == 'f')
setFeatureBits(RISCV::FeatureStdExtF, "f"); setFeatureBits(RISCV::FeatureStdExtF, "f");
else if (Arch[0] == 'd') { else if (Arch[0] == 'd') {
setFeatureBits(RISCV::FeatureStdExtF, "f"); setFeatureBits(RISCV::FeatureStdExtF, "f");
setFeatureBits(RISCV::FeatureStdExtD, "d"); setFeatureBits(RISCV::FeatureStdExtD, "d");
} else if (Arch[0] == 'c') { } else if (Arch[0] == 'c') {
setFeatureBits(RISCV::FeatureStdExtC, "c"); setFeatureBits(RISCV::FeatureStdExtC, "c");
} else if (Arch[0] == 'b') {
setFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
} else if (Arch[0] == 'v') { } else if (Arch[0] == 'v') {
setFeatureBits(RISCV::FeatureStdExtV, "experimental-v"); setFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
} else if (Arch[0] == 's' || Arch[0] == 'x' || Arch[0] == 'z') { } else if (Arch[0] == 's' || Arch[0] == 'x' || Arch[0] == 'z') {
StringRef Ext = StringRef Ext =
Arch.take_until([](char c) { return ::isdigit(c) || c == '_'; }); Arch.take_until([](char c) { return ::isdigit(c) || c == '_'; });
if (Ext == "zba") if (Ext == "zba")
setFeatureBits(RISCV::FeatureStdExtZba, "experimental-zba"); setFeatureBits(RISCV::FeatureStdExtZba, "experimental-zba");
else if (Ext == "zbb") else if (Ext == "zbb")
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines if (Tag != RISCVAttrs::ARCH) {
if (getFeatureBits(RISCV::FeatureStdExtA)) if (getFeatureBits(RISCV::FeatureStdExtA))
formalArchStr = (Twine(formalArchStr) + "_a2p0").str(); formalArchStr = (Twine(formalArchStr) + "_a2p0").str();
if (getFeatureBits(RISCV::FeatureStdExtF)) if (getFeatureBits(RISCV::FeatureStdExtF))
formalArchStr = (Twine(formalArchStr) + "_f2p0").str(); formalArchStr = (Twine(formalArchStr) + "_f2p0").str();
if (getFeatureBits(RISCV::FeatureStdExtD)) if (getFeatureBits(RISCV::FeatureStdExtD))
formalArchStr = (Twine(formalArchStr) + "_d2p0").str(); formalArchStr = (Twine(formalArchStr) + "_d2p0").str();
if (getFeatureBits(RISCV::FeatureStdExtC)) if (getFeatureBits(RISCV::FeatureStdExtC))
formalArchStr = (Twine(formalArchStr) + "_c2p0").str(); formalArchStr = (Twine(formalArchStr) + "_c2p0").str();
if (getFeatureBits(RISCV::FeatureStdExtB))
formalArchStr = (Twine(formalArchStr) + "_b0p93").str();
if (getFeatureBits(RISCV::FeatureStdExtV)) if (getFeatureBits(RISCV::FeatureStdExtV))
formalArchStr = (Twine(formalArchStr) + "_v0p10").str(); formalArchStr = (Twine(formalArchStr) + "_v0p10").str();
if (getFeatureBits(RISCV::FeatureStdExtZfh)) if (getFeatureBits(RISCV::FeatureStdExtZfh))
formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str(); formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str();
if (getFeatureBits(RISCV::FeatureStdExtZba)) if (getFeatureBits(RISCV::FeatureStdExtZba))
formalArchStr = (Twine(formalArchStr) + "_zba0p93").str(); formalArchStr = (Twine(formalArchStr) + "_zba0p93").str();
if (getFeatureBits(RISCV::FeatureStdExtZbb)) if (getFeatureBits(RISCV::FeatureStdExtZbb))
formalArchStr = (Twine(formalArchStr) + "_zbb0p93").str(); formalArchStr = (Twine(formalArchStr) + "_zbb0p93").str();
▲ Show 20 Lines • Show All 565 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Linesvoid RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
if (STI.hasFeature(RISCV::FeatureStdExtA)) if (STI.hasFeature(RISCV::FeatureStdExtA))
Arch += "_a2p0"; Arch += "_a2p0";
if (STI.hasFeature(RISCV::FeatureStdExtF)) if (STI.hasFeature(RISCV::FeatureStdExtF))
Arch += "_f2p0"; Arch += "_f2p0";
if (STI.hasFeature(RISCV::FeatureStdExtD)) if (STI.hasFeature(RISCV::FeatureStdExtD))
Arch += "_d2p0"; Arch += "_d2p0";
if (STI.hasFeature(RISCV::FeatureStdExtC)) if (STI.hasFeature(RISCV::FeatureStdExtC))
Arch += "_c2p0"; Arch += "_c2p0";
if (STI.hasFeature(RISCV::FeatureStdExtB))
Arch += "_b0p93";
if (STI.hasFeature(RISCV::FeatureStdExtV)) if (STI.hasFeature(RISCV::FeatureStdExtV))
Arch += "_v0p10"; Arch += "_v0p10";
if (STI.hasFeature(RISCV::FeatureStdExtZfh)) if (STI.hasFeature(RISCV::FeatureStdExtZfh))
Arch += "_zfh0p1"; Arch += "_zfh0p1";
if (STI.hasFeature(RISCV::FeatureStdExtZba)) if (STI.hasFeature(RISCV::FeatureStdExtZba))
Arch += "_zba0p93"; Arch += "_zba0p93";
if (STI.hasFeature(RISCV::FeatureStdExtZbb)) if (STI.hasFeature(RISCV::FeatureStdExtZbb))
Arch += "_zbb0p93"; Arch += "_zbb0p93";
▲ Show 20 Lines • Show All 75 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCV.td

Show First 20 Lines • Show All 129 Lines • ▼ Show 20 Lines
// Some instructions belong to both the basic and the permutation // Some instructions belong to both the basic and the permutation
// subextensions. They should be enabled if either has been specified. // subextensions. They should be enabled if either has been specified.
def HasStdExtZbbOrZbp def HasStdExtZbbOrZbp
: Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">, : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">,
AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbp), AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbp),
"'Zbb' (Base 'B' Instructions) or " "'Zbb' (Base 'B' Instructions) or "
"'Zbp' (Permutation 'B' Instructions)">; "'Zbp' (Permutation 'B' Instructions)">;
def FeatureStdExtB
: SubtargetFeature<"experimental-b", "HasStdExtB", "true",
"'B' (Bit Manipulation Instructions)",
[FeatureStdExtZba,
FeatureStdExtZbb,
FeatureStdExtZbc,
FeatureStdExtZbe,
FeatureStdExtZbf,
FeatureStdExtZbm,
FeatureStdExtZbp,
FeatureStdExtZbr,
FeatureStdExtZbs,
FeatureStdExtZbt]>;
def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
AssemblerPredicate<(all_of FeatureStdExtB),
"'B' (Bit Manipulation Instructions)">;
def FeatureNoRVCHints def FeatureNoRVCHints
: SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false", : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
"Disable RVC Hint Instructions.">; "Disable RVC Hint Instructions.">;
def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">, def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
AssemblerPredicate<(all_of(not FeatureNoRVCHints)), AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
"RVC Hint Instructions">; "RVC Hint Instructions">;
def FeatureStdExtV def FeatureStdExtV
▲ Show 20 Lines • Show All 170 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfo.td

Show First 20 Lines • Show All 1,454 Lines • ▼ Show 20 Lines
// Standard extensions // Standard extensions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
include "RISCVInstrInfoM.td" include "RISCVInstrInfoM.td"
include "RISCVInstrInfoA.td" include "RISCVInstrInfoA.td"
include "RISCVInstrInfoF.td" include "RISCVInstrInfoF.td"
include "RISCVInstrInfoD.td" include "RISCVInstrInfoD.td"
include "RISCVInstrInfoC.td" include "RISCVInstrInfoC.td"
include "RISCVInstrInfoB.td" include "RISCVInstrInfoZb.td"
include "RISCVInstrInfoV.td" include "RISCVInstrInfoV.td"
include "RISCVInstrInfoZfh.td" include "RISCVInstrInfoZfh.td"

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

  • This file was moved to llvm/lib/Target/RISCV/RISCVInstrInfoZb.td.

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

  • This file was moved from llvm/lib/Target/RISCV/RISCVInstrInfoB.td.
//===-- RISCVInstrInfoB.td - RISC-V 'B' instructions -------*- tablegen -*-===// //===-- RISCVInstrInfoZb.td - RISC-V Bitmanip instructions -*- tablegen -*-===//
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file describes the RISC-V instructions from the standard 'B' Bitmanip // This file describes the RISC-V instructions from the standard Bitmanip
// extension, version 0.93. // extensions, version 0.93.
// This version is still experimental as the 'B' extension hasn't been // This version is still experimental as the Bitmanip extensions haven't been
// ratified yet. // ratified yet.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Operand and SDNode transformation definitions. // Operand and SDNode transformation definitions.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 1,115 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVSubtarget.h

Show All 33 Lines
class RISCVSubtarget : public RISCVGenSubtargetInfo { class RISCVSubtarget : public RISCVGenSubtargetInfo {
virtual void anchor(); virtual void anchor();
bool HasStdExtM = false; bool HasStdExtM = false;
bool HasStdExtA = false; bool HasStdExtA = false;
bool HasStdExtF = false; bool HasStdExtF = false;
bool HasStdExtD = false; bool HasStdExtD = false;
bool HasStdExtC = false; bool HasStdExtC = false;
bool HasStdExtB = false;
bool HasStdExtZba = false; bool HasStdExtZba = false;
bool HasStdExtZbb = false; bool HasStdExtZbb = false;
bool HasStdExtZbc = false; bool HasStdExtZbc = false;
bool HasStdExtZbe = false; bool HasStdExtZbe = false;
bool HasStdExtZbf = false; bool HasStdExtZbf = false;
bool HasStdExtZbm = false; bool HasStdExtZbm = false;
bool HasStdExtZbp = false; bool HasStdExtZbp = false;
bool HasStdExtZbr = false; bool HasStdExtZbr = false;
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
return &TSInfo; return &TSInfo;
} }
bool enableMachineScheduler() const override { return true; } bool enableMachineScheduler() const override { return true; }
bool hasStdExtM() const { return HasStdExtM; } bool hasStdExtM() const { return HasStdExtM; }
bool hasStdExtA() const { return HasStdExtA; } bool hasStdExtA() const { return HasStdExtA; }
bool hasStdExtF() const { return HasStdExtF; } bool hasStdExtF() const { return HasStdExtF; }
bool hasStdExtD() const { return HasStdExtD; } bool hasStdExtD() const { return HasStdExtD; }
bool hasStdExtC() const { return HasStdExtC; } bool hasStdExtC() const { return HasStdExtC; }
bool hasStdExtB() const { return HasStdExtB; }
bool hasStdExtZba() const { return HasStdExtZba; } bool hasStdExtZba() const { return HasStdExtZba; }
bool hasStdExtZbb() const { return HasStdExtZbb; } bool hasStdExtZbb() const { return HasStdExtZbb; }
bool hasStdExtZbc() const { return HasStdExtZbc; } bool hasStdExtZbc() const { return HasStdExtZbc; }
bool hasStdExtZbe() const { return HasStdExtZbe; } bool hasStdExtZbe() const { return HasStdExtZbe; }
bool hasStdExtZbf() const { return HasStdExtZbf; } bool hasStdExtZbf() const { return HasStdExtZbf; }
bool hasStdExtZbm() const { return HasStdExtZbm; } bool hasStdExtZbm() const { return HasStdExtZbm; }
bool hasStdExtZbp() const { return HasStdExtZbp; } bool hasStdExtZbp() const { return HasStdExtZbp; }
bool hasStdExtZbr() const { return HasStdExtZbr; } bool hasStdExtZbr() const { return HasStdExtZbr; }
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/attributes.ll

;; Generate ELF attributes from llc. ;; Generate ELF attributes from llc.
; RUN: llc -mtriple=riscv32 -mattr=+m %s -o - | FileCheck --check-prefix=RV32M %s ; RUN: llc -mtriple=riscv32 -mattr=+m %s -o - | FileCheck --check-prefix=RV32M %s
; RUN: llc -mtriple=riscv32 -mattr=+a %s -o - | FileCheck --check-prefix=RV32A %s ; RUN: llc -mtriple=riscv32 -mattr=+a %s -o - | FileCheck --check-prefix=RV32A %s
; RUN: llc -mtriple=riscv32 -mattr=+f %s -o - | FileCheck --check-prefix=RV32F %s ; RUN: llc -mtriple=riscv32 -mattr=+f %s -o - | FileCheck --check-prefix=RV32F %s
; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefix=RV32D %s ; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefix=RV32D %s
; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefix=RV32C %s ; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefix=RV32C %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-b %s -o - | FileCheck --check-prefix=RV32B %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-zvamo,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32V %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-zvamo,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32V %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh %s -o - | FileCheck --check-prefix=RV32ZFH %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh %s -o - | FileCheck --check-prefix=RV32ZFH %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zba %s -o - | FileCheck --check-prefix=RV32ZBA %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zba %s -o - | FileCheck --check-prefix=RV32ZBA %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb %s -o - | FileCheck --check-prefix=RV32ZBB %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb %s -o - | FileCheck --check-prefix=RV32ZBB %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbc %s -o - | FileCheck --check-prefix=RV32ZBC %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbc %s -o - | FileCheck --check-prefix=RV32ZBC %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe %s -o - | FileCheck --check-prefix=RV32ZBE %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe %s -o - | FileCheck --check-prefix=RV32ZBE %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV32ZBF %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV32ZBF %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV32ZBM %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV32ZBM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV32ZBP %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV32ZBP %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s
; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-b %s -o - | FileCheck --check-prefix=RV64B %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zvamo,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64V %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zvamo,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64V %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh %s -o - | FileCheck --check-prefix=RV64ZFH %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh %s -o - | FileCheck --check-prefix=RV64ZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zba %s -o - | FileCheck --check-prefix=RV64ZBA %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zba %s -o - | FileCheck --check-prefix=RV64ZBA %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb %s -o - | FileCheck --check-prefix=RV64ZBB %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb %s -o - | FileCheck --check-prefix=RV64ZBB %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbc %s -o - | FileCheck --check-prefix=RV64ZBC %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbc %s -o - | FileCheck --check-prefix=RV64ZBC %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe %s -o - | FileCheck --check-prefix=RV64ZBE %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe %s -o - | FileCheck --check-prefix=RV64ZBE %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV64ZBF %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV64ZBF %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV64ZBM %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV64ZBM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV64ZBP %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV64ZBP %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64COMBINED %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64COMBINED %s
; RV32M: .attribute 5, "rv32i2p0_m2p0" ; RV32M: .attribute 5, "rv32i2p0_m2p0"
; RV32A: .attribute 5, "rv32i2p0_a2p0" ; RV32A: .attribute 5, "rv32i2p0_a2p0"
; RV32F: .attribute 5, "rv32i2p0_f2p0" ; RV32F: .attribute 5, "rv32i2p0_f2p0"
; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
; RV32C: .attribute 5, "rv32i2p0_c2p0" ; RV32C: .attribute 5, "rv32i2p0_c2p0"
; RV32B: .attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10" ; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1" ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93" ; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93"
; RV32ZBB: .attribute 5, "rv32i2p0_zbb0p93" ; RV32ZBB: .attribute 5, "rv32i2p0_zbb0p93"
; RV32ZBC: .attribute 5, "rv32i2p0_zbc0p93" ; RV32ZBC: .attribute 5, "rv32i2p0_zbc0p93"
; RV32ZBE: .attribute 5, "rv32i2p0_zbe0p93" ; RV32ZBE: .attribute 5, "rv32i2p0_zbe0p93"
; RV32ZBF: .attribute 5, "rv32i2p0_zbf0p93" ; RV32ZBF: .attribute 5, "rv32i2p0_zbf0p93"
; RV32ZBM: .attribute 5, "rv32i2p0_zbm0p93" ; RV32ZBM: .attribute 5, "rv32i2p0_zbm0p93"
; RV32ZBP: .attribute 5, "rv32i2p0_zbp0p93" ; RV32ZBP: .attribute 5, "rv32i2p0_zbp0p93"
; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93" ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93" ; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93"
; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93" ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10" ; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10"
; RV64M: .attribute 5, "rv64i2p0_m2p0" ; RV64M: .attribute 5, "rv64i2p0_m2p0"
; RV64A: .attribute 5, "rv64i2p0_a2p0" ; RV64A: .attribute 5, "rv64i2p0_a2p0"
; RV64F: .attribute 5, "rv64i2p0_f2p0" ; RV64F: .attribute 5, "rv64i2p0_f2p0"
; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
; RV64C: .attribute 5, "rv64i2p0_c2p0" ; RV64C: .attribute 5, "rv64i2p0_c2p0"
; RV64B: .attribute 5, "rv64i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh0p1" ; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh0p1"
; RV64ZBA: .attribute 5, "rv64i2p0_zba0p93" ; RV64ZBA: .attribute 5, "rv64i2p0_zba0p93"
; RV64ZBB: .attribute 5, "rv64i2p0_zbb0p93" ; RV64ZBB: .attribute 5, "rv64i2p0_zbb0p93"
; RV64ZBC: .attribute 5, "rv64i2p0_zbc0p93" ; RV64ZBC: .attribute 5, "rv64i2p0_zbc0p93"
; RV64ZBE: .attribute 5, "rv64i2p0_zbe0p93" ; RV64ZBE: .attribute 5, "rv64i2p0_zbe0p93"
; RV64ZBF: .attribute 5, "rv64i2p0_zbf0p93" ; RV64ZBF: .attribute 5, "rv64i2p0_zbf0p93"
; RV64ZBM: .attribute 5, "rv64i2p0_zbm0p93" ; RV64ZBM: .attribute 5, "rv64i2p0_zbm0p93"
; RV64ZBP: .attribute 5, "rv64i2p0_zbp0p93" ; RV64ZBP: .attribute 5, "rv64i2p0_zbp0p93"
Show All 11 Lines

llvm/test/CodeGen/RISCV/rv32zba.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32B
; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-zba -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-zba -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBA ; RUN: | FileCheck %s -check-prefix=RV32ZBA
define signext i16 @sh1add(i64 %0, i16* %1) { define signext i16 @sh1add(i64 %0, i16* %1) {
; RV32I-LABEL: sh1add: ; RV32I-LABEL: sh1add:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: lh a0, 0(a0) ; RV32I-NEXT: lh a0, 0(a0)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sh1add:
; RV32B: # %bb.0:
; RV32B-NEXT: sh1add a0, a0, a2
; RV32B-NEXT: lh a0, 0(a0)
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: sh1add: ; RV32ZBA-LABEL: sh1add:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh1add a0, a0, a2 ; RV32ZBA-NEXT: sh1add a0, a0, a2
; RV32ZBA-NEXT: lh a0, 0(a0) ; RV32ZBA-NEXT: lh a0, 0(a0)
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%3 = getelementptr inbounds i16, i16* %1, i64 %0 %3 = getelementptr inbounds i16, i16* %1, i64 %0
%4 = load i16, i16* %3 %4 = load i16, i16* %3
ret i16 %4 ret i16 %4
} }
define i32 @sh2add(i64 %0, i32* %1) { define i32 @sh2add(i64 %0, i32* %1) {
; RV32I-LABEL: sh2add: ; RV32I-LABEL: sh2add:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 2 ; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: lw a0, 0(a0) ; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sh2add:
; RV32B: # %bb.0:
; RV32B-NEXT: sh2add a0, a0, a2
; RV32B-NEXT: lw a0, 0(a0)
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: sh2add: ; RV32ZBA-LABEL: sh2add:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh2add a0, a0, a2 ; RV32ZBA-NEXT: sh2add a0, a0, a2
; RV32ZBA-NEXT: lw a0, 0(a0) ; RV32ZBA-NEXT: lw a0, 0(a0)
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%3 = getelementptr inbounds i32, i32* %1, i64 %0 %3 = getelementptr inbounds i32, i32* %1, i64 %0
%4 = load i32, i32* %3 %4 = load i32, i32* %3
ret i32 %4 ret i32 %4
} }
define i64 @sh3add(i64 %0, i64* %1) { define i64 @sh3add(i64 %0, i64* %1) {
; RV32I-LABEL: sh3add: ; RV32I-LABEL: sh3add:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 3 ; RV32I-NEXT: slli a0, a0, 3
; RV32I-NEXT: add a1, a2, a0 ; RV32I-NEXT: add a1, a2, a0
; RV32I-NEXT: lw a0, 0(a1) ; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: lw a1, 4(a1) ; RV32I-NEXT: lw a1, 4(a1)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sh3add:
; RV32B: # %bb.0:
; RV32B-NEXT: sh3add a1, a0, a2
; RV32B-NEXT: lw a0, 0(a1)
; RV32B-NEXT: lw a1, 4(a1)
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: sh3add: ; RV32ZBA-LABEL: sh3add:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a1, a0, a2 ; RV32ZBA-NEXT: sh3add a1, a0, a2
; RV32ZBA-NEXT: lw a0, 0(a1) ; RV32ZBA-NEXT: lw a0, 0(a1)
; RV32ZBA-NEXT: lw a1, 4(a1) ; RV32ZBA-NEXT: lw a1, 4(a1)
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%3 = getelementptr inbounds i64, i64* %1, i64 %0 %3 = getelementptr inbounds i64, i64* %1, i64 %0
%4 = load i64, i64* %3 %4 = load i64, i64* %3
ret i64 %4 ret i64 %4
} }
define i32 @addmul6(i32 %a, i32 %b) { define i32 @addmul6(i32 %a, i32 %b) {
; RV32I-LABEL: addmul6: ; RV32I-LABEL: addmul6:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 6 ; RV32I-NEXT: addi a2, zero, 6
; RV32I-NEXT: mul a0, a0, a2 ; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: addmul6:
; RV32B: # %bb.0:
; RV32B-NEXT: sh1add a0, a0, a0
; RV32B-NEXT: sh1add a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: addmul6: ; RV32ZBA-LABEL: addmul6:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh1add a0, a0, a0 ; RV32ZBA-NEXT: sh1add a0, a0, a0
; RV32ZBA-NEXT: sh1add a0, a0, a1 ; RV32ZBA-NEXT: sh1add a0, a0, a1
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 6 %c = mul i32 %a, 6
%d = add i32 %c, %b %d = add i32 %c, %b
ret i32 %d ret i32 %d
} }
define i32 @addmul10(i32 %a, i32 %b) { define i32 @addmul10(i32 %a, i32 %b) {
; RV32I-LABEL: addmul10: ; RV32I-LABEL: addmul10:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 10 ; RV32I-NEXT: addi a2, zero, 10
; RV32I-NEXT: mul a0, a0, a2 ; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: addmul10:
; RV32B: # %bb.0:
; RV32B-NEXT: sh2add a0, a0, a0
; RV32B-NEXT: sh1add a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: addmul10: ; RV32ZBA-LABEL: addmul10:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh2add a0, a0, a0 ; RV32ZBA-NEXT: sh2add a0, a0, a0
; RV32ZBA-NEXT: sh1add a0, a0, a1 ; RV32ZBA-NEXT: sh1add a0, a0, a1
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 10 %c = mul i32 %a, 10
%d = add i32 %c, %b %d = add i32 %c, %b
ret i32 %d ret i32 %d
} }
define i32 @addmul12(i32 %a, i32 %b) { define i32 @addmul12(i32 %a, i32 %b) {
; RV32I-LABEL: addmul12: ; RV32I-LABEL: addmul12:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 12 ; RV32I-NEXT: addi a2, zero, 12
; RV32I-NEXT: mul a0, a0, a2 ; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: addmul12:
; RV32B: # %bb.0:
; RV32B-NEXT: sh1add a0, a0, a0
; RV32B-NEXT: sh2add a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: addmul12: ; RV32ZBA-LABEL: addmul12:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh1add a0, a0, a0 ; RV32ZBA-NEXT: sh1add a0, a0, a0
; RV32ZBA-NEXT: sh2add a0, a0, a1 ; RV32ZBA-NEXT: sh2add a0, a0, a1
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 12 %c = mul i32 %a, 12
%d = add i32 %c, %b %d = add i32 %c, %b
ret i32 %d ret i32 %d
} }
define i32 @addmul18(i32 %a, i32 %b) { define i32 @addmul18(i32 %a, i32 %b) {
; RV32I-LABEL: addmul18: ; RV32I-LABEL: addmul18:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 18 ; RV32I-NEXT: addi a2, zero, 18
; RV32I-NEXT: mul a0, a0, a2 ; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: addmul18:
; RV32B: # %bb.0:
; RV32B-NEXT: sh3add a0, a0, a0
; RV32B-NEXT: sh1add a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: addmul18: ; RV32ZBA-LABEL: addmul18:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a0, a0, a0 ; RV32ZBA-NEXT: sh3add a0, a0, a0
; RV32ZBA-NEXT: sh1add a0, a0, a1 ; RV32ZBA-NEXT: sh1add a0, a0, a1
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 18 %c = mul i32 %a, 18
%d = add i32 %c, %b %d = add i32 %c, %b
ret i32 %d ret i32 %d
} }
define i32 @addmul20(i32 %a, i32 %b) { define i32 @addmul20(i32 %a, i32 %b) {
; RV32I-LABEL: addmul20: ; RV32I-LABEL: addmul20:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 20 ; RV32I-NEXT: addi a2, zero, 20
; RV32I-NEXT: mul a0, a0, a2 ; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: addmul20:
; RV32B: # %bb.0:
; RV32B-NEXT: sh2add a0, a0, a0
; RV32B-NEXT: sh2add a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: addmul20: ; RV32ZBA-LABEL: addmul20:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh2add a0, a0, a0 ; RV32ZBA-NEXT: sh2add a0, a0, a0
; RV32ZBA-NEXT: sh2add a0, a0, a1 ; RV32ZBA-NEXT: sh2add a0, a0, a1
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 20 %c = mul i32 %a, 20
%d = add i32 %c, %b %d = add i32 %c, %b
ret i32 %d ret i32 %d
} }
define i32 @addmul24(i32 %a, i32 %b) { define i32 @addmul24(i32 %a, i32 %b) {
; RV32I-LABEL: addmul24: ; RV32I-LABEL: addmul24:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 24 ; RV32I-NEXT: addi a2, zero, 24
; RV32I-NEXT: mul a0, a0, a2 ; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: addmul24:
; RV32B: # %bb.0:
; RV32B-NEXT: sh1add a0, a0, a0
; RV32B-NEXT: sh3add a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: addmul24: ; RV32ZBA-LABEL: addmul24:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh1add a0, a0, a0 ; RV32ZBA-NEXT: sh1add a0, a0, a0
; RV32ZBA-NEXT: sh3add a0, a0, a1 ; RV32ZBA-NEXT: sh3add a0, a0, a1
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 24 %c = mul i32 %a, 24
%d = add i32 %c, %b %d = add i32 %c, %b
ret i32 %d ret i32 %d
} }
define i32 @addmul36(i32 %a, i32 %b) { define i32 @addmul36(i32 %a, i32 %b) {
; RV32I-LABEL: addmul36: ; RV32I-LABEL: addmul36:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 36 ; RV32I-NEXT: addi a2, zero, 36
; RV32I-NEXT: mul a0, a0, a2 ; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: addmul36:
; RV32B: # %bb.0:
; RV32B-NEXT: sh3add a0, a0, a0
; RV32B-NEXT: sh2add a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: addmul36: ; RV32ZBA-LABEL: addmul36:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a0, a0, a0 ; RV32ZBA-NEXT: sh3add a0, a0, a0
; RV32ZBA-NEXT: sh2add a0, a0, a1 ; RV32ZBA-NEXT: sh2add a0, a0, a1
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 36 %c = mul i32 %a, 36
%d = add i32 %c, %b %d = add i32 %c, %b
ret i32 %d ret i32 %d
} }
define i32 @addmul40(i32 %a, i32 %b) { define i32 @addmul40(i32 %a, i32 %b) {
; RV32I-LABEL: addmul40: ; RV32I-LABEL: addmul40:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 40 ; RV32I-NEXT: addi a2, zero, 40
; RV32I-NEXT: mul a0, a0, a2 ; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: addmul40:
; RV32B: # %bb.0:
; RV32B-NEXT: sh2add a0, a0, a0
; RV32B-NEXT: sh3add a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: addmul40: ; RV32ZBA-LABEL: addmul40:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh2add a0, a0, a0 ; RV32ZBA-NEXT: sh2add a0, a0, a0
; RV32ZBA-NEXT: sh3add a0, a0, a1 ; RV32ZBA-NEXT: sh3add a0, a0, a1
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 40 %c = mul i32 %a, 40
%d = add i32 %c, %b %d = add i32 %c, %b
ret i32 %d ret i32 %d
} }
define i32 @addmul72(i32 %a, i32 %b) { define i32 @addmul72(i32 %a, i32 %b) {
; RV32I-LABEL: addmul72: ; RV32I-LABEL: addmul72:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 72 ; RV32I-NEXT: addi a2, zero, 72
; RV32I-NEXT: mul a0, a0, a2 ; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: addmul72:
; RV32B: # %bb.0:
; RV32B-NEXT: sh3add a0, a0, a0
; RV32B-NEXT: sh3add a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: addmul72: ; RV32ZBA-LABEL: addmul72:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a0, a0, a0 ; RV32ZBA-NEXT: sh3add a0, a0, a0
; RV32ZBA-NEXT: sh3add a0, a0, a1 ; RV32ZBA-NEXT: sh3add a0, a0, a1
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 72 %c = mul i32 %a, 72
%d = add i32 %c, %b %d = add i32 %c, %b
ret i32 %d ret i32 %d
} }
define i32 @mul96(i32 %a) { define i32 @mul96(i32 %a) {
; RV32I-LABEL: mul96: ; RV32I-LABEL: mul96:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 96 ; RV32I-NEXT: addi a1, zero, 96
; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: mul96:
; RV32B: # %bb.0:
; RV32B-NEXT: sh1add a0, a0, a0
; RV32B-NEXT: slli a0, a0, 5
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: mul96: ; RV32ZBA-LABEL: mul96:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh1add a0, a0, a0 ; RV32ZBA-NEXT: sh1add a0, a0, a0
; RV32ZBA-NEXT: slli a0, a0, 5 ; RV32ZBA-NEXT: slli a0, a0, 5
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 96 %c = mul i32 %a, 96
ret i32 %c ret i32 %c
} }
define i32 @mul160(i32 %a) { define i32 @mul160(i32 %a) {
; RV32I-LABEL: mul160: ; RV32I-LABEL: mul160:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 160 ; RV32I-NEXT: addi a1, zero, 160
; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: mul160:
; RV32B: # %bb.0:
; RV32B-NEXT: sh2add a0, a0, a0
; RV32B-NEXT: slli a0, a0, 5
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: mul160: ; RV32ZBA-LABEL: mul160:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh2add a0, a0, a0 ; RV32ZBA-NEXT: sh2add a0, a0, a0
; RV32ZBA-NEXT: slli a0, a0, 5 ; RV32ZBA-NEXT: slli a0, a0, 5
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 160 %c = mul i32 %a, 160
ret i32 %c ret i32 %c
} }
define i32 @mul288(i32 %a) { define i32 @mul288(i32 %a) {
; RV32I-LABEL: mul288: ; RV32I-LABEL: mul288:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 288 ; RV32I-NEXT: addi a1, zero, 288
; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: mul288:
; RV32B: # %bb.0:
; RV32B-NEXT: sh3add a0, a0, a0
; RV32B-NEXT: slli a0, a0, 5
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: mul288: ; RV32ZBA-LABEL: mul288:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a0, a0, a0 ; RV32ZBA-NEXT: sh3add a0, a0, a0
; RV32ZBA-NEXT: slli a0, a0, 5 ; RV32ZBA-NEXT: slli a0, a0, 5
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 288 %c = mul i32 %a, 288
ret i32 %c ret i32 %c
} }
define i32 @mul258(i32 %a) { define i32 @mul258(i32 %a) {
; RV32I-LABEL: mul258: ; RV32I-LABEL: mul258:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 258 ; RV32I-NEXT: addi a1, zero, 258
; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: mul258:
; RV32B: # %bb.0:
; RV32B-NEXT: addi a1, zero, 258
; RV32B-NEXT: mul a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: mul258: ; RV32ZBA-LABEL: mul258:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: addi a1, zero, 258 ; RV32ZBA-NEXT: addi a1, zero, 258
; RV32ZBA-NEXT: mul a0, a0, a1 ; RV32ZBA-NEXT: mul a0, a0, a1
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 258 %c = mul i32 %a, 258
ret i32 %c ret i32 %c
} }
define i32 @mul260(i32 %a) { define i32 @mul260(i32 %a) {
; RV32I-LABEL: mul260: ; RV32I-LABEL: mul260:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 260 ; RV32I-NEXT: addi a1, zero, 260
; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: mul260:
; RV32B: # %bb.0:
; RV32B-NEXT: addi a1, zero, 260
; RV32B-NEXT: mul a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: mul260: ; RV32ZBA-LABEL: mul260:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: addi a1, zero, 260 ; RV32ZBA-NEXT: addi a1, zero, 260
; RV32ZBA-NEXT: mul a0, a0, a1 ; RV32ZBA-NEXT: mul a0, a0, a1
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 260 %c = mul i32 %a, 260
ret i32 %c ret i32 %c
} }
define i32 @mul264(i32 %a) { define i32 @mul264(i32 %a) {
; RV32I-LABEL: mul264: ; RV32I-LABEL: mul264:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 264 ; RV32I-NEXT: addi a1, zero, 264
; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: mul264:
; RV32B: # %bb.0:
; RV32B-NEXT: addi a1, zero, 264
; RV32B-NEXT: mul a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: mul264: ; RV32ZBA-LABEL: mul264:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: addi a1, zero, 264 ; RV32ZBA-NEXT: addi a1, zero, 264
; RV32ZBA-NEXT: mul a0, a0, a1 ; RV32ZBA-NEXT: mul a0, a0, a1
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 264 %c = mul i32 %a, 264
ret i32 %c ret i32 %c
} }
define i32 @mul11(i32 %a) { define i32 @mul11(i32 %a) {
; RV32I-LABEL: mul11: ; RV32I-LABEL: mul11:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 11 ; RV32I-NEXT: addi a1, zero, 11
; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: mul11:
; RV32B: # %bb.0:
; RV32B-NEXT: sh2add a1, a0, a0
; RV32B-NEXT: sh1add a0, a1, a0
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: mul11: ; RV32ZBA-LABEL: mul11:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh2add a1, a0, a0 ; RV32ZBA-NEXT: sh2add a1, a0, a0
; RV32ZBA-NEXT: sh1add a0, a1, a0 ; RV32ZBA-NEXT: sh1add a0, a1, a0
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 11 %c = mul i32 %a, 11
ret i32 %c ret i32 %c
} }
define i32 @mul19(i32 %a) { define i32 @mul19(i32 %a) {
; RV32I-LABEL: mul19: ; RV32I-LABEL: mul19:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 19 ; RV32I-NEXT: addi a1, zero, 19
; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: mul19:
; RV32B: # %bb.0:
; RV32B-NEXT: sh3add a1, a0, a0
; RV32B-NEXT: sh1add a0, a1, a0
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: mul19: ; RV32ZBA-LABEL: mul19:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a1, a0, a0 ; RV32ZBA-NEXT: sh3add a1, a0, a0
; RV32ZBA-NEXT: sh1add a0, a1, a0 ; RV32ZBA-NEXT: sh1add a0, a1, a0
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 19 %c = mul i32 %a, 19
ret i32 %c ret i32 %c
} }
define i32 @mul13(i32 %a) { define i32 @mul13(i32 %a) {
; RV32I-LABEL: mul13: ; RV32I-LABEL: mul13:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 13 ; RV32I-NEXT: addi a1, zero, 13
; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: mul13:
; RV32B: # %bb.0:
; RV32B-NEXT: sh1add a1, a0, a0
; RV32B-NEXT: sh2add a0, a1, a0
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: mul13: ; RV32ZBA-LABEL: mul13:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh1add a1, a0, a0 ; RV32ZBA-NEXT: sh1add a1, a0, a0
; RV32ZBA-NEXT: sh2add a0, a1, a0 ; RV32ZBA-NEXT: sh2add a0, a1, a0
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 13 %c = mul i32 %a, 13
ret i32 %c ret i32 %c
} }
define i32 @mul21(i32 %a) { define i32 @mul21(i32 %a) {
; RV32I-LABEL: mul21: ; RV32I-LABEL: mul21:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 21 ; RV32I-NEXT: addi a1, zero, 21
; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: mul21:
; RV32B: # %bb.0:
; RV32B-NEXT: sh2add a1, a0, a0
; RV32B-NEXT: sh2add a0, a1, a0
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: mul21: ; RV32ZBA-LABEL: mul21:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh2add a1, a0, a0 ; RV32ZBA-NEXT: sh2add a1, a0, a0
; RV32ZBA-NEXT: sh2add a0, a1, a0 ; RV32ZBA-NEXT: sh2add a0, a1, a0
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 21 %c = mul i32 %a, 21
ret i32 %c ret i32 %c
} }
define i32 @mul37(i32 %a) { define i32 @mul37(i32 %a) {
; RV32I-LABEL: mul37: ; RV32I-LABEL: mul37:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 37 ; RV32I-NEXT: addi a1, zero, 37
; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: mul37:
; RV32B: # %bb.0:
; RV32B-NEXT: sh3add a1, a0, a0
; RV32B-NEXT: sh2add a0, a1, a0
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: mul37: ; RV32ZBA-LABEL: mul37:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a1, a0, a0 ; RV32ZBA-NEXT: sh3add a1, a0, a0
; RV32ZBA-NEXT: sh2add a0, a1, a0 ; RV32ZBA-NEXT: sh2add a0, a1, a0
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 37 %c = mul i32 %a, 37
ret i32 %c ret i32 %c
} }
define i32 @mul25(i32 %a) { define i32 @mul25(i32 %a) {
; RV32I-LABEL: mul25: ; RV32I-LABEL: mul25:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 25 ; RV32I-NEXT: addi a1, zero, 25
; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: mul25:
; RV32B: # %bb.0:
; RV32B-NEXT: sh1add a1, a0, a0
; RV32B-NEXT: sh3add a0, a1, a0
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: mul25: ; RV32ZBA-LABEL: mul25:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh1add a1, a0, a0 ; RV32ZBA-NEXT: sh1add a1, a0, a0
; RV32ZBA-NEXT: sh3add a0, a1, a0 ; RV32ZBA-NEXT: sh3add a0, a1, a0
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 25 %c = mul i32 %a, 25
ret i32 %c ret i32 %c
} }
define i32 @mul41(i32 %a) { define i32 @mul41(i32 %a) {
; RV32I-LABEL: mul41: ; RV32I-LABEL: mul41:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 41 ; RV32I-NEXT: addi a1, zero, 41
; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: mul41:
; RV32B: # %bb.0:
; RV32B-NEXT: sh2add a1, a0, a0
; RV32B-NEXT: sh3add a0, a1, a0
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: mul41: ; RV32ZBA-LABEL: mul41:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh2add a1, a0, a0 ; RV32ZBA-NEXT: sh2add a1, a0, a0
; RV32ZBA-NEXT: sh3add a0, a1, a0 ; RV32ZBA-NEXT: sh3add a0, a1, a0
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 41 %c = mul i32 %a, 41
ret i32 %c ret i32 %c
} }
define i32 @mul73(i32 %a) { define i32 @mul73(i32 %a) {
; RV32I-LABEL: mul73: ; RV32I-LABEL: mul73:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 73 ; RV32I-NEXT: addi a1, zero, 73
; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: mul73:
; RV32B: # %bb.0:
; RV32B-NEXT: sh3add a1, a0, a0
; RV32B-NEXT: sh3add a0, a1, a0
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: mul73: ; RV32ZBA-LABEL: mul73:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a1, a0, a0 ; RV32ZBA-NEXT: sh3add a1, a0, a0
; RV32ZBA-NEXT: sh3add a0, a1, a0 ; RV32ZBA-NEXT: sh3add a0, a1, a0
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 73 %c = mul i32 %a, 73
ret i32 %c ret i32 %c
} }
define i32 @mul27(i32 %a) { define i32 @mul27(i32 %a) {
; RV32I-LABEL: mul27: ; RV32I-LABEL: mul27:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 27 ; RV32I-NEXT: addi a1, zero, 27
; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: mul27:
; RV32B: # %bb.0:
; RV32B-NEXT: sh3add a0, a0, a0
; RV32B-NEXT: sh1add a0, a0, a0
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: mul27: ; RV32ZBA-LABEL: mul27:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a0, a0, a0 ; RV32ZBA-NEXT: sh3add a0, a0, a0
; RV32ZBA-NEXT: sh1add a0, a0, a0 ; RV32ZBA-NEXT: sh1add a0, a0, a0
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 27 %c = mul i32 %a, 27
ret i32 %c ret i32 %c
} }
define i32 @mul45(i32 %a) { define i32 @mul45(i32 %a) {
; RV32I-LABEL: mul45: ; RV32I-LABEL: mul45:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 45 ; RV32I-NEXT: addi a1, zero, 45
; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: mul45:
; RV32B: # %bb.0:
; RV32B-NEXT: sh3add a0, a0, a0
; RV32B-NEXT: sh2add a0, a0, a0
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: mul45: ; RV32ZBA-LABEL: mul45:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a0, a0, a0 ; RV32ZBA-NEXT: sh3add a0, a0, a0
; RV32ZBA-NEXT: sh2add a0, a0, a0 ; RV32ZBA-NEXT: sh2add a0, a0, a0
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 45 %c = mul i32 %a, 45
ret i32 %c ret i32 %c
} }
define i32 @mul81(i32 %a) { define i32 @mul81(i32 %a) {
; RV32I-LABEL: mul81: ; RV32I-LABEL: mul81:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 81 ; RV32I-NEXT: addi a1, zero, 81
; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: mul81:
; RV32B: # %bb.0:
; RV32B-NEXT: sh3add a0, a0, a0
; RV32B-NEXT: sh3add a0, a0, a0
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: mul81: ; RV32ZBA-LABEL: mul81:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a0, a0, a0 ; RV32ZBA-NEXT: sh3add a0, a0, a0
; RV32ZBA-NEXT: sh3add a0, a0, a0 ; RV32ZBA-NEXT: sh3add a0, a0, a0
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 81 %c = mul i32 %a, 81
ret i32 %c ret i32 %c
} }
define i32 @mul4098(i32 %a) { define i32 @mul4098(i32 %a) {
; RV32I-LABEL: mul4098: ; RV32I-LABEL: mul4098:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1 ; RV32I-NEXT: lui a1, 1
; RV32I-NEXT: addi a1, a1, 2 ; RV32I-NEXT: addi a1, a1, 2
; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: mul4098:
; RV32B: # %bb.0:
; RV32B-NEXT: slli a1, a0, 12
; RV32B-NEXT: sh1add a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: mul4098: ; RV32ZBA-LABEL: mul4098:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: slli a1, a0, 12 ; RV32ZBA-NEXT: slli a1, a0, 12
; RV32ZBA-NEXT: sh1add a0, a0, a1 ; RV32ZBA-NEXT: sh1add a0, a0, a1
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 4098 %c = mul i32 %a, 4098
ret i32 %c ret i32 %c
} }
define i32 @mul4100(i32 %a) { define i32 @mul4100(i32 %a) {
; RV32I-LABEL: mul4100: ; RV32I-LABEL: mul4100:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1 ; RV32I-NEXT: lui a1, 1
; RV32I-NEXT: addi a1, a1, 4 ; RV32I-NEXT: addi a1, a1, 4
; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: mul4100:
; RV32B: # %bb.0:
; RV32B-NEXT: slli a1, a0, 12
; RV32B-NEXT: sh2add a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: mul4100: ; RV32ZBA-LABEL: mul4100:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: slli a1, a0, 12 ; RV32ZBA-NEXT: slli a1, a0, 12
; RV32ZBA-NEXT: sh2add a0, a0, a1 ; RV32ZBA-NEXT: sh2add a0, a0, a1
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 4100 %c = mul i32 %a, 4100
ret i32 %c ret i32 %c
} }
define i32 @mul4104(i32 %a) { define i32 @mul4104(i32 %a) {
; RV32I-LABEL: mul4104: ; RV32I-LABEL: mul4104:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1 ; RV32I-NEXT: lui a1, 1
; RV32I-NEXT: addi a1, a1, 8 ; RV32I-NEXT: addi a1, a1, 8
; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: mul4104:
; RV32B: # %bb.0:
; RV32B-NEXT: slli a1, a0, 12
; RV32B-NEXT: sh3add a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: mul4104: ; RV32ZBA-LABEL: mul4104:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: slli a1, a0, 12 ; RV32ZBA-NEXT: slli a1, a0, 12
; RV32ZBA-NEXT: sh3add a0, a0, a1 ; RV32ZBA-NEXT: sh3add a0, a0, a1
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = mul i32 %a, 4104 %c = mul i32 %a, 4104
ret i32 %c ret i32 %c
} }
define i32 @add4104(i32 %a) { define i32 @add4104(i32 %a) {
; RV32I-LABEL: add4104: ; RV32I-LABEL: add4104:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1 ; RV32I-NEXT: lui a1, 1
; RV32I-NEXT: addi a1, a1, 8 ; RV32I-NEXT: addi a1, a1, 8
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: add4104:
; RV32B: # %bb.0:
; RV32B-NEXT: addi a1, zero, 1026
; RV32B-NEXT: sh2add a0, a1, a0
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: add4104: ; RV32ZBA-LABEL: add4104:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: addi a1, zero, 1026 ; RV32ZBA-NEXT: addi a1, zero, 1026
; RV32ZBA-NEXT: sh2add a0, a1, a0 ; RV32ZBA-NEXT: sh2add a0, a1, a0
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = add i32 %a, 4104 %c = add i32 %a, 4104
ret i32 %c ret i32 %c
} }
define i32 @add8208(i32 %a) { define i32 @add8208(i32 %a) {
; RV32I-LABEL: add8208: ; RV32I-LABEL: add8208:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 2 ; RV32I-NEXT: lui a1, 2
; RV32I-NEXT: addi a1, a1, 16 ; RV32I-NEXT: addi a1, a1, 16
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: add8208:
; RV32B: # %bb.0:
; RV32B-NEXT: addi a1, zero, 1026
; RV32B-NEXT: sh3add a0, a1, a0
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: add8208: ; RV32ZBA-LABEL: add8208:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: addi a1, zero, 1026 ; RV32ZBA-NEXT: addi a1, zero, 1026
; RV32ZBA-NEXT: sh3add a0, a1, a0 ; RV32ZBA-NEXT: sh3add a0, a1, a0
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = add i32 %a, 8208 %c = add i32 %a, 8208
ret i32 %c ret i32 %c
} }
define i32 @addshl_5_6(i32 %a, i32 %b) { define i32 @addshl_5_6(i32 %a, i32 %b) {
; RV32I-LABEL: addshl_5_6: ; RV32I-LABEL: addshl_5_6:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 5 ; RV32I-NEXT: slli a0, a0, 5
; RV32I-NEXT: slli a1, a1, 6 ; RV32I-NEXT: slli a1, a1, 6
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: addshl_5_6:
; RV32B: # %bb.0:
; RV32B-NEXT: sh1add a0, a1, a0
; RV32B-NEXT: slli a0, a0, 5
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: addshl_5_6: ; RV32ZBA-LABEL: addshl_5_6:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh1add a0, a1, a0 ; RV32ZBA-NEXT: sh1add a0, a1, a0
; RV32ZBA-NEXT: slli a0, a0, 5 ; RV32ZBA-NEXT: slli a0, a0, 5
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = shl i32 %a, 5 %c = shl i32 %a, 5
%d = shl i32 %b, 6 %d = shl i32 %b, 6
%e = add i32 %c, %d %e = add i32 %c, %d
ret i32 %e ret i32 %e
} }
define i32 @addshl_5_7(i32 %a, i32 %b) { define i32 @addshl_5_7(i32 %a, i32 %b) {
; RV32I-LABEL: addshl_5_7: ; RV32I-LABEL: addshl_5_7:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 5 ; RV32I-NEXT: slli a0, a0, 5
; RV32I-NEXT: slli a1, a1, 7 ; RV32I-NEXT: slli a1, a1, 7
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: addshl_5_7:
; RV32B: # %bb.0:
; RV32B-NEXT: sh2add a0, a1, a0
; RV32B-NEXT: slli a0, a0, 5
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: addshl_5_7: ; RV32ZBA-LABEL: addshl_5_7:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh2add a0, a1, a0 ; RV32ZBA-NEXT: sh2add a0, a1, a0
; RV32ZBA-NEXT: slli a0, a0, 5 ; RV32ZBA-NEXT: slli a0, a0, 5
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = shl i32 %a, 5 %c = shl i32 %a, 5
%d = shl i32 %b, 7 %d = shl i32 %b, 7
%e = add i32 %c, %d %e = add i32 %c, %d
ret i32 %e ret i32 %e
} }
define i32 @addshl_5_8(i32 %a, i32 %b) { define i32 @addshl_5_8(i32 %a, i32 %b) {
; RV32I-LABEL: addshl_5_8: ; RV32I-LABEL: addshl_5_8:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 5 ; RV32I-NEXT: slli a0, a0, 5
; RV32I-NEXT: slli a1, a1, 8 ; RV32I-NEXT: slli a1, a1, 8
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: addshl_5_8:
; RV32B: # %bb.0:
; RV32B-NEXT: sh3add a0, a1, a0
; RV32B-NEXT: slli a0, a0, 5
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: addshl_5_8: ; RV32ZBA-LABEL: addshl_5_8:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a0, a1, a0 ; RV32ZBA-NEXT: sh3add a0, a1, a0
; RV32ZBA-NEXT: slli a0, a0, 5 ; RV32ZBA-NEXT: slli a0, a0, 5
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = shl i32 %a, 5 %c = shl i32 %a, 5
%d = shl i32 %b, 8 %d = shl i32 %b, 8
%e = add i32 %c, %d %e = add i32 %c, %d
ret i32 %e ret i32 %e
} }

llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32B
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBB ; RUN: | FileCheck %s -check-prefix=RV32ZBB
declare i32 @llvm.riscv.orc.b.i32(i32) declare i32 @llvm.riscv.orc.b.i32(i32)
define i32 @orcb(i32 %a) nounwind { define i32 @orcb(i32 %a) nounwind {
; RV32B-LABEL: orcb:
; RV32B: # %bb.0:
; RV32B-NEXT: orc.b a0, a0
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: orcb: ; RV32ZBB-LABEL: orcb:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: orc.b a0, a0 ; RV32ZBB-NEXT: orc.b a0, a0
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
%tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a) %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
ret i32 %tmp ret i32 %tmp
} }

llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32B
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBB ; RUN: | FileCheck %s -check-prefix=RV32ZBB
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBP ; RUN: | FileCheck %s -check-prefix=RV32ZBP
define i32 @andn_i32(i32 %a, i32 %b) nounwind { define i32 @andn_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: andn_i32: ; RV32I-LABEL: andn_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: not a1, a1 ; RV32I-NEXT: not a1, a1
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: andn_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: andn a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: andn_i32: ; RV32ZBB-LABEL: andn_i32:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: andn a0, a0, a1 ; RV32ZBB-NEXT: andn a0, a0, a1
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
; ;
; RV32ZBP-LABEL: andn_i32: ; RV32ZBP-LABEL: andn_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: andn a0, a0, a1 ; RV32ZBP-NEXT: andn a0, a0, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%neg = xor i32 %b, -1 %neg = xor i32 %b, -1
%and = and i32 %neg, %a %and = and i32 %neg, %a
ret i32 %and ret i32 %and
} }
define i64 @andn_i64(i64 %a, i64 %b) nounwind { define i64 @andn_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: andn_i64: ; RV32I-LABEL: andn_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: not a3, a3 ; RV32I-NEXT: not a3, a3
; RV32I-NEXT: not a2, a2 ; RV32I-NEXT: not a2, a2
; RV32I-NEXT: and a0, a2, a0 ; RV32I-NEXT: and a0, a2, a0
; RV32I-NEXT: and a1, a3, a1 ; RV32I-NEXT: and a1, a3, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: andn_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: andn a0, a0, a2
; RV32B-NEXT: andn a1, a1, a3
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: andn_i64: ; RV32ZBB-LABEL: andn_i64:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: andn a0, a0, a2 ; RV32ZBB-NEXT: andn a0, a0, a2
; RV32ZBB-NEXT: andn a1, a1, a3 ; RV32ZBB-NEXT: andn a1, a1, a3
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
; ;
; RV32ZBP-LABEL: andn_i64: ; RV32ZBP-LABEL: andn_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: andn a0, a0, a2 ; RV32ZBP-NEXT: andn a0, a0, a2
; RV32ZBP-NEXT: andn a1, a1, a3 ; RV32ZBP-NEXT: andn a1, a1, a3
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%neg = xor i64 %b, -1 %neg = xor i64 %b, -1
%and = and i64 %neg, %a %and = and i64 %neg, %a
ret i64 %and ret i64 %and
} }
define i32 @orn_i32(i32 %a, i32 %b) nounwind { define i32 @orn_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: orn_i32: ; RV32I-LABEL: orn_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: not a1, a1 ; RV32I-NEXT: not a1, a1
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: orn_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: orn a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: orn_i32: ; RV32ZBB-LABEL: orn_i32:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: orn a0, a0, a1 ; RV32ZBB-NEXT: orn a0, a0, a1
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
; ;
; RV32ZBP-LABEL: orn_i32: ; RV32ZBP-LABEL: orn_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orn a0, a0, a1 ; RV32ZBP-NEXT: orn a0, a0, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%neg = xor i32 %b, -1 %neg = xor i32 %b, -1
%or = or i32 %neg, %a %or = or i32 %neg, %a
ret i32 %or ret i32 %or
} }
define i64 @orn_i64(i64 %a, i64 %b) nounwind { define i64 @orn_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: orn_i64: ; RV32I-LABEL: orn_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: not a3, a3 ; RV32I-NEXT: not a3, a3
; RV32I-NEXT: not a2, a2 ; RV32I-NEXT: not a2, a2
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: orn_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: orn a0, a0, a2
; RV32B-NEXT: orn a1, a1, a3
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: orn_i64: ; RV32ZBB-LABEL: orn_i64:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: orn a0, a0, a2 ; RV32ZBB-NEXT: orn a0, a0, a2
; RV32ZBB-NEXT: orn a1, a1, a3 ; RV32ZBB-NEXT: orn a1, a1, a3
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
; ;
; RV32ZBP-LABEL: orn_i64: ; RV32ZBP-LABEL: orn_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orn a0, a0, a2 ; RV32ZBP-NEXT: orn a0, a0, a2
; RV32ZBP-NEXT: orn a1, a1, a3 ; RV32ZBP-NEXT: orn a1, a1, a3
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%neg = xor i64 %b, -1 %neg = xor i64 %b, -1
%or = or i64 %neg, %a %or = or i64 %neg, %a
ret i64 %or ret i64 %or
} }
define i32 @xnor_i32(i32 %a, i32 %b) nounwind { define i32 @xnor_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: xnor_i32: ; RV32I-LABEL: xnor_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: not a0, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: xnor_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: xnor a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: xnor_i32: ; RV32ZBB-LABEL: xnor_i32:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: xnor a0, a0, a1 ; RV32ZBB-NEXT: xnor a0, a0, a1
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
; ;
; RV32ZBP-LABEL: xnor_i32: ; RV32ZBP-LABEL: xnor_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: xnor a0, a0, a1 ; RV32ZBP-NEXT: xnor a0, a0, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%neg = xor i32 %a, -1 %neg = xor i32 %a, -1
%xor = xor i32 %neg, %b %xor = xor i32 %neg, %b
ret i32 %xor ret i32 %xor
} }
define i64 @xnor_i64(i64 %a, i64 %b) nounwind { define i64 @xnor_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: xnor_i64: ; RV32I-LABEL: xnor_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: xor a1, a1, a3 ; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: xor a0, a0, a2 ; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: not a0, a0
; RV32I-NEXT: not a1, a1 ; RV32I-NEXT: not a1, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: xnor_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: xnor a0, a0, a2
; RV32B-NEXT: xnor a1, a1, a3
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: xnor_i64: ; RV32ZBB-LABEL: xnor_i64:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: xnor a0, a0, a2 ; RV32ZBB-NEXT: xnor a0, a0, a2
; RV32ZBB-NEXT: xnor a1, a1, a3 ; RV32ZBB-NEXT: xnor a1, a1, a3
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
; ;
; RV32ZBP-LABEL: xnor_i64: ; RV32ZBP-LABEL: xnor_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
Show All 11 Lines
; RV32I-LABEL: rol_i32: ; RV32I-LABEL: rol_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: sll a2, a0, a1 ; RV32I-NEXT: sll a2, a0, a1
; RV32I-NEXT: neg a1, a1 ; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: srl a0, a0, a1 ; RV32I-NEXT: srl a0, a0, a1
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: rol_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: rol a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: rol_i32: ; RV32ZBB-LABEL: rol_i32:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: rol a0, a0, a1 ; RV32ZBB-NEXT: rol a0, a0, a1
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
; ;
; RV32ZBP-LABEL: rol_i32: ; RV32ZBP-LABEL: rol_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rol a0, a0, a1 ; RV32ZBP-NEXT: rol a0, a0, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%or = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %b) %or = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %b)
ret i32 %or ret i32 %or
} }
; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32.
; This test is presented here in case future expansions of the experimental-b ; This test is presented here in case future expansions of the experimental-b
; extension introduce instructions suitable for this pattern. ; extension introduce instructions suitable for this pattern.
declare i64 @llvm.fshl.i64(i64, i64, i64) declare i64 @llvm.fshl.i64(i64, i64, i64)
define i64 @rol_i64(i64 %a, i64 %b) nounwind { define i64 @rol_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: rol_i64: ; RV32I-LABEL: rol_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 31 Lines
; RV32I-NEXT: bgez t0, .LBB7_7 ; RV32I-NEXT: bgez t0, .LBB7_7
; RV32I-NEXT: .LBB7_6: ; RV32I-NEXT: .LBB7_6:
; RV32I-NEXT: sll a0, a0, a2 ; RV32I-NEXT: sll a0, a0, a2
; RV32I-NEXT: or a3, a3, a0 ; RV32I-NEXT: or a3, a3, a0
; RV32I-NEXT: .LBB7_7: ; RV32I-NEXT: .LBB7_7:
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: rol_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: sll a7, a1, a2
; RV32B-NEXT: andi a4, a2, 63
; RV32B-NEXT: addi a6, zero, 31
; RV32B-NEXT: sub a5, a6, a4
; RV32B-NEXT: srli a3, a0, 1
; RV32B-NEXT: srl a3, a3, a5
; RV32B-NEXT: or a7, a7, a3
; RV32B-NEXT: addi t1, a4, -32
; RV32B-NEXT: sll a5, a0, t1
; RV32B-NEXT: slti a3, t1, 0
; RV32B-NEXT: cmov a7, a3, a7, a5
; RV32B-NEXT: neg a5, a2
; RV32B-NEXT: srl t0, a1, a5
; RV32B-NEXT: andi t2, a5, 63
; RV32B-NEXT: addi a4, t2, -32
; RV32B-NEXT: srai a3, a4, 31
; RV32B-NEXT: and a3, a3, t0
; RV32B-NEXT: or a7, a7, a3
; RV32B-NEXT: srl t0, a0, a5
; RV32B-NEXT: sub a5, a6, t2
; RV32B-NEXT: slli a3, a1, 1
; RV32B-NEXT: sll a3, a3, a5
; RV32B-NEXT: or a3, t0, a3
; RV32B-NEXT: srl a1, a1, a4
; RV32B-NEXT: slti a4, a4, 0
; RV32B-NEXT: cmov a1, a4, a3, a1
; RV32B-NEXT: sll a0, a0, a2
; RV32B-NEXT: srai a2, t1, 31
; RV32B-NEXT: and a0, a2, a0
; RV32B-NEXT: or a0, a0, a1
; RV32B-NEXT: mv a1, a7
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: rol_i64: ; RV32ZBB-LABEL: rol_i64:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: mv a7, a1 ; RV32ZBB-NEXT: mv a7, a1
; RV32ZBB-NEXT: andi a1, a2, 63 ; RV32ZBB-NEXT: andi a1, a2, 63
; RV32ZBB-NEXT: addi t0, a1, -32 ; RV32ZBB-NEXT: addi t0, a1, -32
; RV32ZBB-NEXT: addi a6, zero, 31 ; RV32ZBB-NEXT: addi a6, zero, 31
; RV32ZBB-NEXT: bltz t0, .LBB7_2 ; RV32ZBB-NEXT: bltz t0, .LBB7_2
; RV32ZBB-NEXT: # %bb.1: ; RV32ZBB-NEXT: # %bb.1:
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; RV32I-LABEL: ror_i32: ; RV32I-LABEL: ror_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srl a2, a0, a1 ; RV32I-NEXT: srl a2, a0, a1
; RV32I-NEXT: neg a1, a1 ; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sll a0, a0, a1 ; RV32I-NEXT: sll a0, a0, a1
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: ror_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: ror a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: ror_i32: ; RV32ZBB-LABEL: ror_i32:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: ror a0, a0, a1 ; RV32ZBB-NEXT: ror a0, a0, a1
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
; ;
; RV32ZBP-LABEL: ror_i32: ; RV32ZBP-LABEL: ror_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: ror a0, a0, a1 ; RV32ZBP-NEXT: ror a0, a0, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%or = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %b) %or = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %b)
ret i32 %or ret i32 %or
} }
; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32.
; This test is presented here in case future expansions of the experimental-b ; This test is presented here in case future expansions of the experimental-b
; extension introduce instructions suitable for this pattern. ; extension introduce instructions suitable for this pattern.
declare i64 @llvm.fshr.i64(i64, i64, i64) declare i64 @llvm.fshr.i64(i64, i64, i64)
define i64 @ror_i64(i64 %a, i64 %b) nounwind { define i64 @ror_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: ror_i64: ; RV32I-LABEL: ror_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 31 Lines
; RV32I-NEXT: bgez a7, .LBB9_7 ; RV32I-NEXT: bgez a7, .LBB9_7
; RV32I-NEXT: .LBB9_6: ; RV32I-NEXT: .LBB9_6:
; RV32I-NEXT: srl a1, a1, a2 ; RV32I-NEXT: srl a1, a1, a2
; RV32I-NEXT: or a3, a3, a1 ; RV32I-NEXT: or a3, a3, a1
; RV32I-NEXT: .LBB9_7: ; RV32I-NEXT: .LBB9_7:
; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: ror_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: srl a7, a0, a2
; RV32B-NEXT: andi a4, a2, 63
; RV32B-NEXT: addi a6, zero, 31
; RV32B-NEXT: sub a5, a6, a4
; RV32B-NEXT: slli a3, a1, 1
; RV32B-NEXT: sll a3, a3, a5
; RV32B-NEXT: or a7, a7, a3
; RV32B-NEXT: addi t1, a4, -32
; RV32B-NEXT: srl a5, a1, t1
; RV32B-NEXT: slti a3, t1, 0
; RV32B-NEXT: cmov a7, a3, a7, a5
; RV32B-NEXT: neg a5, a2
; RV32B-NEXT: sll t0, a0, a5
; RV32B-NEXT: andi t2, a5, 63
; RV32B-NEXT: addi a4, t2, -32
; RV32B-NEXT: srai a3, a4, 31
; RV32B-NEXT: and a3, a3, t0
; RV32B-NEXT: or a7, a7, a3
; RV32B-NEXT: sll t0, a1, a5
; RV32B-NEXT: sub a5, a6, t2
; RV32B-NEXT: srli a3, a0, 1
; RV32B-NEXT: srl a3, a3, a5
; RV32B-NEXT: or a3, t0, a3
; RV32B-NEXT: sll a0, a0, a4
; RV32B-NEXT: slti a4, a4, 0
; RV32B-NEXT: cmov a0, a4, a3, a0
; RV32B-NEXT: srl a1, a1, a2
; RV32B-NEXT: srai a2, t1, 31
; RV32B-NEXT: and a1, a2, a1
; RV32B-NEXT: or a1, a1, a0
; RV32B-NEXT: mv a0, a7
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: ror_i64: ; RV32ZBB-LABEL: ror_i64:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: mv t0, a0 ; RV32ZBB-NEXT: mv t0, a0
; RV32ZBB-NEXT: andi a0, a2, 63 ; RV32ZBB-NEXT: andi a0, a2, 63
; RV32ZBB-NEXT: addi a7, a0, -32 ; RV32ZBB-NEXT: addi a7, a0, -32
; RV32ZBB-NEXT: addi a6, zero, 31 ; RV32ZBB-NEXT: addi a6, zero, 31
; RV32ZBB-NEXT: bltz a7, .LBB9_2 ; RV32ZBB-NEXT: bltz a7, .LBB9_2
; RV32ZBB-NEXT: # %bb.1: ; RV32ZBB-NEXT: # %bb.1:
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
define i32 @rori_i32_fshl(i32 %a) nounwind { define i32 @rori_i32_fshl(i32 %a) nounwind {
; RV32I-LABEL: rori_i32_fshl: ; RV32I-LABEL: rori_i32_fshl:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: slli a0, a0, 31 ; RV32I-NEXT: slli a0, a0, 31
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: rori_i32_fshl:
; RV32B: # %bb.0:
; RV32B-NEXT: rori a0, a0, 1
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: rori_i32_fshl: ; RV32ZBB-LABEL: rori_i32_fshl:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: rori a0, a0, 1 ; RV32ZBB-NEXT: rori a0, a0, 1
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
; ;
; RV32ZBP-LABEL: rori_i32_fshl: ; RV32ZBP-LABEL: rori_i32_fshl:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rori a0, a0, 1 ; RV32ZBP-NEXT: rori a0, a0, 1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 31) %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 31)
ret i32 %1 ret i32 %1
} }
define i32 @rori_i32_fshr(i32 %a) nounwind { define i32 @rori_i32_fshr(i32 %a) nounwind {
; RV32I-LABEL: rori_i32_fshr: ; RV32I-LABEL: rori_i32_fshr:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 1 ; RV32I-NEXT: slli a1, a0, 1
; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: srli a0, a0, 31
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: rori_i32_fshr:
; RV32B: # %bb.0:
; RV32B-NEXT: rori a0, a0, 31
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: rori_i32_fshr: ; RV32ZBB-LABEL: rori_i32_fshr:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: rori a0, a0, 31 ; RV32ZBB-NEXT: rori a0, a0, 31
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
; ;
; RV32ZBP-LABEL: rori_i32_fshr: ; RV32ZBP-LABEL: rori_i32_fshr:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rori a0, a0, 31 ; RV32ZBP-NEXT: rori a0, a0, 31
Show All 9 Lines
; RV32I-NEXT: srli a3, a0, 1 ; RV32I-NEXT: srli a3, a0, 1
; RV32I-NEXT: or a2, a3, a2 ; RV32I-NEXT: or a2, a3, a2
; RV32I-NEXT: srli a1, a1, 1 ; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: slli a0, a0, 31 ; RV32I-NEXT: slli a0, a0, 31
; RV32I-NEXT: or a1, a0, a1 ; RV32I-NEXT: or a1, a0, a1
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: rori_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: fsri a2, a0, a1, 1
; RV32B-NEXT: fsri a1, a1, a0, 1
; RV32B-NEXT: mv a0, a2
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: rori_i64: ; RV32ZBB-LABEL: rori_i64:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: slli a2, a1, 31 ; RV32ZBB-NEXT: slli a2, a1, 31
; RV32ZBB-NEXT: srli a3, a0, 1 ; RV32ZBB-NEXT: srli a3, a0, 1
; RV32ZBB-NEXT: or a2, a3, a2 ; RV32ZBB-NEXT: or a2, a3, a2
; RV32ZBB-NEXT: srli a1, a1, 1 ; RV32ZBB-NEXT: srli a1, a1, 1
; RV32ZBB-NEXT: slli a0, a0, 31 ; RV32ZBB-NEXT: slli a0, a0, 31
; RV32ZBB-NEXT: or a1, a0, a1 ; RV32ZBB-NEXT: or a1, a0, a1
Show All 21 Lines
; RV32I-NEXT: srli a3, a1, 31 ; RV32I-NEXT: srli a3, a1, 31
; RV32I-NEXT: or a2, a3, a2 ; RV32I-NEXT: or a2, a3, a2
; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: srli a0, a0, 31
; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: or a1, a1, a0 ; RV32I-NEXT: or a1, a1, a0
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: rori_i64_fshr:
; RV32B: # %bb.0:
; RV32B-NEXT: fsri a2, a1, a0, 31
; RV32B-NEXT: fsri a1, a0, a1, 31
; RV32B-NEXT: mv a0, a2
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: rori_i64_fshr: ; RV32ZBB-LABEL: rori_i64_fshr:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: slli a2, a0, 1 ; RV32ZBB-NEXT: slli a2, a0, 1
; RV32ZBB-NEXT: srli a3, a1, 31 ; RV32ZBB-NEXT: srli a3, a1, 31
; RV32ZBB-NEXT: or a2, a3, a2 ; RV32ZBB-NEXT: or a2, a3, a2
; RV32ZBB-NEXT: srli a0, a0, 31 ; RV32ZBB-NEXT: srli a0, a0, 31
; RV32ZBB-NEXT: slli a1, a1, 1 ; RV32ZBB-NEXT: slli a1, a1, 1
; RV32ZBB-NEXT: or a1, a1, a0 ; RV32ZBB-NEXT: or a1, a1, a0
Show All 16 Lines
define i8 @srli_i8(i8 %a) nounwind { define i8 @srli_i8(i8 %a) nounwind {
; RV32I-LABEL: srli_i8: ; RV32I-LABEL: srli_i8:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 192 ; RV32I-NEXT: andi a0, a0, 192
; RV32I-NEXT: srli a0, a0, 6 ; RV32I-NEXT: srli a0, a0, 6
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: srli_i8:
; RV32B: # %bb.0:
; RV32B-NEXT: andi a0, a0, 192
; RV32B-NEXT: srli a0, a0, 6
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: srli_i8: ; RV32ZBB-LABEL: srli_i8:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: andi a0, a0, 192 ; RV32ZBB-NEXT: andi a0, a0, 192
; RV32ZBB-NEXT: srli a0, a0, 6 ; RV32ZBB-NEXT: srli a0, a0, 6
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
; ;
; RV32ZBP-LABEL: srli_i8: ; RV32ZBP-LABEL: srli_i8:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: andi a0, a0, 192 ; RV32ZBP-NEXT: andi a0, a0, 192
; RV32ZBP-NEXT: srli a0, a0, 6 ; RV32ZBP-NEXT: srli a0, a0, 6
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%1 = lshr i8 %a, 6 %1 = lshr i8 %a, 6
ret i8 %1 ret i8 %1
} }
define i8 @srai_i8(i8 %a) nounwind { define i8 @srai_i8(i8 %a) nounwind {
; RV32I-LABEL: srai_i8: ; RV32I-LABEL: srai_i8:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 29 ; RV32I-NEXT: srai a0, a0, 29
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: srai_i8:
; RV32B: # %bb.0:
; RV32B-NEXT: sext.b a0, a0
; RV32B-NEXT: srai a0, a0, 5
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: srai_i8: ; RV32ZBB-LABEL: srai_i8:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: sext.b a0, a0 ; RV32ZBB-NEXT: sext.b a0, a0
; RV32ZBB-NEXT: srai a0, a0, 5 ; RV32ZBB-NEXT: srai a0, a0, 5
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
; ;
; RV32ZBP-LABEL: srai_i8: ; RV32ZBP-LABEL: srai_i8:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: slli a0, a0, 24 ; RV32ZBP-NEXT: slli a0, a0, 24
; RV32ZBP-NEXT: srai a0, a0, 29 ; RV32ZBP-NEXT: srai a0, a0, 29
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%1 = ashr i8 %a, 5 %1 = ashr i8 %a, 5
ret i8 %1 ret i8 %1
} }
define i16 @srli_i16(i16 %a) nounwind { define i16 @srli_i16(i16 %a) nounwind {
; RV32I-LABEL: srli_i16: ; RV32I-LABEL: srli_i16:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srli a0, a0, 22 ; RV32I-NEXT: srli a0, a0, 22
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: srli_i16:
; RV32B: # %bb.0:
; RV32B-NEXT: zext.h a0, a0
; RV32B-NEXT: srli a0, a0, 6
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: srli_i16: ; RV32ZBB-LABEL: srli_i16:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: zext.h a0, a0 ; RV32ZBB-NEXT: zext.h a0, a0
; RV32ZBB-NEXT: srli a0, a0, 6 ; RV32ZBB-NEXT: srli a0, a0, 6
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
; ;
; RV32ZBP-LABEL: srli_i16: ; RV32ZBP-LABEL: srli_i16:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zext.h a0, a0 ; RV32ZBP-NEXT: zext.h a0, a0
; RV32ZBP-NEXT: srli a0, a0, 6 ; RV32ZBP-NEXT: srli a0, a0, 6
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%1 = lshr i16 %a, 6 %1 = lshr i16 %a, 6
ret i16 %1 ret i16 %1
} }
define i16 @srai_i16(i16 %a) nounwind { define i16 @srai_i16(i16 %a) nounwind {
; RV32I-LABEL: srai_i16: ; RV32I-LABEL: srai_i16:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srai a0, a0, 25 ; RV32I-NEXT: srai a0, a0, 25
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: srai_i16:
; RV32B: # %bb.0:
; RV32B-NEXT: sext.h a0, a0
; RV32B-NEXT: srai a0, a0, 9
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: srai_i16: ; RV32ZBB-LABEL: srai_i16:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: sext.h a0, a0 ; RV32ZBB-NEXT: sext.h a0, a0
; RV32ZBB-NEXT: srai a0, a0, 9 ; RV32ZBB-NEXT: srai a0, a0, 9
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
; ;
; RV32ZBP-LABEL: srai_i16: ; RV32ZBP-LABEL: srai_i16:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: slli a0, a0, 16 ; RV32ZBP-NEXT: slli a0, a0, 16
; RV32ZBP-NEXT: srai a0, a0, 25 ; RV32ZBP-NEXT: srai a0, a0, 25
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%1 = ashr i16 %a, 9 %1 = ashr i16 %a, 9
ret i16 %1 ret i16 %1
} }

llvm/test/CodeGen/RISCV/rv32zbb.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32B
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBB ; RUN: | FileCheck %s -check-prefix=RV32ZBB
declare i32 @llvm.ctlz.i32(i32, i1) declare i32 @llvm.ctlz.i32(i32, i1)
define i32 @ctlz_i32(i32 %a) nounwind { define i32 @ctlz_i32(i32 %a) nounwind {
; RV32I-LABEL: ctlz_i32: ; RV32I-LABEL: ctlz_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 34 Lines
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_2: ; RV32I-NEXT: .LBB0_2:
; RV32I-NEXT: addi a0, zero, 32 ; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: ctlz_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: clz a0, a0
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: ctlz_i32: ; RV32ZBB-LABEL: ctlz_i32:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: clz a0, a0 ; RV32ZBB-NEXT: clz a0, a0
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
%1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false) %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
ret i32 %1 ret i32 %1
} }
▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Lines
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: ctlz_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: clz a2, a1
; RV32B-NEXT: clz a0, a0
; RV32B-NEXT: addi a0, a0, 32
; RV32B-NEXT: cmov a0, a1, a2, a0
; RV32B-NEXT: mv a1, zero
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: ctlz_i64: ; RV32ZBB-LABEL: ctlz_i64:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: bnez a1, .LBB1_2 ; RV32ZBB-NEXT: bnez a1, .LBB1_2
; RV32ZBB-NEXT: # %bb.1: ; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: clz a0, a0 ; RV32ZBB-NEXT: clz a0, a0
; RV32ZBB-NEXT: addi a0, a0, 32 ; RV32ZBB-NEXT: addi a0, a0, 32
; RV32ZBB-NEXT: mv a1, zero ; RV32ZBB-NEXT: mv a1, zero
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
Show All 39 Lines
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB2_2: ; RV32I-NEXT: .LBB2_2:
; RV32I-NEXT: addi a0, zero, 32 ; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: cttz_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: ctz a0, a0
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: cttz_i32: ; RV32ZBB-LABEL: cttz_i32:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: ctz a0, a0 ; RV32ZBB-NEXT: ctz a0, a0
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
%1 = call i32 @llvm.cttz.i32(i32 %a, i1 false) %1 = call i32 @llvm.cttz.i32(i32 %a, i1 false)
ret i32 %1 ret i32 %1
} }
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: cttz_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: ctz a2, a0
; RV32B-NEXT: ctz a1, a1
; RV32B-NEXT: addi a1, a1, 32
; RV32B-NEXT: cmov a0, a0, a2, a1
; RV32B-NEXT: mv a1, zero
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: cttz_i64: ; RV32ZBB-LABEL: cttz_i64:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: bnez a0, .LBB3_2 ; RV32ZBB-NEXT: bnez a0, .LBB3_2
; RV32ZBB-NEXT: # %bb.1: ; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: ctz a0, a1 ; RV32ZBB-NEXT: ctz a0, a1
; RV32ZBB-NEXT: addi a0, a0, 32 ; RV32ZBB-NEXT: addi a0, a0, 32
; RV32ZBB-NEXT: mv a1, zero ; RV32ZBB-NEXT: mv a1, zero
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
Show All 31 Lines
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257 ; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3@plt ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: ctpop_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: cpop a0, a0
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: ctpop_i32: ; RV32ZBB-LABEL: ctpop_i32:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: cpop a0, a0 ; RV32ZBB-NEXT: cpop a0, a0
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
%1 = call i32 @llvm.ctpop.i32(i32 %a) %1 = call i32 @llvm.ctpop.i32(i32 %a)
ret i32 %1 ret i32 %1
} }
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: ctpop_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: cpop a1, a1
; RV32B-NEXT: cpop a0, a0
; RV32B-NEXT: add a0, a0, a1
; RV32B-NEXT: mv a1, zero
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: ctpop_i64: ; RV32ZBB-LABEL: ctpop_i64:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: cpop a1, a1 ; RV32ZBB-NEXT: cpop a1, a1
; RV32ZBB-NEXT: cpop a0, a0 ; RV32ZBB-NEXT: cpop a0, a0
; RV32ZBB-NEXT: add a0, a0, a1 ; RV32ZBB-NEXT: add a0, a0, a1
; RV32ZBB-NEXT: mv a1, zero ; RV32ZBB-NEXT: mv a1, zero
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
%1 = call i64 @llvm.ctpop.i64(i64 %a) %1 = call i64 @llvm.ctpop.i64(i64 %a)
ret i64 %1 ret i64 %1
} }
define i32 @sextb_i32(i32 %a) nounwind { define i32 @sextb_i32(i32 %a) nounwind {
; RV32I-LABEL: sextb_i32: ; RV32I-LABEL: sextb_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sextb_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: sext.b a0, a0
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: sextb_i32: ; RV32ZBB-LABEL: sextb_i32:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: sext.b a0, a0 ; RV32ZBB-NEXT: sext.b a0, a0
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
%shl = shl i32 %a, 24 %shl = shl i32 %a, 24
%shr = ashr exact i32 %shl, 24 %shr = ashr exact i32 %shl, 24
ret i32 %shr ret i32 %shr
} }
define i64 @sextb_i64(i64 %a) nounwind { define i64 @sextb_i64(i64 %a) nounwind {
; RV32I-LABEL: sextb_i64: ; RV32I-LABEL: sextb_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 24 ; RV32I-NEXT: slli a1, a0, 24
; RV32I-NEXT: srai a0, a1, 24 ; RV32I-NEXT: srai a0, a1, 24
; RV32I-NEXT: srai a1, a1, 31 ; RV32I-NEXT: srai a1, a1, 31
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sextb_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: sext.b a0, a0
; RV32B-NEXT: srai a1, a0, 31
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: sextb_i64: ; RV32ZBB-LABEL: sextb_i64:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: sext.b a0, a0 ; RV32ZBB-NEXT: sext.b a0, a0
; RV32ZBB-NEXT: srai a1, a0, 31 ; RV32ZBB-NEXT: srai a1, a0, 31
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
%shl = shl i64 %a, 56 %shl = shl i64 %a, 56
%shr = ashr exact i64 %shl, 56 %shr = ashr exact i64 %shl, 56
ret i64 %shr ret i64 %shr
} }
define i32 @sexth_i32(i32 %a) nounwind { define i32 @sexth_i32(i32 %a) nounwind {
; RV32I-LABEL: sexth_i32: ; RV32I-LABEL: sexth_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sexth_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: sext.h a0, a0
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: sexth_i32: ; RV32ZBB-LABEL: sexth_i32:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: sext.h a0, a0 ; RV32ZBB-NEXT: sext.h a0, a0
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
%shl = shl i32 %a, 16 %shl = shl i32 %a, 16
%shr = ashr exact i32 %shl, 16 %shr = ashr exact i32 %shl, 16
ret i32 %shr ret i32 %shr
} }
define i64 @sexth_i64(i64 %a) nounwind { define i64 @sexth_i64(i64 %a) nounwind {
; RV32I-LABEL: sexth_i64: ; RV32I-LABEL: sexth_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 16 ; RV32I-NEXT: slli a1, a0, 16
; RV32I-NEXT: srai a0, a1, 16 ; RV32I-NEXT: srai a0, a1, 16
; RV32I-NEXT: srai a1, a1, 31 ; RV32I-NEXT: srai a1, a1, 31
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sexth_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: sext.h a0, a0
; RV32B-NEXT: srai a1, a0, 31
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: sexth_i64: ; RV32ZBB-LABEL: sexth_i64:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: sext.h a0, a0 ; RV32ZBB-NEXT: sext.h a0, a0
; RV32ZBB-NEXT: srai a1, a0, 31 ; RV32ZBB-NEXT: srai a1, a0, 31
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
%shl = shl i64 %a, 48 %shl = shl i64 %a, 48
%shr = ashr exact i64 %shl, 48 %shr = ashr exact i64 %shl, 48
ret i64 %shr ret i64 %shr
} }
define i32 @min_i32(i32 %a, i32 %b) nounwind { define i32 @min_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: min_i32: ; RV32I-LABEL: min_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: blt a0, a1, .LBB10_2 ; RV32I-NEXT: blt a0, a1, .LBB10_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB10_2: ; RV32I-NEXT: .LBB10_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: min_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: min a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: min_i32: ; RV32ZBB-LABEL: min_i32:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: min a0, a0, a1 ; RV32ZBB-NEXT: min a0, a0, a1
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
%cmp = icmp slt i32 %a, %b %cmp = icmp slt i32 %a, %b
%cond = select i1 %cmp, i32 %a, i32 %b %cond = select i1 %cmp, i32 %a, i32 %b
ret i32 %cond ret i32 %cond
} }
Show All 15 Lines
; RV32I-NEXT: sltu a4, a0, a2 ; RV32I-NEXT: sltu a4, a0, a2
; RV32I-NEXT: bnez a4, .LBB11_4 ; RV32I-NEXT: bnez a4, .LBB11_4
; RV32I-NEXT: .LBB11_3: ; RV32I-NEXT: .LBB11_3:
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: .LBB11_4: ; RV32I-NEXT: .LBB11_4:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: min_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: slt a4, a1, a3
; RV32B-NEXT: cmov a4, a4, a0, a2
; RV32B-NEXT: minu a0, a0, a2
; RV32B-NEXT: xor a2, a1, a3
; RV32B-NEXT: cmov a0, a2, a4, a0
; RV32B-NEXT: min a1, a1, a3
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: min_i64: ; RV32ZBB-LABEL: min_i64:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: mv a4, a0 ; RV32ZBB-NEXT: mv a4, a0
; RV32ZBB-NEXT: bge a1, a3, .LBB11_3 ; RV32ZBB-NEXT: bge a1, a3, .LBB11_3
; RV32ZBB-NEXT: # %bb.1: ; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: beq a1, a3, .LBB11_4 ; RV32ZBB-NEXT: beq a1, a3, .LBB11_4
; RV32ZBB-NEXT: .LBB11_2: ; RV32ZBB-NEXT: .LBB11_2:
; RV32ZBB-NEXT: min a1, a1, a3 ; RV32ZBB-NEXT: min a1, a1, a3
Show All 14 Lines
; RV32I-LABEL: max_i32: ; RV32I-LABEL: max_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: blt a1, a0, .LBB12_2 ; RV32I-NEXT: blt a1, a0, .LBB12_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB12_2: ; RV32I-NEXT: .LBB12_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: max_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: max a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: max_i32: ; RV32ZBB-LABEL: max_i32:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: max a0, a0, a1 ; RV32ZBB-NEXT: max a0, a0, a1
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
%cmp = icmp sgt i32 %a, %b %cmp = icmp sgt i32 %a, %b
%cond = select i1 %cmp, i32 %a, i32 %b %cond = select i1 %cmp, i32 %a, i32 %b
ret i32 %cond ret i32 %cond
} }
Show All 15 Lines
; RV32I-NEXT: sltu a4, a2, a0 ; RV32I-NEXT: sltu a4, a2, a0
; RV32I-NEXT: bnez a4, .LBB13_4 ; RV32I-NEXT: bnez a4, .LBB13_4
; RV32I-NEXT: .LBB13_3: ; RV32I-NEXT: .LBB13_3:
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: .LBB13_4: ; RV32I-NEXT: .LBB13_4:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: max_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: slt a4, a3, a1
; RV32B-NEXT: cmov a4, a4, a0, a2
; RV32B-NEXT: maxu a0, a0, a2
; RV32B-NEXT: xor a2, a1, a3
; RV32B-NEXT: cmov a0, a2, a4, a0
; RV32B-NEXT: max a1, a1, a3
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: max_i64: ; RV32ZBB-LABEL: max_i64:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: mv a4, a0 ; RV32ZBB-NEXT: mv a4, a0
; RV32ZBB-NEXT: bge a3, a1, .LBB13_3 ; RV32ZBB-NEXT: bge a3, a1, .LBB13_3
; RV32ZBB-NEXT: # %bb.1: ; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: beq a1, a3, .LBB13_4 ; RV32ZBB-NEXT: beq a1, a3, .LBB13_4
; RV32ZBB-NEXT: .LBB13_2: ; RV32ZBB-NEXT: .LBB13_2:
; RV32ZBB-NEXT: max a1, a1, a3 ; RV32ZBB-NEXT: max a1, a1, a3
Show All 14 Lines
; RV32I-LABEL: minu_i32: ; RV32I-LABEL: minu_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: bltu a0, a1, .LBB14_2 ; RV32I-NEXT: bltu a0, a1, .LBB14_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB14_2: ; RV32I-NEXT: .LBB14_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: minu_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: minu a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: minu_i32: ; RV32ZBB-LABEL: minu_i32:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: minu a0, a0, a1 ; RV32ZBB-NEXT: minu a0, a0, a1
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
%cmp = icmp ult i32 %a, %b %cmp = icmp ult i32 %a, %b
%cond = select i1 %cmp, i32 %a, i32 %b %cond = select i1 %cmp, i32 %a, i32 %b
ret i32 %cond ret i32 %cond
} }
Show All 15 Lines
; RV32I-NEXT: sltu a4, a0, a2 ; RV32I-NEXT: sltu a4, a0, a2
; RV32I-NEXT: bnez a4, .LBB15_4 ; RV32I-NEXT: bnez a4, .LBB15_4
; RV32I-NEXT: .LBB15_3: ; RV32I-NEXT: .LBB15_3:
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: .LBB15_4: ; RV32I-NEXT: .LBB15_4:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: minu_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: sltu a4, a1, a3
; RV32B-NEXT: cmov a4, a4, a0, a2
; RV32B-NEXT: minu a0, a0, a2
; RV32B-NEXT: xor a2, a1, a3
; RV32B-NEXT: cmov a0, a2, a4, a0
; RV32B-NEXT: minu a1, a1, a3
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: minu_i64: ; RV32ZBB-LABEL: minu_i64:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: mv a4, a0 ; RV32ZBB-NEXT: mv a4, a0
; RV32ZBB-NEXT: bgeu a1, a3, .LBB15_3 ; RV32ZBB-NEXT: bgeu a1, a3, .LBB15_3
; RV32ZBB-NEXT: # %bb.1: ; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: beq a1, a3, .LBB15_4 ; RV32ZBB-NEXT: beq a1, a3, .LBB15_4
; RV32ZBB-NEXT: .LBB15_2: ; RV32ZBB-NEXT: .LBB15_2:
; RV32ZBB-NEXT: minu a1, a1, a3 ; RV32ZBB-NEXT: minu a1, a1, a3
Show All 14 Lines
; RV32I-LABEL: maxu_i32: ; RV32I-LABEL: maxu_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: bltu a1, a0, .LBB16_2 ; RV32I-NEXT: bltu a1, a0, .LBB16_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB16_2: ; RV32I-NEXT: .LBB16_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: maxu_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: maxu a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: maxu_i32: ; RV32ZBB-LABEL: maxu_i32:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: maxu a0, a0, a1 ; RV32ZBB-NEXT: maxu a0, a0, a1
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
%cmp = icmp ugt i32 %a, %b %cmp = icmp ugt i32 %a, %b
%cond = select i1 %cmp, i32 %a, i32 %b %cond = select i1 %cmp, i32 %a, i32 %b
ret i32 %cond ret i32 %cond
} }
Show All 15 Lines
; RV32I-NEXT: sltu a4, a2, a0 ; RV32I-NEXT: sltu a4, a2, a0
; RV32I-NEXT: bnez a4, .LBB17_4 ; RV32I-NEXT: bnez a4, .LBB17_4
; RV32I-NEXT: .LBB17_3: ; RV32I-NEXT: .LBB17_3:
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: .LBB17_4: ; RV32I-NEXT: .LBB17_4:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: maxu_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: sltu a4, a3, a1
; RV32B-NEXT: cmov a4, a4, a0, a2
; RV32B-NEXT: maxu a0, a0, a2
; RV32B-NEXT: xor a2, a1, a3
; RV32B-NEXT: cmov a0, a2, a4, a0
; RV32B-NEXT: maxu a1, a1, a3
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: maxu_i64: ; RV32ZBB-LABEL: maxu_i64:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: mv a4, a0 ; RV32ZBB-NEXT: mv a4, a0
; RV32ZBB-NEXT: bgeu a3, a1, .LBB17_3 ; RV32ZBB-NEXT: bgeu a3, a1, .LBB17_3
; RV32ZBB-NEXT: # %bb.1: ; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: beq a1, a3, .LBB17_4 ; RV32ZBB-NEXT: beq a1, a3, .LBB17_4
; RV32ZBB-NEXT: .LBB17_2: ; RV32ZBB-NEXT: .LBB17_2:
; RV32ZBB-NEXT: maxu a1, a1, a3 ; RV32ZBB-NEXT: maxu a1, a1, a3
Show All 15 Lines
define i32 @abs_i32(i32 %x) { define i32 @abs_i32(i32 %x) {
; RV32I-LABEL: abs_i32: ; RV32I-LABEL: abs_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srai a1, a0, 31 ; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: abs_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: neg a1, a0
; RV32B-NEXT: max a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: abs_i32: ; RV32ZBB-LABEL: abs_i32:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: neg a1, a0 ; RV32ZBB-NEXT: neg a1, a0
; RV32ZBB-NEXT: max a0, a0, a1 ; RV32ZBB-NEXT: max a0, a0, a1
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true) %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
ret i32 %abs ret i32 %abs
} }
declare i64 @llvm.abs.i64(i64, i1 immarg) declare i64 @llvm.abs.i64(i64, i1 immarg)
define i64 @abs_i64(i64 %x) { define i64 @abs_i64(i64 %x) {
; RV32I-LABEL: abs_i64: ; RV32I-LABEL: abs_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: bgez a1, .LBB19_2 ; RV32I-NEXT: bgez a1, .LBB19_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: snez a2, a0 ; RV32I-NEXT: snez a2, a0
; RV32I-NEXT: neg a0, a0 ; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: add a1, a1, a2 ; RV32I-NEXT: add a1, a1, a2
; RV32I-NEXT: neg a1, a1 ; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: .LBB19_2: ; RV32I-NEXT: .LBB19_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: abs_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: neg a2, a0
; RV32B-NEXT: slti a3, a1, 0
; RV32B-NEXT: cmov a2, a3, a2, a0
; RV32B-NEXT: snez a0, a0
; RV32B-NEXT: add a0, a1, a0
; RV32B-NEXT: neg a0, a0
; RV32B-NEXT: cmov a1, a3, a0, a1
; RV32B-NEXT: mv a0, a2
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: abs_i64: ; RV32ZBB-LABEL: abs_i64:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: bgez a1, .LBB19_2 ; RV32ZBB-NEXT: bgez a1, .LBB19_2
; RV32ZBB-NEXT: # %bb.1: ; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: snez a2, a0 ; RV32ZBB-NEXT: snez a2, a0
; RV32ZBB-NEXT: neg a0, a0 ; RV32ZBB-NEXT: neg a0, a0
; RV32ZBB-NEXT: add a1, a1, a2 ; RV32ZBB-NEXT: add a1, a1, a2
; RV32ZBB-NEXT: neg a1, a1 ; RV32ZBB-NEXT: neg a1, a1
; RV32ZBB-NEXT: .LBB19_2: ; RV32ZBB-NEXT: .LBB19_2:
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
%abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
ret i64 %abs ret i64 %abs
} }
define i32 @zexth_i32(i32 %a) nounwind { define i32 @zexth_i32(i32 %a) nounwind {
; RV32I-LABEL: zexth_i32: ; RV32I-LABEL: zexth_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: zexth_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: zext.h a0, a0
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: zexth_i32: ; RV32ZBB-LABEL: zexth_i32:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: zext.h a0, a0 ; RV32ZBB-NEXT: zext.h a0, a0
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
%and = and i32 %a, 65535 %and = and i32 %a, 65535
ret i32 %and ret i32 %and
} }
define i64 @zexth_i64(i64 %a) nounwind { define i64 @zexth_i64(i64 %a) nounwind {
; RV32I-LABEL: zexth_i64: ; RV32I-LABEL: zexth_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: zexth_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: zext.h a0, a0
; RV32B-NEXT: mv a1, zero
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: zexth_i64: ; RV32ZBB-LABEL: zexth_i64:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: zext.h a0, a0 ; RV32ZBB-NEXT: zext.h a0, a0
; RV32ZBB-NEXT: mv a1, zero ; RV32ZBB-NEXT: mv a1, zero
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
%and = and i64 %a, 65535 %and = and i64 %a, 65535
ret i64 %and ret i64 %and
} }
Show All 12 Lines
; RV32I-NEXT: slli a2, a0, 8 ; RV32I-NEXT: slli a2, a0, 8
; RV32I-NEXT: lui a3, 4080 ; RV32I-NEXT: lui a3, 4080
; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: bswap_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: rev8 a0, a0
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: bswap_i32: ; RV32ZBB-LABEL: bswap_i32:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: rev8 a0, a0 ; RV32ZBB-NEXT: rev8 a0, a0
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
%1 = tail call i32 @llvm.bswap.i32(i32 %a) %1 = tail call i32 @llvm.bswap.i32(i32 %a)
ret i32 %1 ret i32 %1
} }
Show All 21 Lines
; RV32I-NEXT: slli a3, a0, 8 ; RV32I-NEXT: slli a3, a0, 8
; RV32I-NEXT: and a3, a3, a5 ; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a1, a0, a1 ; RV32I-NEXT: or a1, a0, a1
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: bswap_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: rev8 a2, a1
; RV32B-NEXT: rev8 a1, a0
; RV32B-NEXT: mv a0, a2
; RV32B-NEXT: ret
;
; RV32ZBB-LABEL: bswap_i64: ; RV32ZBB-LABEL: bswap_i64:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: rev8 a2, a1 ; RV32ZBB-NEXT: rev8 a2, a1
; RV32ZBB-NEXT: rev8 a1, a0 ; RV32ZBB-NEXT: rev8 a1, a0
; RV32ZBB-NEXT: mv a0, a2 ; RV32ZBB-NEXT: mv a0, a2
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
%1 = call i64 @llvm.bswap.i64(i64 %a) %1 = call i64 @llvm.bswap.i64(i64 %a)
ret i64 %1 ret i64 %1
} }

llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32B
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbc -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbc -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBC ; RUN: | FileCheck %s -check-prefix=RV32ZBC
declare i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b) declare i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
define i32 @clmul32(i32 %a, i32 %b) nounwind { define i32 @clmul32(i32 %a, i32 %b) nounwind {
; RV32B-LABEL: clmul32:
; RV32B: # %bb.0:
; RV32B-NEXT: clmul a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBC-LABEL: clmul32: ; RV32ZBC-LABEL: clmul32:
; RV32ZBC: # %bb.0: ; RV32ZBC: # %bb.0:
; RV32ZBC-NEXT: clmul a0, a0, a1 ; RV32ZBC-NEXT: clmul a0, a0, a1
; RV32ZBC-NEXT: ret ; RV32ZBC-NEXT: ret
%tmp = call i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
ret i32 %tmp ret i32 %tmp
} }
declare i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b) declare i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
define i32 @clmul32h(i32 %a, i32 %b) nounwind { define i32 @clmul32h(i32 %a, i32 %b) nounwind {
; RV32B-LABEL: clmul32h:
; RV32B: # %bb.0:
; RV32B-NEXT: clmulh a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBC-LABEL: clmul32h: ; RV32ZBC-LABEL: clmul32h:
; RV32ZBC: # %bb.0: ; RV32ZBC: # %bb.0:
; RV32ZBC-NEXT: clmulh a0, a0, a1 ; RV32ZBC-NEXT: clmulh a0, a0, a1
; RV32ZBC-NEXT: ret ; RV32ZBC-NEXT: ret
%tmp = call i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
ret i32 %tmp ret i32 %tmp
} }
declare i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b) declare i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b)
define i32 @clmul32r(i32 %a, i32 %b) nounwind { define i32 @clmul32r(i32 %a, i32 %b) nounwind {
; RV32B-LABEL: clmul32r:
; RV32B: # %bb.0:
; RV32B-NEXT: clmulr a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBC-LABEL: clmul32r: ; RV32ZBC-LABEL: clmul32r:
; RV32ZBC: # %bb.0: ; RV32ZBC: # %bb.0:
; RV32ZBC-NEXT: clmulr a0, a0, a1 ; RV32ZBC-NEXT: clmulr a0, a0, a1
; RV32ZBC-NEXT: ret ; RV32ZBC-NEXT: ret
%tmp = call i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b)
ret i32 %tmp ret i32 %tmp
} }

llvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32B
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBE ; RUN: | FileCheck %s -check-prefix=RV32ZBE
declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b) declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
define i32 @bcompress32(i32 %a, i32 %b) nounwind { define i32 @bcompress32(i32 %a, i32 %b) nounwind {
; RV32B-LABEL: bcompress32:
; RV32B: # %bb.0:
; RV32B-NEXT: bcompress a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBE-LABEL: bcompress32: ; RV32ZBE-LABEL: bcompress32:
; RV32ZBE: # %bb.0: ; RV32ZBE: # %bb.0:
; RV32ZBE-NEXT: bcompress a0, a0, a1 ; RV32ZBE-NEXT: bcompress a0, a0, a1
; RV32ZBE-NEXT: ret ; RV32ZBE-NEXT: ret
%tmp = call i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
ret i32 %tmp ret i32 %tmp
} }
declare i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b) declare i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
define i32 @bdecompress32(i32 %a, i32 %b) nounwind { define i32 @bdecompress32(i32 %a, i32 %b) nounwind {
; RV32B-LABEL: bdecompress32:
; RV32B: # %bb.0:
; RV32B-NEXT: bdecompress a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBE-LABEL: bdecompress32: ; RV32ZBE-LABEL: bdecompress32:
; RV32ZBE: # %bb.0: ; RV32ZBE: # %bb.0:
; RV32ZBE-NEXT: bdecompress a0, a0, a1 ; RV32ZBE-NEXT: bdecompress a0, a0, a1
; RV32ZBE-NEXT: ret ; RV32ZBE-NEXT: ret
%tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
ret i32 %tmp ret i32 %tmp
} }

llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32B
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBP ; RUN: | FileCheck %s -check-prefix=RV32ZBP
declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b) declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
define i32 @grev32(i32 %a, i32 %b) nounwind { define i32 @grev32(i32 %a, i32 %b) nounwind {
; RV32B-LABEL: grev32:
; RV32B: # %bb.0:
; RV32B-NEXT: grev a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev32: ; RV32ZBP-LABEL: grev32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: grev a0, a0, a1 ; RV32ZBP-NEXT: grev a0, a0, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
ret i32 %tmp ret i32 %tmp
} }
define i32 @grev32_demandedbits(i32 %a, i32 %b) nounwind { define i32 @grev32_demandedbits(i32 %a, i32 %b) nounwind {
; RV32B-LABEL: grev32_demandedbits:
; RV32B: # %bb.0:
; RV32B-NEXT: grev a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev32_demandedbits: ; RV32ZBP-LABEL: grev32_demandedbits:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: grev a0, a0, a1 ; RV32ZBP-NEXT: grev a0, a0, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%c = and i32 %b, 31 %c = and i32 %b, 31
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
ret i32 %tmp ret i32 %tmp
} }
define i32 @grevi32(i32 %a) nounwind { define i32 @grevi32(i32 %a) nounwind {
; RV32B-LABEL: grevi32:
; RV32B: # %bb.0:
; RV32B-NEXT: grevi a0, a0, 13
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grevi32: ; RV32ZBP-LABEL: grevi32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: grevi a0, a0, 13 ; RV32ZBP-NEXT: grevi a0, a0, 13
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 13) %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 13)
ret i32 %tmp ret i32 %tmp
} }
declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b) declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
define i32 @gorc32(i32 %a, i32 %b) nounwind { define i32 @gorc32(i32 %a, i32 %b) nounwind {
; RV32B-LABEL: gorc32:
; RV32B: # %bb.0:
; RV32B-NEXT: gorc a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc32: ; RV32ZBP-LABEL: gorc32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: gorc a0, a0, a1 ; RV32ZBP-NEXT: gorc a0, a0, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
ret i32 %tmp ret i32 %tmp
} }
define i32 @gorc32_demandedbits(i32 %a, i32 %b) nounwind { define i32 @gorc32_demandedbits(i32 %a, i32 %b) nounwind {
; RV32B-LABEL: gorc32_demandedbits:
; RV32B: # %bb.0:
; RV32B-NEXT: gorc a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc32_demandedbits: ; RV32ZBP-LABEL: gorc32_demandedbits:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: gorc a0, a0, a1 ; RV32ZBP-NEXT: gorc a0, a0, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%c = and i32 %b, 31 %c = and i32 %b, 31
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
ret i32 %tmp ret i32 %tmp
} }
define i32 @gorci32(i32 %a) nounwind { define i32 @gorci32(i32 %a) nounwind {
; RV32B-LABEL: gorci32:
; RV32B: # %bb.0:
; RV32B-NEXT: gorci a0, a0, 13
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorci32: ; RV32ZBP-LABEL: gorci32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: gorci a0, a0, 13 ; RV32ZBP-NEXT: gorci a0, a0, 13
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 13) %tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 13)
ret i32 %tmp ret i32 %tmp
} }
declare i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b) declare i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
define i32 @shfl32(i32 %a, i32 %b) nounwind { define i32 @shfl32(i32 %a, i32 %b) nounwind {
; RV32B-LABEL: shfl32:
; RV32B: # %bb.0:
; RV32B-NEXT: shfl a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: shfl32: ; RV32ZBP-LABEL: shfl32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: shfl a0, a0, a1 ; RV32ZBP-NEXT: shfl a0, a0, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
ret i32 %tmp ret i32 %tmp
} }
define i32 @shfl32_demandedbits(i32 %a, i32 %b) nounwind { define i32 @shfl32_demandedbits(i32 %a, i32 %b) nounwind {
; RV32B-LABEL: shfl32_demandedbits:
; RV32B: # %bb.0:
; RV32B-NEXT: shfl a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: shfl32_demandedbits: ; RV32ZBP-LABEL: shfl32_demandedbits:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: shfl a0, a0, a1 ; RV32ZBP-NEXT: shfl a0, a0, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%c = and i32 %b, 15 %c = and i32 %b, 15
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 %c) %tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 %c)
ret i32 %tmp ret i32 %tmp
} }
define i32 @shfli32(i32 %a) nounwind { define i32 @shfli32(i32 %a) nounwind {
; RV32B-LABEL: shfli32:
; RV32B: # %bb.0:
; RV32B-NEXT: shfli a0, a0, 13
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: shfli32: ; RV32ZBP-LABEL: shfli32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: shfli a0, a0, 13 ; RV32ZBP-NEXT: shfli a0, a0, 13
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 13) %tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 13)
ret i32 %tmp ret i32 %tmp
} }
declare i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b) declare i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b)
define i32 @unshfl32(i32 %a, i32 %b) nounwind { define i32 @unshfl32(i32 %a, i32 %b) nounwind {
; RV32B-LABEL: unshfl32:
; RV32B: # %bb.0:
; RV32B-NEXT: unshfl a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: unshfl32: ; RV32ZBP-LABEL: unshfl32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: unshfl a0, a0, a1 ; RV32ZBP-NEXT: unshfl a0, a0, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b)
ret i32 %tmp ret i32 %tmp
} }
define i32 @unshfl32_demandedbits(i32 %a, i32 %b) nounwind { define i32 @unshfl32_demandedbits(i32 %a, i32 %b) nounwind {
; RV32B-LABEL: unshfl32_demandedbits:
; RV32B: # %bb.0:
; RV32B-NEXT: unshfl a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: unshfl32_demandedbits: ; RV32ZBP-LABEL: unshfl32_demandedbits:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: unshfl a0, a0, a1 ; RV32ZBP-NEXT: unshfl a0, a0, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%c = and i32 %b, 15 %c = and i32 %b, 15
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %c) %tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %c)
ret i32 %tmp ret i32 %tmp
} }
define i32 @unshfli32(i32 %a) nounwind { define i32 @unshfli32(i32 %a) nounwind {
; RV32B-LABEL: unshfli32:
; RV32B: # %bb.0:
; RV32B-NEXT: unshfli a0, a0, 13
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: unshfli32: ; RV32ZBP-LABEL: unshfli32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: unshfli a0, a0, 13 ; RV32ZBP-NEXT: unshfli a0, a0, 13
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 13) %tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 13)
ret i32 %tmp ret i32 %tmp
} }
declare i32 @llvm.riscv.xperm.n.i32(i32 %a, i32 %b) declare i32 @llvm.riscv.xperm.n.i32(i32 %a, i32 %b)
define i32 @xpermn32(i32 %a, i32 %b) nounwind { define i32 @xpermn32(i32 %a, i32 %b) nounwind {
; RV32B-LABEL: xpermn32:
; RV32B: # %bb.0:
; RV32B-NEXT: xperm.n a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: xpermn32: ; RV32ZBP-LABEL: xpermn32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: xperm.n a0, a0, a1 ; RV32ZBP-NEXT: xperm.n a0, a0, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.xperm.n.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.xperm.n.i32(i32 %a, i32 %b)
ret i32 %tmp ret i32 %tmp
} }
declare i32 @llvm.riscv.xperm.b.i32(i32 %a, i32 %b) declare i32 @llvm.riscv.xperm.b.i32(i32 %a, i32 %b)
define i32 @xpermb32(i32 %a, i32 %b) nounwind { define i32 @xpermb32(i32 %a, i32 %b) nounwind {
; RV32B-LABEL: xpermb32:
; RV32B: # %bb.0:
; RV32B-NEXT: xperm.b a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: xpermb32: ; RV32ZBP-LABEL: xpermb32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: xperm.b a0, a0, a1 ; RV32ZBP-NEXT: xperm.b a0, a0, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.xperm.b.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.xperm.b.i32(i32 %a, i32 %b)
ret i32 %tmp ret i32 %tmp
} }
declare i32 @llvm.riscv.xperm.h.i32(i32 %a, i32 %b) declare i32 @llvm.riscv.xperm.h.i32(i32 %a, i32 %b)
define i32 @xpermh32(i32 %a, i32 %b) nounwind { define i32 @xpermh32(i32 %a, i32 %b) nounwind {
; RV32B-LABEL: xpermh32:
; RV32B: # %bb.0:
; RV32B-NEXT: xperm.h a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: xpermh32: ; RV32ZBP-LABEL: xpermh32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: xperm.h a0, a0, a1 ; RV32ZBP-NEXT: xperm.h a0, a0, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.xperm.h.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.xperm.h.i32(i32 %a, i32 %b)
ret i32 %tmp ret i32 %tmp
} }

llvm/test/CodeGen/RISCV/rv32zbp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32B
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBP ; RUN: | FileCheck %s -check-prefix=RV32ZBP
define i32 @gorc1_i32(i32 %a) nounwind { define i32 @gorc1_i32(i32 %a) nounwind {
; RV32I-LABEL: gorc1_i32: ; RV32I-LABEL: gorc1_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 1 ; RV32I-NEXT: slli a1, a0, 1
; RV32I-NEXT: lui a2, 699051 ; RV32I-NEXT: lui a2, 699051
; RV32I-NEXT: addi a2, a2, -1366 ; RV32I-NEXT: addi a2, a2, -1366
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a2, a0, 1 ; RV32I-NEXT: srli a2, a0, 1
; RV32I-NEXT: lui a3, 349525 ; RV32I-NEXT: lui a3, 349525
; RV32I-NEXT: addi a3, a3, 1365 ; RV32I-NEXT: addi a3, a3, 1365
; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc1_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: orc.p a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc1_i32: ; RV32ZBP-LABEL: gorc1_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc.p a0, a0 ; RV32ZBP-NEXT: orc.p a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i32 %a, 1 %and = shl i32 %a, 1
%shl = and i32 %and, -1431655766 %shl = and i32 %and, -1431655766
%and1 = lshr i32 %a, 1 %and1 = lshr i32 %a, 1
%shr = and i32 %and1, 1431655765 %shr = and i32 %and1, 1431655765
Show All 18 Lines
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc1_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: orc.p a0, a0
; RV32B-NEXT: orc.p a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc1_i64: ; RV32ZBP-LABEL: gorc1_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc.p a0, a0 ; RV32ZBP-NEXT: orc.p a0, a0
; RV32ZBP-NEXT: orc.p a1, a1 ; RV32ZBP-NEXT: orc.p a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i64 %a, 1 %and = shl i64 %a, 1
%shl = and i64 %and, -6148914691236517206 %shl = and i64 %and, -6148914691236517206
%and1 = lshr i64 %a, 1 %and1 = lshr i64 %a, 1
Show All 13 Lines
; RV32I-NEXT: srli a2, a0, 2 ; RV32I-NEXT: srli a2, a0, 2
; RV32I-NEXT: lui a3, 209715 ; RV32I-NEXT: lui a3, 209715
; RV32I-NEXT: addi a3, a3, 819 ; RV32I-NEXT: addi a3, a3, 819
; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc2_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: orc2.n a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc2_i32: ; RV32ZBP-LABEL: gorc2_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc2.n a0, a0 ; RV32ZBP-NEXT: orc2.n a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i32 %a, 2 %and = shl i32 %a, 2
%shl = and i32 %and, -858993460 %shl = and i32 %and, -858993460
%and1 = lshr i32 %a, 2 %and1 = lshr i32 %a, 2
%shr = and i32 %and1, 858993459 %shr = and i32 %and1, 858993459
Show All 18 Lines
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc2_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: orc2.n a0, a0
; RV32B-NEXT: orc2.n a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc2_i64: ; RV32ZBP-LABEL: gorc2_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc2.n a0, a0 ; RV32ZBP-NEXT: orc2.n a0, a0
; RV32ZBP-NEXT: orc2.n a1, a1 ; RV32ZBP-NEXT: orc2.n a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i64 %a, 2 %and = shl i64 %a, 2
%shl = and i64 %and, -3689348814741910324 %shl = and i64 %and, -3689348814741910324
%and1 = lshr i64 %a, 2 %and1 = lshr i64 %a, 2
Show All 23 Lines
; RV32I-NEXT: srli a2, a0, 2 ; RV32I-NEXT: srli a2, a0, 2
; RV32I-NEXT: lui a3, 209715 ; RV32I-NEXT: lui a3, 209715
; RV32I-NEXT: addi a3, a3, 819 ; RV32I-NEXT: addi a3, a3, 819
; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc3_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: orc.n a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc3_i32: ; RV32ZBP-LABEL: gorc3_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc.n a0, a0 ; RV32ZBP-NEXT: orc.n a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i32 %a, 1 %and1 = shl i32 %a, 1
%shl1 = and i32 %and1, -1431655766 %shl1 = and i32 %and1, -1431655766
%and1b = lshr i32 %a, 1 %and1b = lshr i32 %a, 1
%shr1 = and i32 %and1b, 1431655765 %shr1 = and i32 %and1b, 1431655765
Show All 40 Lines
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc3_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: orc.n a0, a0
; RV32B-NEXT: orc.n a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc3_i64: ; RV32ZBP-LABEL: gorc3_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc.n a0, a0 ; RV32ZBP-NEXT: orc.n a0, a0
; RV32ZBP-NEXT: orc.n a1, a1 ; RV32ZBP-NEXT: orc.n a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
%shl1 = and i64 %and1, -6148914691236517206 %shl1 = and i64 %and1, -6148914691236517206
%and1b = lshr i64 %a, 1 %and1b = lshr i64 %a, 1
Show All 19 Lines
; RV32I-NEXT: srli a2, a0, 4 ; RV32I-NEXT: srli a2, a0, 4
; RV32I-NEXT: lui a3, 61681 ; RV32I-NEXT: lui a3, 61681
; RV32I-NEXT: addi a3, a3, -241 ; RV32I-NEXT: addi a3, a3, -241
; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc4_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: orc4.b a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc4_i32: ; RV32ZBP-LABEL: gorc4_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc4.b a0, a0 ; RV32ZBP-NEXT: orc4.b a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i32 %a, 4 %and = shl i32 %a, 4
%shl = and i32 %and, -252645136 %shl = and i32 %and, -252645136
%and1 = lshr i32 %a, 4 %and1 = lshr i32 %a, 4
%shr = and i32 %and1, 252645135 %shr = and i32 %and1, 252645135
Show All 18 Lines
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc4_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: orc4.b a0, a0
; RV32B-NEXT: orc4.b a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc4_i64: ; RV32ZBP-LABEL: gorc4_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc4.b a0, a0 ; RV32ZBP-NEXT: orc4.b a0, a0
; RV32ZBP-NEXT: orc4.b a1, a1 ; RV32ZBP-NEXT: orc4.b a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i64 %a, 4 %and = shl i64 %a, 4
%shl = and i64 %and, -1085102592571150096 %shl = and i64 %and, -1085102592571150096
%and1 = lshr i64 %a, 4 %and1 = lshr i64 %a, 4
Show All 23 Lines
; RV32I-NEXT: srli a2, a0, 4 ; RV32I-NEXT: srli a2, a0, 4
; RV32I-NEXT: lui a3, 61681 ; RV32I-NEXT: lui a3, 61681
; RV32I-NEXT: addi a3, a3, -241 ; RV32I-NEXT: addi a3, a3, -241
; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc5_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: gorci a0, a0, 5
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc5_i32: ; RV32ZBP-LABEL: gorc5_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: gorci a0, a0, 5 ; RV32ZBP-NEXT: gorci a0, a0, 5
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i32 %a, 1 %and1 = shl i32 %a, 1
%shl1 = and i32 %and1, -1431655766 %shl1 = and i32 %and1, -1431655766
%and1b = lshr i32 %a, 1 %and1b = lshr i32 %a, 1
%shr1 = and i32 %and1b, 1431655765 %shr1 = and i32 %and1b, 1431655765
Show All 40 Lines
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc5_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: gorci a0, a0, 5
; RV32B-NEXT: gorci a1, a1, 5
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc5_i64: ; RV32ZBP-LABEL: gorc5_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: gorci a0, a0, 5 ; RV32ZBP-NEXT: gorci a0, a0, 5
; RV32ZBP-NEXT: gorci a1, a1, 5 ; RV32ZBP-NEXT: gorci a1, a1, 5
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
%shl1 = and i64 %and1, -6148914691236517206 %shl1 = and i64 %and1, -6148914691236517206
%and1b = lshr i64 %a, 1 %and1b = lshr i64 %a, 1
Show All 29 Lines
; RV32I-NEXT: srli a2, a0, 4 ; RV32I-NEXT: srli a2, a0, 4
; RV32I-NEXT: lui a3, 61681 ; RV32I-NEXT: lui a3, 61681
; RV32I-NEXT: addi a3, a3, -241 ; RV32I-NEXT: addi a3, a3, -241
; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc6_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: orc2.b a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc6_i32: ; RV32ZBP-LABEL: gorc6_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc2.b a0, a0 ; RV32ZBP-NEXT: orc2.b a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i32 %a, 2 %and1 = shl i32 %a, 2
%shl1 = and i32 %and1, -858993460 %shl1 = and i32 %and1, -858993460
%and1b = lshr i32 %a, 2 %and1b = lshr i32 %a, 2
%shr1 = and i32 %and1b, 858993459 %shr1 = and i32 %and1b, 858993459
Show All 40 Lines
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc6_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: orc2.b a0, a0
; RV32B-NEXT: orc2.b a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc6_i64: ; RV32ZBP-LABEL: gorc6_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc2.b a0, a0 ; RV32ZBP-NEXT: orc2.b a0, a0
; RV32ZBP-NEXT: orc2.b a1, a1 ; RV32ZBP-NEXT: orc2.b a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 2 %and1 = shl i64 %a, 2
%shl1 = and i64 %and1, -3689348814741910324 %shl1 = and i64 %and1, -3689348814741910324
%and1b = lshr i64 %a, 2 %and1b = lshr i64 %a, 2
Show All 39 Lines
; RV32I-NEXT: srli a2, a0, 4 ; RV32I-NEXT: srli a2, a0, 4
; RV32I-NEXT: lui a3, 61681 ; RV32I-NEXT: lui a3, 61681
; RV32I-NEXT: addi a3, a3, -241 ; RV32I-NEXT: addi a3, a3, -241
; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc7_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: orc.b a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc7_i32: ; RV32ZBP-LABEL: gorc7_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc.b a0, a0 ; RV32ZBP-NEXT: orc.b a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i32 %a, 1 %and1 = shl i32 %a, 1
%shl1 = and i32 %and1, -1431655766 %shl1 = and i32 %and1, -1431655766
%and1b = lshr i32 %a, 1 %and1b = lshr i32 %a, 1
%shr1 = and i32 %and1b, 1431655765 %shr1 = and i32 %and1b, 1431655765
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc7_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: orc.b a0, a0
; RV32B-NEXT: orc.b a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc7_i64: ; RV32ZBP-LABEL: gorc7_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc.b a0, a0 ; RV32ZBP-NEXT: orc.b a0, a0
; RV32ZBP-NEXT: orc.b a1, a1 ; RV32ZBP-NEXT: orc.b a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
%shl1 = and i64 %and1, -6148914691236517206 %shl1 = and i64 %and1, -6148914691236517206
%and1b = lshr i64 %a, 1 %and1b = lshr i64 %a, 1
Show All 25 Lines
; RV32I-NEXT: srli a2, a0, 8 ; RV32I-NEXT: srli a2, a0, 8
; RV32I-NEXT: lui a3, 4080 ; RV32I-NEXT: lui a3, 4080
; RV32I-NEXT: addi a3, a3, 255 ; RV32I-NEXT: addi a3, a3, 255
; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc8_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: orc8.h a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc8_i32: ; RV32ZBP-LABEL: gorc8_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc8.h a0, a0 ; RV32ZBP-NEXT: orc8.h a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i32 %a, 8 %and = shl i32 %a, 8
%shl = and i32 %and, -16711936 %shl = and i32 %and, -16711936
%and1 = lshr i32 %a, 8 %and1 = lshr i32 %a, 8
%shr = and i32 %and1, 16711935 %shr = and i32 %and1, 16711935
Show All 18 Lines
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc8_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: orc8.h a0, a0
; RV32B-NEXT: orc8.h a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc8_i64: ; RV32ZBP-LABEL: gorc8_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc8.h a0, a0 ; RV32ZBP-NEXT: orc8.h a0, a0
; RV32ZBP-NEXT: orc8.h a1, a1 ; RV32ZBP-NEXT: orc8.h a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i64 %a, 8 %and = shl i64 %a, 8
%shl = and i64 %and, -71777214294589696 %shl = and i64 %and, -71777214294589696
%and1 = lshr i64 %a, 8 %and1 = lshr i64 %a, 8
%shr = and i64 %and1, 71777214294589695 %shr = and i64 %and1, 71777214294589695
%or = or i64 %shr, %a %or = or i64 %shr, %a
%or2 = or i64 %or, %shl %or2 = or i64 %or, %shl
ret i64 %or2 ret i64 %or2
} }
define i32 @gorc16_i32(i32 %a) nounwind { define i32 @gorc16_i32(i32 %a) nounwind {
; RV32I-LABEL: gorc16_i32: ; RV32I-LABEL: gorc16_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 16 ; RV32I-NEXT: slli a1, a0, 16
; RV32I-NEXT: srli a2, a0, 16 ; RV32I-NEXT: srli a2, a0, 16
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc16_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: orc16 a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc16_i32: ; RV32ZBP-LABEL: gorc16_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc16 a0, a0 ; RV32ZBP-NEXT: orc16 a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%shl = shl i32 %a, 16 %shl = shl i32 %a, 16
%shr = lshr i32 %a, 16 %shr = lshr i32 %a, 16
%or = or i32 %shr, %a %or = or i32 %shr, %a
%or2 = or i32 %or, %shl %or2 = or i32 %or, %shl
ret i32 %or2 ret i32 %or2
} }
define i32 @gorc16_rotl_i32(i32 %a) nounwind { define i32 @gorc16_rotl_i32(i32 %a) nounwind {
; RV32I-LABEL: gorc16_rotl_i32: ; RV32I-LABEL: gorc16_rotl_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: srli a1, a0, 16
; RV32I-NEXT: slli a2, a0, 16 ; RV32I-NEXT: slli a2, a0, 16
; RV32I-NEXT: or a1, a2, a1 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc16_rotl_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: orc16 a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc16_rotl_i32: ; RV32ZBP-LABEL: gorc16_rotl_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc16 a0, a0 ; RV32ZBP-NEXT: orc16 a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%rot = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 16) %rot = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 16)
%or = or i32 %rot, %a %or = or i32 %rot, %a
ret i32 %or ret i32 %or
} }
define i32 @gorc16_rotr_i32(i32 %a) nounwind { define i32 @gorc16_rotr_i32(i32 %a) nounwind {
; RV32I-LABEL: gorc16_rotr_i32: ; RV32I-LABEL: gorc16_rotr_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 16 ; RV32I-NEXT: slli a1, a0, 16
; RV32I-NEXT: srli a2, a0, 16 ; RV32I-NEXT: srli a2, a0, 16
; RV32I-NEXT: or a1, a2, a1 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc16_rotr_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: orc16 a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc16_rotr_i32: ; RV32ZBP-LABEL: gorc16_rotr_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc16 a0, a0 ; RV32ZBP-NEXT: orc16 a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%rot = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 16) %rot = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 16)
%or = or i32 %rot, %a %or = or i32 %rot, %a
ret i32 %or ret i32 %or
} }
define i64 @gorc16_i64(i64 %a) nounwind { define i64 @gorc16_i64(i64 %a) nounwind {
; RV32I-LABEL: gorc16_i64: ; RV32I-LABEL: gorc16_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a1, 16 ; RV32I-NEXT: slli a2, a1, 16
; RV32I-NEXT: slli a3, a0, 16 ; RV32I-NEXT: slli a3, a0, 16
; RV32I-NEXT: srli a4, a0, 16 ; RV32I-NEXT: srli a4, a0, 16
; RV32I-NEXT: srli a5, a1, 16 ; RV32I-NEXT: srli a5, a1, 16
; RV32I-NEXT: or a1, a5, a1 ; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: or a0, a4, a0 ; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc16_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: orc16 a0, a0
; RV32B-NEXT: orc16 a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc16_i64: ; RV32ZBP-LABEL: gorc16_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc16 a0, a0 ; RV32ZBP-NEXT: orc16 a0, a0
; RV32ZBP-NEXT: orc16 a1, a1 ; RV32ZBP-NEXT: orc16 a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i64 %a, 16 %and = shl i64 %a, 16
%shl = and i64 %and, -281470681808896 %shl = and i64 %and, -281470681808896
%and1 = lshr i64 %a, 16 %and1 = lshr i64 %a, 16
Show All 20 Lines
; RV32I-NEXT: slli a1, a0, 2 ; RV32I-NEXT: slli a1, a0, 2
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a2, a0, 2 ; RV32I-NEXT: srli a2, a0, 2
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc2b_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: orc2.n a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc2b_i32: ; RV32ZBP-LABEL: gorc2b_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc2.n a0, a0 ; RV32ZBP-NEXT: orc2.n a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i32 %a, 2 %and1 = shl i32 %a, 2
%shl1 = and i32 %and1, -858993460 %shl1 = and i32 %and1, -858993460
%and1b = lshr i32 %a, 2 %and1b = lshr i32 %a, 2
%shr1 = and i32 %and1b, 858993459 %shr1 = and i32 %and1b, 858993459
Show All 37 Lines
; RV32I-NEXT: and a5, a5, a2 ; RV32I-NEXT: and a5, a5, a2
; RV32I-NEXT: and a2, a4, a2 ; RV32I-NEXT: and a2, a4, a2
; RV32I-NEXT: or a1, a2, a1 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc2b_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: orc2.n a0, a0
; RV32B-NEXT: orc2.n a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc2b_i64: ; RV32ZBP-LABEL: gorc2b_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc2.n a0, a0 ; RV32ZBP-NEXT: orc2.n a0, a0
; RV32ZBP-NEXT: orc2.n a1, a1 ; RV32ZBP-NEXT: orc2.n a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 2 %and1 = shl i64 %a, 2
%shl1 = and i64 %and1, -3689348814741910324 %shl1 = and i64 %and1, -3689348814741910324
%and1b = lshr i64 %a, 2 %and1b = lshr i64 %a, 2
Show All 36 Lines
; RV32I-NEXT: slli a1, a0, 1 ; RV32I-NEXT: slli a1, a0, 1
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a2, a0, 1 ; RV32I-NEXT: srli a2, a0, 1
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc3b_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: orc.n a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc3b_i32: ; RV32ZBP-LABEL: gorc3b_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc.n a0, a0 ; RV32ZBP-NEXT: orc.n a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i32 %a, 1 %and1 = shl i32 %a, 1
%shl1 = and i32 %and1, -1431655766 %shl1 = and i32 %and1, -1431655766
%and1b = lshr i32 %a, 1 %and1b = lshr i32 %a, 1
%shr1 = and i32 %and1b, 1431655765 %shr1 = and i32 %and1b, 1431655765
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; RV32I-NEXT: and a5, a5, a2 ; RV32I-NEXT: and a5, a5, a2
; RV32I-NEXT: and a2, a4, a2 ; RV32I-NEXT: and a2, a4, a2
; RV32I-NEXT: or a1, a2, a1 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: gorc3b_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: orc.n a0, a0
; RV32B-NEXT: orc.n a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: gorc3b_i64: ; RV32ZBP-LABEL: gorc3b_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc.n a0, a0 ; RV32ZBP-NEXT: orc.n a0, a0
; RV32ZBP-NEXT: orc.n a1, a1 ; RV32ZBP-NEXT: orc.n a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
%shl1 = and i64 %and1, -6148914691236517206 %shl1 = and i64 %and1, -6148914691236517206
%and1b = lshr i64 %a, 1 %and1b = lshr i64 %a, 1
Show All 24 Lines
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a0, a0, 1 ; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev1_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: rev.p a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev1_i32: ; RV32ZBP-LABEL: grev1_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.p a0, a0 ; RV32ZBP-NEXT: rev.p a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i32 %a, 1 %and = shl i32 %a, 1
%shl = and i32 %and, -1431655766 %shl = and i32 %and, -1431655766
%and1 = lshr i32 %a, 1 %and1 = lshr i32 %a, 1
%shr = and i32 %and1, 1431655765 %shr = and i32 %and1, 1431655765
Show All 15 Lines
; RV32I-NEXT: lui a4, 349525 ; RV32I-NEXT: lui a4, 349525
; RV32I-NEXT: addi a4, a4, 1365 ; RV32I-NEXT: addi a4, a4, 1365
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: and a0, a0, a4 ; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev1_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: rev.p a0, a0
; RV32B-NEXT: rev.p a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev1_i64: ; RV32ZBP-LABEL: grev1_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.p a0, a0 ; RV32ZBP-NEXT: rev.p a0, a0
; RV32ZBP-NEXT: rev.p a1, a1 ; RV32ZBP-NEXT: rev.p a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i64 %a, 1 %and = shl i64 %a, 1
%shl = and i64 %and, -6148914691236517206 %shl = and i64 %and, -6148914691236517206
%and1 = lshr i64 %a, 1 %and1 = lshr i64 %a, 1
Show All 11 Lines
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: lui a2, 209715 ; RV32I-NEXT: lui a2, 209715
; RV32I-NEXT: addi a2, a2, 819 ; RV32I-NEXT: addi a2, a2, 819
; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev2_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: rev2.n a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev2_i32: ; RV32ZBP-LABEL: grev2_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev2.n a0, a0 ; RV32ZBP-NEXT: rev2.n a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i32 %a, 2 %and = shl i32 %a, 2
%shl = and i32 %and, -858993460 %shl = and i32 %and, -858993460
%and1 = lshr i32 %a, 2 %and1 = lshr i32 %a, 2
%shr = and i32 %and1, 858993459 %shr = and i32 %and1, 858993459
Show All 15 Lines
; RV32I-NEXT: lui a4, 209715 ; RV32I-NEXT: lui a4, 209715
; RV32I-NEXT: addi a4, a4, 819 ; RV32I-NEXT: addi a4, a4, 819
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: and a0, a0, a4 ; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev2_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: rev2.n a0, a0
; RV32B-NEXT: rev2.n a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev2_i64: ; RV32ZBP-LABEL: grev2_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev2.n a0, a0 ; RV32ZBP-NEXT: rev2.n a0, a0
; RV32ZBP-NEXT: rev2.n a1, a1 ; RV32ZBP-NEXT: rev2.n a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i64 %a, 2 %and = shl i64 %a, 2
%shl = and i64 %and, -3689348814741910324 %shl = and i64 %and, -3689348814741910324
%and1 = lshr i64 %a, 2 %and1 = lshr i64 %a, 2
Show All 20 Lines
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: lui a2, 209715 ; RV32I-NEXT: lui a2, 209715
; RV32I-NEXT: addi a2, a2, 819 ; RV32I-NEXT: addi a2, a2, 819
; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev3_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: rev.n a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev3_i32: ; RV32ZBP-LABEL: grev3_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.n a0, a0 ; RV32ZBP-NEXT: rev.n a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i32 %a, 1 %and1 = shl i32 %a, 1
%shl1 = and i32 %and1, -1431655766 %shl1 = and i32 %and1, -1431655766
%and1b = lshr i32 %a, 1 %and1b = lshr i32 %a, 1
%shr1 = and i32 %and1b, 1431655765 %shr1 = and i32 %and1b, 1431655765
Show All 34 Lines
; RV32I-NEXT: lui a4, 209715 ; RV32I-NEXT: lui a4, 209715
; RV32I-NEXT: addi a4, a4, 819 ; RV32I-NEXT: addi a4, a4, 819
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: and a0, a0, a4 ; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev3_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: rev.n a0, a0
; RV32B-NEXT: rev.n a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev3_i64: ; RV32ZBP-LABEL: grev3_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.n a0, a0 ; RV32ZBP-NEXT: rev.n a0, a0
; RV32ZBP-NEXT: rev.n a1, a1 ; RV32ZBP-NEXT: rev.n a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
%shl1 = and i64 %and1, -6148914691236517206 %shl1 = and i64 %and1, -6148914691236517206
%and1b = lshr i64 %a, 1 %and1b = lshr i64 %a, 1
Show All 16 Lines
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a0, a0, 4 ; RV32I-NEXT: srli a0, a0, 4
; RV32I-NEXT: lui a2, 61681 ; RV32I-NEXT: lui a2, 61681
; RV32I-NEXT: addi a2, a2, -241 ; RV32I-NEXT: addi a2, a2, -241
; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev4_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: rev4.b a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev4_i32: ; RV32ZBP-LABEL: grev4_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev4.b a0, a0 ; RV32ZBP-NEXT: rev4.b a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i32 %a, 4 %and = shl i32 %a, 4
%shl = and i32 %and, -252645136 %shl = and i32 %and, -252645136
%and1 = lshr i32 %a, 4 %and1 = lshr i32 %a, 4
%shr = and i32 %and1, 252645135 %shr = and i32 %and1, 252645135
Show All 15 Lines
; RV32I-NEXT: lui a4, 61681 ; RV32I-NEXT: lui a4, 61681
; RV32I-NEXT: addi a4, a4, -241 ; RV32I-NEXT: addi a4, a4, -241
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: and a0, a0, a4 ; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev4_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: rev4.b a0, a0
; RV32B-NEXT: rev4.b a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev4_i64: ; RV32ZBP-LABEL: grev4_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev4.b a0, a0 ; RV32ZBP-NEXT: rev4.b a0, a0
; RV32ZBP-NEXT: rev4.b a1, a1 ; RV32ZBP-NEXT: rev4.b a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i64 %a, 4 %and = shl i64 %a, 4
%shl = and i64 %and, -1085102592571150096 %shl = and i64 %and, -1085102592571150096
%and1 = lshr i64 %a, 4 %and1 = lshr i64 %a, 4
Show All 20 Lines
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a0, a0, 4 ; RV32I-NEXT: srli a0, a0, 4
; RV32I-NEXT: lui a2, 61681 ; RV32I-NEXT: lui a2, 61681
; RV32I-NEXT: addi a2, a2, -241 ; RV32I-NEXT: addi a2, a2, -241
; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev5_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: grevi a0, a0, 5
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev5_i32: ; RV32ZBP-LABEL: grev5_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: grevi a0, a0, 5 ; RV32ZBP-NEXT: grevi a0, a0, 5
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i32 %a, 1 %and1 = shl i32 %a, 1
%shl1 = and i32 %and1, -1431655766 %shl1 = and i32 %and1, -1431655766
%and1b = lshr i32 %a, 1 %and1b = lshr i32 %a, 1
%shr1 = and i32 %and1b, 1431655765 %shr1 = and i32 %and1b, 1431655765
Show All 34 Lines
; RV32I-NEXT: lui a4, 61681 ; RV32I-NEXT: lui a4, 61681
; RV32I-NEXT: addi a4, a4, -241 ; RV32I-NEXT: addi a4, a4, -241
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: and a0, a0, a4 ; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev5_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: grevi a0, a0, 5
; RV32B-NEXT: grevi a1, a1, 5
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev5_i64: ; RV32ZBP-LABEL: grev5_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: grevi a0, a0, 5 ; RV32ZBP-NEXT: grevi a0, a0, 5
; RV32ZBP-NEXT: grevi a1, a1, 5 ; RV32ZBP-NEXT: grevi a1, a1, 5
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
%shl1 = and i64 %and1, -6148914691236517206 %shl1 = and i64 %and1, -6148914691236517206
%and1b = lshr i64 %a, 1 %and1b = lshr i64 %a, 1
Show All 26 Lines
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a0, a0, 4 ; RV32I-NEXT: srli a0, a0, 4
; RV32I-NEXT: lui a2, 61681 ; RV32I-NEXT: lui a2, 61681
; RV32I-NEXT: addi a2, a2, -241 ; RV32I-NEXT: addi a2, a2, -241
; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev6_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: rev2.b a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev6_i32: ; RV32ZBP-LABEL: grev6_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev2.b a0, a0 ; RV32ZBP-NEXT: rev2.b a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i32 %a, 2 %and1 = shl i32 %a, 2
%shl1 = and i32 %and1, -858993460 %shl1 = and i32 %and1, -858993460
%and1b = lshr i32 %a, 2 %and1b = lshr i32 %a, 2
%shr1 = and i32 %and1b, 858993459 %shr1 = and i32 %and1b, 858993459
Show All 34 Lines
; RV32I-NEXT: lui a4, 61681 ; RV32I-NEXT: lui a4, 61681
; RV32I-NEXT: addi a4, a4, -241 ; RV32I-NEXT: addi a4, a4, -241
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: and a0, a0, a4 ; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev6_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: rev2.b a0, a0
; RV32B-NEXT: rev2.b a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev6_i64: ; RV32ZBP-LABEL: grev6_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev2.b a0, a0 ; RV32ZBP-NEXT: rev2.b a0, a0
; RV32ZBP-NEXT: rev2.b a1, a1 ; RV32ZBP-NEXT: rev2.b a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 2 %and1 = shl i64 %a, 2
%shl1 = and i64 %and1, -3689348814741910324 %shl1 = and i64 %and1, -3689348814741910324
%and1b = lshr i64 %a, 2 %and1b = lshr i64 %a, 2
Show All 34 Lines
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a0, a0, 4 ; RV32I-NEXT: srli a0, a0, 4
; RV32I-NEXT: lui a2, 61681 ; RV32I-NEXT: lui a2, 61681
; RV32I-NEXT: addi a2, a2, -241 ; RV32I-NEXT: addi a2, a2, -241
; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev7_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: rev.b a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev7_i32: ; RV32ZBP-LABEL: grev7_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.b a0, a0 ; RV32ZBP-NEXT: rev.b a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i32 %a, 1 %and1 = shl i32 %a, 1
%shl1 = and i32 %and1, -1431655766 %shl1 = and i32 %and1, -1431655766
%and1b = lshr i32 %a, 1 %and1b = lshr i32 %a, 1
%shr1 = and i32 %and1b, 1431655765 %shr1 = and i32 %and1b, 1431655765
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; RV32I-NEXT: lui a4, 61681 ; RV32I-NEXT: lui a4, 61681
; RV32I-NEXT: addi a4, a4, -241 ; RV32I-NEXT: addi a4, a4, -241
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: and a0, a0, a4 ; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev7_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: rev.b a0, a0
; RV32B-NEXT: rev.b a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev7_i64: ; RV32ZBP-LABEL: grev7_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.b a0, a0 ; RV32ZBP-NEXT: rev.b a0, a0
; RV32ZBP-NEXT: rev.b a1, a1 ; RV32ZBP-NEXT: rev.b a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
%shl1 = and i64 %and1, -6148914691236517206 %shl1 = and i64 %and1, -6148914691236517206
%and1b = lshr i64 %a, 1 %and1b = lshr i64 %a, 1
Show All 21 Lines
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a0, a0, 8 ; RV32I-NEXT: srli a0, a0, 8
; RV32I-NEXT: lui a2, 4080 ; RV32I-NEXT: lui a2, 4080
; RV32I-NEXT: addi a2, a2, 255 ; RV32I-NEXT: addi a2, a2, 255
; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev8_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: rev8.h a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev8_i32: ; RV32ZBP-LABEL: grev8_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev8.h a0, a0 ; RV32ZBP-NEXT: rev8.h a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i32 %a, 8 %and = shl i32 %a, 8
%shl = and i32 %and, -16711936 %shl = and i32 %and, -16711936
%and1 = lshr i32 %a, 8 %and1 = lshr i32 %a, 8
%shr = and i32 %and1, 16711935 %shr = and i32 %and1, 16711935
Show All 15 Lines
; RV32I-NEXT: lui a4, 4080 ; RV32I-NEXT: lui a4, 4080
; RV32I-NEXT: addi a4, a4, 255 ; RV32I-NEXT: addi a4, a4, 255
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: and a0, a0, a4 ; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev8_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: rev8.h a0, a0
; RV32B-NEXT: rev8.h a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev8_i64: ; RV32ZBP-LABEL: grev8_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev8.h a0, a0 ; RV32ZBP-NEXT: rev8.h a0, a0
; RV32ZBP-NEXT: rev8.h a1, a1 ; RV32ZBP-NEXT: rev8.h a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i64 %a, 8 %and = shl i64 %a, 8
%shl = and i64 %and, -71777214294589696 %shl = and i64 %and, -71777214294589696
%and1 = lshr i64 %a, 8 %and1 = lshr i64 %a, 8
%shr = and i64 %and1, 71777214294589695 %shr = and i64 %and1, 71777214294589695
%or = or i64 %shl, %shr %or = or i64 %shl, %shr
ret i64 %or ret i64 %or
} }
define i32 @grev16_i32(i32 %a) nounwind { define i32 @grev16_i32(i32 %a) nounwind {
; RV32I-LABEL: grev16_i32: ; RV32I-LABEL: grev16_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 16 ; RV32I-NEXT: slli a1, a0, 16
; RV32I-NEXT: srli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev16_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: rori a0, a0, 16
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev16_i32: ; RV32ZBP-LABEL: grev16_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rori a0, a0, 16 ; RV32ZBP-NEXT: rori a0, a0, 16
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%shl = shl i32 %a, 16 %shl = shl i32 %a, 16
%shr = lshr i32 %a, 16 %shr = lshr i32 %a, 16
%or = or i32 %shl, %shr %or = or i32 %shl, %shr
ret i32 %or ret i32 %or
Show All 18 Lines
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a0, a0, 1 ; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev3b_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: rev.n a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev3b_i32: ; RV32ZBP-LABEL: grev3b_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.n a0, a0 ; RV32ZBP-NEXT: rev.n a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and2 = shl i32 %a, 2 %and2 = shl i32 %a, 2
%shl2 = and i32 %and2, -858993460 %shl2 = and i32 %and2, -858993460
%and2b = lshr i32 %a, 2 %and2b = lshr i32 %a, 2
%shr2 = and i32 %and2b, 858993459 %shr2 = and i32 %and2b, 858993459
Show All 34 Lines
; RV32I-NEXT: lui a4, 349525 ; RV32I-NEXT: lui a4, 349525
; RV32I-NEXT: addi a4, a4, 1365 ; RV32I-NEXT: addi a4, a4, 1365
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: and a0, a0, a4 ; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev3b_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: rev.n a0, a0
; RV32B-NEXT: rev.n a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev3b_i64: ; RV32ZBP-LABEL: grev3b_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.n a0, a0 ; RV32ZBP-NEXT: rev.n a0, a0
; RV32ZBP-NEXT: rev.n a1, a1 ; RV32ZBP-NEXT: rev.n a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and2 = shl i64 %a, 2 %and2 = shl i64 %a, 2
%shl2 = and i64 %and2, -3689348814741910324 %shl2 = and i64 %and2, -3689348814741910324
%and2b = lshr i64 %a, 2 %and2b = lshr i64 %a, 2
Show All 31 Lines
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: slli a1, a0, 1 ; RV32I-NEXT: slli a1, a0, 1
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a0, a0, 1 ; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev2b_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: rev2.n a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev2b_i32: ; RV32ZBP-LABEL: grev2b_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev2.n a0, a0 ; RV32ZBP-NEXT: rev2.n a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i32 %a, 1 %and1 = shl i32 %a, 1
%shl1 = and i32 %and1, -1431655766 %shl1 = and i32 %and1, -1431655766
%and1b = lshr i32 %a, 1 %and1b = lshr i32 %a, 1
%shr1 = and i32 %and1b, 1431655765 %shr1 = and i32 %and1b, 1431655765
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; RV32I-NEXT: srli a0, a0, 1 ; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: srli a1, a1, 1 ; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: and a1, a1, a5 ; RV32I-NEXT: and a1, a1, a5
; RV32I-NEXT: and a0, a0, a5 ; RV32I-NEXT: and a0, a0, a5
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev2b_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: rev2.n a0, a0
; RV32B-NEXT: rev2.n a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev2b_i64: ; RV32ZBP-LABEL: grev2b_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev2.n a0, a0 ; RV32ZBP-NEXT: rev2.n a0, a0
; RV32ZBP-NEXT: rev2.n a1, a1 ; RV32ZBP-NEXT: rev2.n a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
%shl1 = and i64 %and1, -6148914691236517206 %shl1 = and i64 %and1, -6148914691236517206
%and1b = lshr i64 %a, 1 %and1b = lshr i64 %a, 1
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: slli a1, a0, 2 ; RV32I-NEXT: slli a1, a0, 2
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, a5 ; RV32I-NEXT: and a0, a0, a5
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev0_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev0_i32: ; RV32ZBP-LABEL: grev0_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i32 %a, 1 %and1 = shl i32 %a, 1
%shl1 = and i32 %and1, -1431655766 %shl1 = and i32 %and1, -1431655766
%and1b = lshr i32 %a, 1 %and1b = lshr i32 %a, 1
%shr1 = and i32 %and1b, 1431655765 %shr1 = and i32 %and1b, 1431655765
%or1 = or i32 %shl1, %shr1 %or1 = or i32 %shl1, %shr1
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: srli a1, a1, 2 ; RV32I-NEXT: srli a1, a1, 2
; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a5, a1 ; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev0_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev0_i64: ; RV32ZBP-LABEL: grev0_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
%shl1 = and i64 %and1, -6148914691236517206 %shl1 = and i64 %and1, -6148914691236517206
%and1b = lshr i64 %a, 1 %and1b = lshr i64 %a, 1
%shr1 = and i64 %and1b, 6148914691236517205 %shr1 = and i64 %and1b, 6148914691236517205
%or1 = or i64 %shl1, %shr1 %or1 = or i64 %shl1, %shr1
Show All 21 Lines
define signext i32 @grev16_i32_fshl(i32 signext %a) nounwind { define signext i32 @grev16_i32_fshl(i32 signext %a) nounwind {
; RV32I-LABEL: grev16_i32_fshl: ; RV32I-LABEL: grev16_i32_fshl:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: srli a1, a0, 16
; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev16_i32_fshl:
; RV32B: # %bb.0:
; RV32B-NEXT: rori a0, a0, 16
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev16_i32_fshl: ; RV32ZBP-LABEL: grev16_i32_fshl:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rori a0, a0, 16 ; RV32ZBP-NEXT: rori a0, a0, 16
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%or = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 16) %or = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 16)
ret i32 %or ret i32 %or
} }
define signext i32 @grev16_i32_fshr(i32 signext %a) nounwind { define signext i32 @grev16_i32_fshr(i32 signext %a) nounwind {
; RV32I-LABEL: grev16_i32_fshr: ; RV32I-LABEL: grev16_i32_fshr:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 16 ; RV32I-NEXT: slli a1, a0, 16
; RV32I-NEXT: srli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev16_i32_fshr:
; RV32B: # %bb.0:
; RV32B-NEXT: rori a0, a0, 16
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev16_i32_fshr: ; RV32ZBP-LABEL: grev16_i32_fshr:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rori a0, a0, 16 ; RV32ZBP-NEXT: rori a0, a0, 16
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%or = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 16) %or = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 16)
ret i32 %or ret i32 %or
} }
define i64 @grev16_i64(i64 %a) nounwind { define i64 @grev16_i64(i64 %a) nounwind {
; RV32I-LABEL: grev16_i64: ; RV32I-LABEL: grev16_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a1, 16 ; RV32I-NEXT: slli a2, a1, 16
; RV32I-NEXT: srli a3, a0, 16 ; RV32I-NEXT: srli a3, a0, 16
; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: srli a1, a1, 16 ; RV32I-NEXT: srli a1, a1, 16
; RV32I-NEXT: or a1, a2, a1 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: grev16_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: rori a0, a0, 16
; RV32B-NEXT: rori a1, a1, 16
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: grev16_i64: ; RV32ZBP-LABEL: grev16_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rori a0, a0, 16 ; RV32ZBP-NEXT: rori a0, a0, 16
; RV32ZBP-NEXT: rori a1, a1, 16 ; RV32ZBP-NEXT: rori a1, a1, 16
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i64 %a, 16 %and = shl i64 %a, 16
%shl = and i64 %and, -281470681808896 %shl = and i64 %and, -281470681808896
%and1 = lshr i64 %a, 16 %and1 = lshr i64 %a, 16
Show All 10 Lines
; RV32I-NEXT: srli a1, a0, 8 ; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: slli a0, a0, 8 ; RV32I-NEXT: slli a0, a0, 8
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: bswap_i16:
; RV32B: # %bb.0:
; RV32B-NEXT: rev8.h a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: bswap_i16: ; RV32ZBP-LABEL: bswap_i16:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev8.h a0, a0 ; RV32ZBP-NEXT: rev8.h a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%1 = tail call i16 @llvm.bswap.i16(i16 %a) %1 = tail call i16 @llvm.bswap.i16(i16 %a)
ret i16 %1 ret i16 %1
} }
Show All 11 Lines
; RV32I-NEXT: slli a2, a0, 8 ; RV32I-NEXT: slli a2, a0, 8
; RV32I-NEXT: lui a3, 4080 ; RV32I-NEXT: lui a3, 4080
; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: bswap_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: rev8 a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: bswap_i32: ; RV32ZBP-LABEL: bswap_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev8 a0, a0 ; RV32ZBP-NEXT: rev8 a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%1 = tail call i32 @llvm.bswap.i32(i32 %a) %1 = tail call i32 @llvm.bswap.i32(i32 %a)
ret i32 %1 ret i32 %1
} }
Show All 21 Lines
; RV32I-NEXT: slli a3, a0, 8 ; RV32I-NEXT: slli a3, a0, 8
; RV32I-NEXT: and a3, a3, a5 ; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a1, a0, a1 ; RV32I-NEXT: or a1, a0, a1
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: bswap_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: rev8 a2, a1
; RV32B-NEXT: rev8 a1, a0
; RV32B-NEXT: mv a0, a2
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: bswap_i64: ; RV32ZBP-LABEL: bswap_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev8 a2, a1 ; RV32ZBP-NEXT: rev8 a2, a1
; RV32ZBP-NEXT: rev8 a1, a0 ; RV32ZBP-NEXT: rev8 a1, a0
; RV32ZBP-NEXT: mv a0, a2 ; RV32ZBP-NEXT: mv a0, a2
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%1 = call i64 @llvm.bswap.i64(i64 %a) %1 = call i64 @llvm.bswap.i64(i64 %a)
ret i64 %1 ret i64 %1
Show All 15 Lines
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: andi a1, a0, 85 ; RV32I-NEXT: andi a1, a0, 85
; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: srli a0, a0, 1 ; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: andi a0, a0, 85 ; RV32I-NEXT: andi a0, a0, 85
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: bitreverse_i8:
; RV32B: # %bb.0:
; RV32B-NEXT: rev.b a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: bitreverse_i8: ; RV32ZBP-LABEL: bitreverse_i8:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.b a0, a0 ; RV32ZBP-NEXT: rev.b a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%1 = tail call i8 @llvm.bitreverse.i8(i8 %a) %1 = tail call i8 @llvm.bitreverse.i8(i8 %a)
ret i8 %1 ret i8 %1
} }
Show All 23 Lines
; RV32I-NEXT: lui a2, 5 ; RV32I-NEXT: lui a2, 5
; RV32I-NEXT: addi a2, a2, 1365 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: bitreverse_i16:
; RV32B: # %bb.0:
; RV32B-NEXT: rev.h a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: bitreverse_i16: ; RV32ZBP-LABEL: bitreverse_i16:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.h a0, a0 ; RV32ZBP-NEXT: rev.h a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%1 = tail call i16 @llvm.bitreverse.i16(i16 %a) %1 = tail call i16 @llvm.bitreverse.i16(i16 %a)
ret i16 %1 ret i16 %1
} }
Show All 32 Lines
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: bitreverse_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: rev a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: bitreverse_i32: ; RV32ZBP-LABEL: bitreverse_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev a0, a0 ; RV32ZBP-NEXT: rev a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%1 = tail call i32 @llvm.bitreverse.i32(i32 %a) %1 = tail call i32 @llvm.bitreverse.i32(i32 %a)
ret i32 %1 ret i32 %1
} }
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a1, a1, a0 ; RV32I-NEXT: or a1, a1, a0
; RV32I-NEXT: mv a0, t0 ; RV32I-NEXT: mv a0, t0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: bitreverse_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: rev a2, a1
; RV32B-NEXT: rev a1, a0
; RV32B-NEXT: mv a0, a2
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: bitreverse_i64: ; RV32ZBP-LABEL: bitreverse_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev a2, a1 ; RV32ZBP-NEXT: rev a2, a1
; RV32ZBP-NEXT: rev a1, a0 ; RV32ZBP-NEXT: rev a1, a0
; RV32ZBP-NEXT: mv a0, a2 ; RV32ZBP-NEXT: mv a0, a2
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%1 = call i64 @llvm.bitreverse.i64(i64 %a) %1 = call i64 @llvm.bitreverse.i64(i64 %a)
ret i64 %1 ret i64 %1
Show All 14 Lines
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: slli a1, a0, 16 ; RV32I-NEXT: slli a1, a0, 16
; RV32I-NEXT: srli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: bswap_rotr_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: rev8.h a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: bswap_rotr_i32: ; RV32ZBP-LABEL: bswap_rotr_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev8.h a0, a0 ; RV32ZBP-NEXT: rev8.h a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%1 = call i32 @llvm.bswap.i32(i32 %a) %1 = call i32 @llvm.bswap.i32(i32 %a)
%2 = call i32 @llvm.fshr.i32(i32 %1, i32 %1, i32 16) %2 = call i32 @llvm.fshr.i32(i32 %1, i32 %1, i32 16)
ret i32 %2 ret i32 %2
} }
Show All 13 Lines
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: srli a1, a0, 16
; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: bswap_rotl_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: rev8.h a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: bswap_rotl_i32: ; RV32ZBP-LABEL: bswap_rotl_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev8.h a0, a0 ; RV32ZBP-NEXT: rev8.h a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%1 = call i32 @llvm.bswap.i32(i32 %a) %1 = call i32 @llvm.bswap.i32(i32 %a)
%2 = call i32 @llvm.fshl.i32(i32 %1, i32 %1, i32 16) %2 = call i32 @llvm.fshl.i32(i32 %1, i32 %1, i32 16)
ret i32 %2 ret i32 %2
} }
Show All 40 Lines
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: slli a2, a0, 8 ; RV32I-NEXT: slli a2, a0, 8
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: bitreverse_bswap_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: rev.b a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: bitreverse_bswap_i32: ; RV32ZBP-LABEL: bitreverse_bswap_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.b a0, a0 ; RV32ZBP-NEXT: rev.b a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%1 = call i32 @llvm.bitreverse.i32(i32 %a) %1 = call i32 @llvm.bitreverse.i32(i32 %a)
%2 = call i32 @llvm.bswap.i32(i32 %1) %2 = call i32 @llvm.bswap.i32(i32 %1)
ret i32 %2 ret i32 %2
} }
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
; RV32I-NEXT: or a2, a2, a3 ; RV32I-NEXT: or a2, a2, a3
; RV32I-NEXT: slli a3, a1, 8 ; RV32I-NEXT: slli a3, a1, 8
; RV32I-NEXT: and a3, a3, a6 ; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: slli a1, a1, 24
; RV32I-NEXT: or a1, a1, a3 ; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: bitreverse_bswap_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: rev.b a0, a0
; RV32B-NEXT: rev.b a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: bitreverse_bswap_i64: ; RV32ZBP-LABEL: bitreverse_bswap_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.b a0, a0 ; RV32ZBP-NEXT: rev.b a0, a0
; RV32ZBP-NEXT: rev.b a1, a1 ; RV32ZBP-NEXT: rev.b a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%1 = call i64 @llvm.bitreverse.i64(i64 %a) %1 = call i64 @llvm.bitreverse.i64(i64 %a)
%2 = call i64 @llvm.bswap.i64(i64 %1) %2 = call i64 @llvm.bswap.i64(i64 %1)
ret i64 %2 ret i64 %2
Show All 12 Lines
; RV32I-NEXT: or a1, a2, a1 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: srli a0, a0, 1 ; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: lui a2, 139810 ; RV32I-NEXT: lui a2, 139810
; RV32I-NEXT: addi a2, a2, 546 ; RV32I-NEXT: addi a2, a2, 546
; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: shfl1_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: zip.n a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: shfl1_i32: ; RV32ZBP-LABEL: shfl1_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zip.n a0, a0 ; RV32ZBP-NEXT: zip.n a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = and i32 %a, -1717986919 %and = and i32 %a, -1717986919
%shl = shl i32 %a, 1 %shl = shl i32 %a, 1
%and1 = and i32 %shl, 1145324612 %and1 = and i32 %shl, 1145324612
%or = or i32 %and1, %and %or = or i32 %and1, %and
Show All 23 Lines
; RV32I-NEXT: lui a4, 139810 ; RV32I-NEXT: lui a4, 139810
; RV32I-NEXT: addi a4, a4, 546 ; RV32I-NEXT: addi a4, a4, 546
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: and a0, a0, a4 ; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: or a0, a3, a0 ; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: or a1, a2, a1 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: shfl1_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: zip.n a0, a0
; RV32B-NEXT: zip.n a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: shfl1_i64: ; RV32ZBP-LABEL: shfl1_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zip.n a0, a0 ; RV32ZBP-NEXT: zip.n a0, a0
; RV32ZBP-NEXT: zip.n a1, a1 ; RV32ZBP-NEXT: zip.n a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = and i64 %a, -7378697629483820647 %and = and i64 %a, -7378697629483820647
%shl = shl i64 %a, 1 %shl = shl i64 %a, 1
%and1 = and i64 %shl, 4919131752989213764 %and1 = and i64 %shl, 4919131752989213764
Show All 17 Lines
; RV32I-NEXT: or a1, a2, a1 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: lui a2, 49345 ; RV32I-NEXT: lui a2, 49345
; RV32I-NEXT: addi a2, a2, -1012 ; RV32I-NEXT: addi a2, a2, -1012
; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: shfl2_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: zip2.b a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: shfl2_i32: ; RV32ZBP-LABEL: shfl2_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zip2.b a0, a0 ; RV32ZBP-NEXT: zip2.b a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = and i32 %a, -1010580541 %and = and i32 %a, -1010580541
%shl = shl i32 %a, 2 %shl = shl i32 %a, 2
%and1 = and i32 %shl, 808464432 %and1 = and i32 %shl, 808464432
%or = or i32 %and1, %and %or = or i32 %and1, %and
Show All 23 Lines
; RV32I-NEXT: lui a4, 49345 ; RV32I-NEXT: lui a4, 49345
; RV32I-NEXT: addi a4, a4, -1012 ; RV32I-NEXT: addi a4, a4, -1012
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: and a0, a0, a4 ; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: shfl2_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: zip2.b a0, a0
; RV32B-NEXT: zip2.b a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: shfl2_i64: ; RV32ZBP-LABEL: shfl2_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zip2.b a0, a0 ; RV32ZBP-NEXT: zip2.b a0, a0
; RV32ZBP-NEXT: zip2.b a1, a1 ; RV32ZBP-NEXT: zip2.b a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = and i64 %a, -4340410370284600381 %and = and i64 %a, -4340410370284600381
%shl = shl i64 %a, 2 %shl = shl i64 %a, 2
%and1 = and i64 %shl, 3472328296227680304 %and1 = and i64 %shl, 3472328296227680304
Show All 17 Lines
; RV32I-NEXT: srli a0, a0, 4 ; RV32I-NEXT: srli a0, a0, 4
; RV32I-NEXT: lui a3, 3840 ; RV32I-NEXT: lui a3, 3840
; RV32I-NEXT: addi a3, a3, 240 ; RV32I-NEXT: addi a3, a3, 240
; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: shfl4_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: zip4.h a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: shfl4_i32: ; RV32ZBP-LABEL: shfl4_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zip4.h a0, a0 ; RV32ZBP-NEXT: zip4.h a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = and i32 %a, -267390961 %and = and i32 %a, -267390961
%shl = shl i32 %a, 4 %shl = shl i32 %a, 4
%and1 = and i32 %shl, 251662080 %and1 = and i32 %shl, 251662080
%shr = lshr i32 %a, 4 %shr = lshr i32 %a, 4
Show All 23 Lines
; RV32I-NEXT: and a0, a0, a4 ; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: shfl4_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: zip4.h a0, a0
; RV32B-NEXT: zip4.h a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: shfl4_i64: ; RV32ZBP-LABEL: shfl4_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zip4.h a0, a0 ; RV32ZBP-NEXT: zip4.h a0, a0
; RV32ZBP-NEXT: zip4.h a1, a1 ; RV32ZBP-NEXT: zip4.h a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = and i64 %a, -1148435428713435121 %and = and i64 %a, -1148435428713435121
%shl = shl i64 %a, 4 %shl = shl i64 %a, 4
%and1 = and i64 %shl, 1080880403494997760 %and1 = and i64 %shl, 1080880403494997760
Show All 16 Lines
; RV32I-NEXT: srli a0, a0, 8 ; RV32I-NEXT: srli a0, a0, 8
; RV32I-NEXT: lui a3, 16 ; RV32I-NEXT: lui a3, 16
; RV32I-NEXT: addi a3, a3, -256 ; RV32I-NEXT: addi a3, a3, -256
; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: shfl8_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: zip8 a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: shfl8_i32: ; RV32ZBP-LABEL: shfl8_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zip8 a0, a0 ; RV32ZBP-NEXT: zip8 a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = and i32 %a, -16776961 %and = and i32 %a, -16776961
%shl = shl i32 %a, 8 %shl = shl i32 %a, 8
%and1 = and i32 %shl, 16711680 %and1 = and i32 %shl, 16711680
%shr = lshr i32 %a, 8 %shr = lshr i32 %a, 8
Show All 22 Lines
; RV32I-NEXT: and a0, a0, a4 ; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a0, a6 ; RV32I-NEXT: or a0, a0, a6
; RV32I-NEXT: or a0, a3, a0 ; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: or a1, a5, a1 ; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: shfl8_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: zip8 a0, a0
; RV32B-NEXT: zip8 a1, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: shfl8_i64: ; RV32ZBP-LABEL: shfl8_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zip8 a0, a0 ; RV32ZBP-NEXT: zip8 a0, a0
; RV32ZBP-NEXT: zip8 a1, a1 ; RV32ZBP-NEXT: zip8 a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = and i64 %a, -72056494543077121 %and = and i64 %a, -72056494543077121
%shl = shl i64 %a, 8 %shl = shl i64 %a, 8
%and1 = and i64 %shl, 71776119077928960 %and1 = and i64 %shl, 71776119077928960
Show All 9 Lines
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 16 ; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -1 ; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: slli a1, a1, 16 ; RV32I-NEXT: slli a1, a1, 16
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: pack_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: pack a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: pack_i32: ; RV32ZBP-LABEL: pack_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: pack a0, a0, a1 ; RV32ZBP-NEXT: pack a0, a0, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%shl = and i32 %a, 65535 %shl = and i32 %a, 65535
%shl1 = shl i32 %b, 16 %shl1 = shl i32 %b, 16
%or = or i32 %shl1, %shl %or = or i32 %shl1, %shl
ret i32 %or ret i32 %or
} }
; As we are not matching directly i64 code patterns on RV32 some i64 patterns ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32. ; don't have yet any matching bit manipulation instructions on RV32.
; This test is presented here in case future expansions of the experimental-b ; This test is presented here in case future expansions of the experimental-b
; extension introduce instructions suitable for this pattern. ; extension introduce instructions suitable for this pattern.
define i64 @pack_i64(i64 %a, i64 %b) nounwind { define i64 @pack_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: pack_i64: ; RV32I-LABEL: pack_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a1, a2 ; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: pack_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: mv a1, a2
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: pack_i64: ; RV32ZBP-LABEL: pack_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: mv a1, a2 ; RV32ZBP-NEXT: mv a1, a2
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%shl = and i64 %a, 4294967295 %shl = and i64 %a, 4294967295
%shl1 = shl i64 %b, 32 %shl1 = shl i64 %b, 32
%or = or i64 %shl1, %shl %or = or i64 %shl1, %shl
ret i64 %or ret i64 %or
} }
define i32 @packu_i32(i32 %a, i32 %b) nounwind { define i32 @packu_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: packu_i32: ; RV32I-LABEL: packu_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: lui a2, 1048560 ; RV32I-NEXT: lui a2, 1048560
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: packu_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: packu a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: packu_i32: ; RV32ZBP-LABEL: packu_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: packu a0, a0, a1 ; RV32ZBP-NEXT: packu a0, a0, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%shr = lshr i32 %a, 16 %shr = lshr i32 %a, 16
%shr1 = and i32 %b, -65536 %shr1 = and i32 %b, -65536
%or = or i32 %shr1, %shr %or = or i32 %shr1, %shr
ret i32 %or ret i32 %or
} }
; As we are not matching directly i64 code patterns on RV32 some i64 patterns ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32. ; don't have yet any matching bit manipulation instructions on RV32.
; This test is presented here in case future expansions of the experimental-b ; This test is presented here in case future expansions of the experimental-b
; extension introduce instructions suitable for this pattern. ; extension introduce instructions suitable for this pattern.
define i64 @packu_i64(i64 %a, i64 %b) nounwind { define i64 @packu_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: packu_i64: ; RV32I-LABEL: packu_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: packu_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: mv a0, a1
; RV32B-NEXT: mv a1, a3
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: packu_i64: ; RV32ZBP-LABEL: packu_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: mv a0, a1 ; RV32ZBP-NEXT: mv a0, a1
; RV32ZBP-NEXT: mv a1, a3 ; RV32ZBP-NEXT: mv a1, a3
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%shr = lshr i64 %a, 32 %shr = lshr i64 %a, 32
%shr1 = and i64 %b, -4294967296 %shr1 = and i64 %b, -4294967296
%or = or i64 %shr1, %shr %or = or i64 %shr1, %shr
ret i64 %or ret i64 %or
} }
define i32 @packh_i32(i32 %a, i32 %b) nounwind { define i32 @packh_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: packh_i32: ; RV32I-LABEL: packh_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 255 ; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: slli a1, a1, 24
; RV32I-NEXT: srli a1, a1, 16 ; RV32I-NEXT: srli a1, a1, 16
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: packh_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: packh a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: packh_i32: ; RV32ZBP-LABEL: packh_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: packh a0, a0, a1 ; RV32ZBP-NEXT: packh a0, a0, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = and i32 %a, 255 %and = and i32 %a, 255
%and1 = shl i32 %b, 8 %and1 = shl i32 %b, 8
%shl = and i32 %and1, 65280 %shl = and i32 %and1, 65280
%or = or i32 %shl, %and %or = or i32 %shl, %and
ret i32 %or ret i32 %or
} }
define i64 @packh_i64(i64 %a, i64 %b) nounwind { define i64 @packh_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: packh_i64: ; RV32I-LABEL: packh_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 255 ; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: slli a1, a2, 24 ; RV32I-NEXT: slli a1, a2, 24
; RV32I-NEXT: srli a1, a1, 16 ; RV32I-NEXT: srli a1, a1, 16
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: packh_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: packh a0, a0, a2
; RV32B-NEXT: mv a1, zero
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: packh_i64: ; RV32ZBP-LABEL: packh_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: packh a0, a0, a2 ; RV32ZBP-NEXT: packh a0, a0, a2
; RV32ZBP-NEXT: mv a1, zero ; RV32ZBP-NEXT: mv a1, zero
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = and i64 %a, 255 %and = and i64 %a, 255
%and1 = shl i64 %b, 8 %and1 = shl i64 %b, 8
%shl = and i64 %and1, 65280 %shl = and i64 %and1, 65280
%or = or i64 %shl, %and %or = or i64 %shl, %and
ret i64 %or ret i64 %or
} }
define i32 @zexth_i32(i32 %a) nounwind { define i32 @zexth_i32(i32 %a) nounwind {
; RV32I-LABEL: zexth_i32: ; RV32I-LABEL: zexth_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: zexth_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: zext.h a0, a0
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: zexth_i32: ; RV32ZBP-LABEL: zexth_i32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zext.h a0, a0 ; RV32ZBP-NEXT: zext.h a0, a0
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = and i32 %a, 65535 %and = and i32 %a, 65535
ret i32 %and ret i32 %and
} }
define i64 @zexth_i64(i64 %a) nounwind { define i64 @zexth_i64(i64 %a) nounwind {
; RV32I-LABEL: zexth_i64: ; RV32I-LABEL: zexth_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: zexth_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: zext.h a0, a0
; RV32B-NEXT: mv a1, zero
; RV32B-NEXT: ret
;
; RV32ZBP-LABEL: zexth_i64: ; RV32ZBP-LABEL: zexth_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zext.h a0, a0 ; RV32ZBP-NEXT: zext.h a0, a0
; RV32ZBP-NEXT: mv a1, zero ; RV32ZBP-NEXT: mv a1, zero
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = and i64 %a, 65535 %and = and i64 %a, 65535
ret i64 %and ret i64 %and
} }

llvm/test/CodeGen/RISCV/rv32zbs.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32B
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBS ; RUN: | FileCheck %s -check-prefix=RV32ZBS
define i32 @sbclr_i32(i32 %a, i32 %b) nounwind { define i32 @sbclr_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sbclr_i32: ; RV32I-LABEL: sbclr_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 1 ; RV32I-NEXT: addi a2, zero, 1
; RV32I-NEXT: sll a1, a2, a1 ; RV32I-NEXT: sll a1, a2, a1
; RV32I-NEXT: not a1, a1 ; RV32I-NEXT: not a1, a1
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbclr_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: bclr a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbclr_i32: ; RV32ZBS-LABEL: sbclr_i32:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bclr a0, a0, a1 ; RV32ZBS-NEXT: bclr a0, a0, a1
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%and = and i32 %b, 31 %and = and i32 %b, 31
%shl = shl nuw i32 1, %and %shl = shl nuw i32 1, %and
%neg = xor i32 %shl, -1 %neg = xor i32 %shl, -1
%and1 = and i32 %neg, %a %and1 = and i32 %neg, %a
ret i32 %and1 ret i32 %and1
} }
define i32 @sbclr_i32_no_mask(i32 %a, i32 %b) nounwind { define i32 @sbclr_i32_no_mask(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sbclr_i32_no_mask: ; RV32I-LABEL: sbclr_i32_no_mask:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 1 ; RV32I-NEXT: addi a2, zero, 1
; RV32I-NEXT: sll a1, a2, a1 ; RV32I-NEXT: sll a1, a2, a1
; RV32I-NEXT: not a1, a1 ; RV32I-NEXT: not a1, a1
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbclr_i32_no_mask:
; RV32B: # %bb.0:
; RV32B-NEXT: bclr a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbclr_i32_no_mask: ; RV32ZBS-LABEL: sbclr_i32_no_mask:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bclr a0, a0, a1 ; RV32ZBS-NEXT: bclr a0, a0, a1
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%shl = shl nuw i32 1, %b %shl = shl nuw i32 1, %b
%neg = xor i32 %shl, -1 %neg = xor i32 %shl, -1
%and1 = and i32 %neg, %a %and1 = and i32 %neg, %a
ret i32 %and1 ret i32 %and1
Show All 12 Lines
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB2_2: ; RV32I-NEXT: .LBB2_2:
; RV32I-NEXT: sll a2, a3, a2 ; RV32I-NEXT: sll a2, a3, a2
; RV32I-NEXT: not a2, a2 ; RV32I-NEXT: not a2, a2
; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbclr_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: bset a3, zero, a2
; RV32B-NEXT: andi a2, a2, 63
; RV32B-NEXT: addi a2, a2, -32
; RV32B-NEXT: srai a4, a2, 31
; RV32B-NEXT: and a3, a4, a3
; RV32B-NEXT: slti a4, a2, 0
; RV32B-NEXT: bclr a2, a1, a2
; RV32B-NEXT: cmov a1, a4, a1, a2
; RV32B-NEXT: andn a0, a0, a3
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbclr_i64: ; RV32ZBS-LABEL: sbclr_i64:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: andi a3, a2, 63 ; RV32ZBS-NEXT: andi a3, a2, 63
; RV32ZBS-NEXT: addi a3, a3, -32 ; RV32ZBS-NEXT: addi a3, a3, -32
; RV32ZBS-NEXT: bltz a3, .LBB2_2 ; RV32ZBS-NEXT: bltz a3, .LBB2_2
; RV32ZBS-NEXT: # %bb.1: ; RV32ZBS-NEXT: # %bb.1:
; RV32ZBS-NEXT: bclr a1, a1, a3 ; RV32ZBS-NEXT: bclr a1, a1, a3
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
Show All 10 Lines
define i32 @sbset_i32(i32 %a, i32 %b) nounwind { define i32 @sbset_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sbset_i32: ; RV32I-LABEL: sbset_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 1 ; RV32I-NEXT: addi a2, zero, 1
; RV32I-NEXT: sll a1, a2, a1 ; RV32I-NEXT: sll a1, a2, a1
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbset_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: bset a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbset_i32: ; RV32ZBS-LABEL: sbset_i32:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bset a0, a0, a1 ; RV32ZBS-NEXT: bset a0, a0, a1
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%and = and i32 %b, 31 %and = and i32 %b, 31
%shl = shl nuw i32 1, %and %shl = shl nuw i32 1, %and
%or = or i32 %shl, %a %or = or i32 %shl, %a
ret i32 %or ret i32 %or
} }
define i32 @sbset_i32_no_mask(i32 %a, i32 %b) nounwind { define i32 @sbset_i32_no_mask(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sbset_i32_no_mask: ; RV32I-LABEL: sbset_i32_no_mask:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 1 ; RV32I-NEXT: addi a2, zero, 1
; RV32I-NEXT: sll a1, a2, a1 ; RV32I-NEXT: sll a1, a2, a1
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbset_i32_no_mask:
; RV32B: # %bb.0:
; RV32B-NEXT: bset a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbset_i32_no_mask: ; RV32ZBS-LABEL: sbset_i32_no_mask:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bset a0, a0, a1 ; RV32ZBS-NEXT: bset a0, a0, a1
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%shl = shl nuw i32 1, %b %shl = shl nuw i32 1, %b
%or = or i32 %shl, %a %or = or i32 %shl, %a
ret i32 %or ret i32 %or
} }
; We can use sbsetw for 1 << x by setting the first source to zero. ; We can use sbsetw for 1 << x by setting the first source to zero.
define signext i32 @sbset_i32_zero(i32 signext %a) nounwind { define signext i32 @sbset_i32_zero(i32 signext %a) nounwind {
; RV32I-LABEL: sbset_i32_zero: ; RV32I-LABEL: sbset_i32_zero:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 1 ; RV32I-NEXT: addi a1, zero, 1
; RV32I-NEXT: sll a0, a1, a0 ; RV32I-NEXT: sll a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbset_i32_zero:
; RV32B: # %bb.0:
; RV32B-NEXT: bset a0, zero, a0
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbset_i32_zero: ; RV32ZBS-LABEL: sbset_i32_zero:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bset a0, zero, a0 ; RV32ZBS-NEXT: bset a0, zero, a0
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%shl = shl i32 1, %a %shl = shl i32 1, %a
ret i32 %shl ret i32 %shl
} }
; As we are not matching directly i64 code patterns on RV32 some i64 patterns ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32. ; don't have yet any matching bit manipulation instructions on RV32.
; This test is presented here in case future expansions of the experimental-b ; This test is presented here in case future expansions of the experimental-b
; extension introduce instructions suitable for this pattern. ; extension introduce instructions suitable for this pattern.
define i64 @sbset_i64(i64 %a, i64 %b) nounwind { define i64 @sbset_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: sbset_i64: ; RV32I-LABEL: sbset_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a3, zero, 1 ; RV32I-NEXT: addi a3, zero, 1
; RV32I-NEXT: sll a2, a3, a2 ; RV32I-NEXT: sll a2, a3, a2
; RV32I-NEXT: srai a3, a2, 31 ; RV32I-NEXT: srai a3, a2, 31
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbset_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: bset a3, zero, a2
; RV32B-NEXT: srai a3, a3, 31
; RV32B-NEXT: bset a0, a0, a2
; RV32B-NEXT: or a1, a3, a1
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbset_i64: ; RV32ZBS-LABEL: sbset_i64:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bset a3, zero, a2 ; RV32ZBS-NEXT: bset a3, zero, a2
; RV32ZBS-NEXT: srai a3, a3, 31 ; RV32ZBS-NEXT: srai a3, a3, 31
; RV32ZBS-NEXT: bset a0, a0, a2 ; RV32ZBS-NEXT: bset a0, a0, a2
; RV32ZBS-NEXT: or a1, a3, a1 ; RV32ZBS-NEXT: or a1, a3, a1
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%1 = trunc i64 %b to i32 %1 = trunc i64 %b to i32
Show All 14 Lines
; RV32I-NEXT: mv a0, zero ; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: sll a1, a2, a1 ; RV32I-NEXT: sll a1, a2, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB7_2: ; RV32I-NEXT: .LBB7_2:
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: sll a0, a2, a0 ; RV32I-NEXT: sll a0, a2, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbset_i64_zero:
; RV32B: # %bb.0:
; RV32B-NEXT: addi a2, a0, -32
; RV32B-NEXT: bset a1, zero, a2
; RV32B-NEXT: slti a3, a2, 0
; RV32B-NEXT: cmov a1, a3, zero, a1
; RV32B-NEXT: bset a0, zero, a0
; RV32B-NEXT: srai a2, a2, 31
; RV32B-NEXT: and a0, a2, a0
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbset_i64_zero: ; RV32ZBS-LABEL: sbset_i64_zero:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: addi a1, a0, -32 ; RV32ZBS-NEXT: addi a1, a0, -32
; RV32ZBS-NEXT: bltz a1, .LBB7_2 ; RV32ZBS-NEXT: bltz a1, .LBB7_2
; RV32ZBS-NEXT: # %bb.1: ; RV32ZBS-NEXT: # %bb.1:
; RV32ZBS-NEXT: mv a0, zero ; RV32ZBS-NEXT: mv a0, zero
; RV32ZBS-NEXT: bset a1, zero, a1 ; RV32ZBS-NEXT: bset a1, zero, a1
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
; RV32ZBS-NEXT: .LBB7_2: ; RV32ZBS-NEXT: .LBB7_2:
; RV32ZBS-NEXT: mv a1, zero ; RV32ZBS-NEXT: mv a1, zero
; RV32ZBS-NEXT: bset a0, zero, a0 ; RV32ZBS-NEXT: bset a0, zero, a0
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%shl = shl i64 1, %a %shl = shl i64 1, %a
ret i64 %shl ret i64 %shl
} }
define i32 @sbinv_i32(i32 %a, i32 %b) nounwind { define i32 @sbinv_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sbinv_i32: ; RV32I-LABEL: sbinv_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 1 ; RV32I-NEXT: addi a2, zero, 1
; RV32I-NEXT: sll a1, a2, a1 ; RV32I-NEXT: sll a1, a2, a1
; RV32I-NEXT: xor a0, a1, a0 ; RV32I-NEXT: xor a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbinv_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: binv a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbinv_i32: ; RV32ZBS-LABEL: sbinv_i32:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: binv a0, a0, a1 ; RV32ZBS-NEXT: binv a0, a0, a1
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%and = and i32 %b, 31 %and = and i32 %b, 31
%shl = shl nuw i32 1, %and %shl = shl nuw i32 1, %and
%xor = xor i32 %shl, %a %xor = xor i32 %shl, %a
ret i32 %xor ret i32 %xor
Show All 9 Lines
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a3, zero, 1 ; RV32I-NEXT: addi a3, zero, 1
; RV32I-NEXT: sll a2, a3, a2 ; RV32I-NEXT: sll a2, a3, a2
; RV32I-NEXT: srai a3, a2, 31 ; RV32I-NEXT: srai a3, a2, 31
; RV32I-NEXT: xor a0, a2, a0 ; RV32I-NEXT: xor a0, a2, a0
; RV32I-NEXT: xor a1, a3, a1 ; RV32I-NEXT: xor a1, a3, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbinv_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: bset a3, zero, a2
; RV32B-NEXT: srai a3, a3, 31
; RV32B-NEXT: binv a0, a0, a2
; RV32B-NEXT: xor a1, a3, a1
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbinv_i64: ; RV32ZBS-LABEL: sbinv_i64:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bset a3, zero, a2 ; RV32ZBS-NEXT: bset a3, zero, a2
; RV32ZBS-NEXT: srai a3, a3, 31 ; RV32ZBS-NEXT: srai a3, a3, 31
; RV32ZBS-NEXT: binv a0, a0, a2 ; RV32ZBS-NEXT: binv a0, a0, a2
; RV32ZBS-NEXT: xor a1, a3, a1 ; RV32ZBS-NEXT: xor a1, a3, a1
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%1 = trunc i64 %b to i32 %1 = trunc i64 %b to i32
%conv = and i32 %1, 63 %conv = and i32 %1, 63
%shl = shl nuw i32 1, %conv %shl = shl nuw i32 1, %conv
%conv1 = sext i32 %shl to i64 %conv1 = sext i32 %shl to i64
%xor = xor i64 %conv1, %a %xor = xor i64 %conv1, %a
ret i64 %xor ret i64 %xor
} }
define i32 @sbext_i32(i32 %a, i32 %b) nounwind { define i32 @sbext_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sbext_i32: ; RV32I-LABEL: sbext_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srl a0, a0, a1 ; RV32I-NEXT: srl a0, a0, a1
; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbext_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: bext a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbext_i32: ; RV32ZBS-LABEL: sbext_i32:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bext a0, a0, a1 ; RV32ZBS-NEXT: bext a0, a0, a1
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%and = and i32 %b, 31 %and = and i32 %b, 31
%shr = lshr i32 %a, %and %shr = lshr i32 %a, %and
%and1 = and i32 %shr, 1 %and1 = and i32 %shr, 1
ret i32 %and1 ret i32 %and1
} }
define i32 @sbext_i32_no_mask(i32 %a, i32 %b) nounwind { define i32 @sbext_i32_no_mask(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sbext_i32_no_mask: ; RV32I-LABEL: sbext_i32_no_mask:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srl a0, a0, a1 ; RV32I-NEXT: srl a0, a0, a1
; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbext_i32_no_mask:
; RV32B: # %bb.0:
; RV32B-NEXT: bext a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbext_i32_no_mask: ; RV32ZBS-LABEL: sbext_i32_no_mask:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bext a0, a0, a1 ; RV32ZBS-NEXT: bext a0, a0, a1
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%shr = lshr i32 %a, %b %shr = lshr i32 %a, %b
%and1 = and i32 %shr, 1 %and1 = and i32 %shr, 1
ret i32 %and1 ret i32 %and1
} }
Show All 19 Lines
; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: sll a1, a1, a2 ; RV32I-NEXT: sll a1, a1, a2
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: .LBB12_3: ; RV32I-NEXT: .LBB12_3:
; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbext_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: srl a0, a0, a2
; RV32B-NEXT: andi a2, a2, 63
; RV32B-NEXT: addi a3, zero, 31
; RV32B-NEXT: sub a3, a3, a2
; RV32B-NEXT: slli a4, a1, 1
; RV32B-NEXT: sll a3, a4, a3
; RV32B-NEXT: or a0, a0, a3
; RV32B-NEXT: addi a2, a2, -32
; RV32B-NEXT: srl a1, a1, a2
; RV32B-NEXT: slti a2, a2, 0
; RV32B-NEXT: cmov a0, a2, a0, a1
; RV32B-NEXT: andi a0, a0, 1
; RV32B-NEXT: mv a1, zero
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbext_i64: ; RV32ZBS-LABEL: sbext_i64:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: andi a3, a2, 63 ; RV32ZBS-NEXT: andi a3, a2, 63
; RV32ZBS-NEXT: addi a4, a3, -32 ; RV32ZBS-NEXT: addi a4, a3, -32
; RV32ZBS-NEXT: bltz a4, .LBB12_2 ; RV32ZBS-NEXT: bltz a4, .LBB12_2
; RV32ZBS-NEXT: # %bb.1: ; RV32ZBS-NEXT: # %bb.1:
; RV32ZBS-NEXT: srl a0, a1, a4 ; RV32ZBS-NEXT: srl a0, a1, a4
; RV32ZBS-NEXT: j .LBB12_3 ; RV32ZBS-NEXT: j .LBB12_3
Show All 16 Lines
define i32 @sbexti_i32(i32 %a) nounwind { define i32 @sbexti_i32(i32 %a) nounwind {
; RV32I-LABEL: sbexti_i32: ; RV32I-LABEL: sbexti_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a0, a0, 5 ; RV32I-NEXT: srli a0, a0, 5
; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbexti_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: bexti a0, a0, 5
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbexti_i32: ; RV32ZBS-LABEL: sbexti_i32:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bexti a0, a0, 5 ; RV32ZBS-NEXT: bexti a0, a0, 5
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%shr = lshr i32 %a, 5 %shr = lshr i32 %a, 5
%and = and i32 %shr, 1 %and = and i32 %shr, 1
ret i32 %and ret i32 %and
} }
define i64 @sbexti_i64(i64 %a) nounwind { define i64 @sbexti_i64(i64 %a) nounwind {
; RV32I-LABEL: sbexti_i64: ; RV32I-LABEL: sbexti_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a0, a0, 5 ; RV32I-NEXT: srli a0, a0, 5
; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbexti_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: bexti a0, a0, 5
; RV32B-NEXT: mv a1, zero
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbexti_i64: ; RV32ZBS-LABEL: sbexti_i64:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bexti a0, a0, 5 ; RV32ZBS-NEXT: bexti a0, a0, 5
; RV32ZBS-NEXT: mv a1, zero ; RV32ZBS-NEXT: mv a1, zero
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%shr = lshr i64 %a, 5 %shr = lshr i64 %a, 5
%and = and i64 %shr, 1 %and = and i64 %shr, 1
ret i64 %and ret i64 %and
} }
define i32 @sbclri_i32_10(i32 %a) nounwind { define i32 @sbclri_i32_10(i32 %a) nounwind {
; RV32I-LABEL: sbclri_i32_10: ; RV32I-LABEL: sbclri_i32_10:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, -1025 ; RV32I-NEXT: andi a0, a0, -1025
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbclri_i32_10:
; RV32B: # %bb.0:
; RV32B-NEXT: andi a0, a0, -1025
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbclri_i32_10: ; RV32ZBS-LABEL: sbclri_i32_10:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: andi a0, a0, -1025 ; RV32ZBS-NEXT: andi a0, a0, -1025
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%and = and i32 %a, -1025 %and = and i32 %a, -1025
ret i32 %and ret i32 %and
} }
define i32 @sbclri_i32_11(i32 %a) nounwind { define i32 @sbclri_i32_11(i32 %a) nounwind {
; RV32I-LABEL: sbclri_i32_11: ; RV32I-LABEL: sbclri_i32_11:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1048575 ; RV32I-NEXT: lui a1, 1048575
; RV32I-NEXT: addi a1, a1, 2047 ; RV32I-NEXT: addi a1, a1, 2047
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbclri_i32_11:
; RV32B: # %bb.0:
; RV32B-NEXT: bclri a0, a0, 11
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbclri_i32_11: ; RV32ZBS-LABEL: sbclri_i32_11:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bclri a0, a0, 11 ; RV32ZBS-NEXT: bclri a0, a0, 11
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%and = and i32 %a, -2049 %and = and i32 %a, -2049
ret i32 %and ret i32 %and
} }
define i32 @sbclri_i32_30(i32 %a) nounwind { define i32 @sbclri_i32_30(i32 %a) nounwind {
; RV32I-LABEL: sbclri_i32_30: ; RV32I-LABEL: sbclri_i32_30:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 786432 ; RV32I-NEXT: lui a1, 786432
; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbclri_i32_30:
; RV32B: # %bb.0:
; RV32B-NEXT: bclri a0, a0, 30
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbclri_i32_30: ; RV32ZBS-LABEL: sbclri_i32_30:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bclri a0, a0, 30 ; RV32ZBS-NEXT: bclri a0, a0, 30
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%and = and i32 %a, -1073741825 %and = and i32 %a, -1073741825
ret i32 %and ret i32 %and
} }
define i32 @sbclri_i32_31(i32 %a) nounwind { define i32 @sbclri_i32_31(i32 %a) nounwind {
; RV32I-LABEL: sbclri_i32_31: ; RV32I-LABEL: sbclri_i32_31:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbclri_i32_31:
; RV32B: # %bb.0:
; RV32B-NEXT: bclri a0, a0, 31
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbclri_i32_31: ; RV32ZBS-LABEL: sbclri_i32_31:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bclri a0, a0, 31 ; RV32ZBS-NEXT: bclri a0, a0, 31
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%and = and i32 %a, -2147483649 %and = and i32 %a, -2147483649
ret i32 %and ret i32 %and
} }
define i32 @sbclri_i32_large0(i32 %a) nounwind { define i32 @sbclri_i32_large0(i32 %a) nounwind {
; RV32I-LABEL: sbclri_i32_large0: ; RV32I-LABEL: sbclri_i32_large0:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1044480 ; RV32I-NEXT: lui a1, 1044480
; RV32I-NEXT: addi a1, a1, -256 ; RV32I-NEXT: addi a1, a1, -256
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbclri_i32_large0:
; RV32B: # %bb.0:
; RV32B-NEXT: andi a0, a0, -256
; RV32B-NEXT: bclri a0, a0, 24
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbclri_i32_large0: ; RV32ZBS-LABEL: sbclri_i32_large0:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: andi a0, a0, -256 ; RV32ZBS-NEXT: andi a0, a0, -256
; RV32ZBS-NEXT: bclri a0, a0, 24 ; RV32ZBS-NEXT: bclri a0, a0, 24
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%and = and i32 %a, -16777472 %and = and i32 %a, -16777472
ret i32 %and ret i32 %and
} }
define i32 @sbclri_i32_large1(i32 %a) nounwind { define i32 @sbclri_i32_large1(i32 %a) nounwind {
; RV32I-LABEL: sbclri_i32_large1: ; RV32I-LABEL: sbclri_i32_large1:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1044464 ; RV32I-NEXT: lui a1, 1044464
; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbclri_i32_large1:
; RV32B: # %bb.0:
; RV32B-NEXT: bclri a0, a0, 16
; RV32B-NEXT: bclri a0, a0, 24
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbclri_i32_large1: ; RV32ZBS-LABEL: sbclri_i32_large1:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bclri a0, a0, 16 ; RV32ZBS-NEXT: bclri a0, a0, 16
; RV32ZBS-NEXT: bclri a0, a0, 24 ; RV32ZBS-NEXT: bclri a0, a0, 24
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%and = and i32 %a, -16842753 %and = and i32 %a, -16842753
ret i32 %and ret i32 %and
} }
define i32 @sbclri_i32_large2(i32 %0) { define i32 @sbclri_i32_large2(i32 %0) {
; RV32I-LABEL: sbclri_i32_large2: ; RV32I-LABEL: sbclri_i32_large2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: addi a1, a1, -5 ; RV32I-NEXT: addi a1, a1, -5
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbclri_i32_large2:
; RV32B: # %bb.0:
; RV32B-NEXT: bclri a0, a0, 2
; RV32B-NEXT: bclri a0, a0, 31
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbclri_i32_large2: ; RV32ZBS-LABEL: sbclri_i32_large2:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bclri a0, a0, 2 ; RV32ZBS-NEXT: bclri a0, a0, 2
; RV32ZBS-NEXT: bclri a0, a0, 31 ; RV32ZBS-NEXT: bclri a0, a0, 31
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%2 = and i32 %0, 2147483643 %2 = and i32 %0, 2147483643
ret i32 %2 ret i32 %2
} }
define i32 @sbclri_i32_large3(i32 %0) { define i32 @sbclri_i32_large3(i32 %0) {
; RV32I-LABEL: sbclri_i32_large3: ; RV32I-LABEL: sbclri_i32_large3:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: addi a1, a1, -6 ; RV32I-NEXT: addi a1, a1, -6
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbclri_i32_large3:
; RV32B: # %bb.0:
; RV32B-NEXT: andi a0, a0, -6
; RV32B-NEXT: bclri a0, a0, 31
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbclri_i32_large3: ; RV32ZBS-LABEL: sbclri_i32_large3:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: andi a0, a0, -6 ; RV32ZBS-NEXT: andi a0, a0, -6
; RV32ZBS-NEXT: bclri a0, a0, 31 ; RV32ZBS-NEXT: bclri a0, a0, 31
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%2 = and i32 %0, 2147483642 %2 = and i32 %0, 2147483642
ret i32 %2 ret i32 %2
} }
define i32 @sbseti_i32_10(i32 %a) nounwind { define i32 @sbseti_i32_10(i32 %a) nounwind {
; RV32I-LABEL: sbseti_i32_10: ; RV32I-LABEL: sbseti_i32_10:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: ori a0, a0, 1024 ; RV32I-NEXT: ori a0, a0, 1024
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbseti_i32_10:
; RV32B: # %bb.0:
; RV32B-NEXT: ori a0, a0, 1024
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbseti_i32_10: ; RV32ZBS-LABEL: sbseti_i32_10:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: ori a0, a0, 1024 ; RV32ZBS-NEXT: ori a0, a0, 1024
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%or = or i32 %a, 1024 %or = or i32 %a, 1024
ret i32 %or ret i32 %or
} }
define i32 @sbseti_i32_11(i32 %a) nounwind { define i32 @sbseti_i32_11(i32 %a) nounwind {
; RV32I-LABEL: sbseti_i32_11: ; RV32I-LABEL: sbseti_i32_11:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1 ; RV32I-NEXT: lui a1, 1
; RV32I-NEXT: addi a1, a1, -2048 ; RV32I-NEXT: addi a1, a1, -2048
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbseti_i32_11:
; RV32B: # %bb.0:
; RV32B-NEXT: bseti a0, a0, 11
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbseti_i32_11: ; RV32ZBS-LABEL: sbseti_i32_11:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bseti a0, a0, 11 ; RV32ZBS-NEXT: bseti a0, a0, 11
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%or = or i32 %a, 2048 %or = or i32 %a, 2048
ret i32 %or ret i32 %or
} }
define i32 @sbseti_i32_30(i32 %a) nounwind { define i32 @sbseti_i32_30(i32 %a) nounwind {
; RV32I-LABEL: sbseti_i32_30: ; RV32I-LABEL: sbseti_i32_30:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 262144 ; RV32I-NEXT: lui a1, 262144
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbseti_i32_30:
; RV32B: # %bb.0:
; RV32B-NEXT: bseti a0, a0, 30
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbseti_i32_30: ; RV32ZBS-LABEL: sbseti_i32_30:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bseti a0, a0, 30 ; RV32ZBS-NEXT: bseti a0, a0, 30
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%or = or i32 %a, 1073741824 %or = or i32 %a, 1073741824
ret i32 %or ret i32 %or
} }
define i32 @sbseti_i32_31(i32 %a) nounwind { define i32 @sbseti_i32_31(i32 %a) nounwind {
; RV32I-LABEL: sbseti_i32_31: ; RV32I-LABEL: sbseti_i32_31:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbseti_i32_31:
; RV32B: # %bb.0:
; RV32B-NEXT: bseti a0, a0, 31
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbseti_i32_31: ; RV32ZBS-LABEL: sbseti_i32_31:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bseti a0, a0, 31 ; RV32ZBS-NEXT: bseti a0, a0, 31
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%or = or i32 %a, 2147483648 %or = or i32 %a, 2147483648
ret i32 %or ret i32 %or
} }
define i32 @sbinvi_i32_10(i32 %a) nounwind { define i32 @sbinvi_i32_10(i32 %a) nounwind {
; RV32I-LABEL: sbinvi_i32_10: ; RV32I-LABEL: sbinvi_i32_10:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: xori a0, a0, 1024 ; RV32I-NEXT: xori a0, a0, 1024
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbinvi_i32_10:
; RV32B: # %bb.0:
; RV32B-NEXT: xori a0, a0, 1024
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbinvi_i32_10: ; RV32ZBS-LABEL: sbinvi_i32_10:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: xori a0, a0, 1024 ; RV32ZBS-NEXT: xori a0, a0, 1024
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%xor = xor i32 %a, 1024 %xor = xor i32 %a, 1024
ret i32 %xor ret i32 %xor
} }
define i32 @sbinvi_i32_11(i32 %a) nounwind { define i32 @sbinvi_i32_11(i32 %a) nounwind {
; RV32I-LABEL: sbinvi_i32_11: ; RV32I-LABEL: sbinvi_i32_11:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1 ; RV32I-NEXT: lui a1, 1
; RV32I-NEXT: addi a1, a1, -2048 ; RV32I-NEXT: addi a1, a1, -2048
; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbinvi_i32_11:
; RV32B: # %bb.0:
; RV32B-NEXT: binvi a0, a0, 11
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbinvi_i32_11: ; RV32ZBS-LABEL: sbinvi_i32_11:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: binvi a0, a0, 11 ; RV32ZBS-NEXT: binvi a0, a0, 11
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%xor = xor i32 %a, 2048 %xor = xor i32 %a, 2048
ret i32 %xor ret i32 %xor
} }
define i32 @sbinvi_i32_30(i32 %a) nounwind { define i32 @sbinvi_i32_30(i32 %a) nounwind {
; RV32I-LABEL: sbinvi_i32_30: ; RV32I-LABEL: sbinvi_i32_30:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 262144 ; RV32I-NEXT: lui a1, 262144
; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbinvi_i32_30:
; RV32B: # %bb.0:
; RV32B-NEXT: binvi a0, a0, 30
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbinvi_i32_30: ; RV32ZBS-LABEL: sbinvi_i32_30:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: binvi a0, a0, 30 ; RV32ZBS-NEXT: binvi a0, a0, 30
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%xor = xor i32 %a, 1073741824 %xor = xor i32 %a, 1073741824
ret i32 %xor ret i32 %xor
} }
define i32 @sbinvi_i32_31(i32 %a) nounwind { define i32 @sbinvi_i32_31(i32 %a) nounwind {
; RV32I-LABEL: sbinvi_i32_31: ; RV32I-LABEL: sbinvi_i32_31:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: sbinvi_i32_31:
; RV32B: # %bb.0:
; RV32B-NEXT: binvi a0, a0, 31
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: sbinvi_i32_31: ; RV32ZBS-LABEL: sbinvi_i32_31:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: binvi a0, a0, 31 ; RV32ZBS-NEXT: binvi a0, a0, 31
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%xor = xor i32 %a, 2147483648 %xor = xor i32 %a, 2147483648
ret i32 %xor ret i32 %xor
} }
define i32 @xor_i32_4098(i32 %a) nounwind { define i32 @xor_i32_4098(i32 %a) nounwind {
; RV32I-LABEL: xor_i32_4098: ; RV32I-LABEL: xor_i32_4098:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1 ; RV32I-NEXT: lui a1, 1
; RV32I-NEXT: addi a1, a1, 2 ; RV32I-NEXT: addi a1, a1, 2
; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: xor_i32_4098:
; RV32B: # %bb.0:
; RV32B-NEXT: binvi a0, a0, 1
; RV32B-NEXT: binvi a0, a0, 12
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: xor_i32_4098: ; RV32ZBS-LABEL: xor_i32_4098:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: binvi a0, a0, 1 ; RV32ZBS-NEXT: binvi a0, a0, 1
; RV32ZBS-NEXT: binvi a0, a0, 12 ; RV32ZBS-NEXT: binvi a0, a0, 12
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%xor = xor i32 %a, 4098 %xor = xor i32 %a, 4098
ret i32 %xor ret i32 %xor
} }
define i32 @xor_i32_4099(i32 %a) nounwind { define i32 @xor_i32_4099(i32 %a) nounwind {
; RV32I-LABEL: xor_i32_4099: ; RV32I-LABEL: xor_i32_4099:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1 ; RV32I-NEXT: lui a1, 1
; RV32I-NEXT: addi a1, a1, 3 ; RV32I-NEXT: addi a1, a1, 3
; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: xor_i32_4099:
; RV32B: # %bb.0:
; RV32B-NEXT: xori a0, a0, 3
; RV32B-NEXT: binvi a0, a0, 12
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: xor_i32_4099: ; RV32ZBS-LABEL: xor_i32_4099:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: xori a0, a0, 3 ; RV32ZBS-NEXT: xori a0, a0, 3
; RV32ZBS-NEXT: binvi a0, a0, 12 ; RV32ZBS-NEXT: binvi a0, a0, 12
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%xor = xor i32 %a, 4099 %xor = xor i32 %a, 4099
ret i32 %xor ret i32 %xor
} }
define i32 @xor_i32_96(i32 %a) nounwind { define i32 @xor_i32_96(i32 %a) nounwind {
; RV32I-LABEL: xor_i32_96: ; RV32I-LABEL: xor_i32_96:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: xori a0, a0, 96 ; RV32I-NEXT: xori a0, a0, 96
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: xor_i32_96:
; RV32B: # %bb.0:
; RV32B-NEXT: xori a0, a0, 96
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: xor_i32_96: ; RV32ZBS-LABEL: xor_i32_96:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: xori a0, a0, 96 ; RV32ZBS-NEXT: xori a0, a0, 96
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%xor = xor i32 %a, 96 %xor = xor i32 %a, 96
ret i32 %xor ret i32 %xor
} }
define i32 @xor_i32_66901(i32 %a) nounwind { define i32 @xor_i32_66901(i32 %a) nounwind {
; RV32I-LABEL: xor_i32_66901: ; RV32I-LABEL: xor_i32_66901:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, 1365 ; RV32I-NEXT: addi a1, a1, 1365
; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: xor_i32_66901:
; RV32B: # %bb.0:
; RV32B-NEXT: xori a0, a0, 1365
; RV32B-NEXT: binvi a0, a0, 16
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: xor_i32_66901: ; RV32ZBS-LABEL: xor_i32_66901:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: xori a0, a0, 1365 ; RV32ZBS-NEXT: xori a0, a0, 1365
; RV32ZBS-NEXT: binvi a0, a0, 16 ; RV32ZBS-NEXT: binvi a0, a0, 16
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%xor = xor i32 %a, 66901 %xor = xor i32 %a, 66901
ret i32 %xor ret i32 %xor
} }
define i32 @or_i32_4098(i32 %a) nounwind { define i32 @or_i32_4098(i32 %a) nounwind {
; RV32I-LABEL: or_i32_4098: ; RV32I-LABEL: or_i32_4098:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1 ; RV32I-NEXT: lui a1, 1
; RV32I-NEXT: addi a1, a1, 2 ; RV32I-NEXT: addi a1, a1, 2
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: or_i32_4098:
; RV32B: # %bb.0:
; RV32B-NEXT: bseti a0, a0, 1
; RV32B-NEXT: bseti a0, a0, 12
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: or_i32_4098: ; RV32ZBS-LABEL: or_i32_4098:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bseti a0, a0, 1 ; RV32ZBS-NEXT: bseti a0, a0, 1
; RV32ZBS-NEXT: bseti a0, a0, 12 ; RV32ZBS-NEXT: bseti a0, a0, 12
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%or = or i32 %a, 4098 %or = or i32 %a, 4098
ret i32 %or ret i32 %or
} }
define i32 @or_i32_4099(i32 %a) nounwind { define i32 @or_i32_4099(i32 %a) nounwind {
; RV32I-LABEL: or_i32_4099: ; RV32I-LABEL: or_i32_4099:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1 ; RV32I-NEXT: lui a1, 1
; RV32I-NEXT: addi a1, a1, 3 ; RV32I-NEXT: addi a1, a1, 3
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: or_i32_4099:
; RV32B: # %bb.0:
; RV32B-NEXT: ori a0, a0, 3
; RV32B-NEXT: bseti a0, a0, 12
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: or_i32_4099: ; RV32ZBS-LABEL: or_i32_4099:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: ori a0, a0, 3 ; RV32ZBS-NEXT: ori a0, a0, 3
; RV32ZBS-NEXT: bseti a0, a0, 12 ; RV32ZBS-NEXT: bseti a0, a0, 12
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%or = or i32 %a, 4099 %or = or i32 %a, 4099
ret i32 %or ret i32 %or
} }
define i32 @or_i32_96(i32 %a) nounwind { define i32 @or_i32_96(i32 %a) nounwind {
; RV32I-LABEL: or_i32_96: ; RV32I-LABEL: or_i32_96:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: ori a0, a0, 96 ; RV32I-NEXT: ori a0, a0, 96
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: or_i32_96:
; RV32B: # %bb.0:
; RV32B-NEXT: ori a0, a0, 96
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: or_i32_96: ; RV32ZBS-LABEL: or_i32_96:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: ori a0, a0, 96 ; RV32ZBS-NEXT: ori a0, a0, 96
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%or = or i32 %a, 96 %or = or i32 %a, 96
ret i32 %or ret i32 %or
} }
define i32 @or_i32_66901(i32 %a) nounwind { define i32 @or_i32_66901(i32 %a) nounwind {
; RV32I-LABEL: or_i32_66901: ; RV32I-LABEL: or_i32_66901:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, 1365 ; RV32I-NEXT: addi a1, a1, 1365
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: or_i32_66901:
; RV32B: # %bb.0:
; RV32B-NEXT: ori a0, a0, 1365
; RV32B-NEXT: bseti a0, a0, 16
; RV32B-NEXT: ret
;
; RV32ZBS-LABEL: or_i32_66901: ; RV32ZBS-LABEL: or_i32_66901:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: ori a0, a0, 1365 ; RV32ZBS-NEXT: ori a0, a0, 1365
; RV32ZBS-NEXT: bseti a0, a0, 16 ; RV32ZBS-NEXT: bseti a0, a0, 16
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
%or = or i32 %a, 66901 %or = or i32 %a, 66901
ret i32 %or ret i32 %or
} }

llvm/test/CodeGen/RISCV/rv32zbt.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32B
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBT ; RUN: | FileCheck %s -check-prefix=RV32ZBT
define i32 @cmix_i32(i32 %a, i32 %b, i32 %c) nounwind { define i32 @cmix_i32(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: cmix_i32: ; RV32I-LABEL: cmix_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: not a1, a1 ; RV32I-NEXT: not a1, a1
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: cmix_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: cmix a0, a1, a0, a2
; RV32B-NEXT: ret
;
; RV32ZBT-LABEL: cmix_i32: ; RV32ZBT-LABEL: cmix_i32:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: cmix a0, a1, a0, a2 ; RV32ZBT-NEXT: cmix a0, a1, a0, a2
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%and = and i32 %b, %a %and = and i32 %b, %a
%neg = xor i32 %b, -1 %neg = xor i32 %b, -1
%and1 = and i32 %neg, %c %and1 = and i32 %neg, %c
%or = or i32 %and1, %and %or = or i32 %and1, %and
ret i32 %or ret i32 %or
} }
define i64 @cmix_i64(i64 %a, i64 %b, i64 %c) nounwind { define i64 @cmix_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: cmix_i64: ; RV32I-LABEL: cmix_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: and a1, a3, a1 ; RV32I-NEXT: and a1, a3, a1
; RV32I-NEXT: and a0, a2, a0 ; RV32I-NEXT: and a0, a2, a0
; RV32I-NEXT: not a2, a2 ; RV32I-NEXT: not a2, a2
; RV32I-NEXT: not a3, a3 ; RV32I-NEXT: not a3, a3
; RV32I-NEXT: and a3, a3, a5 ; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: cmix_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: cmix a0, a2, a0, a4
; RV32B-NEXT: cmix a1, a3, a1, a5
; RV32B-NEXT: ret
;
; RV32ZBT-LABEL: cmix_i64: ; RV32ZBT-LABEL: cmix_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: cmix a0, a2, a0, a4 ; RV32ZBT-NEXT: cmix a0, a2, a0, a4
; RV32ZBT-NEXT: cmix a1, a3, a1, a5 ; RV32ZBT-NEXT: cmix a1, a3, a1, a5
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%and = and i64 %b, %a %and = and i64 %b, %a
%neg = xor i64 %b, -1 %neg = xor i64 %b, -1
%and1 = and i64 %neg, %c %and1 = and i64 %neg, %c
%or = or i64 %and1, %and %or = or i64 %and1, %and
ret i64 %or ret i64 %or
} }
define i32 @cmov_i32(i32 %a, i32 %b, i32 %c) nounwind { define i32 @cmov_i32(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: cmov_i32: ; RV32I-LABEL: cmov_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beqz a1, .LBB2_2 ; RV32I-NEXT: beqz a1, .LBB2_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: .LBB2_2: ; RV32I-NEXT: .LBB2_2:
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: cmov_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: cmov a0, a1, a0, a2
; RV32B-NEXT: ret
;
; RV32ZBT-LABEL: cmov_i32: ; RV32ZBT-LABEL: cmov_i32:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: cmov a0, a1, a0, a2 ; RV32ZBT-NEXT: cmov a0, a1, a0, a2
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool.not = icmp eq i32 %b, 0 %tobool.not = icmp eq i32 %b, 0
%cond = select i1 %tobool.not, i32 %c, i32 %a %cond = select i1 %tobool.not, i32 %c, i32 %a
ret i32 %cond ret i32 %cond
} }
define i32 @cmov_sle_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define i32 @cmov_sle_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_sle_i32: ; RV32I-LABEL: cmov_sle_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: bge a2, a1, .LBB3_2 ; RV32I-NEXT: bge a2, a1, .LBB3_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB3_2: ; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: cmov_sle_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: slt a1, a2, a1
; RV32B-NEXT: cmov a0, a1, a3, a0
; RV32B-NEXT: ret
;
; RV32ZBT-LABEL: cmov_sle_i32: ; RV32ZBT-LABEL: cmov_sle_i32:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: slt a1, a2, a1 ; RV32ZBT-NEXT: slt a1, a2, a1
; RV32ZBT-NEXT: cmov a0, a1, a3, a0 ; RV32ZBT-NEXT: cmov a0, a1, a3, a0
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool = icmp sle i32 %b, %c %tobool = icmp sle i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define i32 @cmov_sge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define i32 @cmov_sge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_sge_i32: ; RV32I-LABEL: cmov_sge_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: bge a1, a2, .LBB4_2 ; RV32I-NEXT: bge a1, a2, .LBB4_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB4_2: ; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: cmov_sge_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: slt a1, a1, a2
; RV32B-NEXT: cmov a0, a1, a3, a0
; RV32B-NEXT: ret
;
; RV32ZBT-LABEL: cmov_sge_i32: ; RV32ZBT-LABEL: cmov_sge_i32:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: slt a1, a1, a2 ; RV32ZBT-NEXT: slt a1, a1, a2
; RV32ZBT-NEXT: cmov a0, a1, a3, a0 ; RV32ZBT-NEXT: cmov a0, a1, a3, a0
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool = icmp sge i32 %b, %c %tobool = icmp sge i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define i32 @cmov_ule_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define i32 @cmov_ule_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_ule_i32: ; RV32I-LABEL: cmov_ule_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: bgeu a2, a1, .LBB5_2 ; RV32I-NEXT: bgeu a2, a1, .LBB5_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB5_2: ; RV32I-NEXT: .LBB5_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: cmov_ule_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: sltu a1, a2, a1
; RV32B-NEXT: cmov a0, a1, a3, a0
; RV32B-NEXT: ret
;
; RV32ZBT-LABEL: cmov_ule_i32: ; RV32ZBT-LABEL: cmov_ule_i32:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: sltu a1, a2, a1 ; RV32ZBT-NEXT: sltu a1, a2, a1
; RV32ZBT-NEXT: cmov a0, a1, a3, a0 ; RV32ZBT-NEXT: cmov a0, a1, a3, a0
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool = icmp ule i32 %b, %c %tobool = icmp ule i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define i32 @cmov_uge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define i32 @cmov_uge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_uge_i32: ; RV32I-LABEL: cmov_uge_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: bgeu a1, a2, .LBB6_2 ; RV32I-NEXT: bgeu a1, a2, .LBB6_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB6_2: ; RV32I-NEXT: .LBB6_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: cmov_uge_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: sltu a1, a1, a2
; RV32B-NEXT: cmov a0, a1, a3, a0
; RV32B-NEXT: ret
;
; RV32ZBT-LABEL: cmov_uge_i32: ; RV32ZBT-LABEL: cmov_uge_i32:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: sltu a1, a1, a2 ; RV32ZBT-NEXT: sltu a1, a1, a2
; RV32ZBT-NEXT: cmov a0, a1, a3, a0 ; RV32ZBT-NEXT: cmov a0, a1, a3, a0
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool = icmp uge i32 %b, %c %tobool = icmp uge i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind { define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: cmov_i64: ; RV32I-LABEL: cmov_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: or a2, a2, a3 ; RV32I-NEXT: or a2, a2, a3
; RV32I-NEXT: beqz a2, .LBB7_2 ; RV32I-NEXT: beqz a2, .LBB7_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: mv a5, a1 ; RV32I-NEXT: mv a5, a1
; RV32I-NEXT: .LBB7_2: ; RV32I-NEXT: .LBB7_2:
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: cmov_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: or a2, a2, a3
; RV32B-NEXT: cmov a0, a2, a0, a4
; RV32B-NEXT: cmov a1, a2, a1, a5
; RV32B-NEXT: ret
;
; RV32ZBT-LABEL: cmov_i64: ; RV32ZBT-LABEL: cmov_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: or a2, a2, a3 ; RV32ZBT-NEXT: or a2, a2, a3
; RV32ZBT-NEXT: cmov a0, a2, a0, a4 ; RV32ZBT-NEXT: cmov a0, a2, a0, a4
; RV32ZBT-NEXT: cmov a1, a2, a1, a5 ; RV32ZBT-NEXT: cmov a1, a2, a1, a5
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool.not = icmp eq i64 %b, 0 %tobool.not = icmp eq i64 %b, 0
%cond = select i1 %tobool.not, i64 %c, i64 %a %cond = select i1 %tobool.not, i64 %c, i64 %a
Show All 14 Lines
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: bnez a2, .LBB8_4 ; RV32I-NEXT: bnez a2, .LBB8_4
; RV32I-NEXT: .LBB8_3: ; RV32I-NEXT: .LBB8_3:
; RV32I-NEXT: mv a0, a6 ; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: .LBB8_4: ; RV32I-NEXT: .LBB8_4:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: cmov_sle_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: xor t0, a3, a5
; RV32B-NEXT: sltu a2, a4, a2
; RV32B-NEXT: xori a2, a2, 1
; RV32B-NEXT: slt a3, a5, a3
; RV32B-NEXT: xori a3, a3, 1
; RV32B-NEXT: cmov a2, t0, a3, a2
; RV32B-NEXT: cmov a0, a2, a0, a6
; RV32B-NEXT: cmov a1, a2, a1, a7
; RV32B-NEXT: ret
;
; RV32ZBT-LABEL: cmov_sle_i64: ; RV32ZBT-LABEL: cmov_sle_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: xor t0, a3, a5 ; RV32ZBT-NEXT: xor t0, a3, a5
; RV32ZBT-NEXT: sltu a2, a4, a2 ; RV32ZBT-NEXT: sltu a2, a4, a2
; RV32ZBT-NEXT: xori a2, a2, 1 ; RV32ZBT-NEXT: xori a2, a2, 1
; RV32ZBT-NEXT: slt a3, a5, a3 ; RV32ZBT-NEXT: slt a3, a5, a3
; RV32ZBT-NEXT: xori a3, a3, 1 ; RV32ZBT-NEXT: xori a3, a3, 1
; RV32ZBT-NEXT: cmov a2, t0, a3, a2 ; RV32ZBT-NEXT: cmov a2, t0, a3, a2
Show All 19 Lines
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: bnez a2, .LBB9_4 ; RV32I-NEXT: bnez a2, .LBB9_4
; RV32I-NEXT: .LBB9_3: ; RV32I-NEXT: .LBB9_3:
; RV32I-NEXT: mv a0, a6 ; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: .LBB9_4: ; RV32I-NEXT: .LBB9_4:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: cmov_sge_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: xor t0, a3, a5
; RV32B-NEXT: sltu a2, a2, a4
; RV32B-NEXT: xori a2, a2, 1
; RV32B-NEXT: slt a3, a3, a5
; RV32B-NEXT: xori a3, a3, 1
; RV32B-NEXT: cmov a2, t0, a3, a2
; RV32B-NEXT: cmov a0, a2, a0, a6
; RV32B-NEXT: cmov a1, a2, a1, a7
; RV32B-NEXT: ret
;
; RV32ZBT-LABEL: cmov_sge_i64: ; RV32ZBT-LABEL: cmov_sge_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: xor t0, a3, a5 ; RV32ZBT-NEXT: xor t0, a3, a5
; RV32ZBT-NEXT: sltu a2, a2, a4 ; RV32ZBT-NEXT: sltu a2, a2, a4
; RV32ZBT-NEXT: xori a2, a2, 1 ; RV32ZBT-NEXT: xori a2, a2, 1
; RV32ZBT-NEXT: slt a3, a3, a5 ; RV32ZBT-NEXT: slt a3, a3, a5
; RV32ZBT-NEXT: xori a3, a3, 1 ; RV32ZBT-NEXT: xori a3, a3, 1
; RV32ZBT-NEXT: cmov a2, t0, a3, a2 ; RV32ZBT-NEXT: cmov a2, t0, a3, a2
Show All 19 Lines
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: bnez a2, .LBB10_4 ; RV32I-NEXT: bnez a2, .LBB10_4
; RV32I-NEXT: .LBB10_3: ; RV32I-NEXT: .LBB10_3:
; RV32I-NEXT: mv a0, a6 ; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: .LBB10_4: ; RV32I-NEXT: .LBB10_4:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: cmov_ule_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: xor t0, a3, a5
; RV32B-NEXT: sltu a2, a4, a2
; RV32B-NEXT: xori a2, a2, 1
; RV32B-NEXT: sltu a3, a5, a3
; RV32B-NEXT: xori a3, a3, 1
; RV32B-NEXT: cmov a2, t0, a3, a2
; RV32B-NEXT: cmov a0, a2, a0, a6
; RV32B-NEXT: cmov a1, a2, a1, a7
; RV32B-NEXT: ret
;
; RV32ZBT-LABEL: cmov_ule_i64: ; RV32ZBT-LABEL: cmov_ule_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: xor t0, a3, a5 ; RV32ZBT-NEXT: xor t0, a3, a5
; RV32ZBT-NEXT: sltu a2, a4, a2 ; RV32ZBT-NEXT: sltu a2, a4, a2
; RV32ZBT-NEXT: xori a2, a2, 1 ; RV32ZBT-NEXT: xori a2, a2, 1
; RV32ZBT-NEXT: sltu a3, a5, a3 ; RV32ZBT-NEXT: sltu a3, a5, a3
; RV32ZBT-NEXT: xori a3, a3, 1 ; RV32ZBT-NEXT: xori a3, a3, 1
; RV32ZBT-NEXT: cmov a2, t0, a3, a2 ; RV32ZBT-NEXT: cmov a2, t0, a3, a2
Show All 19 Lines
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: bnez a2, .LBB11_4 ; RV32I-NEXT: bnez a2, .LBB11_4
; RV32I-NEXT: .LBB11_3: ; RV32I-NEXT: .LBB11_3:
; RV32I-NEXT: mv a0, a6 ; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: .LBB11_4: ; RV32I-NEXT: .LBB11_4:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: cmov_uge_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: xor t0, a3, a5
; RV32B-NEXT: sltu a2, a2, a4
; RV32B-NEXT: xori a2, a2, 1
; RV32B-NEXT: sltu a3, a3, a5
; RV32B-NEXT: xori a3, a3, 1
; RV32B-NEXT: cmov a2, t0, a3, a2
; RV32B-NEXT: cmov a0, a2, a0, a6
; RV32B-NEXT: cmov a1, a2, a1, a7
; RV32B-NEXT: ret
;
; RV32ZBT-LABEL: cmov_uge_i64: ; RV32ZBT-LABEL: cmov_uge_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: xor t0, a3, a5 ; RV32ZBT-NEXT: xor t0, a3, a5
; RV32ZBT-NEXT: sltu a2, a2, a4 ; RV32ZBT-NEXT: sltu a2, a2, a4
; RV32ZBT-NEXT: xori a2, a2, 1 ; RV32ZBT-NEXT: xori a2, a2, 1
; RV32ZBT-NEXT: sltu a3, a3, a5 ; RV32ZBT-NEXT: sltu a3, a3, a5
; RV32ZBT-NEXT: xori a3, a3, 1 ; RV32ZBT-NEXT: xori a3, a3, 1
; RV32ZBT-NEXT: cmov a2, t0, a3, a2 ; RV32ZBT-NEXT: cmov a2, t0, a3, a2
Show All 12 Lines
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: sll a0, a0, a2 ; RV32I-NEXT: sll a0, a0, a2
; RV32I-NEXT: not a2, a2 ; RV32I-NEXT: not a2, a2
; RV32I-NEXT: srli a1, a1, 1 ; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: srl a1, a1, a2 ; RV32I-NEXT: srl a1, a1, a2
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: fshl_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: andi a2, a2, 31
; RV32B-NEXT: fsl a0, a0, a1, a2
; RV32B-NEXT: ret
;
; RV32ZBT-LABEL: fshl_i32: ; RV32ZBT-LABEL: fshl_i32:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: andi a2, a2, 31 ; RV32ZBT-NEXT: andi a2, a2, 31
; RV32ZBT-NEXT: fsl a0, a0, a1, a2 ; RV32ZBT-NEXT: fsl a0, a0, a1, a2
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c) %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c)
ret i32 %1 ret i32 %1
} }
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; RV32I-NEXT: bgez a7, .LBB13_7 ; RV32I-NEXT: bgez a7, .LBB13_7
; RV32I-NEXT: .LBB13_6: ; RV32I-NEXT: .LBB13_6:
; RV32I-NEXT: sll a0, a0, a4 ; RV32I-NEXT: sll a0, a0, a4
; RV32I-NEXT: or a2, a2, a0 ; RV32I-NEXT: or a2, a2, a0
; RV32I-NEXT: .LBB13_7: ; RV32I-NEXT: .LBB13_7:
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: fshl_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: sll a7, a1, a4
; RV32B-NEXT: andi a5, a4, 63
; RV32B-NEXT: addi a6, zero, 31
; RV32B-NEXT: sub t0, a6, a5
; RV32B-NEXT: srli a1, a0, 1
; RV32B-NEXT: srl a1, a1, t0
; RV32B-NEXT: or a7, a7, a1
; RV32B-NEXT: addi t1, a5, -32
; RV32B-NEXT: sll t0, a0, t1
; RV32B-NEXT: slti a1, t1, 0
; RV32B-NEXT: cmov t0, a1, a7, t0
; RV32B-NEXT: not a7, a4
; RV32B-NEXT: srli t4, a3, 1
; RV32B-NEXT: srl t2, t4, a7
; RV32B-NEXT: addi a1, zero, 63
; RV32B-NEXT: andn t3, a1, a4
; RV32B-NEXT: addi a5, t3, -32
; RV32B-NEXT: srai a1, a5, 31
; RV32B-NEXT: and a1, a1, t2
; RV32B-NEXT: or a1, t0, a1
; RV32B-NEXT: fsri a2, a2, a3, 1
; RV32B-NEXT: srl a7, a2, a7
; RV32B-NEXT: sub a3, a6, t3
; RV32B-NEXT: slli a2, t4, 1
; RV32B-NEXT: sll a2, a2, a3
; RV32B-NEXT: or a2, a7, a2
; RV32B-NEXT: srl a3, t4, a5
; RV32B-NEXT: slti a5, a5, 0
; RV32B-NEXT: cmov a2, a5, a2, a3
; RV32B-NEXT: sll a0, a0, a4
; RV32B-NEXT: srai a3, t1, 31
; RV32B-NEXT: and a0, a3, a0
; RV32B-NEXT: or a0, a0, a2
; RV32B-NEXT: ret
;
; RV32ZBT-LABEL: fshl_i64: ; RV32ZBT-LABEL: fshl_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: sll a7, a1, a4 ; RV32ZBT-NEXT: sll a7, a1, a4
; RV32ZBT-NEXT: andi a5, a4, 63 ; RV32ZBT-NEXT: andi a5, a4, 63
; RV32ZBT-NEXT: addi a6, zero, 31 ; RV32ZBT-NEXT: addi a6, zero, 31
; RV32ZBT-NEXT: sub t0, a6, a5 ; RV32ZBT-NEXT: sub t0, a6, a5
; RV32ZBT-NEXT: srli a1, a0, 1 ; RV32ZBT-NEXT: srli a1, a0, 1
; RV32ZBT-NEXT: srl a1, a1, t0 ; RV32ZBT-NEXT: srl a1, a1, t0
Show All 35 Lines
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srl a1, a1, a2 ; RV32I-NEXT: srl a1, a1, a2
; RV32I-NEXT: not a2, a2 ; RV32I-NEXT: not a2, a2
; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: sll a0, a0, a2 ; RV32I-NEXT: sll a0, a0, a2
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: fshr_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: andi a2, a2, 31
; RV32B-NEXT: fsr a0, a1, a0, a2
; RV32B-NEXT: ret
;
; RV32ZBT-LABEL: fshr_i32: ; RV32ZBT-LABEL: fshr_i32:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: andi a2, a2, 31 ; RV32ZBT-NEXT: andi a2, a2, 31
; RV32ZBT-NEXT: fsr a0, a1, a0, a2 ; RV32ZBT-NEXT: fsr a0, a1, a0, a2
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c) %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)
ret i32 %1 ret i32 %1
} }
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: bgez a6, .LBB15_7 ; RV32I-NEXT: bgez a6, .LBB15_7
; RV32I-NEXT: .LBB15_6: ; RV32I-NEXT: .LBB15_6:
; RV32I-NEXT: srl a2, a3, a4 ; RV32I-NEXT: srl a2, a3, a4
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: .LBB15_7: ; RV32I-NEXT: .LBB15_7:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: fshr_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: srl a7, a2, a4
; RV32B-NEXT: andi a5, a4, 63
; RV32B-NEXT: addi a6, zero, 31
; RV32B-NEXT: sub t0, a6, a5
; RV32B-NEXT: slli a2, a3, 1
; RV32B-NEXT: sll a2, a2, t0
; RV32B-NEXT: or a7, a7, a2
; RV32B-NEXT: addi t2, a5, -32
; RV32B-NEXT: srl t0, a3, t2
; RV32B-NEXT: slti a2, t2, 0
; RV32B-NEXT: cmov a7, a2, a7, t0
; RV32B-NEXT: not t3, a4
; RV32B-NEXT: slli t0, a0, 1
; RV32B-NEXT: sll t1, t0, t3
; RV32B-NEXT: addi a5, zero, 63
; RV32B-NEXT: andn t4, a5, a4
; RV32B-NEXT: addi a2, t4, -32
; RV32B-NEXT: srai a5, a2, 31
; RV32B-NEXT: and a5, a5, t1
; RV32B-NEXT: or a7, a5, a7
; RV32B-NEXT: fsri a1, a0, a1, 31
; RV32B-NEXT: sll a1, a1, t3
; RV32B-NEXT: sub a5, a6, t4
; RV32B-NEXT: bclri a0, a0, 31
; RV32B-NEXT: srl a0, a0, a5
; RV32B-NEXT: or a0, a1, a0
; RV32B-NEXT: sll a1, t0, a2
; RV32B-NEXT: slti a2, a2, 0
; RV32B-NEXT: cmov a0, a2, a0, a1
; RV32B-NEXT: srl a1, a3, a4
; RV32B-NEXT: srai a2, t2, 31
; RV32B-NEXT: and a1, a2, a1
; RV32B-NEXT: or a1, a0, a1
; RV32B-NEXT: mv a0, a7
; RV32B-NEXT: ret
;
; RV32ZBT-LABEL: fshr_i64: ; RV32ZBT-LABEL: fshr_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: srl a7, a2, a4 ; RV32ZBT-NEXT: srl a7, a2, a4
; RV32ZBT-NEXT: andi a5, a4, 63 ; RV32ZBT-NEXT: andi a5, a4, 63
; RV32ZBT-NEXT: addi a6, zero, 31 ; RV32ZBT-NEXT: addi a6, zero, 31
; RV32ZBT-NEXT: sub t0, a6, a5 ; RV32ZBT-NEXT: sub t0, a6, a5
; RV32ZBT-NEXT: slli a2, a3, 1 ; RV32ZBT-NEXT: slli a2, a3, 1
; RV32ZBT-NEXT: sll a2, a2, t0 ; RV32ZBT-NEXT: sll a2, a2, t0
Show All 34 Lines
define i32 @fshri_i32(i32 %a, i32 %b) nounwind { define i32 @fshri_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: fshri_i32: ; RV32I-LABEL: fshri_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a1, a1, 5 ; RV32I-NEXT: srli a1, a1, 5
; RV32I-NEXT: slli a0, a0, 27 ; RV32I-NEXT: slli a0, a0, 27
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: fshri_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: fsri a0, a1, a0, 5
; RV32B-NEXT: ret
;
; RV32ZBT-LABEL: fshri_i32: ; RV32ZBT-LABEL: fshri_i32:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: fsri a0, a1, a0, 5 ; RV32ZBT-NEXT: fsri a0, a1, a0, 5
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 5) %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 5)
ret i32 %1 ret i32 %1
} }
define i64 @fshri_i64(i64 %a, i64 %b) nounwind { define i64 @fshri_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: fshri_i64: ; RV32I-LABEL: fshri_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a3, 27 ; RV32I-NEXT: slli a1, a3, 27
; RV32I-NEXT: srli a2, a2, 5 ; RV32I-NEXT: srli a2, a2, 5
; RV32I-NEXT: or a2, a2, a1 ; RV32I-NEXT: or a2, a2, a1
; RV32I-NEXT: srli a1, a3, 5 ; RV32I-NEXT: srli a1, a3, 5
; RV32I-NEXT: slli a0, a0, 27 ; RV32I-NEXT: slli a0, a0, 27
; RV32I-NEXT: or a1, a0, a1 ; RV32I-NEXT: or a1, a0, a1
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: fshri_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: fsri a2, a2, a3, 5
; RV32B-NEXT: fsri a1, a3, a0, 5
; RV32B-NEXT: mv a0, a2
; RV32B-NEXT: ret
;
; RV32ZBT-LABEL: fshri_i64: ; RV32ZBT-LABEL: fshri_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: fsri a2, a2, a3, 5 ; RV32ZBT-NEXT: fsri a2, a2, a3, 5
; RV32ZBT-NEXT: fsri a1, a3, a0, 5 ; RV32ZBT-NEXT: fsri a1, a3, a0, 5
; RV32ZBT-NEXT: mv a0, a2 ; RV32ZBT-NEXT: mv a0, a2
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 5) %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 5)
ret i64 %1 ret i64 %1
} }
define i32 @fshli_i32(i32 %a, i32 %b) nounwind { define i32 @fshli_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: fshli_i32: ; RV32I-LABEL: fshli_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a1, a1, 27 ; RV32I-NEXT: srli a1, a1, 27
; RV32I-NEXT: slli a0, a0, 5 ; RV32I-NEXT: slli a0, a0, 5
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: fshli_i32:
; RV32B: # %bb.0:
; RV32B-NEXT: fsri a0, a1, a0, 27
; RV32B-NEXT: ret
;
; RV32ZBT-LABEL: fshli_i32: ; RV32ZBT-LABEL: fshli_i32:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: fsri a0, a1, a0, 27 ; RV32ZBT-NEXT: fsri a0, a1, a0, 27
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 5) %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 5)
ret i32 %1 ret i32 %1
} }
define i64 @fshli_i64(i64 %a, i64 %b) nounwind { define i64 @fshli_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: fshli_i64: ; RV32I-LABEL: fshli_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a2, a3, 27 ; RV32I-NEXT: srli a2, a3, 27
; RV32I-NEXT: slli a3, a0, 5 ; RV32I-NEXT: slli a3, a0, 5
; RV32I-NEXT: or a2, a3, a2 ; RV32I-NEXT: or a2, a3, a2
; RV32I-NEXT: srli a0, a0, 27 ; RV32I-NEXT: srli a0, a0, 27
; RV32I-NEXT: slli a1, a1, 5 ; RV32I-NEXT: slli a1, a1, 5
; RV32I-NEXT: or a1, a1, a0 ; RV32I-NEXT: or a1, a1, a0
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32B-LABEL: fshli_i64:
; RV32B: # %bb.0:
; RV32B-NEXT: fsri a2, a3, a0, 27
; RV32B-NEXT: fsri a1, a0, a1, 27
; RV32B-NEXT: mv a0, a2
; RV32B-NEXT: ret
;
; RV32ZBT-LABEL: fshli_i64: ; RV32ZBT-LABEL: fshli_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: fsri a2, a3, a0, 27 ; RV32ZBT-NEXT: fsri a2, a3, a0, 27
; RV32ZBT-NEXT: fsri a1, a0, a1, 27 ; RV32ZBT-NEXT: fsri a1, a0, a1, 27
; RV32ZBT-NEXT: mv a0, a2 ; RV32ZBT-NEXT: mv a0, a2
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 5) %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 5)
ret i64 %1 ret i64 %1
} }

llvm/test/CodeGen/RISCV/rv64zba.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I ; RUN: | FileCheck %s -check-prefix=RV64I
; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64B
; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-zba -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-zba -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBA ; RUN: | FileCheck %s -check-prefix=RV64ZBA
define i64 @slliuw(i64 %a) nounwind { define i64 @slliuw(i64 %a) nounwind {
; RV64I-LABEL: slliuw: ; RV64I-LABEL: slliuw:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 31 ; RV64I-NEXT: srli a0, a0, 31
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: slliuw:
; RV64B: # %bb.0:
; RV64B-NEXT: slli.uw a0, a0, 1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: slliuw: ; RV64ZBA-LABEL: slliuw:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli.uw a0, a0, 1 ; RV64ZBA-NEXT: slli.uw a0, a0, 1
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%conv1 = shl i64 %a, 1 %conv1 = shl i64 %a, 1
%shl = and i64 %conv1, 8589934590 %shl = and i64 %conv1, 8589934590
ret i64 %shl ret i64 %shl
} }
define i128 @slliuw_2(i32 signext %0, i128* %1) { define i128 @slliuw_2(i32 signext %0, i128* %1) {
; RV64I-LABEL: slliuw_2: ; RV64I-LABEL: slliuw_2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 28 ; RV64I-NEXT: srli a0, a0, 28
; RV64I-NEXT: add a1, a1, a0 ; RV64I-NEXT: add a1, a1, a0
; RV64I-NEXT: ld a0, 0(a1) ; RV64I-NEXT: ld a0, 0(a1)
; RV64I-NEXT: ld a1, 8(a1) ; RV64I-NEXT: ld a1, 8(a1)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: slliuw_2:
; RV64B: # %bb.0:
; RV64B-NEXT: slli.uw a0, a0, 4
; RV64B-NEXT: add a1, a1, a0
; RV64B-NEXT: ld a0, 0(a1)
; RV64B-NEXT: ld a1, 8(a1)
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: slliuw_2: ; RV64ZBA-LABEL: slliuw_2:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli.uw a0, a0, 4 ; RV64ZBA-NEXT: slli.uw a0, a0, 4
; RV64ZBA-NEXT: add a1, a1, a0 ; RV64ZBA-NEXT: add a1, a1, a0
; RV64ZBA-NEXT: ld a0, 0(a1) ; RV64ZBA-NEXT: ld a0, 0(a1)
; RV64ZBA-NEXT: ld a1, 8(a1) ; RV64ZBA-NEXT: ld a1, 8(a1)
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%3 = zext i32 %0 to i64 %3 = zext i32 %0 to i64
%4 = getelementptr inbounds i128, i128* %1, i64 %3 %4 = getelementptr inbounds i128, i128* %1, i64 %3
%5 = load i128, i128* %4 %5 = load i128, i128* %4
ret i128 %5 ret i128 %5
} }
define i64 @adduw(i64 %a, i64 %b) nounwind { define i64 @adduw(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: adduw: ; RV64I-LABEL: adduw:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a1, 32 ; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a1, a1, 32 ; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: adduw:
; RV64B: # %bb.0:
; RV64B-NEXT: add.uw a0, a1, a0
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: adduw: ; RV64ZBA-LABEL: adduw:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: add.uw a0, a1, a0 ; RV64ZBA-NEXT: add.uw a0, a1, a0
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%and = and i64 %b, 4294967295 %and = and i64 %b, 4294967295
%add = add i64 %and, %a %add = add i64 %and, %a
ret i64 %add ret i64 %add
} }
define signext i8 @adduw_2(i32 signext %0, i8* %1) { define signext i8 @adduw_2(i32 signext %0, i8* %1) {
; RV64I-LABEL: adduw_2: ; RV64I-LABEL: adduw_2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: lb a0, 0(a0) ; RV64I-NEXT: lb a0, 0(a0)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: adduw_2:
; RV64B: # %bb.0:
; RV64B-NEXT: add.uw a0, a0, a1
; RV64B-NEXT: lb a0, 0(a0)
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: adduw_2: ; RV64ZBA-LABEL: adduw_2:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: add.uw a0, a0, a1 ; RV64ZBA-NEXT: add.uw a0, a0, a1
; RV64ZBA-NEXT: lb a0, 0(a0) ; RV64ZBA-NEXT: lb a0, 0(a0)
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%3 = zext i32 %0 to i64 %3 = zext i32 %0 to i64
%4 = getelementptr inbounds i8, i8* %1, i64 %3 %4 = getelementptr inbounds i8, i8* %1, i64 %3
%5 = load i8, i8* %4 %5 = load i8, i8* %4
ret i8 %5 ret i8 %5
} }
define i64 @zextw_i64(i64 %a) nounwind { define i64 @zextw_i64(i64 %a) nounwind {
; RV64I-LABEL: zextw_i64: ; RV64I-LABEL: zextw_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: zextw_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: zext.w a0, a0
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: zextw_i64: ; RV64ZBA-LABEL: zextw_i64:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: zext.w a0, a0 ; RV64ZBA-NEXT: zext.w a0, a0
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%and = and i64 %a, 4294967295 %and = and i64 %a, 4294967295
ret i64 %and ret i64 %and
} }
; This makes sure targetShrinkDemandedConstant changes the and immmediate to ; This makes sure targetShrinkDemandedConstant changes the and immmediate to
; allow zext.w or slli+srli. ; allow zext.w or slli+srli.
define i64 @zextw_demandedbits_i64(i64 %0) { define i64 @zextw_demandedbits_i64(i64 %0) {
; RV64I-LABEL: zextw_demandedbits_i64: ; RV64I-LABEL: zextw_demandedbits_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: ori a0, a0, 1 ; RV64I-NEXT: ori a0, a0, 1
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: zextw_demandedbits_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: ori a0, a0, 1
; RV64B-NEXT: zext.w a0, a0
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: zextw_demandedbits_i64: ; RV64ZBA-LABEL: zextw_demandedbits_i64:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: ori a0, a0, 1 ; RV64ZBA-NEXT: ori a0, a0, 1
; RV64ZBA-NEXT: zext.w a0, a0 ; RV64ZBA-NEXT: zext.w a0, a0
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%2 = and i64 %0, 4294967294 %2 = and i64 %0, 4294967294
%3 = or i64 %2, 1 %3 = or i64 %2, 1
ret i64 %3 ret i64 %3
} }
define signext i16 @sh1add(i64 %0, i16* %1) { define signext i16 @sh1add(i64 %0, i16* %1) {
; RV64I-LABEL: sh1add: ; RV64I-LABEL: sh1add:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 1 ; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: lh a0, 0(a0) ; RV64I-NEXT: lh a0, 0(a0)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sh1add:
; RV64B: # %bb.0:
; RV64B-NEXT: sh1add a0, a0, a1
; RV64B-NEXT: lh a0, 0(a0)
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: sh1add: ; RV64ZBA-LABEL: sh1add:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add a0, a0, a1 ; RV64ZBA-NEXT: sh1add a0, a0, a1
; RV64ZBA-NEXT: lh a0, 0(a0) ; RV64ZBA-NEXT: lh a0, 0(a0)
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%3 = getelementptr inbounds i16, i16* %1, i64 %0 %3 = getelementptr inbounds i16, i16* %1, i64 %0
%4 = load i16, i16* %3 %4 = load i16, i16* %3
ret i16 %4 ret i16 %4
} }
define signext i32 @sh2add(i64 %0, i32* %1) { define signext i32 @sh2add(i64 %0, i32* %1) {
; RV64I-LABEL: sh2add: ; RV64I-LABEL: sh2add:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 2 ; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: lw a0, 0(a0) ; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sh2add:
; RV64B: # %bb.0:
; RV64B-NEXT: sh2add a0, a0, a1
; RV64B-NEXT: lw a0, 0(a0)
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: sh2add: ; RV64ZBA-LABEL: sh2add:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a0, a0, a1 ; RV64ZBA-NEXT: sh2add a0, a0, a1
; RV64ZBA-NEXT: lw a0, 0(a0) ; RV64ZBA-NEXT: lw a0, 0(a0)
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%3 = getelementptr inbounds i32, i32* %1, i64 %0 %3 = getelementptr inbounds i32, i32* %1, i64 %0
%4 = load i32, i32* %3 %4 = load i32, i32* %3
ret i32 %4 ret i32 %4
} }
define i64 @sh3add(i64 %0, i64* %1) { define i64 @sh3add(i64 %0, i64* %1) {
; RV64I-LABEL: sh3add: ; RV64I-LABEL: sh3add:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 3 ; RV64I-NEXT: slli a0, a0, 3
; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ld a0, 0(a0) ; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sh3add:
; RV64B: # %bb.0:
; RV64B-NEXT: sh3add a0, a0, a1
; RV64B-NEXT: ld a0, 0(a0)
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: sh3add: ; RV64ZBA-LABEL: sh3add:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a0, a1 ; RV64ZBA-NEXT: sh3add a0, a0, a1
; RV64ZBA-NEXT: ld a0, 0(a0) ; RV64ZBA-NEXT: ld a0, 0(a0)
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%3 = getelementptr inbounds i64, i64* %1, i64 %0 %3 = getelementptr inbounds i64, i64* %1, i64 %0
%4 = load i64, i64* %3 %4 = load i64, i64* %3
ret i64 %4 ret i64 %4
} }
define signext i16 @sh1adduw(i32 signext %0, i16* %1) { define signext i16 @sh1adduw(i32 signext %0, i16* %1) {
; RV64I-LABEL: sh1adduw: ; RV64I-LABEL: sh1adduw:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 31 ; RV64I-NEXT: srli a0, a0, 31
; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: lh a0, 0(a0) ; RV64I-NEXT: lh a0, 0(a0)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sh1adduw:
; RV64B: # %bb.0:
; RV64B-NEXT: sh1add.uw a0, a0, a1
; RV64B-NEXT: lh a0, 0(a0)
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: sh1adduw: ; RV64ZBA-LABEL: sh1adduw:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add.uw a0, a0, a1 ; RV64ZBA-NEXT: sh1add.uw a0, a0, a1
; RV64ZBA-NEXT: lh a0, 0(a0) ; RV64ZBA-NEXT: lh a0, 0(a0)
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%3 = zext i32 %0 to i64 %3 = zext i32 %0 to i64
%4 = getelementptr inbounds i16, i16* %1, i64 %3 %4 = getelementptr inbounds i16, i16* %1, i64 %3
%5 = load i16, i16* %4 %5 = load i16, i16* %4
ret i16 %5 ret i16 %5
} }
define i64 @sh1adduw_2(i64 %0, i64 %1) { define i64 @sh1adduw_2(i64 %0, i64 %1) {
; RV64I-LABEL: sh1adduw_2: ; RV64I-LABEL: sh1adduw_2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 31 ; RV64I-NEXT: srli a0, a0, 31
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sh1adduw_2:
; RV64B: # %bb.0:
; RV64B-NEXT: sh1add.uw a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: sh1adduw_2: ; RV64ZBA-LABEL: sh1adduw_2:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add.uw a0, a0, a1 ; RV64ZBA-NEXT: sh1add.uw a0, a0, a1
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%3 = shl i64 %0, 1 %3 = shl i64 %0, 1
%4 = and i64 %3, 8589934590 %4 = and i64 %3, 8589934590
%5 = add i64 %4, %1 %5 = add i64 %4, %1
ret i64 %5 ret i64 %5
} }
define signext i32 @sh2adduw(i32 signext %0, i32* %1) { define signext i32 @sh2adduw(i32 signext %0, i32* %1) {
; RV64I-LABEL: sh2adduw: ; RV64I-LABEL: sh2adduw:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 30 ; RV64I-NEXT: srli a0, a0, 30
; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: lw a0, 0(a0) ; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sh2adduw:
; RV64B: # %bb.0:
; RV64B-NEXT: sh2add.uw a0, a0, a1
; RV64B-NEXT: lw a0, 0(a0)
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: sh2adduw: ; RV64ZBA-LABEL: sh2adduw:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add.uw a0, a0, a1 ; RV64ZBA-NEXT: sh2add.uw a0, a0, a1
; RV64ZBA-NEXT: lw a0, 0(a0) ; RV64ZBA-NEXT: lw a0, 0(a0)
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%3 = zext i32 %0 to i64 %3 = zext i32 %0 to i64
%4 = getelementptr inbounds i32, i32* %1, i64 %3 %4 = getelementptr inbounds i32, i32* %1, i64 %3
%5 = load i32, i32* %4 %5 = load i32, i32* %4
ret i32 %5 ret i32 %5
} }
define i64 @sh2adduw_2(i64 %0, i64 %1) { define i64 @sh2adduw_2(i64 %0, i64 %1) {
; RV64I-LABEL: sh2adduw_2: ; RV64I-LABEL: sh2adduw_2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 30 ; RV64I-NEXT: srli a0, a0, 30
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sh2adduw_2:
; RV64B: # %bb.0:
; RV64B-NEXT: sh2add.uw a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: sh2adduw_2: ; RV64ZBA-LABEL: sh2adduw_2:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add.uw a0, a0, a1 ; RV64ZBA-NEXT: sh2add.uw a0, a0, a1
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%3 = shl i64 %0, 2 %3 = shl i64 %0, 2
%4 = and i64 %3, 17179869180 %4 = and i64 %3, 17179869180
%5 = add i64 %4, %1 %5 = add i64 %4, %1
ret i64 %5 ret i64 %5
} }
define i64 @sh3adduw(i32 signext %0, i64* %1) { define i64 @sh3adduw(i32 signext %0, i64* %1) {
; RV64I-LABEL: sh3adduw: ; RV64I-LABEL: sh3adduw:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 29 ; RV64I-NEXT: srli a0, a0, 29
; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ld a0, 0(a0) ; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sh3adduw:
; RV64B: # %bb.0:
; RV64B-NEXT: sh3add.uw a0, a0, a1
; RV64B-NEXT: ld a0, 0(a0)
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: sh3adduw: ; RV64ZBA-LABEL: sh3adduw:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add.uw a0, a0, a1 ; RV64ZBA-NEXT: sh3add.uw a0, a0, a1
; RV64ZBA-NEXT: ld a0, 0(a0) ; RV64ZBA-NEXT: ld a0, 0(a0)
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%3 = zext i32 %0 to i64 %3 = zext i32 %0 to i64
%4 = getelementptr inbounds i64, i64* %1, i64 %3 %4 = getelementptr inbounds i64, i64* %1, i64 %3
%5 = load i64, i64* %4 %5 = load i64, i64* %4
ret i64 %5 ret i64 %5
} }
define i64 @sh3adduw_2(i64 %0, i64 %1) { define i64 @sh3adduw_2(i64 %0, i64 %1) {
; RV64I-LABEL: sh3adduw_2: ; RV64I-LABEL: sh3adduw_2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 29 ; RV64I-NEXT: srli a0, a0, 29
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sh3adduw_2:
; RV64B: # %bb.0:
; RV64B-NEXT: sh3add.uw a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: sh3adduw_2: ; RV64ZBA-LABEL: sh3adduw_2:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add.uw a0, a0, a1 ; RV64ZBA-NEXT: sh3add.uw a0, a0, a1
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%3 = shl i64 %0, 3 %3 = shl i64 %0, 3
%4 = and i64 %3, 34359738360 %4 = and i64 %3, 34359738360
%5 = add i64 %4, %1 %5 = add i64 %4, %1
ret i64 %5 ret i64 %5
Show All 9 Lines
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slliw a0, a0, 2 ; RV64I-NEXT: slliw a0, a0, 2
; RV64I-NEXT: addw a0, a0, a1 ; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: sllw a1, a2, a0 ; RV64I-NEXT: sllw a1, a2, a0
; RV64I-NEXT: sraiw a0, a0, 2 ; RV64I-NEXT: sraiw a0, a0, 2
; RV64I-NEXT: mul a0, a1, a0 ; RV64I-NEXT: mul a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sh2add_extra_sext:
; RV64B: # %bb.0:
; RV64B-NEXT: sh2add a0, a0, a1
; RV64B-NEXT: sllw a1, a2, a0
; RV64B-NEXT: sraiw a0, a0, 2
; RV64B-NEXT: mul a0, a1, a0
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: sh2add_extra_sext: ; RV64ZBA-LABEL: sh2add_extra_sext:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a0, a0, a1 ; RV64ZBA-NEXT: sh2add a0, a0, a1
; RV64ZBA-NEXT: sllw a1, a2, a0 ; RV64ZBA-NEXT: sllw a1, a2, a0
; RV64ZBA-NEXT: sraiw a0, a0, 2 ; RV64ZBA-NEXT: sraiw a0, a0, 2
; RV64ZBA-NEXT: mul a0, a1, a0 ; RV64ZBA-NEXT: mul a0, a1, a0
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%a = shl i32 %x, 2 %a = shl i32 %x, 2
Show All 9 Lines
define i64 @addmul6(i64 %a, i64 %b) { define i64 @addmul6(i64 %a, i64 %b) {
; RV64I-LABEL: addmul6: ; RV64I-LABEL: addmul6:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 6 ; RV64I-NEXT: addi a2, zero, 6
; RV64I-NEXT: mul a0, a0, a2 ; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: addmul6:
; RV64B: # %bb.0:
; RV64B-NEXT: sh1add a0, a0, a0
; RV64B-NEXT: sh1add a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: addmul6: ; RV64ZBA-LABEL: addmul6:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add a0, a0, a0 ; RV64ZBA-NEXT: sh1add a0, a0, a0
; RV64ZBA-NEXT: sh1add a0, a0, a1 ; RV64ZBA-NEXT: sh1add a0, a0, a1
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 6 %c = mul i64 %a, 6
%d = add i64 %c, %b %d = add i64 %c, %b
ret i64 %d ret i64 %d
} }
define i64 @addmul10(i64 %a, i64 %b) { define i64 @addmul10(i64 %a, i64 %b) {
; RV64I-LABEL: addmul10: ; RV64I-LABEL: addmul10:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 10 ; RV64I-NEXT: addi a2, zero, 10
; RV64I-NEXT: mul a0, a0, a2 ; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: addmul10:
; RV64B: # %bb.0:
; RV64B-NEXT: sh2add a0, a0, a0
; RV64B-NEXT: sh1add a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: addmul10: ; RV64ZBA-LABEL: addmul10:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a0, a0, a0 ; RV64ZBA-NEXT: sh2add a0, a0, a0
; RV64ZBA-NEXT: sh1add a0, a0, a1 ; RV64ZBA-NEXT: sh1add a0, a0, a1
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 10 %c = mul i64 %a, 10
%d = add i64 %c, %b %d = add i64 %c, %b
ret i64 %d ret i64 %d
} }
define i64 @addmul12(i64 %a, i64 %b) { define i64 @addmul12(i64 %a, i64 %b) {
; RV64I-LABEL: addmul12: ; RV64I-LABEL: addmul12:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 12 ; RV64I-NEXT: addi a2, zero, 12
; RV64I-NEXT: mul a0, a0, a2 ; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: addmul12:
; RV64B: # %bb.0:
; RV64B-NEXT: sh1add a0, a0, a0
; RV64B-NEXT: sh2add a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: addmul12: ; RV64ZBA-LABEL: addmul12:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add a0, a0, a0 ; RV64ZBA-NEXT: sh1add a0, a0, a0
; RV64ZBA-NEXT: sh2add a0, a0, a1 ; RV64ZBA-NEXT: sh2add a0, a0, a1
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 12 %c = mul i64 %a, 12
%d = add i64 %c, %b %d = add i64 %c, %b
ret i64 %d ret i64 %d
} }
define i64 @addmul18(i64 %a, i64 %b) { define i64 @addmul18(i64 %a, i64 %b) {
; RV64I-LABEL: addmul18: ; RV64I-LABEL: addmul18:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 18 ; RV64I-NEXT: addi a2, zero, 18
; RV64I-NEXT: mul a0, a0, a2 ; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: addmul18:
; RV64B: # %bb.0:
; RV64B-NEXT: sh3add a0, a0, a0
; RV64B-NEXT: sh1add a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: addmul18: ; RV64ZBA-LABEL: addmul18:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a0, a0 ; RV64ZBA-NEXT: sh3add a0, a0, a0
; RV64ZBA-NEXT: sh1add a0, a0, a1 ; RV64ZBA-NEXT: sh1add a0, a0, a1
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 18 %c = mul i64 %a, 18
%d = add i64 %c, %b %d = add i64 %c, %b
ret i64 %d ret i64 %d
} }
define i64 @addmul20(i64 %a, i64 %b) { define i64 @addmul20(i64 %a, i64 %b) {
; RV64I-LABEL: addmul20: ; RV64I-LABEL: addmul20:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 20 ; RV64I-NEXT: addi a2, zero, 20
; RV64I-NEXT: mul a0, a0, a2 ; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: addmul20:
; RV64B: # %bb.0:
; RV64B-NEXT: sh2add a0, a0, a0
; RV64B-NEXT: sh2add a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: addmul20: ; RV64ZBA-LABEL: addmul20:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a0, a0, a0 ; RV64ZBA-NEXT: sh2add a0, a0, a0
; RV64ZBA-NEXT: sh2add a0, a0, a1 ; RV64ZBA-NEXT: sh2add a0, a0, a1
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 20 %c = mul i64 %a, 20
%d = add i64 %c, %b %d = add i64 %c, %b
ret i64 %d ret i64 %d
} }
define i64 @addmul24(i64 %a, i64 %b) { define i64 @addmul24(i64 %a, i64 %b) {
; RV64I-LABEL: addmul24: ; RV64I-LABEL: addmul24:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 24 ; RV64I-NEXT: addi a2, zero, 24
; RV64I-NEXT: mul a0, a0, a2 ; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: addmul24:
; RV64B: # %bb.0:
; RV64B-NEXT: sh1add a0, a0, a0
; RV64B-NEXT: sh3add a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: addmul24: ; RV64ZBA-LABEL: addmul24:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add a0, a0, a0 ; RV64ZBA-NEXT: sh1add a0, a0, a0
; RV64ZBA-NEXT: sh3add a0, a0, a1 ; RV64ZBA-NEXT: sh3add a0, a0, a1
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 24 %c = mul i64 %a, 24
%d = add i64 %c, %b %d = add i64 %c, %b
ret i64 %d ret i64 %d
} }
define i64 @addmul36(i64 %a, i64 %b) { define i64 @addmul36(i64 %a, i64 %b) {
; RV64I-LABEL: addmul36: ; RV64I-LABEL: addmul36:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 36 ; RV64I-NEXT: addi a2, zero, 36
; RV64I-NEXT: mul a0, a0, a2 ; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: addmul36:
; RV64B: # %bb.0:
; RV64B-NEXT: sh3add a0, a0, a0
; RV64B-NEXT: sh2add a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: addmul36: ; RV64ZBA-LABEL: addmul36:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a0, a0 ; RV64ZBA-NEXT: sh3add a0, a0, a0
; RV64ZBA-NEXT: sh2add a0, a0, a1 ; RV64ZBA-NEXT: sh2add a0, a0, a1
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 36 %c = mul i64 %a, 36
%d = add i64 %c, %b %d = add i64 %c, %b
ret i64 %d ret i64 %d
} }
define i64 @addmul40(i64 %a, i64 %b) { define i64 @addmul40(i64 %a, i64 %b) {
; RV64I-LABEL: addmul40: ; RV64I-LABEL: addmul40:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 40 ; RV64I-NEXT: addi a2, zero, 40
; RV64I-NEXT: mul a0, a0, a2 ; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: addmul40:
; RV64B: # %bb.0:
; RV64B-NEXT: sh2add a0, a0, a0
; RV64B-NEXT: sh3add a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: addmul40: ; RV64ZBA-LABEL: addmul40:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a0, a0, a0 ; RV64ZBA-NEXT: sh2add a0, a0, a0
; RV64ZBA-NEXT: sh3add a0, a0, a1 ; RV64ZBA-NEXT: sh3add a0, a0, a1
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 40 %c = mul i64 %a, 40
%d = add i64 %c, %b %d = add i64 %c, %b
ret i64 %d ret i64 %d
} }
define i64 @addmul72(i64 %a, i64 %b) { define i64 @addmul72(i64 %a, i64 %b) {
; RV64I-LABEL: addmul72: ; RV64I-LABEL: addmul72:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 72 ; RV64I-NEXT: addi a2, zero, 72
; RV64I-NEXT: mul a0, a0, a2 ; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: addmul72:
; RV64B: # %bb.0:
; RV64B-NEXT: sh3add a0, a0, a0
; RV64B-NEXT: sh3add a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: addmul72: ; RV64ZBA-LABEL: addmul72:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a0, a0 ; RV64ZBA-NEXT: sh3add a0, a0, a0
; RV64ZBA-NEXT: sh3add a0, a0, a1 ; RV64ZBA-NEXT: sh3add a0, a0, a1
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 72 %c = mul i64 %a, 72
%d = add i64 %c, %b %d = add i64 %c, %b
ret i64 %d ret i64 %d
} }
define i64 @mul96(i64 %a) { define i64 @mul96(i64 %a) {
; RV64I-LABEL: mul96: ; RV64I-LABEL: mul96:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 96 ; RV64I-NEXT: addi a1, zero, 96
; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mul96:
; RV64B: # %bb.0:
; RV64B-NEXT: sh1add a0, a0, a0
; RV64B-NEXT: slli a0, a0, 5
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mul96: ; RV64ZBA-LABEL: mul96:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add a0, a0, a0 ; RV64ZBA-NEXT: sh1add a0, a0, a0
; RV64ZBA-NEXT: slli a0, a0, 5 ; RV64ZBA-NEXT: slli a0, a0, 5
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 96 %c = mul i64 %a, 96
ret i64 %c ret i64 %c
} }
define i64 @mul160(i64 %a) { define i64 @mul160(i64 %a) {
; RV64I-LABEL: mul160: ; RV64I-LABEL: mul160:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 160 ; RV64I-NEXT: addi a1, zero, 160
; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mul160:
; RV64B: # %bb.0:
; RV64B-NEXT: sh2add a0, a0, a0
; RV64B-NEXT: slli a0, a0, 5
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mul160: ; RV64ZBA-LABEL: mul160:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a0, a0, a0 ; RV64ZBA-NEXT: sh2add a0, a0, a0
; RV64ZBA-NEXT: slli a0, a0, 5 ; RV64ZBA-NEXT: slli a0, a0, 5
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 160 %c = mul i64 %a, 160
ret i64 %c ret i64 %c
} }
define i64 @mul288(i64 %a) { define i64 @mul288(i64 %a) {
; RV64I-LABEL: mul288: ; RV64I-LABEL: mul288:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 288 ; RV64I-NEXT: addi a1, zero, 288
; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mul288:
; RV64B: # %bb.0:
; RV64B-NEXT: sh3add a0, a0, a0
; RV64B-NEXT: slli a0, a0, 5
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mul288: ; RV64ZBA-LABEL: mul288:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a0, a0 ; RV64ZBA-NEXT: sh3add a0, a0, a0
; RV64ZBA-NEXT: slli a0, a0, 5 ; RV64ZBA-NEXT: slli a0, a0, 5
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 288 %c = mul i64 %a, 288
ret i64 %c ret i64 %c
} }
define i64 @sh1add_imm(i64 %0) { define i64 @sh1add_imm(i64 %0) {
; RV64I-LABEL: sh1add_imm: ; RV64I-LABEL: sh1add_imm:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 1 ; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: addi a0, a0, 5 ; RV64I-NEXT: addi a0, a0, 5
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sh1add_imm:
; RV64B: # %bb.0:
; RV64B-NEXT: slli a0, a0, 1
; RV64B-NEXT: addi a0, a0, 5
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: sh1add_imm: ; RV64ZBA-LABEL: sh1add_imm:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli a0, a0, 1 ; RV64ZBA-NEXT: slli a0, a0, 1
; RV64ZBA-NEXT: addi a0, a0, 5 ; RV64ZBA-NEXT: addi a0, a0, 5
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%a = shl i64 %0, 1 %a = shl i64 %0, 1
%b = add i64 %a, 5 %b = add i64 %a, 5
ret i64 %b ret i64 %b
} }
define i64 @sh2add_imm(i64 %0) { define i64 @sh2add_imm(i64 %0) {
; RV64I-LABEL: sh2add_imm: ; RV64I-LABEL: sh2add_imm:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 2 ; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: addi a0, a0, -6 ; RV64I-NEXT: addi a0, a0, -6
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sh2add_imm:
; RV64B: # %bb.0:
; RV64B-NEXT: slli a0, a0, 2
; RV64B-NEXT: addi a0, a0, -6
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: sh2add_imm: ; RV64ZBA-LABEL: sh2add_imm:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli a0, a0, 2 ; RV64ZBA-NEXT: slli a0, a0, 2
; RV64ZBA-NEXT: addi a0, a0, -6 ; RV64ZBA-NEXT: addi a0, a0, -6
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%a = shl i64 %0, 2 %a = shl i64 %0, 2
%b = add i64 %a, -6 %b = add i64 %a, -6
ret i64 %b ret i64 %b
} }
define i64 @sh3add_imm(i64 %0) { define i64 @sh3add_imm(i64 %0) {
; RV64I-LABEL: sh3add_imm: ; RV64I-LABEL: sh3add_imm:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 3 ; RV64I-NEXT: slli a0, a0, 3
; RV64I-NEXT: ori a0, a0, 7 ; RV64I-NEXT: ori a0, a0, 7
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sh3add_imm:
; RV64B: # %bb.0:
; RV64B-NEXT: slli a0, a0, 3
; RV64B-NEXT: ori a0, a0, 7
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: sh3add_imm: ; RV64ZBA-LABEL: sh3add_imm:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli a0, a0, 3 ; RV64ZBA-NEXT: slli a0, a0, 3
; RV64ZBA-NEXT: ori a0, a0, 7 ; RV64ZBA-NEXT: ori a0, a0, 7
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%a = shl i64 %0, 3 %a = shl i64 %0, 3
%b = add i64 %a, 7 %b = add i64 %a, 7
ret i64 %b ret i64 %b
} }
define i64 @sh1adduw_imm(i32 signext %0) { define i64 @sh1adduw_imm(i32 signext %0) {
; RV64I-LABEL: sh1adduw_imm: ; RV64I-LABEL: sh1adduw_imm:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 31 ; RV64I-NEXT: srli a0, a0, 31
; RV64I-NEXT: addi a0, a0, 11 ; RV64I-NEXT: addi a0, a0, 11
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sh1adduw_imm:
; RV64B: # %bb.0:
; RV64B-NEXT: slli.uw a0, a0, 1
; RV64B-NEXT: addi a0, a0, 11
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: sh1adduw_imm: ; RV64ZBA-LABEL: sh1adduw_imm:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli.uw a0, a0, 1 ; RV64ZBA-NEXT: slli.uw a0, a0, 1
; RV64ZBA-NEXT: addi a0, a0, 11 ; RV64ZBA-NEXT: addi a0, a0, 11
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%a = zext i32 %0 to i64 %a = zext i32 %0 to i64
%b = shl i64 %a, 1 %b = shl i64 %a, 1
%c = add i64 %b, 11 %c = add i64 %b, 11
ret i64 %c ret i64 %c
} }
define i64 @sh2adduw_imm(i32 signext %0) { define i64 @sh2adduw_imm(i32 signext %0) {
; RV64I-LABEL: sh2adduw_imm: ; RV64I-LABEL: sh2adduw_imm:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 30 ; RV64I-NEXT: srli a0, a0, 30
; RV64I-NEXT: addi a0, a0, -12 ; RV64I-NEXT: addi a0, a0, -12
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sh2adduw_imm:
; RV64B: # %bb.0:
; RV64B-NEXT: slli.uw a0, a0, 2
; RV64B-NEXT: addi a0, a0, -12
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: sh2adduw_imm: ; RV64ZBA-LABEL: sh2adduw_imm:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli.uw a0, a0, 2 ; RV64ZBA-NEXT: slli.uw a0, a0, 2
; RV64ZBA-NEXT: addi a0, a0, -12 ; RV64ZBA-NEXT: addi a0, a0, -12
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%a = zext i32 %0 to i64 %a = zext i32 %0 to i64
%b = shl i64 %a, 2 %b = shl i64 %a, 2
%c = add i64 %b, -12 %c = add i64 %b, -12
ret i64 %c ret i64 %c
} }
define i64 @sh3adduw_imm(i32 signext %0) { define i64 @sh3adduw_imm(i32 signext %0) {
; RV64I-LABEL: sh3adduw_imm: ; RV64I-LABEL: sh3adduw_imm:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 29 ; RV64I-NEXT: srli a0, a0, 29
; RV64I-NEXT: addi a0, a0, 13 ; RV64I-NEXT: addi a0, a0, 13
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sh3adduw_imm:
; RV64B: # %bb.0:
; RV64B-NEXT: slli.uw a0, a0, 3
; RV64B-NEXT: addi a0, a0, 13
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: sh3adduw_imm: ; RV64ZBA-LABEL: sh3adduw_imm:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli.uw a0, a0, 3 ; RV64ZBA-NEXT: slli.uw a0, a0, 3
; RV64ZBA-NEXT: addi a0, a0, 13 ; RV64ZBA-NEXT: addi a0, a0, 13
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%a = zext i32 %0 to i64 %a = zext i32 %0 to i64
%b = shl i64 %a, 3 %b = shl i64 %a, 3
%c = add i64 %b, 13 %c = add i64 %b, 13
ret i64 %c ret i64 %c
} }
define i64 @adduw_imm(i32 signext %0) nounwind { define i64 @adduw_imm(i32 signext %0) nounwind {
; RV64I-LABEL: adduw_imm: ; RV64I-LABEL: adduw_imm:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: addi a0, a0, 5 ; RV64I-NEXT: addi a0, a0, 5
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: adduw_imm:
; RV64B: # %bb.0:
; RV64B-NEXT: zext.w a0, a0
; RV64B-NEXT: addi a0, a0, 5
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: adduw_imm: ; RV64ZBA-LABEL: adduw_imm:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: zext.w a0, a0 ; RV64ZBA-NEXT: zext.w a0, a0
; RV64ZBA-NEXT: addi a0, a0, 5 ; RV64ZBA-NEXT: addi a0, a0, 5
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%a = zext i32 %0 to i64 %a = zext i32 %0 to i64
%b = add i64 %a, 5 %b = add i64 %a, 5
ret i64 %b ret i64 %b
} }
define i64 @mul258(i64 %a) { define i64 @mul258(i64 %a) {
; RV64I-LABEL: mul258: ; RV64I-LABEL: mul258:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 258 ; RV64I-NEXT: addi a1, zero, 258
; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mul258:
; RV64B: # %bb.0:
; RV64B-NEXT: addi a1, zero, 258
; RV64B-NEXT: mul a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mul258: ; RV64ZBA-LABEL: mul258:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addi a1, zero, 258 ; RV64ZBA-NEXT: addi a1, zero, 258
; RV64ZBA-NEXT: mul a0, a0, a1 ; RV64ZBA-NEXT: mul a0, a0, a1
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 258 %c = mul i64 %a, 258
ret i64 %c ret i64 %c
} }
define i64 @mul260(i64 %a) { define i64 @mul260(i64 %a) {
; RV64I-LABEL: mul260: ; RV64I-LABEL: mul260:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 260 ; RV64I-NEXT: addi a1, zero, 260
; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mul260:
; RV64B: # %bb.0:
; RV64B-NEXT: addi a1, zero, 260
; RV64B-NEXT: mul a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mul260: ; RV64ZBA-LABEL: mul260:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addi a1, zero, 260 ; RV64ZBA-NEXT: addi a1, zero, 260
; RV64ZBA-NEXT: mul a0, a0, a1 ; RV64ZBA-NEXT: mul a0, a0, a1
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 260 %c = mul i64 %a, 260
ret i64 %c ret i64 %c
} }
define i64 @mul264(i64 %a) { define i64 @mul264(i64 %a) {
; RV64I-LABEL: mul264: ; RV64I-LABEL: mul264:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 264 ; RV64I-NEXT: addi a1, zero, 264
; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mul264:
; RV64B: # %bb.0:
; RV64B-NEXT: addi a1, zero, 264
; RV64B-NEXT: mul a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mul264: ; RV64ZBA-LABEL: mul264:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addi a1, zero, 264 ; RV64ZBA-NEXT: addi a1, zero, 264
; RV64ZBA-NEXT: mul a0, a0, a1 ; RV64ZBA-NEXT: mul a0, a0, a1
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 264 %c = mul i64 %a, 264
ret i64 %c ret i64 %c
} }
define i64 @imm_zextw() nounwind { define i64 @imm_zextw() nounwind {
; RV64I-LABEL: imm_zextw: ; RV64I-LABEL: imm_zextw:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, zero, 1 ; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: addi a0, a0, -2 ; RV64I-NEXT: addi a0, a0, -2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: imm_zextw:
; RV64B: # %bb.0:
; RV64B-NEXT: addi a0, zero, -2
; RV64B-NEXT: zext.w a0, a0
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: imm_zextw: ; RV64ZBA-LABEL: imm_zextw:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addi a0, zero, -2 ; RV64ZBA-NEXT: addi a0, zero, -2
; RV64ZBA-NEXT: zext.w a0, a0 ; RV64ZBA-NEXT: zext.w a0, a0
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
ret i64 4294967294 ; -2 in 32 bits. ret i64 4294967294 ; -2 in 32 bits.
} }
define i64 @imm_zextw2() nounwind { define i64 @imm_zextw2() nounwind {
; RV64I-LABEL: imm_zextw2: ; RV64I-LABEL: imm_zextw2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a0, 171 ; RV64I-NEXT: lui a0, 171
; RV64I-NEXT: addiw a0, a0, -1365 ; RV64I-NEXT: addiw a0, a0, -1365
; RV64I-NEXT: slli a0, a0, 12 ; RV64I-NEXT: slli a0, a0, 12
; RV64I-NEXT: addi a0, a0, -1366 ; RV64I-NEXT: addi a0, a0, -1366
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: imm_zextw2:
; RV64B: # %bb.0:
; RV64B-NEXT: lui a0, 699051
; RV64B-NEXT: addiw a0, a0, -1366
; RV64B-NEXT: zext.w a0, a0
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: imm_zextw2: ; RV64ZBA-LABEL: imm_zextw2:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: lui a0, 699051 ; RV64ZBA-NEXT: lui a0, 699051
; RV64ZBA-NEXT: addiw a0, a0, -1366 ; RV64ZBA-NEXT: addiw a0, a0, -1366
; RV64ZBA-NEXT: zext.w a0, a0 ; RV64ZBA-NEXT: zext.w a0, a0
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
ret i64 2863311530 ; 0xAAAAAAAA ret i64 2863311530 ; 0xAAAAAAAA
} }
define i64 @mul11(i64 %a) { define i64 @mul11(i64 %a) {
; RV64I-LABEL: mul11: ; RV64I-LABEL: mul11:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 11 ; RV64I-NEXT: addi a1, zero, 11
; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mul11:
; RV64B: # %bb.0:
; RV64B-NEXT: sh2add a1, a0, a0
; RV64B-NEXT: sh1add a0, a1, a0
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mul11: ; RV64ZBA-LABEL: mul11:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a1, a0, a0 ; RV64ZBA-NEXT: sh2add a1, a0, a0
; RV64ZBA-NEXT: sh1add a0, a1, a0 ; RV64ZBA-NEXT: sh1add a0, a1, a0
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 11 %c = mul i64 %a, 11
ret i64 %c ret i64 %c
} }
define i64 @mul19(i64 %a) { define i64 @mul19(i64 %a) {
; RV64I-LABEL: mul19: ; RV64I-LABEL: mul19:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 19 ; RV64I-NEXT: addi a1, zero, 19
; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mul19:
; RV64B: # %bb.0:
; RV64B-NEXT: sh3add a1, a0, a0
; RV64B-NEXT: sh1add a0, a1, a0
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mul19: ; RV64ZBA-LABEL: mul19:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a1, a0, a0 ; RV64ZBA-NEXT: sh3add a1, a0, a0
; RV64ZBA-NEXT: sh1add a0, a1, a0 ; RV64ZBA-NEXT: sh1add a0, a1, a0
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 19 %c = mul i64 %a, 19
ret i64 %c ret i64 %c
} }
define i64 @mul13(i64 %a) { define i64 @mul13(i64 %a) {
; RV64I-LABEL: mul13: ; RV64I-LABEL: mul13:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 13 ; RV64I-NEXT: addi a1, zero, 13
; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mul13:
; RV64B: # %bb.0:
; RV64B-NEXT: sh1add a1, a0, a0
; RV64B-NEXT: sh2add a0, a1, a0
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mul13: ; RV64ZBA-LABEL: mul13:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add a1, a0, a0 ; RV64ZBA-NEXT: sh1add a1, a0, a0
; RV64ZBA-NEXT: sh2add a0, a1, a0 ; RV64ZBA-NEXT: sh2add a0, a1, a0
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 13 %c = mul i64 %a, 13
ret i64 %c ret i64 %c
} }
define i64 @mul21(i64 %a) { define i64 @mul21(i64 %a) {
; RV64I-LABEL: mul21: ; RV64I-LABEL: mul21:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 21 ; RV64I-NEXT: addi a1, zero, 21
; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mul21:
; RV64B: # %bb.0:
; RV64B-NEXT: sh2add a1, a0, a0
; RV64B-NEXT: sh2add a0, a1, a0
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mul21: ; RV64ZBA-LABEL: mul21:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a1, a0, a0 ; RV64ZBA-NEXT: sh2add a1, a0, a0
; RV64ZBA-NEXT: sh2add a0, a1, a0 ; RV64ZBA-NEXT: sh2add a0, a1, a0
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 21 %c = mul i64 %a, 21
ret i64 %c ret i64 %c
} }
define i64 @mul37(i64 %a) { define i64 @mul37(i64 %a) {
; RV64I-LABEL: mul37: ; RV64I-LABEL: mul37:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 37 ; RV64I-NEXT: addi a1, zero, 37
; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mul37:
; RV64B: # %bb.0:
; RV64B-NEXT: sh3add a1, a0, a0
; RV64B-NEXT: sh2add a0, a1, a0
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mul37: ; RV64ZBA-LABEL: mul37:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a1, a0, a0 ; RV64ZBA-NEXT: sh3add a1, a0, a0
; RV64ZBA-NEXT: sh2add a0, a1, a0 ; RV64ZBA-NEXT: sh2add a0, a1, a0
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 37 %c = mul i64 %a, 37
ret i64 %c ret i64 %c
} }
define i64 @mul25(i64 %a) { define i64 @mul25(i64 %a) {
; RV64I-LABEL: mul25: ; RV64I-LABEL: mul25:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 25 ; RV64I-NEXT: addi a1, zero, 25
; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mul25:
; RV64B: # %bb.0:
; RV64B-NEXT: sh1add a1, a0, a0
; RV64B-NEXT: sh3add a0, a1, a0
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mul25: ; RV64ZBA-LABEL: mul25:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add a1, a0, a0 ; RV64ZBA-NEXT: sh1add a1, a0, a0
; RV64ZBA-NEXT: sh3add a0, a1, a0 ; RV64ZBA-NEXT: sh3add a0, a1, a0
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 25 %c = mul i64 %a, 25
ret i64 %c ret i64 %c
} }
define i64 @mul41(i64 %a) { define i64 @mul41(i64 %a) {
; RV64I-LABEL: mul41: ; RV64I-LABEL: mul41:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 41 ; RV64I-NEXT: addi a1, zero, 41
; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mul41:
; RV64B: # %bb.0:
; RV64B-NEXT: sh2add a1, a0, a0
; RV64B-NEXT: sh3add a0, a1, a0
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mul41: ; RV64ZBA-LABEL: mul41:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a1, a0, a0 ; RV64ZBA-NEXT: sh2add a1, a0, a0
; RV64ZBA-NEXT: sh3add a0, a1, a0 ; RV64ZBA-NEXT: sh3add a0, a1, a0
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 41 %c = mul i64 %a, 41
ret i64 %c ret i64 %c
} }
define i64 @mul73(i64 %a) { define i64 @mul73(i64 %a) {
; RV64I-LABEL: mul73: ; RV64I-LABEL: mul73:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 73 ; RV64I-NEXT: addi a1, zero, 73
; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mul73:
; RV64B: # %bb.0:
; RV64B-NEXT: sh3add a1, a0, a0
; RV64B-NEXT: sh3add a0, a1, a0
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mul73: ; RV64ZBA-LABEL: mul73:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a1, a0, a0 ; RV64ZBA-NEXT: sh3add a1, a0, a0
; RV64ZBA-NEXT: sh3add a0, a1, a0 ; RV64ZBA-NEXT: sh3add a0, a1, a0
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 73 %c = mul i64 %a, 73
ret i64 %c ret i64 %c
} }
define i64 @mul27(i64 %a) { define i64 @mul27(i64 %a) {
; RV64I-LABEL: mul27: ; RV64I-LABEL: mul27:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 27 ; RV64I-NEXT: addi a1, zero, 27
; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mul27:
; RV64B: # %bb.0:
; RV64B-NEXT: sh3add a0, a0, a0
; RV64B-NEXT: sh1add a0, a0, a0
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mul27: ; RV64ZBA-LABEL: mul27:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a0, a0 ; RV64ZBA-NEXT: sh3add a0, a0, a0
; RV64ZBA-NEXT: sh1add a0, a0, a0 ; RV64ZBA-NEXT: sh1add a0, a0, a0
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 27 %c = mul i64 %a, 27
ret i64 %c ret i64 %c
} }
define i64 @mul45(i64 %a) { define i64 @mul45(i64 %a) {
; RV64I-LABEL: mul45: ; RV64I-LABEL: mul45:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 45 ; RV64I-NEXT: addi a1, zero, 45
; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mul45:
; RV64B: # %bb.0:
; RV64B-NEXT: sh3add a0, a0, a0
; RV64B-NEXT: sh2add a0, a0, a0
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mul45: ; RV64ZBA-LABEL: mul45:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a0, a0 ; RV64ZBA-NEXT: sh3add a0, a0, a0
; RV64ZBA-NEXT: sh2add a0, a0, a0 ; RV64ZBA-NEXT: sh2add a0, a0, a0
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 45 %c = mul i64 %a, 45
ret i64 %c ret i64 %c
} }
define i64 @mul81(i64 %a) { define i64 @mul81(i64 %a) {
; RV64I-LABEL: mul81: ; RV64I-LABEL: mul81:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 81 ; RV64I-NEXT: addi a1, zero, 81
; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mul81:
; RV64B: # %bb.0:
; RV64B-NEXT: sh3add a0, a0, a0
; RV64B-NEXT: sh3add a0, a0, a0
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mul81: ; RV64ZBA-LABEL: mul81:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a0, a0 ; RV64ZBA-NEXT: sh3add a0, a0, a0
; RV64ZBA-NEXT: sh3add a0, a0, a0 ; RV64ZBA-NEXT: sh3add a0, a0, a0
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 81 %c = mul i64 %a, 81
ret i64 %c ret i64 %c
} }
define i64 @mul4098(i64 %a) { define i64 @mul4098(i64 %a) {
; RV64I-LABEL: mul4098: ; RV64I-LABEL: mul4098:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1 ; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, 2 ; RV64I-NEXT: addiw a1, a1, 2
; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mul4098:
; RV64B: # %bb.0:
; RV64B-NEXT: slli a1, a0, 12
; RV64B-NEXT: sh1add a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mul4098: ; RV64ZBA-LABEL: mul4098:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli a1, a0, 12 ; RV64ZBA-NEXT: slli a1, a0, 12
; RV64ZBA-NEXT: sh1add a0, a0, a1 ; RV64ZBA-NEXT: sh1add a0, a0, a1
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 4098 %c = mul i64 %a, 4098
ret i64 %c ret i64 %c
} }
define i64 @mul4100(i64 %a) { define i64 @mul4100(i64 %a) {
; RV64I-LABEL: mul4100: ; RV64I-LABEL: mul4100:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1 ; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, 4 ; RV64I-NEXT: addiw a1, a1, 4
; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mul4100:
; RV64B: # %bb.0:
; RV64B-NEXT: slli a1, a0, 12
; RV64B-NEXT: sh2add a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mul4100: ; RV64ZBA-LABEL: mul4100:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli a1, a0, 12 ; RV64ZBA-NEXT: slli a1, a0, 12
; RV64ZBA-NEXT: sh2add a0, a0, a1 ; RV64ZBA-NEXT: sh2add a0, a0, a1
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 4100 %c = mul i64 %a, 4100
ret i64 %c ret i64 %c
} }
define i64 @mul4104(i64 %a) { define i64 @mul4104(i64 %a) {
; RV64I-LABEL: mul4104: ; RV64I-LABEL: mul4104:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1 ; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, 8 ; RV64I-NEXT: addiw a1, a1, 8
; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mul4104:
; RV64B: # %bb.0:
; RV64B-NEXT: slli a1, a0, 12
; RV64B-NEXT: sh3add a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mul4104: ; RV64ZBA-LABEL: mul4104:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli a1, a0, 12 ; RV64ZBA-NEXT: slli a1, a0, 12
; RV64ZBA-NEXT: sh3add a0, a0, a1 ; RV64ZBA-NEXT: sh3add a0, a0, a1
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i64 %a, 4104 %c = mul i64 %a, 4104
ret i64 %c ret i64 %c
} }
define signext i32 @mulw192(i32 signext %a) { define signext i32 @mulw192(i32 signext %a) {
; RV64I-LABEL: mulw192: ; RV64I-LABEL: mulw192:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 192 ; RV64I-NEXT: addi a1, zero, 192
; RV64I-NEXT: mulw a0, a0, a1 ; RV64I-NEXT: mulw a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mulw192:
; RV64B: # %bb.0:
; RV64B-NEXT: sh1add a0, a0, a0
; RV64B-NEXT: slliw a0, a0, 6
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mulw192: ; RV64ZBA-LABEL: mulw192:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add a0, a0, a0 ; RV64ZBA-NEXT: sh1add a0, a0, a0
; RV64ZBA-NEXT: slliw a0, a0, 6 ; RV64ZBA-NEXT: slliw a0, a0, 6
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i32 %a, 192 %c = mul i32 %a, 192
ret i32 %c ret i32 %c
} }
define signext i32 @mulw320(i32 signext %a) { define signext i32 @mulw320(i32 signext %a) {
; RV64I-LABEL: mulw320: ; RV64I-LABEL: mulw320:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 320 ; RV64I-NEXT: addi a1, zero, 320
; RV64I-NEXT: mulw a0, a0, a1 ; RV64I-NEXT: mulw a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mulw320:
; RV64B: # %bb.0:
; RV64B-NEXT: sh2add a0, a0, a0
; RV64B-NEXT: slliw a0, a0, 6
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mulw320: ; RV64ZBA-LABEL: mulw320:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a0, a0, a0 ; RV64ZBA-NEXT: sh2add a0, a0, a0
; RV64ZBA-NEXT: slliw a0, a0, 6 ; RV64ZBA-NEXT: slliw a0, a0, 6
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i32 %a, 320 %c = mul i32 %a, 320
ret i32 %c ret i32 %c
} }
define signext i32 @mulw576(i32 signext %a) { define signext i32 @mulw576(i32 signext %a) {
; RV64I-LABEL: mulw576: ; RV64I-LABEL: mulw576:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 576 ; RV64I-NEXT: addi a1, zero, 576
; RV64I-NEXT: mulw a0, a0, a1 ; RV64I-NEXT: mulw a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: mulw576:
; RV64B: # %bb.0:
; RV64B-NEXT: sh3add a0, a0, a0
; RV64B-NEXT: slliw a0, a0, 6
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: mulw576: ; RV64ZBA-LABEL: mulw576:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a0, a0 ; RV64ZBA-NEXT: sh3add a0, a0, a0
; RV64ZBA-NEXT: slliw a0, a0, 6 ; RV64ZBA-NEXT: slliw a0, a0, 6
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = mul i32 %a, 576 %c = mul i32 %a, 576
ret i32 %c ret i32 %c
} }
define i64 @add4104(i64 %a) { define i64 @add4104(i64 %a) {
; RV64I-LABEL: add4104: ; RV64I-LABEL: add4104:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1 ; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, 8 ; RV64I-NEXT: addiw a1, a1, 8
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: add4104:
; RV64B: # %bb.0:
; RV64B-NEXT: addi a1, zero, 1026
; RV64B-NEXT: sh2add a0, a1, a0
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: add4104: ; RV64ZBA-LABEL: add4104:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addi a1, zero, 1026 ; RV64ZBA-NEXT: addi a1, zero, 1026
; RV64ZBA-NEXT: sh2add a0, a1, a0 ; RV64ZBA-NEXT: sh2add a0, a1, a0
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = add i64 %a, 4104 %c = add i64 %a, 4104
ret i64 %c ret i64 %c
} }
define i64 @add8208(i64 %a) { define i64 @add8208(i64 %a) {
; RV64I-LABEL: add8208: ; RV64I-LABEL: add8208:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 2 ; RV64I-NEXT: lui a1, 2
; RV64I-NEXT: addiw a1, a1, 16 ; RV64I-NEXT: addiw a1, a1, 16
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: add8208:
; RV64B: # %bb.0:
; RV64B-NEXT: addi a1, zero, 1026
; RV64B-NEXT: sh3add a0, a1, a0
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: add8208: ; RV64ZBA-LABEL: add8208:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addi a1, zero, 1026 ; RV64ZBA-NEXT: addi a1, zero, 1026
; RV64ZBA-NEXT: sh3add a0, a1, a0 ; RV64ZBA-NEXT: sh3add a0, a1, a0
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = add i64 %a, 8208 %c = add i64 %a, 8208
ret i64 %c ret i64 %c
} }
define signext i32 @addshl32_5_6(i32 signext %a, i32 signext %b) { define signext i32 @addshl32_5_6(i32 signext %a, i32 signext %b) {
; RV64I-LABEL: addshl32_5_6: ; RV64I-LABEL: addshl32_5_6:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slliw a0, a0, 5 ; RV64I-NEXT: slliw a0, a0, 5
; RV64I-NEXT: slliw a1, a1, 6 ; RV64I-NEXT: slliw a1, a1, 6
; RV64I-NEXT: addw a0, a0, a1 ; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: addshl32_5_6:
; RV64B: # %bb.0:
; RV64B-NEXT: sh1add a0, a1, a0
; RV64B-NEXT: slliw a0, a0, 5
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: addshl32_5_6: ; RV64ZBA-LABEL: addshl32_5_6:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add a0, a1, a0 ; RV64ZBA-NEXT: sh1add a0, a1, a0
; RV64ZBA-NEXT: slliw a0, a0, 5 ; RV64ZBA-NEXT: slliw a0, a0, 5
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = shl i32 %a, 5 %c = shl i32 %a, 5
%d = shl i32 %b, 6 %d = shl i32 %b, 6
%e = add i32 %c, %d %e = add i32 %c, %d
ret i32 %e ret i32 %e
} }
define i64 @addshl64_5_6(i64 %a, i64 %b) { define i64 @addshl64_5_6(i64 %a, i64 %b) {
; RV64I-LABEL: addshl64_5_6: ; RV64I-LABEL: addshl64_5_6:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 5 ; RV64I-NEXT: slli a0, a0, 5
; RV64I-NEXT: slli a1, a1, 6 ; RV64I-NEXT: slli a1, a1, 6
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: addshl64_5_6:
; RV64B: # %bb.0:
; RV64B-NEXT: sh1add a0, a1, a0
; RV64B-NEXT: slli a0, a0, 5
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: addshl64_5_6: ; RV64ZBA-LABEL: addshl64_5_6:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add a0, a1, a0 ; RV64ZBA-NEXT: sh1add a0, a1, a0
; RV64ZBA-NEXT: slli a0, a0, 5 ; RV64ZBA-NEXT: slli a0, a0, 5
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = shl i64 %a, 5 %c = shl i64 %a, 5
%d = shl i64 %b, 6 %d = shl i64 %b, 6
%e = add i64 %c, %d %e = add i64 %c, %d
ret i64 %e ret i64 %e
} }
define signext i32 @addshl32_5_7(i32 signext %a, i32 signext %b) { define signext i32 @addshl32_5_7(i32 signext %a, i32 signext %b) {
; RV64I-LABEL: addshl32_5_7: ; RV64I-LABEL: addshl32_5_7:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slliw a0, a0, 5 ; RV64I-NEXT: slliw a0, a0, 5
; RV64I-NEXT: slliw a1, a1, 7 ; RV64I-NEXT: slliw a1, a1, 7
; RV64I-NEXT: addw a0, a0, a1 ; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: addshl32_5_7:
; RV64B: # %bb.0:
; RV64B-NEXT: sh2add a0, a1, a0
; RV64B-NEXT: slliw a0, a0, 5
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: addshl32_5_7: ; RV64ZBA-LABEL: addshl32_5_7:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a0, a1, a0 ; RV64ZBA-NEXT: sh2add a0, a1, a0
; RV64ZBA-NEXT: slliw a0, a0, 5 ; RV64ZBA-NEXT: slliw a0, a0, 5
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = shl i32 %a, 5 %c = shl i32 %a, 5
%d = shl i32 %b, 7 %d = shl i32 %b, 7
%e = add i32 %c, %d %e = add i32 %c, %d
ret i32 %e ret i32 %e
} }
define i64 @addshl64_5_7(i64 %a, i64 %b) { define i64 @addshl64_5_7(i64 %a, i64 %b) {
; RV64I-LABEL: addshl64_5_7: ; RV64I-LABEL: addshl64_5_7:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 5 ; RV64I-NEXT: slli a0, a0, 5
; RV64I-NEXT: slli a1, a1, 7 ; RV64I-NEXT: slli a1, a1, 7
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: addshl64_5_7:
; RV64B: # %bb.0:
; RV64B-NEXT: sh2add a0, a1, a0
; RV64B-NEXT: slli a0, a0, 5
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: addshl64_5_7: ; RV64ZBA-LABEL: addshl64_5_7:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a0, a1, a0 ; RV64ZBA-NEXT: sh2add a0, a1, a0
; RV64ZBA-NEXT: slli a0, a0, 5 ; RV64ZBA-NEXT: slli a0, a0, 5
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = shl i64 %a, 5 %c = shl i64 %a, 5
%d = shl i64 %b, 7 %d = shl i64 %b, 7
%e = add i64 %c, %d %e = add i64 %c, %d
ret i64 %e ret i64 %e
} }
define signext i32 @addshl32_5_8(i32 signext %a, i32 signext %b) { define signext i32 @addshl32_5_8(i32 signext %a, i32 signext %b) {
; RV64I-LABEL: addshl32_5_8: ; RV64I-LABEL: addshl32_5_8:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slliw a0, a0, 5 ; RV64I-NEXT: slliw a0, a0, 5
; RV64I-NEXT: slliw a1, a1, 8 ; RV64I-NEXT: slliw a1, a1, 8
; RV64I-NEXT: addw a0, a0, a1 ; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: addshl32_5_8:
; RV64B: # %bb.0:
; RV64B-NEXT: sh3add a0, a1, a0
; RV64B-NEXT: slliw a0, a0, 5
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: addshl32_5_8: ; RV64ZBA-LABEL: addshl32_5_8:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a1, a0 ; RV64ZBA-NEXT: sh3add a0, a1, a0
; RV64ZBA-NEXT: slliw a0, a0, 5 ; RV64ZBA-NEXT: slliw a0, a0, 5
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = shl i32 %a, 5 %c = shl i32 %a, 5
%d = shl i32 %b, 8 %d = shl i32 %b, 8
%e = add i32 %c, %d %e = add i32 %c, %d
ret i32 %e ret i32 %e
} }
define i64 @addshl64_5_8(i64 %a, i64 %b) { define i64 @addshl64_5_8(i64 %a, i64 %b) {
; RV64I-LABEL: addshl64_5_8: ; RV64I-LABEL: addshl64_5_8:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 5 ; RV64I-NEXT: slli a0, a0, 5
; RV64I-NEXT: slli a1, a1, 8 ; RV64I-NEXT: slli a1, a1, 8
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: addshl64_5_8:
; RV64B: # %bb.0:
; RV64B-NEXT: sh3add a0, a1, a0
; RV64B-NEXT: slli a0, a0, 5
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: addshl64_5_8: ; RV64ZBA-LABEL: addshl64_5_8:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a1, a0 ; RV64ZBA-NEXT: sh3add a0, a1, a0
; RV64ZBA-NEXT: slli a0, a0, 5 ; RV64ZBA-NEXT: slli a0, a0, 5
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = shl i64 %a, 5 %c = shl i64 %a, 5
%d = shl i64 %b, 8 %d = shl i64 %b, 8
%e = add i64 %c, %d %e = add i64 %c, %d
ret i64 %e ret i64 %e
} }

llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64B
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBB ; RUN: | FileCheck %s -check-prefix=RV64ZBB
declare i32 @llvm.riscv.orc.b.i32(i32) declare i32 @llvm.riscv.orc.b.i32(i32)
define signext i32 @orcb32(i32 signext %a) nounwind { define signext i32 @orcb32(i32 signext %a) nounwind {
; RV64B-LABEL: orcb32:
; RV64B: # %bb.0:
; RV64B-NEXT: gorciw a0, a0, 7
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: orcb32: ; RV64ZBB-LABEL: orcb32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: orc.b a0, a0 ; RV64ZBB-NEXT: orc.b a0, a0
; RV64ZBB-NEXT: sext.w a0, a0 ; RV64ZBB-NEXT: sext.w a0, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a) %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
ret i32 %tmp ret i32 %tmp
} }
declare i64 @llvm.riscv.orc.b.i64(i64) declare i64 @llvm.riscv.orc.b.i64(i64)
define i64 @orcb64(i64 %a) nounwind { define i64 @orcb64(i64 %a) nounwind {
; RV64B-LABEL: orcb64:
; RV64B: # %bb.0:
; RV64B-NEXT: orc.b a0, a0
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: orcb64: ; RV64ZBB-LABEL: orcb64:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: orc.b a0, a0 ; RV64ZBB-NEXT: orc.b a0, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%tmp = call i64 @llvm.riscv.orc.b.i64(i64 %a) %tmp = call i64 @llvm.riscv.orc.b.i64(i64 %a)
ret i64 %tmp ret i64 %tmp
} }

llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I ; RUN: | FileCheck %s -check-prefix=RV64I
; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64B
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBB ; RUN: | FileCheck %s -check-prefix=RV64ZBB
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBP ; RUN: | FileCheck %s -check-prefix=RV64ZBP
define signext i32 @andn_i32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @andn_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: andn_i32: ; RV64I-LABEL: andn_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: not a1, a1 ; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a0, a1, a0 ; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: andn_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: andn a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: andn_i32: ; RV64ZBB-LABEL: andn_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: andn a0, a0, a1 ; RV64ZBB-NEXT: andn a0, a0, a1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: andn_i32: ; RV64ZBP-LABEL: andn_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: andn a0, a0, a1 ; RV64ZBP-NEXT: andn a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%neg = xor i32 %b, -1 %neg = xor i32 %b, -1
%and = and i32 %neg, %a %and = and i32 %neg, %a
ret i32 %and ret i32 %and
} }
define i64 @andn_i64(i64 %a, i64 %b) nounwind { define i64 @andn_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: andn_i64: ; RV64I-LABEL: andn_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: not a1, a1 ; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a0, a1, a0 ; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: andn_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: andn a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: andn_i64: ; RV64ZBB-LABEL: andn_i64:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: andn a0, a0, a1 ; RV64ZBB-NEXT: andn a0, a0, a1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: andn_i64: ; RV64ZBP-LABEL: andn_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: andn a0, a0, a1 ; RV64ZBP-NEXT: andn a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%neg = xor i64 %b, -1 %neg = xor i64 %b, -1
%and = and i64 %neg, %a %and = and i64 %neg, %a
ret i64 %and ret i64 %and
} }
define signext i32 @orn_i32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @orn_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: orn_i32: ; RV64I-LABEL: orn_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: not a1, a1 ; RV64I-NEXT: not a1, a1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: orn_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: orn a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: orn_i32: ; RV64ZBB-LABEL: orn_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: orn a0, a0, a1 ; RV64ZBB-NEXT: orn a0, a0, a1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: orn_i32: ; RV64ZBP-LABEL: orn_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orn a0, a0, a1 ; RV64ZBP-NEXT: orn a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%neg = xor i32 %b, -1 %neg = xor i32 %b, -1
%or = or i32 %neg, %a %or = or i32 %neg, %a
ret i32 %or ret i32 %or
} }
define i64 @orn_i64(i64 %a, i64 %b) nounwind { define i64 @orn_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: orn_i64: ; RV64I-LABEL: orn_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: not a1, a1 ; RV64I-NEXT: not a1, a1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: orn_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: orn a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: orn_i64: ; RV64ZBB-LABEL: orn_i64:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: orn a0, a0, a1 ; RV64ZBB-NEXT: orn a0, a0, a1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: orn_i64: ; RV64ZBP-LABEL: orn_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orn a0, a0, a1 ; RV64ZBP-NEXT: orn a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%neg = xor i64 %b, -1 %neg = xor i64 %b, -1
%or = or i64 %neg, %a %or = or i64 %neg, %a
ret i64 %or ret i64 %or
} }
define signext i32 @xnor_i32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @xnor_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: xnor_i32: ; RV64I-LABEL: xnor_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: not a0, a0 ; RV64I-NEXT: not a0, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: xnor_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: xnor a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: xnor_i32: ; RV64ZBB-LABEL: xnor_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: xnor a0, a0, a1 ; RV64ZBB-NEXT: xnor a0, a0, a1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: xnor_i32: ; RV64ZBP-LABEL: xnor_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: xnor a0, a0, a1 ; RV64ZBP-NEXT: xnor a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%neg = xor i32 %a, -1 %neg = xor i32 %a, -1
%xor = xor i32 %neg, %b %xor = xor i32 %neg, %b
ret i32 %xor ret i32 %xor
} }
define i64 @xnor_i64(i64 %a, i64 %b) nounwind { define i64 @xnor_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: xnor_i64: ; RV64I-LABEL: xnor_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: not a0, a0 ; RV64I-NEXT: not a0, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: xnor_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: xnor a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: xnor_i64: ; RV64ZBB-LABEL: xnor_i64:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: xnor a0, a0, a1 ; RV64ZBB-NEXT: xnor a0, a0, a1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: xnor_i64: ; RV64ZBP-LABEL: xnor_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: xnor a0, a0, a1 ; RV64ZBP-NEXT: xnor a0, a0, a1
Show All 9 Lines
; RV64I-LABEL: rol_i32: ; RV64I-LABEL: rol_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sllw a2, a0, a1 ; RV64I-NEXT: sllw a2, a0, a1
; RV64I-NEXT: negw a1, a1 ; RV64I-NEXT: negw a1, a1
; RV64I-NEXT: srlw a0, a0, a1 ; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: rol_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: rolw a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: rol_i32: ; RV64ZBB-LABEL: rol_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rolw a0, a0, a1 ; RV64ZBB-NEXT: rolw a0, a0, a1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: rol_i32: ; RV64ZBP-LABEL: rol_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rolw a0, a0, a1 ; RV64ZBP-NEXT: rolw a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %b) %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %b)
ret i32 %1 ret i32 %1
} }
; Similar to rol_i32, but doesn't sign extend the result. ; Similar to rol_i32, but doesn't sign extend the result.
define void @rol_i32_nosext(i32 signext %a, i32 signext %b, i32* %x) nounwind { define void @rol_i32_nosext(i32 signext %a, i32 signext %b, i32* %x) nounwind {
; RV64I-LABEL: rol_i32_nosext: ; RV64I-LABEL: rol_i32_nosext:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sllw a3, a0, a1 ; RV64I-NEXT: sllw a3, a0, a1
; RV64I-NEXT: negw a1, a1 ; RV64I-NEXT: negw a1, a1
; RV64I-NEXT: srlw a0, a0, a1 ; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: or a0, a3, a0 ; RV64I-NEXT: or a0, a3, a0
; RV64I-NEXT: sw a0, 0(a2) ; RV64I-NEXT: sw a0, 0(a2)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: rol_i32_nosext:
; RV64B: # %bb.0:
; RV64B-NEXT: rolw a0, a0, a1
; RV64B-NEXT: sw a0, 0(a2)
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: rol_i32_nosext: ; RV64ZBB-LABEL: rol_i32_nosext:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rolw a0, a0, a1 ; RV64ZBB-NEXT: rolw a0, a0, a1
; RV64ZBB-NEXT: sw a0, 0(a2) ; RV64ZBB-NEXT: sw a0, 0(a2)
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: rol_i32_nosext: ; RV64ZBP-LABEL: rol_i32_nosext:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
Show All 10 Lines
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, -2 ; RV64I-NEXT: addi a1, zero, -2
; RV64I-NEXT: sllw a2, a1, a0 ; RV64I-NEXT: sllw a2, a1, a0
; RV64I-NEXT: negw a0, a0 ; RV64I-NEXT: negw a0, a0
; RV64I-NEXT: srlw a0, a1, a0 ; RV64I-NEXT: srlw a0, a1, a0
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: rol_i32_neg_constant_rhs:
; RV64B: # %bb.0:
; RV64B-NEXT: addi a1, zero, -2
; RV64B-NEXT: rolw a0, a1, a0
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: rol_i32_neg_constant_rhs: ; RV64ZBB-LABEL: rol_i32_neg_constant_rhs:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: addi a1, zero, -2 ; RV64ZBB-NEXT: addi a1, zero, -2
; RV64ZBB-NEXT: rolw a0, a1, a0 ; RV64ZBB-NEXT: rolw a0, a1, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: rol_i32_neg_constant_rhs: ; RV64ZBP-LABEL: rol_i32_neg_constant_rhs:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
Show All 10 Lines
; RV64I-LABEL: rol_i64: ; RV64I-LABEL: rol_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sll a2, a0, a1 ; RV64I-NEXT: sll a2, a0, a1
; RV64I-NEXT: neg a1, a1 ; RV64I-NEXT: neg a1, a1
; RV64I-NEXT: srl a0, a0, a1 ; RV64I-NEXT: srl a0, a0, a1
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: rol_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: rol a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: rol_i64: ; RV64ZBB-LABEL: rol_i64:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rol a0, a0, a1 ; RV64ZBB-NEXT: rol a0, a0, a1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: rol_i64: ; RV64ZBP-LABEL: rol_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rol a0, a0, a1 ; RV64ZBP-NEXT: rol a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%or = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %b) %or = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %b)
ret i64 %or ret i64 %or
} }
declare i32 @llvm.fshr.i32(i32, i32, i32) declare i32 @llvm.fshr.i32(i32, i32, i32)
define signext i32 @ror_i32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @ror_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: ror_i32: ; RV64I-LABEL: ror_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srlw a2, a0, a1 ; RV64I-NEXT: srlw a2, a0, a1
; RV64I-NEXT: negw a1, a1 ; RV64I-NEXT: negw a1, a1
; RV64I-NEXT: sllw a0, a0, a1 ; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: ror_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: rorw a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: ror_i32: ; RV64ZBB-LABEL: ror_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rorw a0, a0, a1 ; RV64ZBB-NEXT: rorw a0, a0, a1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: ror_i32: ; RV64ZBP-LABEL: ror_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rorw a0, a0, a1 ; RV64ZBP-NEXT: rorw a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %b) %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %b)
ret i32 %1 ret i32 %1
} }
; Similar to ror_i32, but doesn't sign extend the result. ; Similar to ror_i32, but doesn't sign extend the result.
define void @ror_i32_nosext(i32 signext %a, i32 signext %b, i32* %x) nounwind { define void @ror_i32_nosext(i32 signext %a, i32 signext %b, i32* %x) nounwind {
; RV64I-LABEL: ror_i32_nosext: ; RV64I-LABEL: ror_i32_nosext:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srlw a3, a0, a1 ; RV64I-NEXT: srlw a3, a0, a1
; RV64I-NEXT: negw a1, a1 ; RV64I-NEXT: negw a1, a1
; RV64I-NEXT: sllw a0, a0, a1 ; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: or a0, a3, a0 ; RV64I-NEXT: or a0, a3, a0
; RV64I-NEXT: sw a0, 0(a2) ; RV64I-NEXT: sw a0, 0(a2)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: ror_i32_nosext:
; RV64B: # %bb.0:
; RV64B-NEXT: rorw a0, a0, a1
; RV64B-NEXT: sw a0, 0(a2)
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: ror_i32_nosext: ; RV64ZBB-LABEL: ror_i32_nosext:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rorw a0, a0, a1 ; RV64ZBB-NEXT: rorw a0, a0, a1
; RV64ZBB-NEXT: sw a0, 0(a2) ; RV64ZBB-NEXT: sw a0, 0(a2)
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: ror_i32_nosext: ; RV64ZBP-LABEL: ror_i32_nosext:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
Show All 10 Lines
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, -2 ; RV64I-NEXT: addi a1, zero, -2
; RV64I-NEXT: srlw a2, a1, a0 ; RV64I-NEXT: srlw a2, a1, a0
; RV64I-NEXT: negw a0, a0 ; RV64I-NEXT: negw a0, a0
; RV64I-NEXT: sllw a0, a1, a0 ; RV64I-NEXT: sllw a0, a1, a0
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: ror_i32_neg_constant_rhs:
; RV64B: # %bb.0:
; RV64B-NEXT: addi a1, zero, -2
; RV64B-NEXT: rorw a0, a1, a0
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: ror_i32_neg_constant_rhs: ; RV64ZBB-LABEL: ror_i32_neg_constant_rhs:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: addi a1, zero, -2 ; RV64ZBB-NEXT: addi a1, zero, -2
; RV64ZBB-NEXT: rorw a0, a1, a0 ; RV64ZBB-NEXT: rorw a0, a1, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: ror_i32_neg_constant_rhs: ; RV64ZBP-LABEL: ror_i32_neg_constant_rhs:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
Show All 10 Lines
; RV64I-LABEL: ror_i64: ; RV64I-LABEL: ror_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srl a2, a0, a1 ; RV64I-NEXT: srl a2, a0, a1
; RV64I-NEXT: neg a1, a1 ; RV64I-NEXT: neg a1, a1
; RV64I-NEXT: sll a0, a0, a1 ; RV64I-NEXT: sll a0, a0, a1
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: ror_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: ror a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: ror_i64: ; RV64ZBB-LABEL: ror_i64:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: ror a0, a0, a1 ; RV64ZBB-NEXT: ror a0, a0, a1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: ror_i64: ; RV64ZBP-LABEL: ror_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: ror a0, a0, a1 ; RV64ZBP-NEXT: ror a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%or = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %b) %or = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %b)
ret i64 %or ret i64 %or
} }
define signext i32 @rori_i32_fshl(i32 signext %a) nounwind { define signext i32 @rori_i32_fshl(i32 signext %a) nounwind {
; RV64I-LABEL: rori_i32_fshl: ; RV64I-LABEL: rori_i32_fshl:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a0, 1 ; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: slliw a0, a0, 31 ; RV64I-NEXT: slliw a0, a0, 31
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: rori_i32_fshl:
; RV64B: # %bb.0:
; RV64B-NEXT: roriw a0, a0, 1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: rori_i32_fshl: ; RV64ZBB-LABEL: rori_i32_fshl:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: roriw a0, a0, 1 ; RV64ZBB-NEXT: roriw a0, a0, 1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: rori_i32_fshl: ; RV64ZBP-LABEL: rori_i32_fshl:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: roriw a0, a0, 1 ; RV64ZBP-NEXT: roriw a0, a0, 1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 31) %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 31)
ret i32 %1 ret i32 %1
} }
; Similar to rori_i32_fshl, but doesn't sign extend the result. ; Similar to rori_i32_fshl, but doesn't sign extend the result.
define void @rori_i32_fshl_nosext(i32 signext %a, i32* %x) nounwind { define void @rori_i32_fshl_nosext(i32 signext %a, i32* %x) nounwind {
; RV64I-LABEL: rori_i32_fshl_nosext: ; RV64I-LABEL: rori_i32_fshl_nosext:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srliw a2, a0, 1 ; RV64I-NEXT: srliw a2, a0, 1
; RV64I-NEXT: slli a0, a0, 31 ; RV64I-NEXT: slli a0, a0, 31
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: sw a0, 0(a1) ; RV64I-NEXT: sw a0, 0(a1)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: rori_i32_fshl_nosext:
; RV64B: # %bb.0:
; RV64B-NEXT: roriw a0, a0, 1
; RV64B-NEXT: sw a0, 0(a1)
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: rori_i32_fshl_nosext: ; RV64ZBB-LABEL: rori_i32_fshl_nosext:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: roriw a0, a0, 1 ; RV64ZBB-NEXT: roriw a0, a0, 1
; RV64ZBB-NEXT: sw a0, 0(a1) ; RV64ZBB-NEXT: sw a0, 0(a1)
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: rori_i32_fshl_nosext: ; RV64ZBP-LABEL: rori_i32_fshl_nosext:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: roriw a0, a0, 1 ; RV64ZBP-NEXT: roriw a0, a0, 1
; RV64ZBP-NEXT: sw a0, 0(a1) ; RV64ZBP-NEXT: sw a0, 0(a1)
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 31) %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 31)
store i32 %1, i32* %x store i32 %1, i32* %x
ret void ret void
} }
define signext i32 @rori_i32_fshr(i32 signext %a) nounwind { define signext i32 @rori_i32_fshr(i32 signext %a) nounwind {
; RV64I-LABEL: rori_i32_fshr: ; RV64I-LABEL: rori_i32_fshr:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slliw a1, a0, 1 ; RV64I-NEXT: slliw a1, a0, 1
; RV64I-NEXT: srliw a0, a0, 31 ; RV64I-NEXT: srliw a0, a0, 31
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: rori_i32_fshr:
; RV64B: # %bb.0:
; RV64B-NEXT: roriw a0, a0, 31
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: rori_i32_fshr: ; RV64ZBB-LABEL: rori_i32_fshr:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: roriw a0, a0, 31 ; RV64ZBB-NEXT: roriw a0, a0, 31
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: rori_i32_fshr: ; RV64ZBP-LABEL: rori_i32_fshr:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: roriw a0, a0, 31 ; RV64ZBP-NEXT: roriw a0, a0, 31
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 31) %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 31)
ret i32 %1 ret i32 %1
} }
; Similar to rori_i32_fshr, but doesn't sign extend the result. ; Similar to rori_i32_fshr, but doesn't sign extend the result.
define void @rori_i32_fshr_nosext(i32 signext %a, i32* %x) nounwind { define void @rori_i32_fshr_nosext(i32 signext %a, i32* %x) nounwind {
; RV64I-LABEL: rori_i32_fshr_nosext: ; RV64I-LABEL: rori_i32_fshr_nosext:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a2, a0, 1 ; RV64I-NEXT: slli a2, a0, 1
; RV64I-NEXT: srliw a0, a0, 31 ; RV64I-NEXT: srliw a0, a0, 31
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: sw a0, 0(a1) ; RV64I-NEXT: sw a0, 0(a1)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: rori_i32_fshr_nosext:
; RV64B: # %bb.0:
; RV64B-NEXT: roriw a0, a0, 31
; RV64B-NEXT: sw a0, 0(a1)
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: rori_i32_fshr_nosext: ; RV64ZBB-LABEL: rori_i32_fshr_nosext:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: roriw a0, a0, 31 ; RV64ZBB-NEXT: roriw a0, a0, 31
; RV64ZBB-NEXT: sw a0, 0(a1) ; RV64ZBB-NEXT: sw a0, 0(a1)
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: rori_i32_fshr_nosext: ; RV64ZBP-LABEL: rori_i32_fshr_nosext:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
Show All 11 Lines
define signext i32 @not_rori_i32(i32 signext %x, i32 signext %y) nounwind { define signext i32 @not_rori_i32(i32 signext %x, i32 signext %y) nounwind {
; RV64I-LABEL: not_rori_i32: ; RV64I-LABEL: not_rori_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slliw a0, a0, 31 ; RV64I-NEXT: slliw a0, a0, 31
; RV64I-NEXT: srliw a1, a1, 1 ; RV64I-NEXT: srliw a1, a1, 1
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: not_rori_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: slliw a0, a0, 31
; RV64B-NEXT: srliw a1, a1, 1
; RV64B-NEXT: or a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: not_rori_i32: ; RV64ZBB-LABEL: not_rori_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: slliw a0, a0, 31 ; RV64ZBB-NEXT: slliw a0, a0, 31
; RV64ZBB-NEXT: srliw a1, a1, 1 ; RV64ZBB-NEXT: srliw a1, a1, 1
; RV64ZBB-NEXT: or a0, a0, a1 ; RV64ZBB-NEXT: or a0, a0, a1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: not_rori_i32: ; RV64ZBP-LABEL: not_rori_i32:
Show All 17 Lines
; RV64I-NEXT: slli a1, a0, 31 ; RV64I-NEXT: slli a1, a0, 31
; RV64I-NEXT: andi a0, a0, -2 ; RV64I-NEXT: andi a0, a0, -2
; RV64I-NEXT: srli a2, a0, 1 ; RV64I-NEXT: srli a2, a0, 1
; RV64I-NEXT: or a1, a1, a2 ; RV64I-NEXT: or a1, a1, a2
; RV64I-NEXT: sext.w a1, a1 ; RV64I-NEXT: sext.w a1, a1
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: roriw_bug:
; RV64B: # %bb.0:
; RV64B-NEXT: slli a1, a0, 31
; RV64B-NEXT: andi a0, a0, -2
; RV64B-NEXT: srli a2, a0, 1
; RV64B-NEXT: or a1, a1, a2
; RV64B-NEXT: sext.w a1, a1
; RV64B-NEXT: xor a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: roriw_bug: ; RV64ZBB-LABEL: roriw_bug:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: slli a1, a0, 31 ; RV64ZBB-NEXT: slli a1, a0, 31
; RV64ZBB-NEXT: andi a0, a0, -2 ; RV64ZBB-NEXT: andi a0, a0, -2
; RV64ZBB-NEXT: srli a2, a0, 1 ; RV64ZBB-NEXT: srli a2, a0, 1
; RV64ZBB-NEXT: or a1, a1, a2 ; RV64ZBB-NEXT: or a1, a1, a2
; RV64ZBB-NEXT: sext.w a1, a1 ; RV64ZBB-NEXT: sext.w a1, a1
; RV64ZBB-NEXT: xor a0, a0, a1 ; RV64ZBB-NEXT: xor a0, a0, a1
Show All 21 Lines
define i64 @rori_i64_fshl(i64 %a) nounwind { define i64 @rori_i64_fshl(i64 %a) nounwind {
; RV64I-LABEL: rori_i64_fshl: ; RV64I-LABEL: rori_i64_fshl:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: slli a0, a0, 63 ; RV64I-NEXT: slli a0, a0, 63
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: rori_i64_fshl:
; RV64B: # %bb.0:
; RV64B-NEXT: rori a0, a0, 1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: rori_i64_fshl: ; RV64ZBB-LABEL: rori_i64_fshl:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rori a0, a0, 1 ; RV64ZBB-NEXT: rori a0, a0, 1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: rori_i64_fshl: ; RV64ZBP-LABEL: rori_i64_fshl:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rori a0, a0, 1 ; RV64ZBP-NEXT: rori a0, a0, 1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 63) %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 63)
ret i64 %1 ret i64 %1
} }
define i64 @rori_i64_fshr(i64 %a) nounwind { define i64 @rori_i64_fshr(i64 %a) nounwind {
; RV64I-LABEL: rori_i64_fshr: ; RV64I-LABEL: rori_i64_fshr:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 1 ; RV64I-NEXT: slli a1, a0, 1
; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: srli a0, a0, 63
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: rori_i64_fshr:
; RV64B: # %bb.0:
; RV64B-NEXT: rori a0, a0, 63
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: rori_i64_fshr: ; RV64ZBB-LABEL: rori_i64_fshr:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rori a0, a0, 63 ; RV64ZBB-NEXT: rori a0, a0, 63
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: rori_i64_fshr: ; RV64ZBP-LABEL: rori_i64_fshr:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rori a0, a0, 63 ; RV64ZBP-NEXT: rori a0, a0, 63
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 63) %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 63)
ret i64 %1 ret i64 %1
} }
define i8 @srli_i8(i8 %a) nounwind { define i8 @srli_i8(i8 %a) nounwind {
; RV64I-LABEL: srli_i8: ; RV64I-LABEL: srli_i8:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, 192 ; RV64I-NEXT: andi a0, a0, 192
; RV64I-NEXT: srli a0, a0, 6 ; RV64I-NEXT: srli a0, a0, 6
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: srli_i8:
; RV64B: # %bb.0:
; RV64B-NEXT: andi a0, a0, 192
; RV64B-NEXT: srli a0, a0, 6
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: srli_i8: ; RV64ZBB-LABEL: srli_i8:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: andi a0, a0, 192 ; RV64ZBB-NEXT: andi a0, a0, 192
; RV64ZBB-NEXT: srli a0, a0, 6 ; RV64ZBB-NEXT: srli a0, a0, 6
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: srli_i8: ; RV64ZBP-LABEL: srli_i8:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: andi a0, a0, 192 ; RV64ZBP-NEXT: andi a0, a0, 192
; RV64ZBP-NEXT: srli a0, a0, 6 ; RV64ZBP-NEXT: srli a0, a0, 6
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = lshr i8 %a, 6 %1 = lshr i8 %a, 6
ret i8 %1 ret i8 %1
} }
define i8 @srai_i8(i8 %a) nounwind { define i8 @srai_i8(i8 %a) nounwind {
; RV64I-LABEL: srai_i8: ; RV64I-LABEL: srai_i8:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: srai a0, a0, 61 ; RV64I-NEXT: srai a0, a0, 61
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: srai_i8:
; RV64B: # %bb.0:
; RV64B-NEXT: sext.b a0, a0
; RV64B-NEXT: srai a0, a0, 5
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: srai_i8: ; RV64ZBB-LABEL: srai_i8:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: sext.b a0, a0 ; RV64ZBB-NEXT: sext.b a0, a0
; RV64ZBB-NEXT: srai a0, a0, 5 ; RV64ZBB-NEXT: srai a0, a0, 5
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: srai_i8: ; RV64ZBP-LABEL: srai_i8:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: slli a0, a0, 56 ; RV64ZBP-NEXT: slli a0, a0, 56
; RV64ZBP-NEXT: srai a0, a0, 61 ; RV64ZBP-NEXT: srai a0, a0, 61
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = ashr i8 %a, 5 %1 = ashr i8 %a, 5
ret i8 %1 ret i8 %1
} }
define i16 @srli_i16(i16 %a) nounwind { define i16 @srli_i16(i16 %a) nounwind {
; RV64I-LABEL: srli_i16: ; RV64I-LABEL: srli_i16:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 54 ; RV64I-NEXT: srli a0, a0, 54
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: srli_i16:
; RV64B: # %bb.0:
; RV64B-NEXT: zext.h a0, a0
; RV64B-NEXT: srli a0, a0, 6
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: srli_i16: ; RV64ZBB-LABEL: srli_i16:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: zext.h a0, a0 ; RV64ZBB-NEXT: zext.h a0, a0
; RV64ZBB-NEXT: srli a0, a0, 6 ; RV64ZBB-NEXT: srli a0, a0, 6
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: srli_i16: ; RV64ZBP-LABEL: srli_i16:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zext.h a0, a0 ; RV64ZBP-NEXT: zext.h a0, a0
; RV64ZBP-NEXT: srli a0, a0, 6 ; RV64ZBP-NEXT: srli a0, a0, 6
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = lshr i16 %a, 6 %1 = lshr i16 %a, 6
ret i16 %1 ret i16 %1
} }
define i16 @srai_i16(i16 %a) nounwind { define i16 @srai_i16(i16 %a) nounwind {
; RV64I-LABEL: srai_i16: ; RV64I-LABEL: srai_i16:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srai a0, a0, 57 ; RV64I-NEXT: srai a0, a0, 57
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: srai_i16:
; RV64B: # %bb.0:
; RV64B-NEXT: sext.h a0, a0
; RV64B-NEXT: srai a0, a0, 9
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: srai_i16: ; RV64ZBB-LABEL: srai_i16:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: sext.h a0, a0 ; RV64ZBB-NEXT: sext.h a0, a0
; RV64ZBB-NEXT: srai a0, a0, 9 ; RV64ZBB-NEXT: srai a0, a0, 9
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
; ;
; RV64ZBP-LABEL: srai_i16: ; RV64ZBP-LABEL: srai_i16:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: slli a0, a0, 48 ; RV64ZBP-NEXT: slli a0, a0, 48
; RV64ZBP-NEXT: srai a0, a0, 57 ; RV64ZBP-NEXT: srai a0, a0, 57
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = ashr i16 %a, 9 %1 = ashr i16 %a, 9
ret i16 %1 ret i16 %1
} }

llvm/test/CodeGen/RISCV/rv64zbb.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I ; RUN: | FileCheck %s -check-prefix=RV64I
; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64B
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBB ; RUN: | FileCheck %s -check-prefix=RV64ZBB
declare i32 @llvm.ctlz.i32(i32, i1) declare i32 @llvm.ctlz.i32(i32, i1)
define signext i32 @ctlz_i32(i32 signext %a) nounwind { define signext i32 @ctlz_i32(i32 signext %a) nounwind {
; RV64I-LABEL: ctlz_i32: ; RV64I-LABEL: ctlz_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; RV64I-NEXT: addi a0, a0, -32 ; RV64I-NEXT: addi a0, a0, -32
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB0_2: ; RV64I-NEXT: .LBB0_2:
; RV64I-NEXT: addi a0, zero, 32 ; RV64I-NEXT: addi a0, zero, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: ctlz_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: clzw a0, a0
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: ctlz_i32: ; RV64ZBB-LABEL: ctlz_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: clzw a0, a0 ; RV64ZBB-NEXT: clzw a0, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false) %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
ret i32 %1 ret i32 %1
} }
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
; RV64I-NEXT: j .LBB1_3 ; RV64I-NEXT: j .LBB1_3
; RV64I-NEXT: .LBB1_2: ; RV64I-NEXT: .LBB1_2:
; RV64I-NEXT: addi a0, zero, 32 ; RV64I-NEXT: addi a0, zero, 32
; RV64I-NEXT: .LBB1_3: # %cond.end ; RV64I-NEXT: .LBB1_3: # %cond.end
; RV64I-NEXT: addi a1, zero, 31 ; RV64I-NEXT: addi a1, zero, 31
; RV64I-NEXT: sub a0, a1, a0 ; RV64I-NEXT: sub a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: log2_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: clzw a0, a0
; RV64B-NEXT: addi a1, zero, 31
; RV64B-NEXT: sub a0, a1, a0
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: log2_i32: ; RV64ZBB-LABEL: log2_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: clzw a0, a0 ; RV64ZBB-NEXT: clzw a0, a0
; RV64ZBB-NEXT: addi a1, zero, 31 ; RV64ZBB-NEXT: addi a1, zero, 31
; RV64ZBB-NEXT: sub a0, a1, a0 ; RV64ZBB-NEXT: sub a0, a1, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false) %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
%2 = sub i32 31, %1 %2 = sub i32 31, %1
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
; RV64I-NEXT: addi a1, a0, -32 ; RV64I-NEXT: addi a1, a0, -32
; RV64I-NEXT: .LBB2_2: # %cond.end ; RV64I-NEXT: .LBB2_2: # %cond.end
; RV64I-NEXT: sub a0, s0, a1 ; RV64I-NEXT: sub a0, s0, a1
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: log2_ceil_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: addiw a0, a0, -1
; RV64B-NEXT: clzw a0, a0
; RV64B-NEXT: addi a1, zero, 32
; RV64B-NEXT: sub a0, a1, a0
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: log2_ceil_i32: ; RV64ZBB-LABEL: log2_ceil_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: addiw a0, a0, -1 ; RV64ZBB-NEXT: addiw a0, a0, -1
; RV64ZBB-NEXT: clzw a0, a0 ; RV64ZBB-NEXT: clzw a0, a0
; RV64ZBB-NEXT: addi a1, zero, 32 ; RV64ZBB-NEXT: addi a1, zero, 32
; RV64ZBB-NEXT: sub a0, a1, a0 ; RV64ZBB-NEXT: sub a0, a1, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%1 = sub i32 %a, 1 %1 = sub i32 %a, 1
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
; RV64I-NEXT: addi a0, a0, -32 ; RV64I-NEXT: addi a0, a0, -32
; RV64I-NEXT: xori a0, a0, 31 ; RV64I-NEXT: xori a0, a0, 31
; RV64I-NEXT: .LBB3_2: ; RV64I-NEXT: .LBB3_2:
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: findLastSet_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: clzw a1, a0
; RV64B-NEXT: xori a1, a1, 31
; RV64B-NEXT: addi a2, zero, -1
; RV64B-NEXT: cmov a0, a0, a1, a2
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: findLastSet_i32: ; RV64ZBB-LABEL: findLastSet_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: mv a1, a0 ; RV64ZBB-NEXT: mv a1, a0
; RV64ZBB-NEXT: addi a0, zero, -1 ; RV64ZBB-NEXT: addi a0, zero, -1
; RV64ZBB-NEXT: beqz a1, .LBB3_2 ; RV64ZBB-NEXT: beqz a1, .LBB3_2
; RV64ZBB-NEXT: # %bb.1: ; RV64ZBB-NEXT: # %bb.1:
; RV64ZBB-NEXT: clzw a0, a1 ; RV64ZBB-NEXT: clzw a0, a1
; RV64ZBB-NEXT: xori a0, a0, 31 ; RV64ZBB-NEXT: xori a0, a0, 31
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
; RV64I-NEXT: addi a0, a0, -32 ; RV64I-NEXT: addi a0, a0, -32
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB4_2: ; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: addi a0, zero, 32 ; RV64I-NEXT: addi a0, zero, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: ctlz_lshr_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: srliw a0, a0, 1
; RV64B-NEXT: clzw a0, a0
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: ctlz_lshr_i32: ; RV64ZBB-LABEL: ctlz_lshr_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: srliw a0, a0, 1 ; RV64ZBB-NEXT: srliw a0, a0, 1
; RV64ZBB-NEXT: clzw a0, a0 ; RV64ZBB-NEXT: clzw a0, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%1 = lshr i32 %a, 1 %1 = lshr i32 %a, 1
%2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false) %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
ret i32 %2 ret i32 %2
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB5_2: ; RV64I-NEXT: .LBB5_2:
; RV64I-NEXT: addi a0, zero, 64 ; RV64I-NEXT: addi a0, zero, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: ctlz_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: clz a0, a0
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: ctlz_i64: ; RV64ZBB-LABEL: ctlz_i64:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: clz a0, a0 ; RV64ZBB-NEXT: clz a0, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%1 = call i64 @llvm.ctlz.i64(i64 %a, i1 false) %1 = call i64 @llvm.ctlz.i64(i64 %a, i1 false)
ret i64 %1 ret i64 %1
} }
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB6_2: ; RV64I-NEXT: .LBB6_2:
; RV64I-NEXT: addi a0, zero, 32 ; RV64I-NEXT: addi a0, zero, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: cttz_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: ctzw a0, a0
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: cttz_i32: ; RV64ZBB-LABEL: cttz_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: ctzw a0, a0 ; RV64ZBB-NEXT: ctzw a0, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%1 = call i32 @llvm.cttz.i32(i32 %a, i1 false) %1 = call i32 @llvm.cttz.i32(i32 %a, i1 false)
ret i32 %1 ret i32 %1
} }
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; RV64I-NEXT: slli a1, a1, 16 ; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: addi a1, a1, 257 ; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3@plt ; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: cttz_zero_undef_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: ctzw a0, a0
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: cttz_zero_undef_i32: ; RV64ZBB-LABEL: cttz_zero_undef_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: ctzw a0, a0 ; RV64ZBB-NEXT: ctzw a0, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%1 = call i32 @llvm.cttz.i32(i32 %a, i1 true) %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true)
ret i32 %1 ret i32 %1
} }
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: srli a0, a1, 56 ; RV64I-NEXT: srli a0, a1, 56
; RV64I-NEXT: .LBB8_2: ; RV64I-NEXT: .LBB8_2:
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: findFirstSet_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: ctzw a1, a0
; RV64B-NEXT: addi a2, zero, -1
; RV64B-NEXT: cmov a0, a0, a1, a2
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: findFirstSet_i32: ; RV64ZBB-LABEL: findFirstSet_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: mv a1, a0 ; RV64ZBB-NEXT: mv a1, a0
; RV64ZBB-NEXT: addi a0, zero, -1 ; RV64ZBB-NEXT: addi a0, zero, -1
; RV64ZBB-NEXT: beqz a1, .LBB8_2 ; RV64ZBB-NEXT: beqz a1, .LBB8_2
; RV64ZBB-NEXT: # %bb.1: ; RV64ZBB-NEXT: # %bb.1:
; RV64ZBB-NEXT: ctzw a0, a1 ; RV64ZBB-NEXT: ctzw a0, a1
; RV64ZBB-NEXT: .LBB8_2: ; RV64ZBB-NEXT: .LBB8_2:
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; RV64I-NEXT: srli a0, a1, 56 ; RV64I-NEXT: srli a0, a1, 56
; RV64I-NEXT: addi a0, a0, 1 ; RV64I-NEXT: addi a0, a0, 1
; RV64I-NEXT: .LBB9_2: ; RV64I-NEXT: .LBB9_2:
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: ffs_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: ctzw a1, a0
; RV64B-NEXT: addi a1, a1, 1
; RV64B-NEXT: cmov a0, a0, a1, zero
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: ffs_i32: ; RV64ZBB-LABEL: ffs_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: mv a1, a0 ; RV64ZBB-NEXT: mv a1, a0
; RV64ZBB-NEXT: mv a0, zero ; RV64ZBB-NEXT: mv a0, zero
; RV64ZBB-NEXT: beqz a1, .LBB9_2 ; RV64ZBB-NEXT: beqz a1, .LBB9_2
; RV64ZBB-NEXT: # %bb.1: ; RV64ZBB-NEXT: # %bb.1:
; RV64ZBB-NEXT: ctzw a0, a1 ; RV64ZBB-NEXT: ctzw a0, a1
; RV64ZBB-NEXT: addi a0, a0, 1 ; RV64ZBB-NEXT: addi a0, a0, 1
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB10_2: ; RV64I-NEXT: .LBB10_2:
; RV64I-NEXT: addi a0, zero, 64 ; RV64I-NEXT: addi a0, zero, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: cttz_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: ctz a0, a0
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: cttz_i64: ; RV64ZBB-LABEL: cttz_i64:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: ctz a0, a0 ; RV64ZBB-NEXT: ctz a0, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%1 = call i64 @llvm.cttz.i64(i64 %a, i1 false) %1 = call i64 @llvm.cttz.i64(i64 %a, i1 false)
ret i64 %1 ret i64 %1
} }
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; RV64I-NEXT: slli a1, a1, 16 ; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: addi a1, a1, 257 ; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3@plt ; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: ctpop_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: cpopw a0, a0
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: ctpop_i32: ; RV64ZBB-LABEL: ctpop_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: cpopw a0, a0 ; RV64ZBB-NEXT: cpopw a0, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%1 = call i32 @llvm.ctpop.i32(i32 %a) %1 = call i32 @llvm.ctpop.i32(i32 %a)
ret i32 %1 ret i32 %1
} }
Show All 38 Lines
; RV64I-NEXT: slli a1, a1, 16 ; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: addi a1, a1, 257 ; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3@plt ; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: ctpop_i32_load:
; RV64B: # %bb.0:
; RV64B-NEXT: lwu a0, 0(a0)
; RV64B-NEXT: cpopw a0, a0
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: ctpop_i32_load: ; RV64ZBB-LABEL: ctpop_i32_load:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: lwu a0, 0(a0) ; RV64ZBB-NEXT: lwu a0, 0(a0)
; RV64ZBB-NEXT: cpopw a0, a0 ; RV64ZBB-NEXT: cpopw a0, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%a = load i32, i32* %p %a = load i32, i32* %p
%1 = call i32 @llvm.ctpop.i32(i32 %a) %1 = call i32 @llvm.ctpop.i32(i32 %a)
ret i32 %1 ret i32 %1
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; RV64I-NEXT: slli a1, a1, 16 ; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: addi a1, a1, 257 ; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3@plt ; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: ctpop_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: cpop a0, a0
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: ctpop_i64: ; RV64ZBB-LABEL: ctpop_i64:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: cpop a0, a0 ; RV64ZBB-NEXT: cpop a0, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%1 = call i64 @llvm.ctpop.i64(i64 %a) %1 = call i64 @llvm.ctpop.i64(i64 %a)
ret i64 %1 ret i64 %1
} }
define signext i32 @sextb_i32(i32 signext %a) nounwind { define signext i32 @sextb_i32(i32 signext %a) nounwind {
; RV64I-LABEL: sextb_i32: ; RV64I-LABEL: sextb_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sextb_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: sext.b a0, a0
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: sextb_i32: ; RV64ZBB-LABEL: sextb_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: sext.b a0, a0 ; RV64ZBB-NEXT: sext.b a0, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%shl = shl i32 %a, 24 %shl = shl i32 %a, 24
%shr = ashr exact i32 %shl, 24 %shr = ashr exact i32 %shl, 24
ret i32 %shr ret i32 %shr
} }
define i64 @sextb_i64(i64 %a) nounwind { define i64 @sextb_i64(i64 %a) nounwind {
; RV64I-LABEL: sextb_i64: ; RV64I-LABEL: sextb_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sextb_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: sext.b a0, a0
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: sextb_i64: ; RV64ZBB-LABEL: sextb_i64:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: sext.b a0, a0 ; RV64ZBB-NEXT: sext.b a0, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%shl = shl i64 %a, 56 %shl = shl i64 %a, 56
%shr = ashr exact i64 %shl, 56 %shr = ashr exact i64 %shl, 56
ret i64 %shr ret i64 %shr
} }
define signext i32 @sexth_i32(i32 signext %a) nounwind { define signext i32 @sexth_i32(i32 signext %a) nounwind {
; RV64I-LABEL: sexth_i32: ; RV64I-LABEL: sexth_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sexth_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: sext.h a0, a0
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: sexth_i32: ; RV64ZBB-LABEL: sexth_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: sext.h a0, a0 ; RV64ZBB-NEXT: sext.h a0, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%shl = shl i32 %a, 16 %shl = shl i32 %a, 16
%shr = ashr exact i32 %shl, 16 %shr = ashr exact i32 %shl, 16
ret i32 %shr ret i32 %shr
} }
define i64 @sexth_i64(i64 %a) nounwind { define i64 @sexth_i64(i64 %a) nounwind {
; RV64I-LABEL: sexth_i64: ; RV64I-LABEL: sexth_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sexth_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: sext.h a0, a0
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: sexth_i64: ; RV64ZBB-LABEL: sexth_i64:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: sext.h a0, a0 ; RV64ZBB-NEXT: sext.h a0, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%shl = shl i64 %a, 48 %shl = shl i64 %a, 48
%shr = ashr exact i64 %shl, 48 %shr = ashr exact i64 %shl, 48
ret i64 %shr ret i64 %shr
} }
define signext i32 @min_i32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @min_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: min_i32: ; RV64I-LABEL: min_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: blt a0, a1, .LBB18_2 ; RV64I-NEXT: blt a0, a1, .LBB18_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: .LBB18_2: ; RV64I-NEXT: .LBB18_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: min_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: min a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: min_i32: ; RV64ZBB-LABEL: min_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: min a0, a0, a1 ; RV64ZBB-NEXT: min a0, a0, a1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%cmp = icmp slt i32 %a, %b %cmp = icmp slt i32 %a, %b
%cond = select i1 %cmp, i32 %a, i32 %b %cond = select i1 %cmp, i32 %a, i32 %b
ret i32 %cond ret i32 %cond
} }
define i64 @min_i64(i64 %a, i64 %b) nounwind { define i64 @min_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: min_i64: ; RV64I-LABEL: min_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: blt a0, a1, .LBB19_2 ; RV64I-NEXT: blt a0, a1, .LBB19_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: .LBB19_2: ; RV64I-NEXT: .LBB19_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: min_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: min a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: min_i64: ; RV64ZBB-LABEL: min_i64:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: min a0, a0, a1 ; RV64ZBB-NEXT: min a0, a0, a1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%cmp = icmp slt i64 %a, %b %cmp = icmp slt i64 %a, %b
%cond = select i1 %cmp, i64 %a, i64 %b %cond = select i1 %cmp, i64 %a, i64 %b
ret i64 %cond ret i64 %cond
} }
define signext i32 @max_i32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @max_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: max_i32: ; RV64I-LABEL: max_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: blt a1, a0, .LBB20_2 ; RV64I-NEXT: blt a1, a0, .LBB20_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: .LBB20_2: ; RV64I-NEXT: .LBB20_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: max_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: max a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: max_i32: ; RV64ZBB-LABEL: max_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: max a0, a0, a1 ; RV64ZBB-NEXT: max a0, a0, a1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%cmp = icmp sgt i32 %a, %b %cmp = icmp sgt i32 %a, %b
%cond = select i1 %cmp, i32 %a, i32 %b %cond = select i1 %cmp, i32 %a, i32 %b
ret i32 %cond ret i32 %cond
} }
define i64 @max_i64(i64 %a, i64 %b) nounwind { define i64 @max_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: max_i64: ; RV64I-LABEL: max_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: blt a1, a0, .LBB21_2 ; RV64I-NEXT: blt a1, a0, .LBB21_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: .LBB21_2: ; RV64I-NEXT: .LBB21_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: max_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: max a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: max_i64: ; RV64ZBB-LABEL: max_i64:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: max a0, a0, a1 ; RV64ZBB-NEXT: max a0, a0, a1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%cmp = icmp sgt i64 %a, %b %cmp = icmp sgt i64 %a, %b
%cond = select i1 %cmp, i64 %a, i64 %b %cond = select i1 %cmp, i64 %a, i64 %b
ret i64 %cond ret i64 %cond
} }
define signext i32 @minu_i32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @minu_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: minu_i32: ; RV64I-LABEL: minu_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bltu a0, a1, .LBB22_2 ; RV64I-NEXT: bltu a0, a1, .LBB22_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: .LBB22_2: ; RV64I-NEXT: .LBB22_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: minu_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: minu a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: minu_i32: ; RV64ZBB-LABEL: minu_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: minu a0, a0, a1 ; RV64ZBB-NEXT: minu a0, a0, a1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%cmp = icmp ult i32 %a, %b %cmp = icmp ult i32 %a, %b
%cond = select i1 %cmp, i32 %a, i32 %b %cond = select i1 %cmp, i32 %a, i32 %b
ret i32 %cond ret i32 %cond
} }
define i64 @minu_i64(i64 %a, i64 %b) nounwind { define i64 @minu_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: minu_i64: ; RV64I-LABEL: minu_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bltu a0, a1, .LBB23_2 ; RV64I-NEXT: bltu a0, a1, .LBB23_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: .LBB23_2: ; RV64I-NEXT: .LBB23_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: minu_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: minu a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: minu_i64: ; RV64ZBB-LABEL: minu_i64:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: minu a0, a0, a1 ; RV64ZBB-NEXT: minu a0, a0, a1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%cmp = icmp ult i64 %a, %b %cmp = icmp ult i64 %a, %b
%cond = select i1 %cmp, i64 %a, i64 %b %cond = select i1 %cmp, i64 %a, i64 %b
ret i64 %cond ret i64 %cond
} }
define signext i32 @maxu_i32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @maxu_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: maxu_i32: ; RV64I-LABEL: maxu_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bltu a1, a0, .LBB24_2 ; RV64I-NEXT: bltu a1, a0, .LBB24_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: .LBB24_2: ; RV64I-NEXT: .LBB24_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: maxu_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: maxu a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: maxu_i32: ; RV64ZBB-LABEL: maxu_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: maxu a0, a0, a1 ; RV64ZBB-NEXT: maxu a0, a0, a1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%cmp = icmp ugt i32 %a, %b %cmp = icmp ugt i32 %a, %b
%cond = select i1 %cmp, i32 %a, i32 %b %cond = select i1 %cmp, i32 %a, i32 %b
ret i32 %cond ret i32 %cond
} }
define i64 @maxu_i64(i64 %a, i64 %b) nounwind { define i64 @maxu_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: maxu_i64: ; RV64I-LABEL: maxu_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bltu a1, a0, .LBB25_2 ; RV64I-NEXT: bltu a1, a0, .LBB25_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: .LBB25_2: ; RV64I-NEXT: .LBB25_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: maxu_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: maxu a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: maxu_i64: ; RV64ZBB-LABEL: maxu_i64:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: maxu a0, a0, a1 ; RV64ZBB-NEXT: maxu a0, a0, a1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%cmp = icmp ugt i64 %a, %b %cmp = icmp ugt i64 %a, %b
%cond = select i1 %cmp, i64 %a, i64 %b %cond = select i1 %cmp, i64 %a, i64 %b
ret i64 %cond ret i64 %cond
} }
declare i32 @llvm.abs.i32(i32, i1 immarg) declare i32 @llvm.abs.i32(i32, i1 immarg)
define i32 @abs_i32(i32 %x) { define i32 @abs_i32(i32 %x) {
; RV64I-LABEL: abs_i32: ; RV64I-LABEL: abs_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: srai a1, a0, 63 ; RV64I-NEXT: srai a1, a0, 63
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: abs_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: sext.w a0, a0
; RV64B-NEXT: neg a1, a0
; RV64B-NEXT: max a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: abs_i32: ; RV64ZBB-LABEL: abs_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: sext.w a0, a0 ; RV64ZBB-NEXT: sext.w a0, a0
; RV64ZBB-NEXT: neg a1, a0 ; RV64ZBB-NEXT: neg a1, a0
; RV64ZBB-NEXT: max a0, a0, a1 ; RV64ZBB-NEXT: max a0, a0, a1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true) %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
ret i32 %abs ret i32 %abs
} }
declare i64 @llvm.abs.i64(i64, i1 immarg) declare i64 @llvm.abs.i64(i64, i1 immarg)
define i64 @abs_i64(i64 %x) { define i64 @abs_i64(i64 %x) {
; RV64I-LABEL: abs_i64: ; RV64I-LABEL: abs_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srai a1, a0, 63 ; RV64I-NEXT: srai a1, a0, 63
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: abs_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: neg a1, a0
; RV64B-NEXT: max a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: abs_i64: ; RV64ZBB-LABEL: abs_i64:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: neg a1, a0 ; RV64ZBB-NEXT: neg a1, a0
; RV64ZBB-NEXT: max a0, a0, a1 ; RV64ZBB-NEXT: max a0, a0, a1
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
ret i64 %abs ret i64 %abs
} }
define i32 @zexth_i32(i32 %a) nounwind { define i32 @zexth_i32(i32 %a) nounwind {
; RV64I-LABEL: zexth_i32: ; RV64I-LABEL: zexth_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: zexth_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: zext.h a0, a0
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: zexth_i32: ; RV64ZBB-LABEL: zexth_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: zext.h a0, a0 ; RV64ZBB-NEXT: zext.h a0, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%and = and i32 %a, 65535 %and = and i32 %a, 65535
ret i32 %and ret i32 %and
} }
define i64 @zexth_i64(i64 %a) nounwind { define i64 @zexth_i64(i64 %a) nounwind {
; RV64I-LABEL: zexth_i64: ; RV64I-LABEL: zexth_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: zexth_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: zext.h a0, a0
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: zexth_i64: ; RV64ZBB-LABEL: zexth_i64:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: zext.h a0, a0 ; RV64ZBB-NEXT: zext.h a0, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%and = and i64 %a, 65535 %and = and i64 %a, 65535
ret i64 %and ret i64 %and
} }
Show All 11 Lines
; RV64I-NEXT: slli a2, a0, 8 ; RV64I-NEXT: slli a2, a0, 8
; RV64I-NEXT: lui a3, 4080 ; RV64I-NEXT: lui a3, 4080
; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: slliw a0, a0, 24 ; RV64I-NEXT: slliw a0, a0, 24
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: bswap_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 24
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: bswap_i32: ; RV64ZBB-LABEL: bswap_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rev8 a0, a0 ; RV64ZBB-NEXT: rev8 a0, a0
; RV64ZBB-NEXT: srai a0, a0, 32 ; RV64ZBB-NEXT: srai a0, a0, 32
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%1 = tail call i32 @llvm.bswap.i32(i32 %a) %1 = tail call i32 @llvm.bswap.i32(i32 %a)
ret i32 %1 ret i32 %1
} }
Show All 12 Lines
; RV64I-NEXT: lui a4, 4080 ; RV64I-NEXT: lui a4, 4080
; RV64I-NEXT: and a3, a3, a4 ; RV64I-NEXT: and a3, a3, a4
; RV64I-NEXT: slli a0, a0, 24 ; RV64I-NEXT: slli a0, a0, 24
; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: sw a0, 0(a1) ; RV64I-NEXT: sw a0, 0(a1)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: bswap_i32_nosext:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 24
; RV64B-NEXT: sw a0, 0(a1)
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: bswap_i32_nosext: ; RV64ZBB-LABEL: bswap_i32_nosext:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rev8 a0, a0 ; RV64ZBB-NEXT: rev8 a0, a0
; RV64ZBB-NEXT: srli a0, a0, 32 ; RV64ZBB-NEXT: srli a0, a0, 32
; RV64ZBB-NEXT: sw a0, 0(a1) ; RV64ZBB-NEXT: sw a0, 0(a1)
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%1 = tail call i32 @llvm.bswap.i32(i32 %a) %1 = tail call i32 @llvm.bswap.i32(i32 %a)
store i32 %1, i32* %x store i32 %1, i32* %x
Show All 30 Lines
; RV64I-NEXT: slli a3, a3, 48 ; RV64I-NEXT: slli a3, a3, 48
; RV64I-NEXT: and a3, a4, a3 ; RV64I-NEXT: and a3, a4, a3
; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: bswap_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: rev8 a0, a0
; RV64B-NEXT: ret
;
; RV64ZBB-LABEL: bswap_i64: ; RV64ZBB-LABEL: bswap_i64:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rev8 a0, a0 ; RV64ZBB-NEXT: rev8 a0, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%1 = call i64 @llvm.bswap.i64(i64 %a) %1 = call i64 @llvm.bswap.i64(i64 %a)
ret i64 %1 ret i64 %1
} }

llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64B
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbc -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbc -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBC ; RUN: | FileCheck %s -check-prefix=RV64ZBC
declare i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b) declare i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
define i64 @clmul64(i64 %a, i64 %b) nounwind { define i64 @clmul64(i64 %a, i64 %b) nounwind {
; RV64B-LABEL: clmul64:
; RV64B: # %bb.0:
; RV64B-NEXT: clmul a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBC-LABEL: clmul64: ; RV64ZBC-LABEL: clmul64:
; RV64ZBC: # %bb.0: ; RV64ZBC: # %bb.0:
; RV64ZBC-NEXT: clmul a0, a0, a1 ; RV64ZBC-NEXT: clmul a0, a0, a1
; RV64ZBC-NEXT: ret ; RV64ZBC-NEXT: ret
%tmp = call i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b) %tmp = call i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
ret i64 %tmp ret i64 %tmp
} }
declare i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b) declare i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b)
define i64 @clmul64h(i64 %a, i64 %b) nounwind { define i64 @clmul64h(i64 %a, i64 %b) nounwind {
; RV64B-LABEL: clmul64h:
; RV64B: # %bb.0:
; RV64B-NEXT: clmulh a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBC-LABEL: clmul64h: ; RV64ZBC-LABEL: clmul64h:
; RV64ZBC: # %bb.0: ; RV64ZBC: # %bb.0:
; RV64ZBC-NEXT: clmulh a0, a0, a1 ; RV64ZBC-NEXT: clmulh a0, a0, a1
; RV64ZBC-NEXT: ret ; RV64ZBC-NEXT: ret
%tmp = call i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b) %tmp = call i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b)
ret i64 %tmp ret i64 %tmp
} }
declare i64 @llvm.riscv.clmulr.i64(i64 %a, i64 %b) declare i64 @llvm.riscv.clmulr.i64(i64 %a, i64 %b)
define i64 @clmul64r(i64 %a, i64 %b) nounwind { define i64 @clmul64r(i64 %a, i64 %b) nounwind {
; RV64B-LABEL: clmul64r:
; RV64B: # %bb.0:
; RV64B-NEXT: clmulr a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBC-LABEL: clmul64r: ; RV64ZBC-LABEL: clmul64r:
; RV64ZBC: # %bb.0: ; RV64ZBC: # %bb.0:
; RV64ZBC-NEXT: clmulr a0, a0, a1 ; RV64ZBC-NEXT: clmulr a0, a0, a1
; RV64ZBC-NEXT: ret ; RV64ZBC-NEXT: ret
%tmp = call i64 @llvm.riscv.clmulr.i64(i64 %a, i64 %b) %tmp = call i64 @llvm.riscv.clmulr.i64(i64 %a, i64 %b)
ret i64 %tmp ret i64 %tmp
} }

llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64B
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBE ; RUN: | FileCheck %s -check-prefix=RV64ZBE
declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b) declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
define signext i32 @bcompress32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @bcompress32(i32 signext %a, i32 signext %b) nounwind {
; RV64B-LABEL: bcompress32:
; RV64B: # %bb.0:
; RV64B-NEXT: bcompressw a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBE-LABEL: bcompress32: ; RV64ZBE-LABEL: bcompress32:
; RV64ZBE: # %bb.0: ; RV64ZBE: # %bb.0:
; RV64ZBE-NEXT: bcompressw a0, a0, a1 ; RV64ZBE-NEXT: bcompressw a0, a0, a1
; RV64ZBE-NEXT: ret ; RV64ZBE-NEXT: ret
%tmp = call i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
ret i32 %tmp ret i32 %tmp
} }
define signext i32 @bcompress32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { define signext i32 @bcompress32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
; RV64B-LABEL: bcompress32_demandedbits:
; RV64B: # %bb.0:
; RV64B-NEXT: add a0, a0, a1
; RV64B-NEXT: add a1, a2, a3
; RV64B-NEXT: bcompressw a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBE-LABEL: bcompress32_demandedbits: ; RV64ZBE-LABEL: bcompress32_demandedbits:
; RV64ZBE: # %bb.0: ; RV64ZBE: # %bb.0:
; RV64ZBE-NEXT: add a0, a0, a1 ; RV64ZBE-NEXT: add a0, a0, a1
; RV64ZBE-NEXT: add a1, a2, a3 ; RV64ZBE-NEXT: add a1, a2, a3
; RV64ZBE-NEXT: bcompressw a0, a0, a1 ; RV64ZBE-NEXT: bcompressw a0, a0, a1
; RV64ZBE-NEXT: ret ; RV64ZBE-NEXT: ret
%e = add i32 %a, %b %e = add i32 %a, %b
%f = add i32 %c, %d %f = add i32 %c, %d
%tmp = call i32 @llvm.riscv.bcompress.i32(i32 %e, i32 %f) %tmp = call i32 @llvm.riscv.bcompress.i32(i32 %e, i32 %f)
ret i32 %tmp ret i32 %tmp
} }
declare i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b) declare i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
define signext i32 @bdecompress32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @bdecompress32(i32 signext %a, i32 signext %b) nounwind {
; RV64B-LABEL: bdecompress32:
; RV64B: # %bb.0:
; RV64B-NEXT: bdecompressw a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBE-LABEL: bdecompress32: ; RV64ZBE-LABEL: bdecompress32:
; RV64ZBE: # %bb.0: ; RV64ZBE: # %bb.0:
; RV64ZBE-NEXT: bdecompressw a0, a0, a1 ; RV64ZBE-NEXT: bdecompressw a0, a0, a1
; RV64ZBE-NEXT: ret ; RV64ZBE-NEXT: ret
%tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
ret i32 %tmp ret i32 %tmp
} }
define signext i32 @bdecompress32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { define signext i32 @bdecompress32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
; RV64B-LABEL: bdecompress32_demandedbits:
; RV64B: # %bb.0:
; RV64B-NEXT: add a0, a0, a1
; RV64B-NEXT: add a1, a2, a3
; RV64B-NEXT: bdecompressw a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBE-LABEL: bdecompress32_demandedbits: ; RV64ZBE-LABEL: bdecompress32_demandedbits:
; RV64ZBE: # %bb.0: ; RV64ZBE: # %bb.0:
; RV64ZBE-NEXT: add a0, a0, a1 ; RV64ZBE-NEXT: add a0, a0, a1
; RV64ZBE-NEXT: add a1, a2, a3 ; RV64ZBE-NEXT: add a1, a2, a3
; RV64ZBE-NEXT: bdecompressw a0, a0, a1 ; RV64ZBE-NEXT: bdecompressw a0, a0, a1
; RV64ZBE-NEXT: ret ; RV64ZBE-NEXT: ret
%e = add i32 %a, %b %e = add i32 %a, %b
%f = add i32 %c, %d %f = add i32 %c, %d
%tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %e, i32 %f) %tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %e, i32 %f)
ret i32 %tmp ret i32 %tmp
} }
declare i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b) declare i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b)
define i64 @bcompress64(i64 %a, i64 %b) nounwind { define i64 @bcompress64(i64 %a, i64 %b) nounwind {
; RV64B-LABEL: bcompress64:
; RV64B: # %bb.0:
; RV64B-NEXT: bcompress a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBE-LABEL: bcompress64: ; RV64ZBE-LABEL: bcompress64:
; RV64ZBE: # %bb.0: ; RV64ZBE: # %bb.0:
; RV64ZBE-NEXT: bcompress a0, a0, a1 ; RV64ZBE-NEXT: bcompress a0, a0, a1
; RV64ZBE-NEXT: ret ; RV64ZBE-NEXT: ret
%tmp = call i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b) %tmp = call i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b)
ret i64 %tmp ret i64 %tmp
} }
declare i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b) declare i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b)
define i64 @bdecompress64(i64 %a, i64 %b) nounwind { define i64 @bdecompress64(i64 %a, i64 %b) nounwind {
; RV64B-LABEL: bdecompress64:
; RV64B: # %bb.0:
; RV64B-NEXT: bdecompress a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBE-LABEL: bdecompress64: ; RV64ZBE-LABEL: bdecompress64:
; RV64ZBE: # %bb.0: ; RV64ZBE: # %bb.0:
; RV64ZBE-NEXT: bdecompress a0, a0, a1 ; RV64ZBE-NEXT: bdecompress a0, a0, a1
; RV64ZBE-NEXT: ret ; RV64ZBE-NEXT: ret
%tmp = call i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b) %tmp = call i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b)
ret i64 %tmp ret i64 %tmp
} }

llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64B
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBP ; RUN: | FileCheck %s -check-prefix=RV64ZBP
declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b) declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
define signext i32 @grev32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @grev32(i32 signext %a, i32 signext %b) nounwind {
; RV64B-LABEL: grev32:
; RV64B: # %bb.0:
; RV64B-NEXT: grevw a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev32: ; RV64ZBP-LABEL: grev32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: grevw a0, a0, a1 ; RV64ZBP-NEXT: grevw a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
ret i32 %tmp ret i32 %tmp
} }
define signext i32 @grev32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c) nounwind { define signext i32 @grev32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
; RV64B-LABEL: grev32_demandedbits:
; RV64B: # %bb.0:
; RV64B-NEXT: add a0, a0, a1
; RV64B-NEXT: grevw a0, a0, a2
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev32_demandedbits: ; RV64ZBP-LABEL: grev32_demandedbits:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: add a0, a0, a1 ; RV64ZBP-NEXT: add a0, a0, a1
; RV64ZBP-NEXT: grevw a0, a0, a2 ; RV64ZBP-NEXT: grevw a0, a0, a2
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%d = add i32 %a, %b %d = add i32 %a, %b
%e = and i32 %c, 31 %e = and i32 %c, 31
%tmp = call i32 @llvm.riscv.grev.i32(i32 %d, i32 %e) %tmp = call i32 @llvm.riscv.grev.i32(i32 %d, i32 %e)
ret i32 %tmp ret i32 %tmp
} }
declare i32 @llvm.riscv.grevi.i32(i32 %a) declare i32 @llvm.riscv.grevi.i32(i32 %a)
define signext i32 @grevi32(i32 signext %a) nounwind { define signext i32 @grevi32(i32 signext %a) nounwind {
; RV64B-LABEL: grevi32:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 13
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grevi32: ; RV64ZBP-LABEL: grevi32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 13 ; RV64ZBP-NEXT: greviw a0, a0, 13
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 13) %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 13)
ret i32 %tmp ret i32 %tmp
} }
declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b) declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
define signext i32 @gorc32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @gorc32(i32 signext %a, i32 signext %b) nounwind {
; RV64B-LABEL: gorc32:
; RV64B: # %bb.0:
; RV64B-NEXT: gorcw a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc32: ; RV64ZBP-LABEL: gorc32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorcw a0, a0, a1 ; RV64ZBP-NEXT: gorcw a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
ret i32 %tmp ret i32 %tmp
} }
define signext i32 @gorc32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c) nounwind { define signext i32 @gorc32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
; RV64B-LABEL: gorc32_demandedbits:
; RV64B: # %bb.0:
; RV64B-NEXT: add a0, a0, a1
; RV64B-NEXT: gorcw a0, a0, a2
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc32_demandedbits: ; RV64ZBP-LABEL: gorc32_demandedbits:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: add a0, a0, a1 ; RV64ZBP-NEXT: add a0, a0, a1
; RV64ZBP-NEXT: gorcw a0, a0, a2 ; RV64ZBP-NEXT: gorcw a0, a0, a2
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%d = add i32 %a, %b %d = add i32 %a, %b
%e = and i32 %c, 31 %e = and i32 %c, 31
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %d, i32 %e) %tmp = call i32 @llvm.riscv.gorc.i32(i32 %d, i32 %e)
ret i32 %tmp ret i32 %tmp
} }
define signext i32 @gorci32(i32 signext %a) nounwind { define signext i32 @gorci32(i32 signext %a) nounwind {
; RV64B-LABEL: gorci32:
; RV64B: # %bb.0:
; RV64B-NEXT: gorciw a0, a0, 13
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorci32: ; RV64ZBP-LABEL: gorci32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 13 ; RV64ZBP-NEXT: gorciw a0, a0, 13
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 13) %tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 13)
ret i32 %tmp ret i32 %tmp
} }
declare i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b) declare i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
define signext i32 @shfl32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @shfl32(i32 signext %a, i32 signext %b) nounwind {
; RV64B-LABEL: shfl32:
; RV64B: # %bb.0:
; RV64B-NEXT: shflw a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: shfl32: ; RV64ZBP-LABEL: shfl32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: shflw a0, a0, a1 ; RV64ZBP-NEXT: shflw a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
ret i32 %tmp ret i32 %tmp
} }
define signext i32 @shfl32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c) nounwind { define signext i32 @shfl32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
; RV64B-LABEL: shfl32_demandedbits:
; RV64B: # %bb.0:
; RV64B-NEXT: add a0, a0, a1
; RV64B-NEXT: shflw a0, a0, a2
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: shfl32_demandedbits: ; RV64ZBP-LABEL: shfl32_demandedbits:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: add a0, a0, a1 ; RV64ZBP-NEXT: add a0, a0, a1
; RV64ZBP-NEXT: shflw a0, a0, a2 ; RV64ZBP-NEXT: shflw a0, a0, a2
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%d = add i32 %a, %b %d = add i32 %a, %b
%e = and i32 %c, 15 %e = and i32 %c, 15
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %d, i32 %e) %tmp = call i32 @llvm.riscv.shfl.i32(i32 %d, i32 %e)
ret i32 %tmp ret i32 %tmp
} }
define signext i32 @shfli32(i32 signext %a) nounwind { define signext i32 @shfli32(i32 signext %a) nounwind {
; RV64B-LABEL: shfli32:
; RV64B: # %bb.0:
; RV64B-NEXT: shfli a0, a0, 13
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: shfli32: ; RV64ZBP-LABEL: shfli32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: shfli a0, a0, 13 ; RV64ZBP-NEXT: shfli a0, a0, 13
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 13) %tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 13)
ret i32 %tmp ret i32 %tmp
} }
declare i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b) declare i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b)
define signext i32 @unshfl32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @unshfl32(i32 signext %a, i32 signext %b) nounwind {
; RV64B-LABEL: unshfl32:
; RV64B: # %bb.0:
; RV64B-NEXT: unshflw a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: unshfl32: ; RV64ZBP-LABEL: unshfl32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: unshflw a0, a0, a1 ; RV64ZBP-NEXT: unshflw a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b)
ret i32 %tmp ret i32 %tmp
} }
define signext i32 @unshfl32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c) nounwind { define signext i32 @unshfl32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
; RV64B-LABEL: unshfl32_demandedbits:
; RV64B: # %bb.0:
; RV64B-NEXT: add a0, a0, a1
; RV64B-NEXT: unshflw a0, a0, a2
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: unshfl32_demandedbits: ; RV64ZBP-LABEL: unshfl32_demandedbits:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: add a0, a0, a1 ; RV64ZBP-NEXT: add a0, a0, a1
; RV64ZBP-NEXT: unshflw a0, a0, a2 ; RV64ZBP-NEXT: unshflw a0, a0, a2
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%d = add i32 %a, %b %d = add i32 %a, %b
%e = and i32 %c, 15 %e = and i32 %c, 15
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %d, i32 %e) %tmp = call i32 @llvm.riscv.unshfl.i32(i32 %d, i32 %e)
ret i32 %tmp ret i32 %tmp
} }
define signext i32 @unshfli32(i32 signext %a) nounwind { define signext i32 @unshfli32(i32 signext %a) nounwind {
; RV64B-LABEL: unshfli32:
; RV64B: # %bb.0:
; RV64B-NEXT: unshfli a0, a0, 13
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: unshfli32: ; RV64ZBP-LABEL: unshfli32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: unshfli a0, a0, 13 ; RV64ZBP-NEXT: unshfli a0, a0, 13
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 13) %tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 13)
ret i32 %tmp ret i32 %tmp
} }
declare i64 @llvm.riscv.grev.i64(i64 %a, i64 %b) declare i64 @llvm.riscv.grev.i64(i64 %a, i64 %b)
define i64 @grev64(i64 %a, i64 %b) nounwind { define i64 @grev64(i64 %a, i64 %b) nounwind {
; RV64B-LABEL: grev64:
; RV64B: # %bb.0:
; RV64B-NEXT: grev a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev64: ; RV64ZBP-LABEL: grev64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: grev a0, a0, a1 ; RV64ZBP-NEXT: grev a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 %b) %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 %b)
ret i64 %tmp ret i64 %tmp
} }
define i64 @grev64_demandedbits(i64 %a, i64 %b) nounwind { define i64 @grev64_demandedbits(i64 %a, i64 %b) nounwind {
; RV64B-LABEL: grev64_demandedbits:
; RV64B: # %bb.0:
; RV64B-NEXT: grev a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev64_demandedbits: ; RV64ZBP-LABEL: grev64_demandedbits:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: grev a0, a0, a1 ; RV64ZBP-NEXT: grev a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%c = and i64 %b, 63 %c = and i64 %b, 63
%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 %c) %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 %c)
ret i64 %tmp ret i64 %tmp
} }
define i64 @grevi64(i64 %a) nounwind { define i64 @grevi64(i64 %a) nounwind {
; RV64B-LABEL: grevi64:
; RV64B: # %bb.0:
; RV64B-NEXT: grevi a0, a0, 13
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grevi64: ; RV64ZBP-LABEL: grevi64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: grevi a0, a0, 13 ; RV64ZBP-NEXT: grevi a0, a0, 13
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 13) %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 13)
ret i64 %tmp ret i64 %tmp
} }
declare i64 @llvm.riscv.gorc.i64(i64 %a, i64 %b) declare i64 @llvm.riscv.gorc.i64(i64 %a, i64 %b)
define i64 @gorc64(i64 %a, i64 %b) nounwind { define i64 @gorc64(i64 %a, i64 %b) nounwind {
; RV64B-LABEL: gorc64:
; RV64B: # %bb.0:
; RV64B-NEXT: gorc a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc64: ; RV64ZBP-LABEL: gorc64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorc a0, a0, a1 ; RV64ZBP-NEXT: gorc a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 %b) %tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 %b)
ret i64 %tmp ret i64 %tmp
} }
define i64 @gorc64_demandedbits(i64 %a, i64 %b) nounwind { define i64 @gorc64_demandedbits(i64 %a, i64 %b) nounwind {
; RV64B-LABEL: gorc64_demandedbits:
; RV64B: # %bb.0:
; RV64B-NEXT: gorc a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc64_demandedbits: ; RV64ZBP-LABEL: gorc64_demandedbits:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorc a0, a0, a1 ; RV64ZBP-NEXT: gorc a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%c = and i64 %b, 63 %c = and i64 %b, 63
%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 %c) %tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 %c)
ret i64 %tmp ret i64 %tmp
} }
declare i64 @llvm.riscv.gorci.i64(i64 %a) declare i64 @llvm.riscv.gorci.i64(i64 %a)
define i64 @gorci64(i64 %a) nounwind { define i64 @gorci64(i64 %a) nounwind {
; RV64B-LABEL: gorci64:
; RV64B: # %bb.0:
; RV64B-NEXT: gorci a0, a0, 13
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorci64: ; RV64ZBP-LABEL: gorci64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorci a0, a0, 13 ; RV64ZBP-NEXT: gorci a0, a0, 13
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 13) %tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 13)
ret i64 %tmp ret i64 %tmp
} }
declare i64 @llvm.riscv.shfl.i64(i64 %a, i64 %b) declare i64 @llvm.riscv.shfl.i64(i64 %a, i64 %b)
define i64 @shfl64(i64 %a, i64 %b) nounwind { define i64 @shfl64(i64 %a, i64 %b) nounwind {
; RV64B-LABEL: shfl64:
; RV64B: # %bb.0:
; RV64B-NEXT: shfl a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: shfl64: ; RV64ZBP-LABEL: shfl64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: shfl a0, a0, a1 ; RV64ZBP-NEXT: shfl a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 %b) %tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 %b)
ret i64 %tmp ret i64 %tmp
} }
define i64 @shfl64_demandedbits(i64 %a, i64 %b) nounwind { define i64 @shfl64_demandedbits(i64 %a, i64 %b) nounwind {
; RV64B-LABEL: shfl64_demandedbits:
; RV64B: # %bb.0:
; RV64B-NEXT: shfl a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: shfl64_demandedbits: ; RV64ZBP-LABEL: shfl64_demandedbits:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: shfl a0, a0, a1 ; RV64ZBP-NEXT: shfl a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%c = and i64 %b, 31 %c = and i64 %b, 31
%tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 %c) %tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 %c)
ret i64 %tmp ret i64 %tmp
} }
define i64 @shfli64(i64 %a) nounwind { define i64 @shfli64(i64 %a) nounwind {
; RV64B-LABEL: shfli64:
; RV64B: # %bb.0:
; RV64B-NEXT: shfli a0, a0, 13
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: shfli64: ; RV64ZBP-LABEL: shfli64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: shfli a0, a0, 13 ; RV64ZBP-NEXT: shfli a0, a0, 13
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 13) %tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 13)
ret i64 %tmp ret i64 %tmp
} }
declare i64 @llvm.riscv.unshfl.i64(i64 %a, i64 %b) declare i64 @llvm.riscv.unshfl.i64(i64 %a, i64 %b)
define i64 @unshfl64(i64 %a, i64 %b) nounwind { define i64 @unshfl64(i64 %a, i64 %b) nounwind {
; RV64B-LABEL: unshfl64:
; RV64B: # %bb.0:
; RV64B-NEXT: unshfl a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: unshfl64: ; RV64ZBP-LABEL: unshfl64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: unshfl a0, a0, a1 ; RV64ZBP-NEXT: unshfl a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.unshfl.i64(i64 %a, i64 %b) %tmp = call i64 @llvm.riscv.unshfl.i64(i64 %a, i64 %b)
ret i64 %tmp ret i64 %tmp
} }
define i64 @unshfl64_demandedbits(i64 %a, i64 %b) nounwind { define i64 @unshfl64_demandedbits(i64 %a, i64 %b) nounwind {
; RV64B-LABEL: unshfl64_demandedbits:
; RV64B: # %bb.0:
; RV64B-NEXT: unshfl a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: unshfl64_demandedbits: ; RV64ZBP-LABEL: unshfl64_demandedbits:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: unshfl a0, a0, a1 ; RV64ZBP-NEXT: unshfl a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%c = and i64 %b, 31 %c = and i64 %b, 31
%tmp = call i64 @llvm.riscv.unshfl.i64(i64 %a, i64 %c) %tmp = call i64 @llvm.riscv.unshfl.i64(i64 %a, i64 %c)
ret i64 %tmp ret i64 %tmp
} }
define i64 @unshfli64(i64 %a) nounwind { define i64 @unshfli64(i64 %a) nounwind {
; RV64B-LABEL: unshfli64:
; RV64B: # %bb.0:
; RV64B-NEXT: unshfli a0, a0, 13
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: unshfli64: ; RV64ZBP-LABEL: unshfli64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: unshfli a0, a0, 13 ; RV64ZBP-NEXT: unshfli a0, a0, 13
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.unshfl.i64(i64 %a, i64 13) %tmp = call i64 @llvm.riscv.unshfl.i64(i64 %a, i64 13)
ret i64 %tmp ret i64 %tmp
} }
declare i64 @llvm.riscv.xperm.n.i64(i64 %a, i64 %b) declare i64 @llvm.riscv.xperm.n.i64(i64 %a, i64 %b)
define i64 @xpermn64(i64 %a, i64 %b) nounwind { define i64 @xpermn64(i64 %a, i64 %b) nounwind {
; RV64B-LABEL: xpermn64:
; RV64B: # %bb.0:
; RV64B-NEXT: xperm.n a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: xpermn64: ; RV64ZBP-LABEL: xpermn64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: xperm.n a0, a0, a1 ; RV64ZBP-NEXT: xperm.n a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.xperm.n.i64(i64 %a, i64 %b) %tmp = call i64 @llvm.riscv.xperm.n.i64(i64 %a, i64 %b)
ret i64 %tmp ret i64 %tmp
} }
declare i64 @llvm.riscv.xperm.b.i64(i64 %a, i64 %b) declare i64 @llvm.riscv.xperm.b.i64(i64 %a, i64 %b)
define i64 @xpermb64(i64 %a, i64 %b) nounwind { define i64 @xpermb64(i64 %a, i64 %b) nounwind {
; RV64B-LABEL: xpermb64:
; RV64B: # %bb.0:
; RV64B-NEXT: xperm.b a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: xpermb64: ; RV64ZBP-LABEL: xpermb64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: xperm.b a0, a0, a1 ; RV64ZBP-NEXT: xperm.b a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.xperm.b.i64(i64 %a, i64 %b) %tmp = call i64 @llvm.riscv.xperm.b.i64(i64 %a, i64 %b)
ret i64 %tmp ret i64 %tmp
} }
declare i64 @llvm.riscv.xperm.h.i64(i64 %a, i64 %b) declare i64 @llvm.riscv.xperm.h.i64(i64 %a, i64 %b)
define i64 @xpermh64(i64 %a, i64 %b) nounwind { define i64 @xpermh64(i64 %a, i64 %b) nounwind {
; RV64B-LABEL: xpermh64:
; RV64B: # %bb.0:
; RV64B-NEXT: xperm.h a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: xpermh64: ; RV64ZBP-LABEL: xpermh64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: xperm.h a0, a0, a1 ; RV64ZBP-NEXT: xperm.h a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.xperm.h.i64(i64 %a, i64 %b) %tmp = call i64 @llvm.riscv.xperm.h.i64(i64 %a, i64 %b)
ret i64 %tmp ret i64 %tmp
} }
declare i64 @llvm.riscv.xperm.w.i64(i64 %a, i64 %b) declare i64 @llvm.riscv.xperm.w.i64(i64 %a, i64 %b)
define i64 @xpermw64(i64 %a, i64 %b) nounwind { define i64 @xpermw64(i64 %a, i64 %b) nounwind {
; RV64B-LABEL: xpermw64:
; RV64B: # %bb.0:
; RV64B-NEXT: xperm.w a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: xpermw64: ; RV64ZBP-LABEL: xpermw64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: xperm.w a0, a0, a1 ; RV64ZBP-NEXT: xperm.w a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.xperm.w.i64(i64 %a, i64 %b) %tmp = call i64 @llvm.riscv.xperm.w.i64(i64 %a, i64 %b)
ret i64 %tmp ret i64 %tmp
} }

llvm/test/CodeGen/RISCV/rv64zbp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I ; RUN: | FileCheck %s -check-prefix=RV64I
; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64B
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBP ; RUN: | FileCheck %s -check-prefix=RV64ZBP
define signext i32 @gorc1_i32(i32 signext %a) nounwind { define signext i32 @gorc1_i32(i32 signext %a) nounwind {
; RV64I-LABEL: gorc1_i32: ; RV64I-LABEL: gorc1_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slliw a1, a0, 1 ; RV64I-NEXT: slliw a1, a0, 1
; RV64I-NEXT: lui a2, 699051 ; RV64I-NEXT: lui a2, 699051
; RV64I-NEXT: addiw a2, a2, -1366 ; RV64I-NEXT: addiw a2, a2, -1366
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a2, a0, 1 ; RV64I-NEXT: srli a2, a0, 1
; RV64I-NEXT: lui a3, 349525 ; RV64I-NEXT: lui a3, 349525
; RV64I-NEXT: addiw a3, a3, 1365 ; RV64I-NEXT: addiw a3, a3, 1365
; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc1_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: gorciw a0, a0, 1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc1_i32: ; RV64ZBP-LABEL: gorc1_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 1 ; RV64ZBP-NEXT: gorciw a0, a0, 1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = shl i32 %a, 1 %and = shl i32 %a, 1
%shl = and i32 %and, -1431655766 %shl = and i32 %and, -1431655766
%and1 = lshr i32 %a, 1 %and1 = lshr i32 %a, 1
%shr = and i32 %and1, 1431655765 %shr = and i32 %and1, 1431655765
Show All 24 Lines
; RV64I-NEXT: addi a3, a3, 1365 ; RV64I-NEXT: addi a3, a3, 1365
; RV64I-NEXT: slli a3, a3, 12 ; RV64I-NEXT: slli a3, a3, 12
; RV64I-NEXT: addi a3, a3, 1365 ; RV64I-NEXT: addi a3, a3, 1365
; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc1_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: orc.p a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc1_i64: ; RV64ZBP-LABEL: gorc1_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc.p a0, a0 ; RV64ZBP-NEXT: orc.p a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = shl i64 %a, 1 %and = shl i64 %a, 1
%shl = and i64 %and, -6148914691236517206 %shl = and i64 %and, -6148914691236517206
%and1 = lshr i64 %a, 1 %and1 = lshr i64 %a, 1
%shr = and i64 %and1, 6148914691236517205 %shr = and i64 %and1, 6148914691236517205
Show All 12 Lines
; RV64I-NEXT: srli a2, a0, 2 ; RV64I-NEXT: srli a2, a0, 2
; RV64I-NEXT: lui a3, 209715 ; RV64I-NEXT: lui a3, 209715
; RV64I-NEXT: addiw a3, a3, 819 ; RV64I-NEXT: addiw a3, a3, 819
; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc2_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: gorciw a0, a0, 2
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc2_i32: ; RV64ZBP-LABEL: gorc2_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 2 ; RV64ZBP-NEXT: gorciw a0, a0, 2
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = shl i32 %a, 2 %and = shl i32 %a, 2
%shl = and i32 %and, -858993460 %shl = and i32 %and, -858993460
%and1 = lshr i32 %a, 2 %and1 = lshr i32 %a, 2
%shr = and i32 %and1, 858993459 %shr = and i32 %and1, 858993459
Show All 24 Lines
; RV64I-NEXT: addi a3, a3, 819 ; RV64I-NEXT: addi a3, a3, 819
; RV64I-NEXT: slli a3, a3, 12 ; RV64I-NEXT: slli a3, a3, 12
; RV64I-NEXT: addi a3, a3, 819 ; RV64I-NEXT: addi a3, a3, 819
; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc2_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: orc2.n a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc2_i64: ; RV64ZBP-LABEL: gorc2_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc2.n a0, a0 ; RV64ZBP-NEXT: orc2.n a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = shl i64 %a, 2 %and = shl i64 %a, 2
%shl = and i64 %and, -3689348814741910324 %shl = and i64 %and, -3689348814741910324
%and1 = lshr i64 %a, 2 %and1 = lshr i64 %a, 2
%shr = and i64 %and1, 3689348814741910323 %shr = and i64 %and1, 3689348814741910323
Show All 22 Lines
; RV64I-NEXT: srli a2, a0, 2 ; RV64I-NEXT: srli a2, a0, 2
; RV64I-NEXT: lui a3, 209715 ; RV64I-NEXT: lui a3, 209715
; RV64I-NEXT: addiw a3, a3, 819 ; RV64I-NEXT: addiw a3, a3, 819
; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc3_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: gorciw a0, a0, 3
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc3_i32: ; RV64ZBP-LABEL: gorc3_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 3 ; RV64ZBP-NEXT: gorciw a0, a0, 3
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i32 %a, 1 %and1 = shl i32 %a, 1
%shl1 = and i32 %and1, -1431655766 %shl1 = and i32 %and1, -1431655766
%and1b = lshr i32 %a, 1 %and1b = lshr i32 %a, 1
%shr1 = and i32 %and1b, 1431655765 %shr1 = and i32 %and1b, 1431655765
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; RV64I-NEXT: addi a3, a3, 819 ; RV64I-NEXT: addi a3, a3, 819
; RV64I-NEXT: slli a3, a3, 12 ; RV64I-NEXT: slli a3, a3, 12
; RV64I-NEXT: addi a3, a3, 819 ; RV64I-NEXT: addi a3, a3, 819
; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc3_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: orc.n a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc3_i64: ; RV64ZBP-LABEL: gorc3_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc.n a0, a0 ; RV64ZBP-NEXT: orc.n a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
%shl1 = and i64 %and1, -6148914691236517206 %shl1 = and i64 %and1, -6148914691236517206
%and1b = lshr i64 %a, 1 %and1b = lshr i64 %a, 1
%shr1 = and i64 %and1b, 6148914691236517205 %shr1 = and i64 %and1b, 6148914691236517205
Show All 18 Lines
; RV64I-NEXT: srli a2, a0, 4 ; RV64I-NEXT: srli a2, a0, 4
; RV64I-NEXT: lui a3, 61681 ; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: addiw a3, a3, -241 ; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc4_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: gorciw a0, a0, 4
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc4_i32: ; RV64ZBP-LABEL: gorc4_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 4 ; RV64ZBP-NEXT: gorciw a0, a0, 4
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = shl i32 %a, 4 %and = shl i32 %a, 4
%shl = and i32 %and, -252645136 %shl = and i32 %and, -252645136
%and1 = lshr i32 %a, 4 %and1 = lshr i32 %a, 4
%shr = and i32 %and1, 252645135 %shr = and i32 %and1, 252645135
Show All 24 Lines
; RV64I-NEXT: addi a3, a3, 241 ; RV64I-NEXT: addi a3, a3, 241
; RV64I-NEXT: slli a3, a3, 12 ; RV64I-NEXT: slli a3, a3, 12
; RV64I-NEXT: addi a3, a3, -241 ; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc4_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: orc4.b a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc4_i64: ; RV64ZBP-LABEL: gorc4_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc4.b a0, a0 ; RV64ZBP-NEXT: orc4.b a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = shl i64 %a, 4 %and = shl i64 %a, 4
%shl = and i64 %and, -1085102592571150096 %shl = and i64 %and, -1085102592571150096
%and1 = lshr i64 %a, 4 %and1 = lshr i64 %a, 4
%shr = and i64 %and1, 1085102592571150095 %shr = and i64 %and1, 1085102592571150095
Show All 22 Lines
; RV64I-NEXT: srli a2, a0, 4 ; RV64I-NEXT: srli a2, a0, 4
; RV64I-NEXT: lui a3, 61681 ; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: addiw a3, a3, -241 ; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc5_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: gorciw a0, a0, 5
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc5_i32: ; RV64ZBP-LABEL: gorc5_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 5 ; RV64ZBP-NEXT: gorciw a0, a0, 5
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i32 %a, 1 %and1 = shl i32 %a, 1
%shl1 = and i32 %and1, -1431655766 %shl1 = and i32 %and1, -1431655766
%and1b = lshr i32 %a, 1 %and1b = lshr i32 %a, 1
%shr1 = and i32 %and1b, 1431655765 %shr1 = and i32 %and1b, 1431655765
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; RV64I-NEXT: addi a3, a3, 241 ; RV64I-NEXT: addi a3, a3, 241
; RV64I-NEXT: slli a3, a3, 12 ; RV64I-NEXT: slli a3, a3, 12
; RV64I-NEXT: addi a3, a3, -241 ; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc5_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: gorci a0, a0, 5
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc5_i64: ; RV64ZBP-LABEL: gorc5_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorci a0, a0, 5 ; RV64ZBP-NEXT: gorci a0, a0, 5
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
%shl1 = and i64 %and1, -6148914691236517206 %shl1 = and i64 %and1, -6148914691236517206
%and1b = lshr i64 %a, 1 %and1b = lshr i64 %a, 1
%shr1 = and i64 %and1b, 6148914691236517205 %shr1 = and i64 %and1b, 6148914691236517205
Show All 28 Lines
; RV64I-NEXT: srli a2, a0, 4 ; RV64I-NEXT: srli a2, a0, 4
; RV64I-NEXT: lui a3, 61681 ; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: addiw a3, a3, -241 ; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc6_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: gorciw a0, a0, 6
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc6_i32: ; RV64ZBP-LABEL: gorc6_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 6 ; RV64ZBP-NEXT: gorciw a0, a0, 6
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i32 %a, 2 %and1 = shl i32 %a, 2
%shl1 = and i32 %and1, -858993460 %shl1 = and i32 %and1, -858993460
%and1b = lshr i32 %a, 2 %and1b = lshr i32 %a, 2
%shr1 = and i32 %and1b, 858993459 %shr1 = and i32 %and1b, 858993459
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; RV64I-NEXT: addi a3, a3, 241 ; RV64I-NEXT: addi a3, a3, 241
; RV64I-NEXT: slli a3, a3, 12 ; RV64I-NEXT: slli a3, a3, 12
; RV64I-NEXT: addi a3, a3, -241 ; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc6_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: orc2.b a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc6_i64: ; RV64ZBP-LABEL: gorc6_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc2.b a0, a0 ; RV64ZBP-NEXT: orc2.b a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i64 %a, 2 %and1 = shl i64 %a, 2
%shl1 = and i64 %and1, -3689348814741910324 %shl1 = and i64 %and1, -3689348814741910324
%and1b = lshr i64 %a, 2 %and1b = lshr i64 %a, 2
%shr1 = and i64 %and1b, 3689348814741910323 %shr1 = and i64 %and1b, 3689348814741910323
Show All 39 Lines
; RV64I-NEXT: lui a3, 61681 ; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: addiw a3, a3, -241 ; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc7_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: gorciw a0, a0, 7
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc7_i32: ; RV64ZBP-LABEL: gorc7_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 7 ; RV64ZBP-NEXT: gorciw a0, a0, 7
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i32 %a, 1 %and1 = shl i32 %a, 1
%shl1 = and i32 %and1, -1431655766 %shl1 = and i32 %and1, -1431655766
%and1b = lshr i32 %a, 1 %and1b = lshr i32 %a, 1
%shr1 = and i32 %and1b, 1431655765 %shr1 = and i32 %and1b, 1431655765
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; RV64I-NEXT: addi a3, a3, 241 ; RV64I-NEXT: addi a3, a3, 241
; RV64I-NEXT: slli a3, a3, 12 ; RV64I-NEXT: slli a3, a3, 12
; RV64I-NEXT: addi a3, a3, -241 ; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc7_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: orc.b a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc7_i64: ; RV64ZBP-LABEL: gorc7_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc.b a0, a0 ; RV64ZBP-NEXT: orc.b a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
%shl1 = and i64 %and1, -6148914691236517206 %shl1 = and i64 %and1, -6148914691236517206
%and1b = lshr i64 %a, 1 %and1b = lshr i64 %a, 1
%shr1 = and i64 %and1b, 6148914691236517205 %shr1 = and i64 %and1b, 6148914691236517205
Show All 24 Lines
; RV64I-NEXT: srli a2, a0, 8 ; RV64I-NEXT: srli a2, a0, 8
; RV64I-NEXT: lui a3, 4080 ; RV64I-NEXT: lui a3, 4080
; RV64I-NEXT: addiw a3, a3, 255 ; RV64I-NEXT: addiw a3, a3, 255
; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc8_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: gorciw a0, a0, 8
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc8_i32: ; RV64ZBP-LABEL: gorc8_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 8 ; RV64ZBP-NEXT: gorciw a0, a0, 8
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = shl i32 %a, 8 %and = shl i32 %a, 8
%shl = and i32 %and, -16711936 %shl = and i32 %and, -16711936
%and1 = lshr i32 %a, 8 %and1 = lshr i32 %a, 8
%shr = and i32 %and1, 16711935 %shr = and i32 %and1, 16711935
Show All 20 Lines
; RV64I-NEXT: addi a3, a3, 255 ; RV64I-NEXT: addi a3, a3, 255
; RV64I-NEXT: slli a3, a3, 16 ; RV64I-NEXT: slli a3, a3, 16
; RV64I-NEXT: addi a3, a3, 255 ; RV64I-NEXT: addi a3, a3, 255
; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc8_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: orc8.h a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc8_i64: ; RV64ZBP-LABEL: gorc8_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc8.h a0, a0 ; RV64ZBP-NEXT: orc8.h a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = shl i64 %a, 8 %and = shl i64 %a, 8
%shl = and i64 %and, -71777214294589696 %shl = and i64 %and, -71777214294589696
%and1 = lshr i64 %a, 8 %and1 = lshr i64 %a, 8
%shr = and i64 %and1, 71777214294589695 %shr = and i64 %and1, 71777214294589695
%or = or i64 %shr, %a %or = or i64 %shr, %a
%or2 = or i64 %or, %shl %or2 = or i64 %or, %shl
ret i64 %or2 ret i64 %or2
} }
define signext i32 @gorc16_i32(i32 signext %a) nounwind { define signext i32 @gorc16_i32(i32 signext %a) nounwind {
; RV64I-LABEL: gorc16_i32: ; RV64I-LABEL: gorc16_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slliw a1, a0, 16 ; RV64I-NEXT: slliw a1, a0, 16
; RV64I-NEXT: srliw a2, a0, 16 ; RV64I-NEXT: srliw a2, a0, 16
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc16_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: gorciw a0, a0, 16
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc16_i32: ; RV64ZBP-LABEL: gorc16_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 16 ; RV64ZBP-NEXT: gorciw a0, a0, 16
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%shl = shl i32 %a, 16 %shl = shl i32 %a, 16
%shr = lshr i32 %a, 16 %shr = lshr i32 %a, 16
%or = or i32 %shr, %a %or = or i32 %shr, %a
%or2 = or i32 %or, %shl %or2 = or i32 %or, %shl
ret i32 %or2 ret i32 %or2
} }
define i32 @gorc16_rotl_i32(i32 %a) nounwind { define i32 @gorc16_rotl_i32(i32 %a) nounwind {
; RV64I-LABEL: gorc16_rotl_i32: ; RV64I-LABEL: gorc16_rotl_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a0, 16 ; RV64I-NEXT: srliw a1, a0, 16
; RV64I-NEXT: slliw a2, a0, 16 ; RV64I-NEXT: slliw a2, a0, 16
; RV64I-NEXT: or a1, a2, a1 ; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc16_rotl_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: gorciw a0, a0, 16
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc16_rotl_i32: ; RV64ZBP-LABEL: gorc16_rotl_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 16 ; RV64ZBP-NEXT: gorciw a0, a0, 16
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%rot = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 16) %rot = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 16)
%or = or i32 %rot, %a %or = or i32 %rot, %a
ret i32 %or ret i32 %or
} }
define i32 @gorc16_rotr_i32(i32 %a) nounwind { define i32 @gorc16_rotr_i32(i32 %a) nounwind {
; RV64I-LABEL: gorc16_rotr_i32: ; RV64I-LABEL: gorc16_rotr_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slliw a1, a0, 16 ; RV64I-NEXT: slliw a1, a0, 16
; RV64I-NEXT: srliw a2, a0, 16 ; RV64I-NEXT: srliw a2, a0, 16
; RV64I-NEXT: or a1, a2, a1 ; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc16_rotr_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: gorciw a0, a0, 16
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc16_rotr_i32: ; RV64ZBP-LABEL: gorc16_rotr_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 16 ; RV64ZBP-NEXT: gorciw a0, a0, 16
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%rot = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 16) %rot = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 16)
%or = or i32 %rot, %a %or = or i32 %rot, %a
ret i32 %or ret i32 %or
} }
Show All 11 Lines
; RV64I-NEXT: slli a2, a2, 20 ; RV64I-NEXT: slli a2, a2, 20
; RV64I-NEXT: addi a2, a2, -1 ; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: srli a2, a2, 16 ; RV64I-NEXT: srli a2, a2, 16
; RV64I-NEXT: and a2, a3, a2 ; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc16_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: orc16.w a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc16_i64: ; RV64ZBP-LABEL: gorc16_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc16.w a0, a0 ; RV64ZBP-NEXT: orc16.w a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = shl i64 %a, 16 %and = shl i64 %a, 16
%shl = and i64 %and, -281470681808896 %shl = and i64 %and, -281470681808896
%and1 = lshr i64 %a, 16 %and1 = lshr i64 %a, 16
%shr = and i64 %and1, 281470681808895 %shr = and i64 %and1, 281470681808895
%or = or i64 %shr, %a %or = or i64 %shr, %a
%or2 = or i64 %or, %shl %or2 = or i64 %or, %shl
ret i64 %or2 ret i64 %or2
} }
define i64 @gorc32(i64 %a) nounwind { define i64 @gorc32(i64 %a) nounwind {
; RV64I-LABEL: gorc32: ; RV64I-LABEL: gorc32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 32 ; RV64I-NEXT: slli a1, a0, 32
; RV64I-NEXT: srli a2, a0, 32 ; RV64I-NEXT: srli a2, a0, 32
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc32:
; RV64B: # %bb.0:
; RV64B-NEXT: orc32 a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc32: ; RV64ZBP-LABEL: gorc32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc32 a0, a0 ; RV64ZBP-NEXT: orc32 a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%shl = shl i64 %a, 32 %shl = shl i64 %a, 32
%shr = lshr i64 %a, 32 %shr = lshr i64 %a, 32
%or = or i64 %shr, %a %or = or i64 %shr, %a
%or2 = or i64 %or, %shl %or2 = or i64 %or, %shl
Show All 17 Lines
; RV64I-NEXT: slliw a1, a0, 2 ; RV64I-NEXT: slliw a1, a0, 2
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a2, a0, 2 ; RV64I-NEXT: srli a2, a0, 2
; RV64I-NEXT: and a2, a2, a4 ; RV64I-NEXT: and a2, a2, a4
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc2b_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: gorciw a0, a0, 2
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc2b_i32: ; RV64ZBP-LABEL: gorc2b_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 2 ; RV64ZBP-NEXT: gorciw a0, a0, 2
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i32 %a, 2 %and1 = shl i32 %a, 2
%shl1 = and i32 %and1, -858993460 %shl1 = and i32 %and1, -858993460
%and1b = lshr i32 %a, 2 %and1b = lshr i32 %a, 2
%shr1 = and i32 %and1b, 858993459 %shr1 = and i32 %and1b, 858993459
Show All 37 Lines
; RV64I-NEXT: slli a1, a0, 2 ; RV64I-NEXT: slli a1, a0, 2
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a2, a0, 2 ; RV64I-NEXT: srli a2, a0, 2
; RV64I-NEXT: and a2, a2, a4 ; RV64I-NEXT: and a2, a2, a4
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc2b_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: orc2.n a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc2b_i64: ; RV64ZBP-LABEL: gorc2b_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc2.n a0, a0 ; RV64ZBP-NEXT: orc2.n a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i64 %a, 2 %and1 = shl i64 %a, 2
%shl1 = and i64 %and1, -3689348814741910324 %shl1 = and i64 %and1, -3689348814741910324
%and1b = lshr i64 %a, 2 %and1b = lshr i64 %a, 2
%shr1 = and i64 %and1b, 3689348814741910323 %shr1 = and i64 %and1b, 3689348814741910323
Show All 36 Lines
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a2, a0, 1 ; RV64I-NEXT: srli a2, a0, 1
; RV64I-NEXT: and a2, a2, a4 ; RV64I-NEXT: and a2, a2, a4
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc3b_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: gorciw a0, a0, 3
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc3b_i32: ; RV64ZBP-LABEL: gorc3b_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 3 ; RV64ZBP-NEXT: gorciw a0, a0, 3
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i32 %a, 1 %and1 = shl i32 %a, 1
%shl1 = and i32 %and1, -1431655766 %shl1 = and i32 %and1, -1431655766
%and1b = lshr i32 %a, 1 %and1b = lshr i32 %a, 1
%shr1 = and i32 %and1b, 1431655765 %shr1 = and i32 %and1b, 1431655765
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; RV64I-NEXT: slli a1, a0, 1 ; RV64I-NEXT: slli a1, a0, 1
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a2, a0, 1 ; RV64I-NEXT: srli a2, a0, 1
; RV64I-NEXT: and a2, a2, a4 ; RV64I-NEXT: and a2, a2, a4
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc3b_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: orc.n a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc3b_i64: ; RV64ZBP-LABEL: gorc3b_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc.n a0, a0 ; RV64ZBP-NEXT: orc.n a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
%shl1 = and i64 %and1, -6148914691236517206 %shl1 = and i64 %and1, -6148914691236517206
%and1b = lshr i64 %a, 1 %and1b = lshr i64 %a, 1
%shr1 = and i64 %and1b, 6148914691236517205 %shr1 = and i64 %and1b, 6148914691236517205
Show All 18 Lines
; RV64I-LABEL: gorc32_rotl: ; RV64I-LABEL: gorc32_rotl:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 32 ; RV64I-NEXT: srli a1, a0, 32
; RV64I-NEXT: slli a2, a0, 32 ; RV64I-NEXT: slli a2, a0, 32
; RV64I-NEXT: or a1, a2, a1 ; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc32_rotl:
; RV64B: # %bb.0:
; RV64B-NEXT: orc32 a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc32_rotl: ; RV64ZBP-LABEL: gorc32_rotl:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc32 a0, a0 ; RV64ZBP-NEXT: orc32 a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%rot = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 32) %rot = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 32)
%or = or i64 %rot, %a %or = or i64 %rot, %a
ret i64 %or ret i64 %or
} }
define i64 @gorc32_rotr(i64 %a) nounwind { define i64 @gorc32_rotr(i64 %a) nounwind {
; RV64I-LABEL: gorc32_rotr: ; RV64I-LABEL: gorc32_rotr:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 32 ; RV64I-NEXT: slli a1, a0, 32
; RV64I-NEXT: srli a2, a0, 32 ; RV64I-NEXT: srli a2, a0, 32
; RV64I-NEXT: or a1, a2, a1 ; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: gorc32_rotr:
; RV64B: # %bb.0:
; RV64B-NEXT: orc32 a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: gorc32_rotr: ; RV64ZBP-LABEL: gorc32_rotr:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc32 a0, a0 ; RV64ZBP-NEXT: orc32 a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%rot = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 32) %rot = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 32)
%or = or i64 %rot, %a %or = or i64 %rot, %a
ret i64 %or ret i64 %or
} }
define signext i32 @grev1_i32(i32 signext %a) nounwind { define signext i32 @grev1_i32(i32 signext %a) nounwind {
; RV64I-LABEL: grev1_i32: ; RV64I-LABEL: grev1_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slliw a1, a0, 1 ; RV64I-NEXT: slliw a1, a0, 1
; RV64I-NEXT: lui a2, 699051 ; RV64I-NEXT: lui a2, 699051
; RV64I-NEXT: addiw a2, a2, -1366 ; RV64I-NEXT: addiw a2, a2, -1366
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365 ; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev1_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev1_i32: ; RV64ZBP-LABEL: grev1_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 1 ; RV64ZBP-NEXT: greviw a0, a0, 1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = shl i32 %a, 1 %and = shl i32 %a, 1
%shl = and i32 %and, -1431655766 %shl = and i32 %and, -1431655766
%and1 = lshr i32 %a, 1 %and1 = lshr i32 %a, 1
%shr = and i32 %and1, 1431655765 %shr = and i32 %and1, 1431655765
Show All 22 Lines
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 12
; RV64I-NEXT: addi a2, a2, 1365 ; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 12
; RV64I-NEXT: addi a2, a2, 1365 ; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev1_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: rev.p a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev1_i64: ; RV64ZBP-LABEL: grev1_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev.p a0, a0 ; RV64ZBP-NEXT: rev.p a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = shl i64 %a, 1 %and = shl i64 %a, 1
%shl = and i64 %and, -6148914691236517206 %shl = and i64 %and, -6148914691236517206
%and1 = lshr i64 %a, 1 %and1 = lshr i64 %a, 1
%shr = and i64 %and1, 6148914691236517205 %shr = and i64 %and1, 6148914691236517205
Show All 10 Lines
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a0, a0, 2 ; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: lui a2, 209715 ; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a2, a2, 819 ; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev2_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 2
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev2_i32: ; RV64ZBP-LABEL: grev2_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 2 ; RV64ZBP-NEXT: greviw a0, a0, 2
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = shl i32 %a, 2 %and = shl i32 %a, 2
%shl = and i32 %and, -858993460 %shl = and i32 %and, -858993460
%and1 = lshr i32 %a, 2 %and1 = lshr i32 %a, 2
%shr = and i32 %and1, 858993459 %shr = and i32 %and1, 858993459
Show All 22 Lines
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 12
; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 12
; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev2_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: rev2.n a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev2_i64: ; RV64ZBP-LABEL: grev2_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev2.n a0, a0 ; RV64ZBP-NEXT: rev2.n a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = shl i64 %a, 2 %and = shl i64 %a, 2
%shl = and i64 %and, -3689348814741910324 %shl = and i64 %and, -3689348814741910324
%and1 = lshr i64 %a, 2 %and1 = lshr i64 %a, 2
%shr = and i64 %and1, 3689348814741910323 %shr = and i64 %and1, 3689348814741910323
Show All 19 Lines
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a0, a0, 2 ; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: lui a2, 209715 ; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a2, a2, 819 ; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev3_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 3
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev3_i32: ; RV64ZBP-LABEL: grev3_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 3 ; RV64ZBP-NEXT: greviw a0, a0, 3
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i32 %a, 1 %and1 = shl i32 %a, 1
%shl1 = and i32 %and1, -1431655766 %shl1 = and i32 %and1, -1431655766
%and1b = lshr i32 %a, 1 %and1b = lshr i32 %a, 1
%shr1 = and i32 %and1b, 1431655765 %shr1 = and i32 %and1b, 1431655765
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 12
; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 12
; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev3_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: rev.n a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev3_i64: ; RV64ZBP-LABEL: grev3_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev.n a0, a0 ; RV64ZBP-NEXT: rev.n a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
%shl1 = and i64 %and1, -6148914691236517206 %shl1 = and i64 %and1, -6148914691236517206
%and1b = lshr i64 %a, 1 %and1b = lshr i64 %a, 1
%shr1 = and i64 %and1b, 6148914691236517205 %shr1 = and i64 %and1b, 6148914691236517205
Show All 15 Lines
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a0, a0, 4 ; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: lui a2, 61681 ; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev4_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 4
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev4_i32: ; RV64ZBP-LABEL: grev4_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 4 ; RV64ZBP-NEXT: greviw a0, a0, 4
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = shl i32 %a, 4 %and = shl i32 %a, 4
%shl = and i32 %and, -252645136 %shl = and i32 %and, -252645136
%and1 = lshr i32 %a, 4 %and1 = lshr i32 %a, 4
%shr = and i32 %and1, 252645135 %shr = and i32 %and1, 252645135
Show All 22 Lines
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 12
; RV64I-NEXT: addi a2, a2, 241 ; RV64I-NEXT: addi a2, a2, 241
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 12
; RV64I-NEXT: addi a2, a2, -241 ; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev4_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: rev4.b a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev4_i64: ; RV64ZBP-LABEL: grev4_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev4.b a0, a0 ; RV64ZBP-NEXT: rev4.b a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = shl i64 %a, 4 %and = shl i64 %a, 4
%shl = and i64 %and, -1085102592571150096 %shl = and i64 %and, -1085102592571150096
%and1 = lshr i64 %a, 4 %and1 = lshr i64 %a, 4
%shr = and i64 %and1, 1085102592571150095 %shr = and i64 %and1, 1085102592571150095
Show All 19 Lines
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a0, a0, 4 ; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: lui a2, 61681 ; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev5_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 5
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev5_i32: ; RV64ZBP-LABEL: grev5_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 5 ; RV64ZBP-NEXT: greviw a0, a0, 5
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i32 %a, 1 %and1 = shl i32 %a, 1
%shl1 = and i32 %and1, -1431655766 %shl1 = and i32 %and1, -1431655766
%and1b = lshr i32 %a, 1 %and1b = lshr i32 %a, 1
%shr1 = and i32 %and1b, 1431655765 %shr1 = and i32 %and1b, 1431655765
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 12
; RV64I-NEXT: addi a2, a2, 241 ; RV64I-NEXT: addi a2, a2, 241
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 12
; RV64I-NEXT: addi a2, a2, -241 ; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev5_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: grevi a0, a0, 5
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev5_i64: ; RV64ZBP-LABEL: grev5_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: grevi a0, a0, 5 ; RV64ZBP-NEXT: grevi a0, a0, 5
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
%shl1 = and i64 %and1, -6148914691236517206 %shl1 = and i64 %and1, -6148914691236517206
%and1b = lshr i64 %a, 1 %and1b = lshr i64 %a, 1
%shr1 = and i64 %and1b, 6148914691236517205 %shr1 = and i64 %and1b, 6148914691236517205
Show All 25 Lines
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a0, a0, 4 ; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: lui a2, 61681 ; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev6_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 6
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev6_i32: ; RV64ZBP-LABEL: grev6_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 6 ; RV64ZBP-NEXT: greviw a0, a0, 6
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i32 %a, 2 %and1 = shl i32 %a, 2
%shl1 = and i32 %and1, -858993460 %shl1 = and i32 %and1, -858993460
%and1b = lshr i32 %a, 2 %and1b = lshr i32 %a, 2
%shr1 = and i32 %and1b, 858993459 %shr1 = and i32 %and1b, 858993459
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 12
; RV64I-NEXT: addi a2, a2, 241 ; RV64I-NEXT: addi a2, a2, 241
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 12
; RV64I-NEXT: addi a2, a2, -241 ; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev6_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: rev2.b a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev6_i64: ; RV64ZBP-LABEL: grev6_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev2.b a0, a0 ; RV64ZBP-NEXT: rev2.b a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i64 %a, 2 %and1 = shl i64 %a, 2
%shl1 = and i64 %and1, -3689348814741910324 %shl1 = and i64 %and1, -3689348814741910324
%and1b = lshr i64 %a, 2 %and1b = lshr i64 %a, 2
%shr1 = and i64 %and1b, 3689348814741910323 %shr1 = and i64 %and1b, 3689348814741910323
Show All 33 Lines
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a0, a0, 4 ; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: lui a2, 61681 ; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev7_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 7
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev7_i32: ; RV64ZBP-LABEL: grev7_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 7 ; RV64ZBP-NEXT: greviw a0, a0, 7
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i32 %a, 1 %and1 = shl i32 %a, 1
%shl1 = and i32 %and1, -1431655766 %shl1 = and i32 %and1, -1431655766
%and1b = lshr i32 %a, 1 %and1b = lshr i32 %a, 1
%shr1 = and i32 %and1b, 1431655765 %shr1 = and i32 %and1b, 1431655765
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 12
; RV64I-NEXT: addi a2, a2, 241 ; RV64I-NEXT: addi a2, a2, 241
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 12
; RV64I-NEXT: addi a2, a2, -241 ; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev7_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: rev.b a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev7_i64: ; RV64ZBP-LABEL: grev7_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev.b a0, a0 ; RV64ZBP-NEXT: rev.b a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
%shl1 = and i64 %and1, -6148914691236517206 %shl1 = and i64 %and1, -6148914691236517206
%and1b = lshr i64 %a, 1 %and1b = lshr i64 %a, 1
%shr1 = and i64 %and1b, 6148914691236517205 %shr1 = and i64 %and1b, 6148914691236517205
Show All 20 Lines
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a0, a0, 8 ; RV64I-NEXT: srli a0, a0, 8
; RV64I-NEXT: lui a2, 4080 ; RV64I-NEXT: lui a2, 4080
; RV64I-NEXT: addiw a2, a2, 255 ; RV64I-NEXT: addiw a2, a2, 255
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev8_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 8
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev8_i32: ; RV64ZBP-LABEL: grev8_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 8 ; RV64ZBP-NEXT: greviw a0, a0, 8
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = shl i32 %a, 8 %and = shl i32 %a, 8
%shl = and i32 %and, -16711936 %shl = and i32 %and, -16711936
%and1 = lshr i32 %a, 8 %and1 = lshr i32 %a, 8
%shr = and i32 %and1, 16711935 %shr = and i32 %and1, 16711935
Show All 18 Lines
; RV64I-NEXT: slli a2, a2, 16 ; RV64I-NEXT: slli a2, a2, 16
; RV64I-NEXT: addi a2, a2, 255 ; RV64I-NEXT: addi a2, a2, 255
; RV64I-NEXT: slli a2, a2, 16 ; RV64I-NEXT: slli a2, a2, 16
; RV64I-NEXT: addi a2, a2, 255 ; RV64I-NEXT: addi a2, a2, 255
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev8_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: rev8.h a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev8_i64: ; RV64ZBP-LABEL: grev8_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev8.h a0, a0 ; RV64ZBP-NEXT: rev8.h a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = shl i64 %a, 8 %and = shl i64 %a, 8
%shl = and i64 %and, -71777214294589696 %shl = and i64 %and, -71777214294589696
%and1 = lshr i64 %a, 8 %and1 = lshr i64 %a, 8
%shr = and i64 %and1, 71777214294589695 %shr = and i64 %and1, 71777214294589695
%or = or i64 %shl, %shr %or = or i64 %shl, %shr
ret i64 %or ret i64 %or
} }
define signext i32 @grev16_i32(i32 signext %a) nounwind { define signext i32 @grev16_i32(i32 signext %a) nounwind {
; RV64I-LABEL: grev16_i32: ; RV64I-LABEL: grev16_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slliw a1, a0, 16 ; RV64I-NEXT: slliw a1, a0, 16
; RV64I-NEXT: srliw a0, a0, 16 ; RV64I-NEXT: srliw a0, a0, 16
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev16_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 16
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev16_i32: ; RV64ZBP-LABEL: grev16_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 16 ; RV64ZBP-NEXT: greviw a0, a0, 16
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%shl = shl i32 %a, 16 %shl = shl i32 %a, 16
%shr = lshr i32 %a, 16 %shr = lshr i32 %a, 16
%or = or i32 %shl, %shr %or = or i32 %shl, %shr
ret i32 %or ret i32 %or
} }
declare i32 @llvm.fshl.i32(i32, i32, i32) declare i32 @llvm.fshl.i32(i32, i32, i32)
declare i32 @llvm.fshr.i32(i32, i32, i32) declare i32 @llvm.fshr.i32(i32, i32, i32)
define signext i32 @grev16_i32_fshl(i32 signext %a) nounwind { define signext i32 @grev16_i32_fshl(i32 signext %a) nounwind {
; RV64I-LABEL: grev16_i32_fshl: ; RV64I-LABEL: grev16_i32_fshl:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a0, 16 ; RV64I-NEXT: srliw a1, a0, 16
; RV64I-NEXT: slliw a0, a0, 16 ; RV64I-NEXT: slliw a0, a0, 16
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev16_i32_fshl:
; RV64B: # %bb.0:
; RV64B-NEXT: roriw a0, a0, 16
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev16_i32_fshl: ; RV64ZBP-LABEL: grev16_i32_fshl:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: roriw a0, a0, 16 ; RV64ZBP-NEXT: roriw a0, a0, 16
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%or = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 16) %or = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 16)
ret i32 %or ret i32 %or
} }
define signext i32 @grev16_i32_fshr(i32 signext %a) nounwind { define signext i32 @grev16_i32_fshr(i32 signext %a) nounwind {
; RV64I-LABEL: grev16_i32_fshr: ; RV64I-LABEL: grev16_i32_fshr:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slliw a1, a0, 16 ; RV64I-NEXT: slliw a1, a0, 16
; RV64I-NEXT: srliw a0, a0, 16 ; RV64I-NEXT: srliw a0, a0, 16
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev16_i32_fshr:
; RV64B: # %bb.0:
; RV64B-NEXT: roriw a0, a0, 16
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev16_i32_fshr: ; RV64ZBP-LABEL: grev16_i32_fshr:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: roriw a0, a0, 16 ; RV64ZBP-NEXT: roriw a0, a0, 16
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%or = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 16) %or = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 16)
ret i32 %or ret i32 %or
} }
Show All 9 Lines
; RV64I-NEXT: srli a0, a0, 16 ; RV64I-NEXT: srli a0, a0, 16
; RV64I-NEXT: slli a2, a2, 20 ; RV64I-NEXT: slli a2, a2, 20
; RV64I-NEXT: addi a2, a2, -1 ; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: srli a2, a2, 16 ; RV64I-NEXT: srli a2, a2, 16
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev16_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: rev16.w a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev16_i64: ; RV64ZBP-LABEL: grev16_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev16.w a0, a0 ; RV64ZBP-NEXT: rev16.w a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = shl i64 %a, 16 %and = shl i64 %a, 16
%shl = and i64 %and, -281470681808896 %shl = and i64 %and, -281470681808896
%and1 = lshr i64 %a, 16 %and1 = lshr i64 %a, 16
%shr = and i64 %and1, 281470681808895 %shr = and i64 %and1, 281470681808895
%or = or i64 %shl, %shr %or = or i64 %shl, %shr
ret i64 %or ret i64 %or
} }
define i64 @grev32(i64 %a) nounwind { define i64 @grev32(i64 %a) nounwind {
; RV64I-LABEL: grev32: ; RV64I-LABEL: grev32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 32 ; RV64I-NEXT: slli a1, a0, 32
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev32:
; RV64B: # %bb.0:
; RV64B-NEXT: rori a0, a0, 32
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev32: ; RV64ZBP-LABEL: grev32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rori a0, a0, 32 ; RV64ZBP-NEXT: rori a0, a0, 32
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%shl = shl i64 %a, 32 %shl = shl i64 %a, 32
%shr = lshr i64 %a, 32 %shr = lshr i64 %a, 32
%or = or i64 %shl, %shr %or = or i64 %shl, %shr
ret i64 %or ret i64 %or
Show All 17 Lines
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365 ; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev3b_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 3
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev3b_i32: ; RV64ZBP-LABEL: grev3b_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 3 ; RV64ZBP-NEXT: greviw a0, a0, 3
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and2 = shl i32 %a, 2 %and2 = shl i32 %a, 2
%shl2 = and i32 %and2, -858993460 %shl2 = and i32 %and2, -858993460
%and2b = lshr i32 %a, 2 %and2b = lshr i32 %a, 2
%shr2 = and i32 %and2b, 858993459 %shr2 = and i32 %and2b, 858993459
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 12
; RV64I-NEXT: addi a2, a2, 1365 ; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 12
; RV64I-NEXT: addi a2, a2, 1365 ; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev3b_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: rev.n a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev3b_i64: ; RV64ZBP-LABEL: grev3b_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev.n a0, a0 ; RV64ZBP-NEXT: rev.n a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and2 = shl i64 %a, 2 %and2 = shl i64 %a, 2
%shl2 = and i64 %and2, -3689348814741910324 %shl2 = and i64 %and2, -3689348814741910324
%and2b = lshr i64 %a, 2 %and2b = lshr i64 %a, 2
%shr2 = and i64 %and2b, 3689348814741910323 %shr2 = and i64 %and2b, 3689348814741910323
Show All 30 Lines
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: slliw a1, a0, 1 ; RV64I-NEXT: slliw a1, a0, 1
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev2b_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 2
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev2b_i32: ; RV64ZBP-LABEL: grev2b_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 2 ; RV64ZBP-NEXT: greviw a0, a0, 2
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i32 %a, 1 %and1 = shl i32 %a, 1
%shl1 = and i32 %and1, -1431655766 %shl1 = and i32 %and1, -1431655766
%and1b = lshr i32 %a, 1 %and1b = lshr i32 %a, 1
%shr1 = and i32 %and1b, 1431655765 %shr1 = and i32 %and1b, 1431655765
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: slli a1, a0, 1 ; RV64I-NEXT: slli a1, a0, 1
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev2b_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: rev2.n a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev2b_i64: ; RV64ZBP-LABEL: grev2b_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev2.n a0, a0 ; RV64ZBP-NEXT: rev2.n a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
%shl1 = and i64 %and1, -6148914691236517206 %shl1 = and i64 %and1, -6148914691236517206
%and1b = lshr i64 %a, 1 %and1b = lshr i64 %a, 1
%shr1 = and i64 %and1b, 6148914691236517205 %shr1 = and i64 %and1b, 6148914691236517205
Show All 40 Lines
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: slliw a1, a0, 2 ; RV64I-NEXT: slliw a1, a0, 2
; RV64I-NEXT: and a1, a1, a4 ; RV64I-NEXT: and a1, a1, a4
; RV64I-NEXT: srli a0, a0, 2 ; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a5 ; RV64I-NEXT: and a0, a0, a5
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev0_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev0_i32: ; RV64ZBP-LABEL: grev0_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i32 %a, 1 %and1 = shl i32 %a, 1
%shl1 = and i32 %and1, -1431655766 %shl1 = and i32 %and1, -1431655766
%and1b = lshr i32 %a, 1 %and1b = lshr i32 %a, 1
%shr1 = and i32 %and1b, 1431655765 %shr1 = and i32 %and1b, 1431655765
%or1 = or i32 %shl1, %shr1 %or1 = or i32 %shl1, %shr1
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: slli a1, a0, 2 ; RV64I-NEXT: slli a1, a0, 2
; RV64I-NEXT: and a1, a1, a4 ; RV64I-NEXT: and a1, a1, a4
; RV64I-NEXT: srli a0, a0, 2 ; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a5 ; RV64I-NEXT: and a0, a0, a5
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev0_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev0_i64: ; RV64ZBP-LABEL: grev0_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
%shl1 = and i64 %and1, -6148914691236517206 %shl1 = and i64 %and1, -6148914691236517206
%and1b = lshr i64 %a, 1 %and1b = lshr i64 %a, 1
%shr1 = and i64 %and1b, 6148914691236517205 %shr1 = and i64 %and1b, 6148914691236517205
%or1 = or i64 %shl1, %shr1 %or1 = or i64 %shl1, %shr1
Show All 21 Lines
define i64 @grev32_fshl(i64 %a) nounwind { define i64 @grev32_fshl(i64 %a) nounwind {
; RV64I-LABEL: grev32_fshl: ; RV64I-LABEL: grev32_fshl:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 32 ; RV64I-NEXT: srli a1, a0, 32
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev32_fshl:
; RV64B: # %bb.0:
; RV64B-NEXT: rori a0, a0, 32
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev32_fshl: ; RV64ZBP-LABEL: grev32_fshl:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rori a0, a0, 32 ; RV64ZBP-NEXT: rori a0, a0, 32
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%or = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 32) %or = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 32)
ret i64 %or ret i64 %or
} }
define i64 @grev32_fshr(i64 %a) nounwind { define i64 @grev32_fshr(i64 %a) nounwind {
; RV64I-LABEL: grev32_fshr: ; RV64I-LABEL: grev32_fshr:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 32 ; RV64I-NEXT: slli a1, a0, 32
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: grev32_fshr:
; RV64B: # %bb.0:
; RV64B-NEXT: rori a0, a0, 32
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: grev32_fshr: ; RV64ZBP-LABEL: grev32_fshr:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rori a0, a0, 32 ; RV64ZBP-NEXT: rori a0, a0, 32
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%or = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 32) %or = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 32)
ret i64 %or ret i64 %or
} }
declare i16 @llvm.bswap.i16(i16) declare i16 @llvm.bswap.i16(i16)
define zeroext i16 @bswap_i16(i16 zeroext %a) nounwind { define zeroext i16 @bswap_i16(i16 zeroext %a) nounwind {
; RV64I-LABEL: bswap_i16: ; RV64I-LABEL: bswap_i16:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 8 ; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: slli a0, a0, 8 ; RV64I-NEXT: slli a0, a0, 8
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: bswap_i16:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 8
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: bswap_i16: ; RV64ZBP-LABEL: bswap_i16:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 8 ; RV64ZBP-NEXT: greviw a0, a0, 8
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = tail call i16 @llvm.bswap.i16(i16 %a) %1 = tail call i16 @llvm.bswap.i16(i16 %a)
ret i16 %1 ret i16 %1
} }
Show All 11 Lines
; RV64I-NEXT: slli a2, a0, 8 ; RV64I-NEXT: slli a2, a0, 8
; RV64I-NEXT: lui a3, 4080 ; RV64I-NEXT: lui a3, 4080
; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: slliw a0, a0, 24 ; RV64I-NEXT: slliw a0, a0, 24
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: bswap_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 24
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: bswap_i32: ; RV64ZBP-LABEL: bswap_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 24 ; RV64ZBP-NEXT: greviw a0, a0, 24
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = tail call i32 @llvm.bswap.i32(i32 %a) %1 = tail call i32 @llvm.bswap.i32(i32 %a)
ret i32 %1 ret i32 %1
} }
Show All 11 Lines
; RV64I-NEXT: lui a4, 4080 ; RV64I-NEXT: lui a4, 4080
; RV64I-NEXT: and a3, a3, a4 ; RV64I-NEXT: and a3, a3, a4
; RV64I-NEXT: slli a0, a0, 24 ; RV64I-NEXT: slli a0, a0, 24
; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: sw a0, 0(a1) ; RV64I-NEXT: sw a0, 0(a1)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: bswap_i32_nosext:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 24
; RV64B-NEXT: sw a0, 0(a1)
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: bswap_i32_nosext: ; RV64ZBP-LABEL: bswap_i32_nosext:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 24 ; RV64ZBP-NEXT: greviw a0, a0, 24
; RV64ZBP-NEXT: sw a0, 0(a1) ; RV64ZBP-NEXT: sw a0, 0(a1)
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = tail call i32 @llvm.bswap.i32(i32 %a) %1 = tail call i32 @llvm.bswap.i32(i32 %a)
store i32 %1, i32* %x store i32 %1, i32* %x
ret void ret void
Show All 29 Lines
; RV64I-NEXT: slli a3, a3, 48 ; RV64I-NEXT: slli a3, a3, 48
; RV64I-NEXT: and a3, a4, a3 ; RV64I-NEXT: and a3, a4, a3
; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: bswap_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: rev8 a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: bswap_i64: ; RV64ZBP-LABEL: bswap_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev8 a0, a0 ; RV64ZBP-NEXT: rev8 a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = call i64 @llvm.bswap.i64(i64 %a) %1 = call i64 @llvm.bswap.i64(i64 %a)
ret i64 %1 ret i64 %1
} }
Show All 13 Lines
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: andi a1, a0, 85 ; RV64I-NEXT: andi a1, a0, 85
; RV64I-NEXT: slli a1, a1, 1 ; RV64I-NEXT: slli a1, a1, 1
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: andi a0, a0, 85 ; RV64I-NEXT: andi a0, a0, 85
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: bitreverse_i8:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 7
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: bitreverse_i8: ; RV64ZBP-LABEL: bitreverse_i8:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 7 ; RV64ZBP-NEXT: greviw a0, a0, 7
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = tail call i8 @llvm.bitreverse.i8(i8 %a) %1 = tail call i8 @llvm.bitreverse.i8(i8 %a)
ret i8 %1 ret i8 %1
} }
Show All 23 Lines
; RV64I-NEXT: lui a2, 5 ; RV64I-NEXT: lui a2, 5
; RV64I-NEXT: addiw a2, a2, 1365 ; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: slli a0, a0, 1 ; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: bitreverse_i16:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 15
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: bitreverse_i16: ; RV64ZBP-LABEL: bitreverse_i16:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 15 ; RV64ZBP-NEXT: greviw a0, a0, 15
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = tail call i16 @llvm.bitreverse.i16(i16 %a) %1 = tail call i16 @llvm.bitreverse.i16(i16 %a)
ret i16 %1 ret i16 %1
} }
Show All 32 Lines
; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365 ; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: slliw a0, a0, 1 ; RV64I-NEXT: slliw a0, a0, 1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: bitreverse_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 31
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: bitreverse_i32: ; RV64ZBP-LABEL: bitreverse_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 31 ; RV64ZBP-NEXT: greviw a0, a0, 31
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = tail call i32 @llvm.bitreverse.i32(i32 %a) %1 = tail call i32 @llvm.bitreverse.i32(i32 %a)
ret i32 %1 ret i32 %1
} }
Show All 32 Lines
; RV64I-NEXT: addiw a3, a3, 1365 ; RV64I-NEXT: addiw a3, a3, 1365
; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: slli a0, a0, 1 ; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: sw a0, 0(a1) ; RV64I-NEXT: sw a0, 0(a1)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: bitreverse_i32_nosext:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 31
; RV64B-NEXT: sw a0, 0(a1)
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: bitreverse_i32_nosext: ; RV64ZBP-LABEL: bitreverse_i32_nosext:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 31 ; RV64ZBP-NEXT: greviw a0, a0, 31
; RV64ZBP-NEXT: sw a0, 0(a1) ; RV64ZBP-NEXT: sw a0, 0(a1)
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = tail call i32 @llvm.bitreverse.i32(i32 %a) %1 = tail call i32 @llvm.bitreverse.i32(i32 %a)
store i32 %1, i32* %x store i32 %1, i32* %x
ret void ret void
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 12
; RV64I-NEXT: addi a2, a2, 1365 ; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: slli a0, a0, 1 ; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: bitreverse_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: rev a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: bitreverse_i64: ; RV64ZBP-LABEL: bitreverse_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev a0, a0 ; RV64ZBP-NEXT: rev a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = call i64 @llvm.bitreverse.i64(i64 %a) %1 = call i64 @llvm.bitreverse.i64(i64 %a)
ret i64 %1 ret i64 %1
} }
Show All 9 Lines
; RV64I-NEXT: srliw a0, a0, 8 ; RV64I-NEXT: srliw a0, a0, 8
; RV64I-NEXT: andi a0, a0, -256 ; RV64I-NEXT: andi a0, a0, -256
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: slliw a0, a0, 16 ; RV64I-NEXT: slliw a0, a0, 16
; RV64I-NEXT: srliw a1, a1, 16 ; RV64I-NEXT: srliw a1, a1, 16
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: bswap_rotr_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 8
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: bswap_rotr_i32: ; RV64ZBP-LABEL: bswap_rotr_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 8 ; RV64ZBP-NEXT: greviw a0, a0, 8
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = call i32 @llvm.bswap.i32(i32 %a) %1 = call i32 @llvm.bswap.i32(i32 %a)
%2 = call i32 @llvm.fshr.i32(i32 %1, i32 %1, i32 16) %2 = call i32 @llvm.fshr.i32(i32 %1, i32 %1, i32 16)
ret i32 %2 ret i32 %2
} }
Show All 10 Lines
; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: slli a0, a0, 24 ; RV64I-NEXT: slli a0, a0, 24
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a0, a0, 16 ; RV64I-NEXT: srliw a0, a0, 16
; RV64I-NEXT: slliw a1, a1, 16 ; RV64I-NEXT: slliw a1, a1, 16
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: bswap_rotl_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 8
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: bswap_rotl_i32: ; RV64ZBP-LABEL: bswap_rotl_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 8 ; RV64ZBP-NEXT: greviw a0, a0, 8
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = call i32 @llvm.bswap.i32(i32 %a) %1 = call i32 @llvm.bswap.i32(i32 %a)
%2 = call i32 @llvm.fshl.i32(i32 %1, i32 %1, i32 16) %2 = call i32 @llvm.fshl.i32(i32 %1, i32 %1, i32 16)
ret i32 %2 ret i32 %2
} }
Show All 40 Lines
; RV64I-NEXT: or a1, a1, a2 ; RV64I-NEXT: or a1, a1, a2
; RV64I-NEXT: slli a2, a0, 8 ; RV64I-NEXT: slli a2, a0, 8
; RV64I-NEXT: and a2, a2, a4 ; RV64I-NEXT: and a2, a2, a4
; RV64I-NEXT: slliw a0, a0, 24 ; RV64I-NEXT: slliw a0, a0, 24
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: bitreverse_bswap_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: greviw a0, a0, 7
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: bitreverse_bswap_i32: ; RV64ZBP-LABEL: bitreverse_bswap_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 7 ; RV64ZBP-NEXT: greviw a0, a0, 7
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = call i32 @llvm.bitreverse.i32(i32 %a) %1 = call i32 @llvm.bitreverse.i32(i32 %a)
%2 = call i32 @llvm.bswap.i32(i32 %1) %2 = call i32 @llvm.bswap.i32(i32 %1)
ret i32 %2 ret i32 %2
} }
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
; RV64I-NEXT: slli a4, a0, 40 ; RV64I-NEXT: slli a4, a0, 40
; RV64I-NEXT: and a1, a4, a1 ; RV64I-NEXT: and a1, a4, a1
; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: bitreverse_bswap_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: rev.b a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: bitreverse_bswap_i64: ; RV64ZBP-LABEL: bitreverse_bswap_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev.b a0, a0 ; RV64ZBP-NEXT: rev.b a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%1 = call i64 @llvm.bitreverse.i64(i64 %a) %1 = call i64 @llvm.bitreverse.i64(i64 %a)
%2 = call i64 @llvm.bswap.i64(i64 %1) %2 = call i64 @llvm.bswap.i64(i64 %1)
ret i64 %2 ret i64 %2
} }
Show All 11 Lines
; RV64I-NEXT: or a1, a2, a1 ; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: lui a2, 139810 ; RV64I-NEXT: lui a2, 139810
; RV64I-NEXT: addiw a2, a2, 546 ; RV64I-NEXT: addiw a2, a2, 546
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: shfl1_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: zip.n a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: shfl1_i32: ; RV64ZBP-LABEL: shfl1_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zip.n a0, a0 ; RV64ZBP-NEXT: zip.n a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = and i32 %a, -1717986919 %and = and i32 %a, -1717986919
%shl = shl i32 %a, 1 %shl = shl i32 %a, 1
%and1 = and i32 %shl, 1145324612 %and1 = and i32 %shl, 1145324612
%or = or i32 %and1, %and %or = or i32 %and1, %and
Show All 28 Lines
; RV64I-NEXT: or a1, a1, a2 ; RV64I-NEXT: or a1, a1, a2
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: slli a2, a3, 13 ; RV64I-NEXT: slli a2, a3, 13
; RV64I-NEXT: addi a2, a2, 546 ; RV64I-NEXT: addi a2, a2, 546
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: shfl1_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: zip.n a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: shfl1_i64: ; RV64ZBP-LABEL: shfl1_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zip.n a0, a0 ; RV64ZBP-NEXT: zip.n a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = and i64 %a, -7378697629483820647 %and = and i64 %a, -7378697629483820647
%shl = shl i64 %a, 1 %shl = shl i64 %a, 1
%and1 = and i64 %shl, 4919131752989213764 %and1 = and i64 %shl, 4919131752989213764
%or = or i64 %and, %and1 %or = or i64 %and, %and1
Show All 16 Lines
; RV64I-NEXT: or a1, a2, a1 ; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: srli a0, a0, 2 ; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: lui a2, 49345 ; RV64I-NEXT: lui a2, 49345
; RV64I-NEXT: addiw a2, a2, -1012 ; RV64I-NEXT: addiw a2, a2, -1012
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: shfl2_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: zip2.b a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: shfl2_i32: ; RV64ZBP-LABEL: shfl2_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zip2.b a0, a0 ; RV64ZBP-NEXT: zip2.b a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = and i32 %a, -1010580541 %and = and i32 %a, -1010580541
%shl = shl i32 %a, 2 %shl = shl i32 %a, 2
%and1 = and i32 %shl, 808464432 %and1 = and i32 %shl, 808464432
%or = or i32 %and1, %and %or = or i32 %and1, %and
Show All 29 Lines
; RV64I-NEXT: slli a2, a3, 14 ; RV64I-NEXT: slli a2, a3, 14
; RV64I-NEXT: addi a2, a2, 193 ; RV64I-NEXT: addi a2, a2, 193
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 12
; RV64I-NEXT: addi a2, a2, -1012 ; RV64I-NEXT: addi a2, a2, -1012
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: shfl2_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: zip2.b a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: shfl2_i64: ; RV64ZBP-LABEL: shfl2_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zip2.b a0, a0 ; RV64ZBP-NEXT: zip2.b a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = and i64 %a, -4340410370284600381 %and = and i64 %a, -4340410370284600381
%shl = shl i64 %a, 2 %shl = shl i64 %a, 2
%and1 = and i64 %shl, 3472328296227680304 %and1 = and i64 %shl, 3472328296227680304
%or = or i64 %and, %and1 %or = or i64 %and, %and1
Show All 16 Lines
; RV64I-NEXT: srli a0, a0, 4 ; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: lui a3, 3840 ; RV64I-NEXT: lui a3, 3840
; RV64I-NEXT: addiw a3, a3, 240 ; RV64I-NEXT: addiw a3, a3, 240
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: shfl4_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: zip4.h a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: shfl4_i32: ; RV64ZBP-LABEL: shfl4_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zip4.h a0, a0 ; RV64ZBP-NEXT: zip4.h a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = and i32 %a, -267390961 %and = and i32 %a, -267390961
%shl = shl i32 %a, 4 %shl = shl i32 %a, 4
%and1 = and i32 %shl, 251662080 %and1 = and i32 %shl, 251662080
%shr = lshr i32 %a, 4 %shr = lshr i32 %a, 4
Show All 30 Lines
; RV64I-NEXT: addi a3, a3, 15 ; RV64I-NEXT: addi a3, a3, 15
; RV64I-NEXT: slli a3, a3, 20 ; RV64I-NEXT: slli a3, a3, 20
; RV64I-NEXT: addi a3, a3, 240 ; RV64I-NEXT: addi a3, a3, 240
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: shfl4_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: zip4.h a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: shfl4_i64: ; RV64ZBP-LABEL: shfl4_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zip4.h a0, a0 ; RV64ZBP-NEXT: zip4.h a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = and i64 %a, -1148435428713435121 %and = and i64 %a, -1148435428713435121
%shl = shl i64 %a, 4 %shl = shl i64 %a, 4
%and1 = and i64 %shl, 1080880403494997760 %and1 = and i64 %shl, 1080880403494997760
%shr = lshr i64 %a, 4 %shr = lshr i64 %a, 4
Show All 15 Lines
; RV64I-NEXT: srli a0, a0, 8 ; RV64I-NEXT: srli a0, a0, 8
; RV64I-NEXT: lui a3, 16 ; RV64I-NEXT: lui a3, 16
; RV64I-NEXT: addiw a3, a3, -256 ; RV64I-NEXT: addiw a3, a3, -256
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: shfl8_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: zip8.w a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: shfl8_i32: ; RV64ZBP-LABEL: shfl8_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zip8.w a0, a0 ; RV64ZBP-NEXT: zip8.w a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = and i32 %a, -16776961 %and = and i32 %a, -16776961
%shl = shl i32 %a, 8 %shl = shl i32 %a, 8
%and1 = and i32 %shl, 16711680 %and1 = and i32 %shl, 16711680
%shr = lshr i32 %a, 8 %shr = lshr i32 %a, 8
Show All 23 Lines
; RV64I-NEXT: addi a3, a3, 1 ; RV64I-NEXT: addi a3, a3, 1
; RV64I-NEXT: slli a3, a3, 16 ; RV64I-NEXT: slli a3, a3, 16
; RV64I-NEXT: addi a3, a3, -256 ; RV64I-NEXT: addi a3, a3, -256
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: shfl8_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: zip8.w a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: shfl8_i64: ; RV64ZBP-LABEL: shfl8_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zip8.w a0, a0 ; RV64ZBP-NEXT: zip8.w a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = and i64 %a, -72056494543077121 %and = and i64 %a, -72056494543077121
%shl = shl i64 %a, 8 %shl = shl i64 %a, 8
%and1 = and i64 %shl, 71776119077928960 %and1 = and i64 %shl, 71776119077928960
%shr = lshr i64 %a, 8 %shr = lshr i64 %a, 8
Show All 17 Lines
; RV64I-NEXT: or a1, a2, a1 ; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: srli a0, a0, 16 ; RV64I-NEXT: srli a0, a0, 16
; RV64I-NEXT: lui a2, 65535 ; RV64I-NEXT: lui a2, 65535
; RV64I-NEXT: slli a2, a2, 4 ; RV64I-NEXT: slli a2, a2, 4
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: shfl16:
; RV64B: # %bb.0:
; RV64B-NEXT: zip16 a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: shfl16: ; RV64ZBP-LABEL: shfl16:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zip16 a0, a0 ; RV64ZBP-NEXT: zip16 a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = and i64 %a, -281474976645121 %and = and i64 %a, -281474976645121
%shl = shl i64 %a, 16 %shl = shl i64 %a, 16
%and1 = and i64 %shl, 281470681743360 %and1 = and i64 %shl, 281470681743360
%or = or i64 %and1, %and %or = or i64 %and1, %and
%shr = lshr i64 %a, 16 %shr = lshr i64 %a, 16
%and2 = and i64 %shr, 4294901760 %and2 = and i64 %shr, 4294901760
%or3 = or i64 %or, %and2 %or3 = or i64 %or, %and2
ret i64 %or3 ret i64 %or3
} }
define signext i32 @pack_i32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @pack_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: pack_i32: ; RV64I-LABEL: pack_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16 ; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1 ; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: slliw a1, a1, 16 ; RV64I-NEXT: slliw a1, a1, 16
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: pack_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: packw a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: pack_i32: ; RV64ZBP-LABEL: pack_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: packw a0, a0, a1 ; RV64ZBP-NEXT: packw a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%shl = and i32 %a, 65535 %shl = and i32 %a, 65535
%shl1 = shl i32 %b, 16 %shl1 = shl i32 %b, 16
%or = or i32 %shl1, %shl %or = or i32 %shl1, %shl
ret i32 %or ret i32 %or
} }
define i64 @pack_i64(i64 %a, i64 %b) nounwind { define i64 @pack_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: pack_i64: ; RV64I-LABEL: pack_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: slli a1, a1, 32 ; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: pack_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: pack a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: pack_i64: ; RV64ZBP-LABEL: pack_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: pack a0, a0, a1 ; RV64ZBP-NEXT: pack a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%shl = and i64 %a, 4294967295 %shl = and i64 %a, 4294967295
%shl1 = shl i64 %b, 32 %shl1 = shl i64 %b, 32
%or = or i64 %shl1, %shl %or = or i64 %shl1, %shl
ret i64 %or ret i64 %or
} }
define signext i32 @packu_i32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @packu_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: packu_i32: ; RV64I-LABEL: packu_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srliw a0, a0, 16 ; RV64I-NEXT: srliw a0, a0, 16
; RV64I-NEXT: lui a2, 1048560 ; RV64I-NEXT: lui a2, 1048560
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: packu_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: packuw a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: packu_i32: ; RV64ZBP-LABEL: packu_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: packuw a0, a0, a1 ; RV64ZBP-NEXT: packuw a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%shr = lshr i32 %a, 16 %shr = lshr i32 %a, 16
%shr1 = and i32 %b, -65536 %shr1 = and i32 %b, -65536
%or = or i32 %shr1, %shr %or = or i32 %shr1, %shr
ret i32 %or ret i32 %or
} }
define i64 @packu_i64(i64 %a, i64 %b) nounwind { define i64 @packu_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: packu_i64: ; RV64I-LABEL: packu_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: addi a2, zero, -1 ; RV64I-NEXT: addi a2, zero, -1
; RV64I-NEXT: slli a2, a2, 32 ; RV64I-NEXT: slli a2, a2, 32
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: packu_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: packu a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: packu_i64: ; RV64ZBP-LABEL: packu_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: packu a0, a0, a1 ; RV64ZBP-NEXT: packu a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%shr = lshr i64 %a, 32 %shr = lshr i64 %a, 32
%shr1 = and i64 %b, -4294967296 %shr1 = and i64 %b, -4294967296
%or = or i64 %shr1, %shr %or = or i64 %shr1, %shr
ret i64 %or ret i64 %or
} }
define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: packh_i32: ; RV64I-LABEL: packh_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, 255 ; RV64I-NEXT: andi a0, a0, 255
; RV64I-NEXT: slli a1, a1, 56 ; RV64I-NEXT: slli a1, a1, 56
; RV64I-NEXT: srli a1, a1, 48 ; RV64I-NEXT: srli a1, a1, 48
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: packh_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: packh a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: packh_i32: ; RV64ZBP-LABEL: packh_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: packh a0, a0, a1 ; RV64ZBP-NEXT: packh a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = and i32 %a, 255 %and = and i32 %a, 255
%and1 = shl i32 %b, 8 %and1 = shl i32 %b, 8
%shl = and i32 %and1, 65280 %shl = and i32 %and1, 65280
%or = or i32 %shl, %and %or = or i32 %shl, %and
ret i32 %or ret i32 %or
} }
define i64 @packh_i64(i64 %a, i64 %b) nounwind { define i64 @packh_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: packh_i64: ; RV64I-LABEL: packh_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, 255 ; RV64I-NEXT: andi a0, a0, 255
; RV64I-NEXT: slli a1, a1, 56 ; RV64I-NEXT: slli a1, a1, 56
; RV64I-NEXT: srli a1, a1, 48 ; RV64I-NEXT: srli a1, a1, 48
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: packh_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: packh a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: packh_i64: ; RV64ZBP-LABEL: packh_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: packh a0, a0, a1 ; RV64ZBP-NEXT: packh a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = and i64 %a, 255 %and = and i64 %a, 255
%and1 = shl i64 %b, 8 %and1 = shl i64 %b, 8
%shl = and i64 %and1, 65280 %shl = and i64 %and1, 65280
%or = or i64 %shl, %and %or = or i64 %shl, %and
ret i64 %or ret i64 %or
} }
define i32 @zexth_i32(i32 %a) nounwind { define i32 @zexth_i32(i32 %a) nounwind {
; RV64I-LABEL: zexth_i32: ; RV64I-LABEL: zexth_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: zexth_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: zext.h a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: zexth_i32: ; RV64ZBP-LABEL: zexth_i32:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zext.h a0, a0 ; RV64ZBP-NEXT: zext.h a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = and i32 %a, 65535 %and = and i32 %a, 65535
ret i32 %and ret i32 %and
} }
define i64 @zexth_i64(i64 %a) nounwind { define i64 @zexth_i64(i64 %a) nounwind {
; RV64I-LABEL: zexth_i64: ; RV64I-LABEL: zexth_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: zexth_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: zext.h a0, a0
; RV64B-NEXT: ret
;
; RV64ZBP-LABEL: zexth_i64: ; RV64ZBP-LABEL: zexth_i64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zext.h a0, a0 ; RV64ZBP-NEXT: zext.h a0, a0
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%and = and i64 %a, 65535 %and = and i64 %a, 65535
ret i64 %and ret i64 %and
} }

llvm/test/CodeGen/RISCV/rv64zbs.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I ; RUN: | FileCheck %s -check-prefix=RV64I
; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64B
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBS ; RUN: | FileCheck %s -check-prefix=RV64ZBS
define signext i32 @sbclr_i32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @sbclr_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: sbclr_i32: ; RV64I-LABEL: sbclr_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 1 ; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: sllw a1, a2, a1 ; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: not a1, a1 ; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a0, a1, a0 ; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbclr_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: addi a2, zero, 1
; RV64B-NEXT: sllw a1, a2, a1
; RV64B-NEXT: andn a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbclr_i32: ; RV64ZBS-LABEL: sbclr_i32:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: addi a2, zero, 1 ; RV64ZBS-NEXT: addi a2, zero, 1
; RV64ZBS-NEXT: sllw a1, a2, a1 ; RV64ZBS-NEXT: sllw a1, a2, a1
; RV64ZBS-NEXT: not a1, a1 ; RV64ZBS-NEXT: not a1, a1
; RV64ZBS-NEXT: and a0, a1, a0 ; RV64ZBS-NEXT: and a0, a1, a0
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%and = and i32 %b, 31 %and = and i32 %b, 31
%shl = shl nuw i32 1, %and %shl = shl nuw i32 1, %and
%neg = xor i32 %shl, -1 %neg = xor i32 %shl, -1
%and1 = and i32 %neg, %a %and1 = and i32 %neg, %a
ret i32 %and1 ret i32 %and1
} }
define signext i32 @sbclr_i32_no_mask(i32 signext %a, i32 signext %b) nounwind { define signext i32 @sbclr_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: sbclr_i32_no_mask: ; RV64I-LABEL: sbclr_i32_no_mask:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 1 ; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: sllw a1, a2, a1 ; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: not a1, a1 ; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a0, a1, a0 ; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbclr_i32_no_mask:
; RV64B: # %bb.0:
; RV64B-NEXT: addi a2, zero, 1
; RV64B-NEXT: sllw a1, a2, a1
; RV64B-NEXT: andn a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbclr_i32_no_mask: ; RV64ZBS-LABEL: sbclr_i32_no_mask:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: addi a2, zero, 1 ; RV64ZBS-NEXT: addi a2, zero, 1
; RV64ZBS-NEXT: sllw a1, a2, a1 ; RV64ZBS-NEXT: sllw a1, a2, a1
; RV64ZBS-NEXT: not a1, a1 ; RV64ZBS-NEXT: not a1, a1
; RV64ZBS-NEXT: and a0, a1, a0 ; RV64ZBS-NEXT: and a0, a1, a0
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%shl = shl i32 1, %b %shl = shl i32 1, %b
%neg = xor i32 %shl, -1 %neg = xor i32 %shl, -1
%and1 = and i32 %neg, %a %and1 = and i32 %neg, %a
ret i32 %and1 ret i32 %and1
} }
define signext i32 @sbclr_i32_load(i32* %p, i32 signext %b) nounwind { define signext i32 @sbclr_i32_load(i32* %p, i32 signext %b) nounwind {
; RV64I-LABEL: sbclr_i32_load: ; RV64I-LABEL: sbclr_i32_load:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lw a0, 0(a0) ; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: addi a2, zero, 1 ; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: sllw a1, a2, a1 ; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: not a1, a1 ; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a0, a1, a0 ; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbclr_i32_load:
; RV64B: # %bb.0:
; RV64B-NEXT: lw a0, 0(a0)
; RV64B-NEXT: addi a2, zero, 1
; RV64B-NEXT: sllw a1, a2, a1
; RV64B-NEXT: andn a0, a0, a1
; RV64B-NEXT: sext.w a0, a0
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbclr_i32_load: ; RV64ZBS-LABEL: sbclr_i32_load:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lw a0, 0(a0) ; RV64ZBS-NEXT: lw a0, 0(a0)
; RV64ZBS-NEXT: addi a2, zero, 1 ; RV64ZBS-NEXT: addi a2, zero, 1
; RV64ZBS-NEXT: sllw a1, a2, a1 ; RV64ZBS-NEXT: sllw a1, a2, a1
; RV64ZBS-NEXT: not a1, a1 ; RV64ZBS-NEXT: not a1, a1
; RV64ZBS-NEXT: and a0, a1, a0 ; RV64ZBS-NEXT: and a0, a1, a0
; RV64ZBS-NEXT: sext.w a0, a0 ; RV64ZBS-NEXT: sext.w a0, a0
Show All 9 Lines
; RV64I-LABEL: sbclr_i64: ; RV64I-LABEL: sbclr_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 1 ; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: sll a1, a2, a1 ; RV64I-NEXT: sll a1, a2, a1
; RV64I-NEXT: not a1, a1 ; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a0, a1, a0 ; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbclr_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: bclr a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbclr_i64: ; RV64ZBS-LABEL: sbclr_i64:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclr a0, a0, a1 ; RV64ZBS-NEXT: bclr a0, a0, a1
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%and = and i64 %b, 63 %and = and i64 %b, 63
%shl = shl nuw i64 1, %and %shl = shl nuw i64 1, %and
%neg = xor i64 %shl, -1 %neg = xor i64 %shl, -1
%and1 = and i64 %neg, %a %and1 = and i64 %neg, %a
ret i64 %and1 ret i64 %and1
} }
define i64 @sbclr_i64_no_mask(i64 %a, i64 %b) nounwind { define i64 @sbclr_i64_no_mask(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: sbclr_i64_no_mask: ; RV64I-LABEL: sbclr_i64_no_mask:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 1 ; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: sll a1, a2, a1 ; RV64I-NEXT: sll a1, a2, a1
; RV64I-NEXT: not a1, a1 ; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a0, a1, a0 ; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbclr_i64_no_mask:
; RV64B: # %bb.0:
; RV64B-NEXT: bclr a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbclr_i64_no_mask: ; RV64ZBS-LABEL: sbclr_i64_no_mask:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclr a0, a0, a1 ; RV64ZBS-NEXT: bclr a0, a0, a1
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%shl = shl i64 1, %b %shl = shl i64 1, %b
%neg = xor i64 %shl, -1 %neg = xor i64 %shl, -1
%and1 = and i64 %neg, %a %and1 = and i64 %neg, %a
ret i64 %and1 ret i64 %and1
} }
define signext i32 @sbset_i32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @sbset_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: sbset_i32: ; RV64I-LABEL: sbset_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 1 ; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: sllw a1, a2, a1 ; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbset_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: addi a2, zero, 1
; RV64B-NEXT: sllw a1, a2, a1
; RV64B-NEXT: or a0, a1, a0
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbset_i32: ; RV64ZBS-LABEL: sbset_i32:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: addi a2, zero, 1 ; RV64ZBS-NEXT: addi a2, zero, 1
; RV64ZBS-NEXT: sllw a1, a2, a1 ; RV64ZBS-NEXT: sllw a1, a2, a1
; RV64ZBS-NEXT: or a0, a1, a0 ; RV64ZBS-NEXT: or a0, a1, a0
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%and = and i32 %b, 31 %and = and i32 %b, 31
%shl = shl nuw i32 1, %and %shl = shl nuw i32 1, %and
%or = or i32 %shl, %a %or = or i32 %shl, %a
ret i32 %or ret i32 %or
} }
define signext i32 @sbset_i32_no_mask(i32 signext %a, i32 signext %b) nounwind { define signext i32 @sbset_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: sbset_i32_no_mask: ; RV64I-LABEL: sbset_i32_no_mask:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 1 ; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: sllw a1, a2, a1 ; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbset_i32_no_mask:
; RV64B: # %bb.0:
; RV64B-NEXT: addi a2, zero, 1
; RV64B-NEXT: sllw a1, a2, a1
; RV64B-NEXT: or a0, a1, a0
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbset_i32_no_mask: ; RV64ZBS-LABEL: sbset_i32_no_mask:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: addi a2, zero, 1 ; RV64ZBS-NEXT: addi a2, zero, 1
; RV64ZBS-NEXT: sllw a1, a2, a1 ; RV64ZBS-NEXT: sllw a1, a2, a1
; RV64ZBS-NEXT: or a0, a1, a0 ; RV64ZBS-NEXT: or a0, a1, a0
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%shl = shl i32 1, %b %shl = shl i32 1, %b
%or = or i32 %shl, %a %or = or i32 %shl, %a
ret i32 %or ret i32 %or
} }
define signext i32 @sbset_i32_load(i32* %p, i32 signext %b) nounwind { define signext i32 @sbset_i32_load(i32* %p, i32 signext %b) nounwind {
; RV64I-LABEL: sbset_i32_load: ; RV64I-LABEL: sbset_i32_load:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lw a0, 0(a0) ; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: addi a2, zero, 1 ; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: sllw a1, a2, a1 ; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbset_i32_load:
; RV64B: # %bb.0:
; RV64B-NEXT: lw a0, 0(a0)
; RV64B-NEXT: addi a2, zero, 1
; RV64B-NEXT: sllw a1, a2, a1
; RV64B-NEXT: or a0, a1, a0
; RV64B-NEXT: sext.w a0, a0
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbset_i32_load: ; RV64ZBS-LABEL: sbset_i32_load:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lw a0, 0(a0) ; RV64ZBS-NEXT: lw a0, 0(a0)
; RV64ZBS-NEXT: addi a2, zero, 1 ; RV64ZBS-NEXT: addi a2, zero, 1
; RV64ZBS-NEXT: sllw a1, a2, a1 ; RV64ZBS-NEXT: sllw a1, a2, a1
; RV64ZBS-NEXT: or a0, a1, a0 ; RV64ZBS-NEXT: or a0, a1, a0
; RV64ZBS-NEXT: sext.w a0, a0 ; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%a = load i32, i32* %p %a = load i32, i32* %p
%shl = shl i32 1, %b %shl = shl i32 1, %b
%or = or i32 %shl, %a %or = or i32 %shl, %a
ret i32 %or ret i32 %or
} }
; We can use sbsetw for 1 << x by setting the first source to zero. ; We can use sbsetw for 1 << x by setting the first source to zero.
define signext i32 @sbset_i32_zero(i32 signext %a) nounwind { define signext i32 @sbset_i32_zero(i32 signext %a) nounwind {
; RV64I-LABEL: sbset_i32_zero: ; RV64I-LABEL: sbset_i32_zero:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 1 ; RV64I-NEXT: addi a1, zero, 1
; RV64I-NEXT: sllw a0, a1, a0 ; RV64I-NEXT: sllw a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbset_i32_zero:
; RV64B: # %bb.0:
; RV64B-NEXT: addi a1, zero, 1
; RV64B-NEXT: sllw a0, a1, a0
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbset_i32_zero: ; RV64ZBS-LABEL: sbset_i32_zero:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: addi a1, zero, 1 ; RV64ZBS-NEXT: addi a1, zero, 1
; RV64ZBS-NEXT: sllw a0, a1, a0 ; RV64ZBS-NEXT: sllw a0, a1, a0
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%shl = shl i32 1, %a %shl = shl i32 1, %a
ret i32 %shl ret i32 %shl
} }
define i64 @sbset_i64(i64 %a, i64 %b) nounwind { define i64 @sbset_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: sbset_i64: ; RV64I-LABEL: sbset_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 1 ; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: sll a1, a2, a1 ; RV64I-NEXT: sll a1, a2, a1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbset_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: bset a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbset_i64: ; RV64ZBS-LABEL: sbset_i64:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bset a0, a0, a1 ; RV64ZBS-NEXT: bset a0, a0, a1
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%conv = and i64 %b, 63 %conv = and i64 %b, 63
%shl = shl nuw i64 1, %conv %shl = shl nuw i64 1, %conv
%or = or i64 %shl, %a %or = or i64 %shl, %a
ret i64 %or ret i64 %or
} }
define i64 @sbset_i64_no_mask(i64 %a, i64 %b) nounwind { define i64 @sbset_i64_no_mask(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: sbset_i64_no_mask: ; RV64I-LABEL: sbset_i64_no_mask:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 1 ; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: sll a1, a2, a1 ; RV64I-NEXT: sll a1, a2, a1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbset_i64_no_mask:
; RV64B: # %bb.0:
; RV64B-NEXT: bset a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbset_i64_no_mask: ; RV64ZBS-LABEL: sbset_i64_no_mask:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bset a0, a0, a1 ; RV64ZBS-NEXT: bset a0, a0, a1
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%shl = shl i64 1, %b %shl = shl i64 1, %b
%or = or i64 %shl, %a %or = or i64 %shl, %a
ret i64 %or ret i64 %or
} }
; We can use sbsetw for 1 << x by setting the first source to zero. ; We can use sbsetw for 1 << x by setting the first source to zero.
define signext i64 @sbset_i64_zero(i64 signext %a) nounwind { define signext i64 @sbset_i64_zero(i64 signext %a) nounwind {
; RV64I-LABEL: sbset_i64_zero: ; RV64I-LABEL: sbset_i64_zero:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 1 ; RV64I-NEXT: addi a1, zero, 1
; RV64I-NEXT: sll a0, a1, a0 ; RV64I-NEXT: sll a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbset_i64_zero:
; RV64B: # %bb.0:
; RV64B-NEXT: bset a0, zero, a0
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbset_i64_zero: ; RV64ZBS-LABEL: sbset_i64_zero:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bset a0, zero, a0 ; RV64ZBS-NEXT: bset a0, zero, a0
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%shl = shl i64 1, %a %shl = shl i64 1, %a
ret i64 %shl ret i64 %shl
} }
define signext i32 @sbinv_i32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @sbinv_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: sbinv_i32: ; RV64I-LABEL: sbinv_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 1 ; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: sllw a1, a2, a1 ; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: xor a0, a1, a0 ; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbinv_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: addi a2, zero, 1
; RV64B-NEXT: sllw a1, a2, a1
; RV64B-NEXT: xor a0, a1, a0
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbinv_i32: ; RV64ZBS-LABEL: sbinv_i32:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: addi a2, zero, 1 ; RV64ZBS-NEXT: addi a2, zero, 1
; RV64ZBS-NEXT: sllw a1, a2, a1 ; RV64ZBS-NEXT: sllw a1, a2, a1
; RV64ZBS-NEXT: xor a0, a1, a0 ; RV64ZBS-NEXT: xor a0, a1, a0
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%and = and i32 %b, 31 %and = and i32 %b, 31
%shl = shl nuw i32 1, %and %shl = shl nuw i32 1, %and
%xor = xor i32 %shl, %a %xor = xor i32 %shl, %a
ret i32 %xor ret i32 %xor
} }
define signext i32 @sbinv_i32_no_mask(i32 signext %a, i32 signext %b) nounwind { define signext i32 @sbinv_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: sbinv_i32_no_mask: ; RV64I-LABEL: sbinv_i32_no_mask:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 1 ; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: sllw a1, a2, a1 ; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: xor a0, a1, a0 ; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbinv_i32_no_mask:
; RV64B: # %bb.0:
; RV64B-NEXT: addi a2, zero, 1
; RV64B-NEXT: sllw a1, a2, a1
; RV64B-NEXT: xor a0, a1, a0
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbinv_i32_no_mask: ; RV64ZBS-LABEL: sbinv_i32_no_mask:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: addi a2, zero, 1 ; RV64ZBS-NEXT: addi a2, zero, 1
; RV64ZBS-NEXT: sllw a1, a2, a1 ; RV64ZBS-NEXT: sllw a1, a2, a1
; RV64ZBS-NEXT: xor a0, a1, a0 ; RV64ZBS-NEXT: xor a0, a1, a0
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%shl = shl i32 1, %b %shl = shl i32 1, %b
%xor = xor i32 %shl, %a %xor = xor i32 %shl, %a
ret i32 %xor ret i32 %xor
} }
define signext i32 @sbinv_i32_load(i32* %p, i32 signext %b) nounwind { define signext i32 @sbinv_i32_load(i32* %p, i32 signext %b) nounwind {
; RV64I-LABEL: sbinv_i32_load: ; RV64I-LABEL: sbinv_i32_load:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lw a0, 0(a0) ; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: addi a2, zero, 1 ; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: sllw a1, a2, a1 ; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: xor a0, a1, a0 ; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbinv_i32_load:
; RV64B: # %bb.0:
; RV64B-NEXT: lw a0, 0(a0)
; RV64B-NEXT: addi a2, zero, 1
; RV64B-NEXT: sllw a1, a2, a1
; RV64B-NEXT: xor a0, a1, a0
; RV64B-NEXT: sext.w a0, a0
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbinv_i32_load: ; RV64ZBS-LABEL: sbinv_i32_load:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lw a0, 0(a0) ; RV64ZBS-NEXT: lw a0, 0(a0)
; RV64ZBS-NEXT: addi a2, zero, 1 ; RV64ZBS-NEXT: addi a2, zero, 1
; RV64ZBS-NEXT: sllw a1, a2, a1 ; RV64ZBS-NEXT: sllw a1, a2, a1
; RV64ZBS-NEXT: xor a0, a1, a0 ; RV64ZBS-NEXT: xor a0, a1, a0
; RV64ZBS-NEXT: sext.w a0, a0 ; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%a = load i32, i32* %p %a = load i32, i32* %p
%shl = shl i32 1, %b %shl = shl i32 1, %b
%xor = xor i32 %shl, %a %xor = xor i32 %shl, %a
ret i32 %xor ret i32 %xor
} }
define i64 @sbinv_i64(i64 %a, i64 %b) nounwind { define i64 @sbinv_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: sbinv_i64: ; RV64I-LABEL: sbinv_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 1 ; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: sll a1, a2, a1 ; RV64I-NEXT: sll a1, a2, a1
; RV64I-NEXT: xor a0, a1, a0 ; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbinv_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: binv a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbinv_i64: ; RV64ZBS-LABEL: sbinv_i64:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binv a0, a0, a1 ; RV64ZBS-NEXT: binv a0, a0, a1
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%conv = and i64 %b, 63 %conv = and i64 %b, 63
%shl = shl nuw i64 1, %conv %shl = shl nuw i64 1, %conv
%xor = xor i64 %shl, %a %xor = xor i64 %shl, %a
ret i64 %xor ret i64 %xor
} }
define i64 @sbinv_i64_no_mask(i64 %a, i64 %b) nounwind { define i64 @sbinv_i64_no_mask(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: sbinv_i64_no_mask: ; RV64I-LABEL: sbinv_i64_no_mask:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 1 ; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: sll a1, a2, a1 ; RV64I-NEXT: sll a1, a2, a1
; RV64I-NEXT: xor a0, a1, a0 ; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbinv_i64_no_mask:
; RV64B: # %bb.0:
; RV64B-NEXT: binv a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbinv_i64_no_mask: ; RV64ZBS-LABEL: sbinv_i64_no_mask:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binv a0, a0, a1 ; RV64ZBS-NEXT: binv a0, a0, a1
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%shl = shl nuw i64 1, %b %shl = shl nuw i64 1, %b
%xor = xor i64 %shl, %a %xor = xor i64 %shl, %a
ret i64 %xor ret i64 %xor
} }
define signext i32 @sbext_i32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @sbext_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: sbext_i32: ; RV64I-LABEL: sbext_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srlw a0, a0, a1 ; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbext_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: srlw a0, a0, a1
; RV64B-NEXT: andi a0, a0, 1
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbext_i32: ; RV64ZBS-LABEL: sbext_i32:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: srlw a0, a0, a1 ; RV64ZBS-NEXT: srlw a0, a0, a1
; RV64ZBS-NEXT: andi a0, a0, 1 ; RV64ZBS-NEXT: andi a0, a0, 1
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%and = and i32 %b, 31 %and = and i32 %b, 31
%shr = lshr i32 %a, %and %shr = lshr i32 %a, %and
%and1 = and i32 %shr, 1 %and1 = and i32 %shr, 1
ret i32 %and1 ret i32 %and1
} }
define signext i32 @sbext_i32_no_mask(i32 signext %a, i32 signext %b) nounwind { define signext i32 @sbext_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: sbext_i32_no_mask: ; RV64I-LABEL: sbext_i32_no_mask:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srlw a0, a0, a1 ; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbext_i32_no_mask:
; RV64B: # %bb.0:
; RV64B-NEXT: srlw a0, a0, a1
; RV64B-NEXT: andi a0, a0, 1
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbext_i32_no_mask: ; RV64ZBS-LABEL: sbext_i32_no_mask:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: srlw a0, a0, a1 ; RV64ZBS-NEXT: srlw a0, a0, a1
; RV64ZBS-NEXT: andi a0, a0, 1 ; RV64ZBS-NEXT: andi a0, a0, 1
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%shr = lshr i32 %a, %b %shr = lshr i32 %a, %b
%and1 = and i32 %shr, 1 %and1 = and i32 %shr, 1
ret i32 %and1 ret i32 %and1
} }
define i64 @sbext_i64(i64 %a, i64 %b) nounwind { define i64 @sbext_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: sbext_i64: ; RV64I-LABEL: sbext_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srl a0, a0, a1 ; RV64I-NEXT: srl a0, a0, a1
; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbext_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: bext a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbext_i64: ; RV64ZBS-LABEL: sbext_i64:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bext a0, a0, a1 ; RV64ZBS-NEXT: bext a0, a0, a1
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%conv = and i64 %b, 63 %conv = and i64 %b, 63
%shr = lshr i64 %a, %conv %shr = lshr i64 %a, %conv
%and1 = and i64 %shr, 1 %and1 = and i64 %shr, 1
ret i64 %and1 ret i64 %and1
} }
define i64 @sbext_i64_no_mask(i64 %a, i64 %b) nounwind { define i64 @sbext_i64_no_mask(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: sbext_i64_no_mask: ; RV64I-LABEL: sbext_i64_no_mask:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srl a0, a0, a1 ; RV64I-NEXT: srl a0, a0, a1
; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbext_i64_no_mask:
; RV64B: # %bb.0:
; RV64B-NEXT: bext a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbext_i64_no_mask: ; RV64ZBS-LABEL: sbext_i64_no_mask:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bext a0, a0, a1 ; RV64ZBS-NEXT: bext a0, a0, a1
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%shr = lshr i64 %a, %b %shr = lshr i64 %a, %b
%and1 = and i64 %shr, 1 %and1 = and i64 %shr, 1
ret i64 %and1 ret i64 %and1
} }
define signext i32 @sbexti_i32(i32 signext %a) nounwind { define signext i32 @sbexti_i32(i32 signext %a) nounwind {
; RV64I-LABEL: sbexti_i32: ; RV64I-LABEL: sbexti_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srli a0, a0, 5 ; RV64I-NEXT: srli a0, a0, 5
; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbexti_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: bexti a0, a0, 5
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbexti_i32: ; RV64ZBS-LABEL: sbexti_i32:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bexti a0, a0, 5 ; RV64ZBS-NEXT: bexti a0, a0, 5
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%shr = lshr i32 %a, 5 %shr = lshr i32 %a, 5
%and = and i32 %shr, 1 %and = and i32 %shr, 1
ret i32 %and ret i32 %and
} }
define i64 @sbexti_i64(i64 %a) nounwind { define i64 @sbexti_i64(i64 %a) nounwind {
; RV64I-LABEL: sbexti_i64: ; RV64I-LABEL: sbexti_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srli a0, a0, 5 ; RV64I-NEXT: srli a0, a0, 5
; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbexti_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: bexti a0, a0, 5
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbexti_i64: ; RV64ZBS-LABEL: sbexti_i64:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bexti a0, a0, 5 ; RV64ZBS-NEXT: bexti a0, a0, 5
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%shr = lshr i64 %a, 5 %shr = lshr i64 %a, 5
%and = and i64 %shr, 1 %and = and i64 %shr, 1
ret i64 %and ret i64 %and
} }
define signext i32 @sbclri_i32_10(i32 signext %a) nounwind { define signext i32 @sbclri_i32_10(i32 signext %a) nounwind {
; RV64I-LABEL: sbclri_i32_10: ; RV64I-LABEL: sbclri_i32_10:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, -1025 ; RV64I-NEXT: andi a0, a0, -1025
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbclri_i32_10:
; RV64B: # %bb.0:
; RV64B-NEXT: andi a0, a0, -1025
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbclri_i32_10: ; RV64ZBS-LABEL: sbclri_i32_10:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: andi a0, a0, -1025 ; RV64ZBS-NEXT: andi a0, a0, -1025
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%and = and i32 %a, -1025 %and = and i32 %a, -1025
ret i32 %and ret i32 %and
} }
define signext i32 @sbclri_i32_11(i32 signext %a) nounwind { define signext i32 @sbclri_i32_11(i32 signext %a) nounwind {
; RV64I-LABEL: sbclri_i32_11: ; RV64I-LABEL: sbclri_i32_11:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575 ; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addiw a1, a1, 2047 ; RV64I-NEXT: addiw a1, a1, 2047
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbclri_i32_11:
; RV64B: # %bb.0:
; RV64B-NEXT: bclri a0, a0, 11
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbclri_i32_11: ; RV64ZBS-LABEL: sbclri_i32_11:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 11 ; RV64ZBS-NEXT: bclri a0, a0, 11
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%and = and i32 %a, -2049 %and = and i32 %a, -2049
ret i32 %and ret i32 %and
} }
define signext i32 @sbclri_i32_30(i32 signext %a) nounwind { define signext i32 @sbclri_i32_30(i32 signext %a) nounwind {
; RV64I-LABEL: sbclri_i32_30: ; RV64I-LABEL: sbclri_i32_30:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 786432 ; RV64I-NEXT: lui a1, 786432
; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbclri_i32_30:
; RV64B: # %bb.0:
; RV64B-NEXT: bclri a0, a0, 30
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbclri_i32_30: ; RV64ZBS-LABEL: sbclri_i32_30:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 30 ; RV64ZBS-NEXT: bclri a0, a0, 30
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%and = and i32 %a, -1073741825 %and = and i32 %a, -1073741825
ret i32 %and ret i32 %and
} }
define signext i32 @sbclri_i32_31(i32 signext %a) nounwind { define signext i32 @sbclri_i32_31(i32 signext %a) nounwind {
; RV64I-LABEL: sbclri_i32_31: ; RV64I-LABEL: sbclri_i32_31:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbclri_i32_31:
; RV64B: # %bb.0:
; RV64B-NEXT: lui a1, 524288
; RV64B-NEXT: addiw a1, a1, -1
; RV64B-NEXT: and a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbclri_i32_31: ; RV64ZBS-LABEL: sbclri_i32_31:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lui a1, 524288 ; RV64ZBS-NEXT: lui a1, 524288
; RV64ZBS-NEXT: addiw a1, a1, -1 ; RV64ZBS-NEXT: addiw a1, a1, -1
; RV64ZBS-NEXT: and a0, a0, a1 ; RV64ZBS-NEXT: and a0, a0, a1
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%and = and i32 %a, -2147483649 %and = and i32 %a, -2147483649
ret i32 %and ret i32 %and
} }
define i64 @sbclri_i64_10(i64 %a) nounwind { define i64 @sbclri_i64_10(i64 %a) nounwind {
; RV64I-LABEL: sbclri_i64_10: ; RV64I-LABEL: sbclri_i64_10:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, -1025 ; RV64I-NEXT: andi a0, a0, -1025
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbclri_i64_10:
; RV64B: # %bb.0:
; RV64B-NEXT: andi a0, a0, -1025
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbclri_i64_10: ; RV64ZBS-LABEL: sbclri_i64_10:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: andi a0, a0, -1025 ; RV64ZBS-NEXT: andi a0, a0, -1025
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%and = and i64 %a, -1025 %and = and i64 %a, -1025
ret i64 %and ret i64 %and
} }
define i64 @sbclri_i64_11(i64 %a) nounwind { define i64 @sbclri_i64_11(i64 %a) nounwind {
; RV64I-LABEL: sbclri_i64_11: ; RV64I-LABEL: sbclri_i64_11:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575 ; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addiw a1, a1, 2047 ; RV64I-NEXT: addiw a1, a1, 2047
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbclri_i64_11:
; RV64B: # %bb.0:
; RV64B-NEXT: bclri a0, a0, 11
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbclri_i64_11: ; RV64ZBS-LABEL: sbclri_i64_11:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 11 ; RV64ZBS-NEXT: bclri a0, a0, 11
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%and = and i64 %a, -2049 %and = and i64 %a, -2049
ret i64 %and ret i64 %and
} }
define i64 @sbclri_i64_30(i64 %a) nounwind { define i64 @sbclri_i64_30(i64 %a) nounwind {
; RV64I-LABEL: sbclri_i64_30: ; RV64I-LABEL: sbclri_i64_30:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 786432 ; RV64I-NEXT: lui a1, 786432
; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbclri_i64_30:
; RV64B: # %bb.0:
; RV64B-NEXT: bclri a0, a0, 30
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbclri_i64_30: ; RV64ZBS-LABEL: sbclri_i64_30:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 30 ; RV64ZBS-NEXT: bclri a0, a0, 30
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%and = and i64 %a, -1073741825 %and = and i64 %a, -1073741825
ret i64 %and ret i64 %and
} }
define i64 @sbclri_i64_31(i64 %a) nounwind { define i64 @sbclri_i64_31(i64 %a) nounwind {
; RV64I-LABEL: sbclri_i64_31: ; RV64I-LABEL: sbclri_i64_31:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, -1 ; RV64I-NEXT: addi a1, zero, -1
; RV64I-NEXT: slli a1, a1, 31 ; RV64I-NEXT: slli a1, a1, 31
; RV64I-NEXT: addi a1, a1, -1 ; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbclri_i64_31:
; RV64B: # %bb.0:
; RV64B-NEXT: bclri a0, a0, 31
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbclri_i64_31: ; RV64ZBS-LABEL: sbclri_i64_31:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 31 ; RV64ZBS-NEXT: bclri a0, a0, 31
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%and = and i64 %a, -2147483649 %and = and i64 %a, -2147483649
ret i64 %and ret i64 %and
} }
define i64 @sbclri_i64_62(i64 %a) nounwind { define i64 @sbclri_i64_62(i64 %a) nounwind {
; RV64I-LABEL: sbclri_i64_62: ; RV64I-LABEL: sbclri_i64_62:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, -1 ; RV64I-NEXT: addi a1, zero, -1
; RV64I-NEXT: slli a1, a1, 62 ; RV64I-NEXT: slli a1, a1, 62
; RV64I-NEXT: addi a1, a1, -1 ; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbclri_i64_62:
; RV64B: # %bb.0:
; RV64B-NEXT: bclri a0, a0, 62
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbclri_i64_62: ; RV64ZBS-LABEL: sbclri_i64_62:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 62 ; RV64ZBS-NEXT: bclri a0, a0, 62
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%and = and i64 %a, -4611686018427387905 %and = and i64 %a, -4611686018427387905
ret i64 %and ret i64 %and
} }
define i64 @sbclri_i64_63(i64 %a) nounwind { define i64 @sbclri_i64_63(i64 %a) nounwind {
; RV64I-LABEL: sbclri_i64_63: ; RV64I-LABEL: sbclri_i64_63:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, -1 ; RV64I-NEXT: addi a1, zero, -1
; RV64I-NEXT: srli a1, a1, 1 ; RV64I-NEXT: srli a1, a1, 1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbclri_i64_63:
; RV64B: # %bb.0:
; RV64B-NEXT: bclri a0, a0, 63
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbclri_i64_63: ; RV64ZBS-LABEL: sbclri_i64_63:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 63 ; RV64ZBS-NEXT: bclri a0, a0, 63
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%and = and i64 %a, -9223372036854775809 %and = and i64 %a, -9223372036854775809
ret i64 %and ret i64 %and
} }
define i64 @sbclri_i64_large0(i64 %a) nounwind { define i64 @sbclri_i64_large0(i64 %a) nounwind {
; RV64I-LABEL: sbclri_i64_large0: ; RV64I-LABEL: sbclri_i64_large0:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1044480 ; RV64I-NEXT: lui a1, 1044480
; RV64I-NEXT: addiw a1, a1, -256 ; RV64I-NEXT: addiw a1, a1, -256
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbclri_i64_large0:
; RV64B: # %bb.0:
; RV64B-NEXT: andi a0, a0, -256
; RV64B-NEXT: bclri a0, a0, 24
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbclri_i64_large0: ; RV64ZBS-LABEL: sbclri_i64_large0:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: andi a0, a0, -256 ; RV64ZBS-NEXT: andi a0, a0, -256
; RV64ZBS-NEXT: bclri a0, a0, 24 ; RV64ZBS-NEXT: bclri a0, a0, 24
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%and = and i64 %a, -16777472 %and = and i64 %a, -16777472
ret i64 %and ret i64 %and
} }
define i64 @sbclri_i64_large1(i64 %a) nounwind { define i64 @sbclri_i64_large1(i64 %a) nounwind {
; RV64I-LABEL: sbclri_i64_large1: ; RV64I-LABEL: sbclri_i64_large1:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1044464 ; RV64I-NEXT: lui a1, 1044464
; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbclri_i64_large1:
; RV64B: # %bb.0:
; RV64B-NEXT: bclri a0, a0, 16
; RV64B-NEXT: bclri a0, a0, 24
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbclri_i64_large1: ; RV64ZBS-LABEL: sbclri_i64_large1:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 16 ; RV64ZBS-NEXT: bclri a0, a0, 16
; RV64ZBS-NEXT: bclri a0, a0, 24 ; RV64ZBS-NEXT: bclri a0, a0, 24
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%and = and i64 %a, -16842753 %and = and i64 %a, -16842753
ret i64 %and ret i64 %and
} }
define signext i32 @sbseti_i32_10(i32 signext %a) nounwind { define signext i32 @sbseti_i32_10(i32 signext %a) nounwind {
; RV64I-LABEL: sbseti_i32_10: ; RV64I-LABEL: sbseti_i32_10:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: ori a0, a0, 1024 ; RV64I-NEXT: ori a0, a0, 1024
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbseti_i32_10:
; RV64B: # %bb.0:
; RV64B-NEXT: ori a0, a0, 1024
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbseti_i32_10: ; RV64ZBS-LABEL: sbseti_i32_10:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: ori a0, a0, 1024 ; RV64ZBS-NEXT: ori a0, a0, 1024
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%or = or i32 %a, 1024 %or = or i32 %a, 1024
ret i32 %or ret i32 %or
} }
define signext i32 @sbseti_i32_11(i32 signext %a) nounwind { define signext i32 @sbseti_i32_11(i32 signext %a) nounwind {
; RV64I-LABEL: sbseti_i32_11: ; RV64I-LABEL: sbseti_i32_11:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1 ; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, -2048 ; RV64I-NEXT: addiw a1, a1, -2048
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbseti_i32_11:
; RV64B: # %bb.0:
; RV64B-NEXT: bseti a0, a0, 11
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbseti_i32_11: ; RV64ZBS-LABEL: sbseti_i32_11:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 11 ; RV64ZBS-NEXT: bseti a0, a0, 11
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%or = or i32 %a, 2048 %or = or i32 %a, 2048
ret i32 %or ret i32 %or
} }
define signext i32 @sbseti_i32_30(i32 signext %a) nounwind { define signext i32 @sbseti_i32_30(i32 signext %a) nounwind {
; RV64I-LABEL: sbseti_i32_30: ; RV64I-LABEL: sbseti_i32_30:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 262144 ; RV64I-NEXT: lui a1, 262144
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbseti_i32_30:
; RV64B: # %bb.0:
; RV64B-NEXT: bseti a0, a0, 30
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbseti_i32_30: ; RV64ZBS-LABEL: sbseti_i32_30:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 30 ; RV64ZBS-NEXT: bseti a0, a0, 30
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%or = or i32 %a, 1073741824 %or = or i32 %a, 1073741824
ret i32 %or ret i32 %or
} }
define signext i32 @sbseti_i32_31(i32 signext %a) nounwind { define signext i32 @sbseti_i32_31(i32 signext %a) nounwind {
; RV64I-LABEL: sbseti_i32_31: ; RV64I-LABEL: sbseti_i32_31:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbseti_i32_31:
; RV64B: # %bb.0:
; RV64B-NEXT: lui a1, 524288
; RV64B-NEXT: or a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbseti_i32_31: ; RV64ZBS-LABEL: sbseti_i32_31:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lui a1, 524288 ; RV64ZBS-NEXT: lui a1, 524288
; RV64ZBS-NEXT: or a0, a0, a1 ; RV64ZBS-NEXT: or a0, a0, a1
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%or = or i32 %a, 2147483648 %or = or i32 %a, 2147483648
ret i32 %or ret i32 %or
} }
define i64 @sbseti_i64_10(i64 %a) nounwind { define i64 @sbseti_i64_10(i64 %a) nounwind {
; RV64I-LABEL: sbseti_i64_10: ; RV64I-LABEL: sbseti_i64_10:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: ori a0, a0, 1024 ; RV64I-NEXT: ori a0, a0, 1024
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbseti_i64_10:
; RV64B: # %bb.0:
; RV64B-NEXT: ori a0, a0, 1024
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbseti_i64_10: ; RV64ZBS-LABEL: sbseti_i64_10:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: ori a0, a0, 1024 ; RV64ZBS-NEXT: ori a0, a0, 1024
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%or = or i64 %a, 1024 %or = or i64 %a, 1024
ret i64 %or ret i64 %or
} }
define i64 @sbseti_i64_11(i64 %a) nounwind { define i64 @sbseti_i64_11(i64 %a) nounwind {
; RV64I-LABEL: sbseti_i64_11: ; RV64I-LABEL: sbseti_i64_11:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1 ; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, -2048 ; RV64I-NEXT: addiw a1, a1, -2048
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbseti_i64_11:
; RV64B: # %bb.0:
; RV64B-NEXT: bseti a0, a0, 11
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbseti_i64_11: ; RV64ZBS-LABEL: sbseti_i64_11:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 11 ; RV64ZBS-NEXT: bseti a0, a0, 11
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%or = or i64 %a, 2048 %or = or i64 %a, 2048
ret i64 %or ret i64 %or
} }
define i64 @sbseti_i64_30(i64 %a) nounwind { define i64 @sbseti_i64_30(i64 %a) nounwind {
; RV64I-LABEL: sbseti_i64_30: ; RV64I-LABEL: sbseti_i64_30:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 262144 ; RV64I-NEXT: lui a1, 262144
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbseti_i64_30:
; RV64B: # %bb.0:
; RV64B-NEXT: bseti a0, a0, 30
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbseti_i64_30: ; RV64ZBS-LABEL: sbseti_i64_30:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 30 ; RV64ZBS-NEXT: bseti a0, a0, 30
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%or = or i64 %a, 1073741824 %or = or i64 %a, 1073741824
ret i64 %or ret i64 %or
} }
define i64 @sbseti_i64_31(i64 %a) nounwind { define i64 @sbseti_i64_31(i64 %a) nounwind {
; RV64I-LABEL: sbseti_i64_31: ; RV64I-LABEL: sbseti_i64_31:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 1 ; RV64I-NEXT: addi a1, zero, 1
; RV64I-NEXT: slli a1, a1, 31 ; RV64I-NEXT: slli a1, a1, 31
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbseti_i64_31:
; RV64B: # %bb.0:
; RV64B-NEXT: bseti a0, a0, 31
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbseti_i64_31: ; RV64ZBS-LABEL: sbseti_i64_31:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 31 ; RV64ZBS-NEXT: bseti a0, a0, 31
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%or = or i64 %a, 2147483648 %or = or i64 %a, 2147483648
ret i64 %or ret i64 %or
} }
define i64 @sbseti_i64_62(i64 %a) nounwind { define i64 @sbseti_i64_62(i64 %a) nounwind {
; RV64I-LABEL: sbseti_i64_62: ; RV64I-LABEL: sbseti_i64_62:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 1 ; RV64I-NEXT: addi a1, zero, 1
; RV64I-NEXT: slli a1, a1, 62 ; RV64I-NEXT: slli a1, a1, 62
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbseti_i64_62:
; RV64B: # %bb.0:
; RV64B-NEXT: bseti a0, a0, 62
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbseti_i64_62: ; RV64ZBS-LABEL: sbseti_i64_62:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 62 ; RV64ZBS-NEXT: bseti a0, a0, 62
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%or = or i64 %a, 4611686018427387904 %or = or i64 %a, 4611686018427387904
ret i64 %or ret i64 %or
} }
define i64 @sbseti_i64_63(i64 %a) nounwind { define i64 @sbseti_i64_63(i64 %a) nounwind {
; RV64I-LABEL: sbseti_i64_63: ; RV64I-LABEL: sbseti_i64_63:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, -1 ; RV64I-NEXT: addi a1, zero, -1
; RV64I-NEXT: slli a1, a1, 63 ; RV64I-NEXT: slli a1, a1, 63
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbseti_i64_63:
; RV64B: # %bb.0:
; RV64B-NEXT: bseti a0, a0, 63
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbseti_i64_63: ; RV64ZBS-LABEL: sbseti_i64_63:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 63 ; RV64ZBS-NEXT: bseti a0, a0, 63
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%or = or i64 %a, 9223372036854775808 %or = or i64 %a, 9223372036854775808
ret i64 %or ret i64 %or
} }
define signext i32 @sbinvi_i32_10(i32 signext %a) nounwind { define signext i32 @sbinvi_i32_10(i32 signext %a) nounwind {
; RV64I-LABEL: sbinvi_i32_10: ; RV64I-LABEL: sbinvi_i32_10:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: xori a0, a0, 1024 ; RV64I-NEXT: xori a0, a0, 1024
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbinvi_i32_10:
; RV64B: # %bb.0:
; RV64B-NEXT: xori a0, a0, 1024
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbinvi_i32_10: ; RV64ZBS-LABEL: sbinvi_i32_10:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: xori a0, a0, 1024 ; RV64ZBS-NEXT: xori a0, a0, 1024
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%xor = xor i32 %a, 1024 %xor = xor i32 %a, 1024
ret i32 %xor ret i32 %xor
} }
define signext i32 @sbinvi_i32_11(i32 signext %a) nounwind { define signext i32 @sbinvi_i32_11(i32 signext %a) nounwind {
; RV64I-LABEL: sbinvi_i32_11: ; RV64I-LABEL: sbinvi_i32_11:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1 ; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, -2048 ; RV64I-NEXT: addiw a1, a1, -2048
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbinvi_i32_11:
; RV64B: # %bb.0:
; RV64B-NEXT: binvi a0, a0, 11
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbinvi_i32_11: ; RV64ZBS-LABEL: sbinvi_i32_11:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 11 ; RV64ZBS-NEXT: binvi a0, a0, 11
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%xor = xor i32 %a, 2048 %xor = xor i32 %a, 2048
ret i32 %xor ret i32 %xor
} }
define signext i32 @sbinvi_i32_30(i32 signext %a) nounwind { define signext i32 @sbinvi_i32_30(i32 signext %a) nounwind {
; RV64I-LABEL: sbinvi_i32_30: ; RV64I-LABEL: sbinvi_i32_30:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 262144 ; RV64I-NEXT: lui a1, 262144
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbinvi_i32_30:
; RV64B: # %bb.0:
; RV64B-NEXT: binvi a0, a0, 30
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbinvi_i32_30: ; RV64ZBS-LABEL: sbinvi_i32_30:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 30 ; RV64ZBS-NEXT: binvi a0, a0, 30
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%xor = xor i32 %a, 1073741824 %xor = xor i32 %a, 1073741824
ret i32 %xor ret i32 %xor
} }
define signext i32 @sbinvi_i32_31(i32 signext %a) nounwind { define signext i32 @sbinvi_i32_31(i32 signext %a) nounwind {
; RV64I-LABEL: sbinvi_i32_31: ; RV64I-LABEL: sbinvi_i32_31:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbinvi_i32_31:
; RV64B: # %bb.0:
; RV64B-NEXT: lui a1, 524288
; RV64B-NEXT: xor a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbinvi_i32_31: ; RV64ZBS-LABEL: sbinvi_i32_31:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lui a1, 524288 ; RV64ZBS-NEXT: lui a1, 524288
; RV64ZBS-NEXT: xor a0, a0, a1 ; RV64ZBS-NEXT: xor a0, a0, a1
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%xor = xor i32 %a, 2147483648 %xor = xor i32 %a, 2147483648
ret i32 %xor ret i32 %xor
} }
define i64 @sbinvi_i64_10(i64 %a) nounwind { define i64 @sbinvi_i64_10(i64 %a) nounwind {
; RV64I-LABEL: sbinvi_i64_10: ; RV64I-LABEL: sbinvi_i64_10:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: xori a0, a0, 1024 ; RV64I-NEXT: xori a0, a0, 1024
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbinvi_i64_10:
; RV64B: # %bb.0:
; RV64B-NEXT: xori a0, a0, 1024
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbinvi_i64_10: ; RV64ZBS-LABEL: sbinvi_i64_10:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: xori a0, a0, 1024 ; RV64ZBS-NEXT: xori a0, a0, 1024
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 1024 %xor = xor i64 %a, 1024
ret i64 %xor ret i64 %xor
} }
define i64 @sbinvi_i64_11(i64 %a) nounwind { define i64 @sbinvi_i64_11(i64 %a) nounwind {
; RV64I-LABEL: sbinvi_i64_11: ; RV64I-LABEL: sbinvi_i64_11:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1 ; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, -2048 ; RV64I-NEXT: addiw a1, a1, -2048
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbinvi_i64_11:
; RV64B: # %bb.0:
; RV64B-NEXT: binvi a0, a0, 11
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbinvi_i64_11: ; RV64ZBS-LABEL: sbinvi_i64_11:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 11 ; RV64ZBS-NEXT: binvi a0, a0, 11
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 2048 %xor = xor i64 %a, 2048
ret i64 %xor ret i64 %xor
} }
define i64 @sbinvi_i64_30(i64 %a) nounwind { define i64 @sbinvi_i64_30(i64 %a) nounwind {
; RV64I-LABEL: sbinvi_i64_30: ; RV64I-LABEL: sbinvi_i64_30:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 262144 ; RV64I-NEXT: lui a1, 262144
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbinvi_i64_30:
; RV64B: # %bb.0:
; RV64B-NEXT: binvi a0, a0, 30
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbinvi_i64_30: ; RV64ZBS-LABEL: sbinvi_i64_30:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 30 ; RV64ZBS-NEXT: binvi a0, a0, 30
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 1073741824 %xor = xor i64 %a, 1073741824
ret i64 %xor ret i64 %xor
} }
define i64 @sbinvi_i64_31(i64 %a) nounwind { define i64 @sbinvi_i64_31(i64 %a) nounwind {
; RV64I-LABEL: sbinvi_i64_31: ; RV64I-LABEL: sbinvi_i64_31:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 1 ; RV64I-NEXT: addi a1, zero, 1
; RV64I-NEXT: slli a1, a1, 31 ; RV64I-NEXT: slli a1, a1, 31
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbinvi_i64_31:
; RV64B: # %bb.0:
; RV64B-NEXT: binvi a0, a0, 31
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbinvi_i64_31: ; RV64ZBS-LABEL: sbinvi_i64_31:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 31 ; RV64ZBS-NEXT: binvi a0, a0, 31
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 2147483648 %xor = xor i64 %a, 2147483648
ret i64 %xor ret i64 %xor
} }
define i64 @sbinvi_i64_62(i64 %a) nounwind { define i64 @sbinvi_i64_62(i64 %a) nounwind {
; RV64I-LABEL: sbinvi_i64_62: ; RV64I-LABEL: sbinvi_i64_62:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 1 ; RV64I-NEXT: addi a1, zero, 1
; RV64I-NEXT: slli a1, a1, 62 ; RV64I-NEXT: slli a1, a1, 62
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbinvi_i64_62:
; RV64B: # %bb.0:
; RV64B-NEXT: binvi a0, a0, 62
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbinvi_i64_62: ; RV64ZBS-LABEL: sbinvi_i64_62:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 62 ; RV64ZBS-NEXT: binvi a0, a0, 62
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 4611686018427387904 %xor = xor i64 %a, 4611686018427387904
ret i64 %xor ret i64 %xor
} }
define i64 @sbinvi_i64_63(i64 %a) nounwind { define i64 @sbinvi_i64_63(i64 %a) nounwind {
; RV64I-LABEL: sbinvi_i64_63: ; RV64I-LABEL: sbinvi_i64_63:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, -1 ; RV64I-NEXT: addi a1, zero, -1
; RV64I-NEXT: slli a1, a1, 63 ; RV64I-NEXT: slli a1, a1, 63
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: sbinvi_i64_63:
; RV64B: # %bb.0:
; RV64B-NEXT: binvi a0, a0, 63
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: sbinvi_i64_63: ; RV64ZBS-LABEL: sbinvi_i64_63:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 63 ; RV64ZBS-NEXT: binvi a0, a0, 63
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 9223372036854775808 %xor = xor i64 %a, 9223372036854775808
ret i64 %xor ret i64 %xor
} }
define i64 @xor_i64_large(i64 %a) nounwind { define i64 @xor_i64_large(i64 %a) nounwind {
; RV64I-LABEL: xor_i64_large: ; RV64I-LABEL: xor_i64_large:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 1 ; RV64I-NEXT: addi a1, zero, 1
; RV64I-NEXT: slli a1, a1, 32 ; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: addi a1, a1, 1 ; RV64I-NEXT: addi a1, a1, 1
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: xor_i64_large:
; RV64B: # %bb.0:
; RV64B-NEXT: binvi a0, a0, 0
; RV64B-NEXT: binvi a0, a0, 32
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: xor_i64_large: ; RV64ZBS-LABEL: xor_i64_large:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 0 ; RV64ZBS-NEXT: binvi a0, a0, 0
; RV64ZBS-NEXT: binvi a0, a0, 32 ; RV64ZBS-NEXT: binvi a0, a0, 32
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 4294967297 %xor = xor i64 %a, 4294967297
ret i64 %xor ret i64 %xor
} }
define i64 @xor_i64_4099(i64 %a) nounwind { define i64 @xor_i64_4099(i64 %a) nounwind {
; RV64I-LABEL: xor_i64_4099: ; RV64I-LABEL: xor_i64_4099:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1 ; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, 3 ; RV64I-NEXT: addiw a1, a1, 3
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: xor_i64_4099:
; RV64B: # %bb.0:
; RV64B-NEXT: xori a0, a0, 3
; RV64B-NEXT: binvi a0, a0, 12
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: xor_i64_4099: ; RV64ZBS-LABEL: xor_i64_4099:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: xori a0, a0, 3 ; RV64ZBS-NEXT: xori a0, a0, 3
; RV64ZBS-NEXT: binvi a0, a0, 12 ; RV64ZBS-NEXT: binvi a0, a0, 12
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 4099 %xor = xor i64 %a, 4099
ret i64 %xor ret i64 %xor
} }
define i64 @xor_i64_96(i64 %a) nounwind { define i64 @xor_i64_96(i64 %a) nounwind {
; RV64I-LABEL: xor_i64_96: ; RV64I-LABEL: xor_i64_96:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: xori a0, a0, 96 ; RV64I-NEXT: xori a0, a0, 96
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: xor_i64_96:
; RV64B: # %bb.0:
; RV64B-NEXT: xori a0, a0, 96
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: xor_i64_96: ; RV64ZBS-LABEL: xor_i64_96:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: xori a0, a0, 96 ; RV64ZBS-NEXT: xori a0, a0, 96
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 96 %xor = xor i64 %a, 96
ret i64 %xor ret i64 %xor
} }
define i64 @or_i64_large(i64 %a) nounwind { define i64 @or_i64_large(i64 %a) nounwind {
; RV64I-LABEL: or_i64_large: ; RV64I-LABEL: or_i64_large:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 1 ; RV64I-NEXT: addi a1, zero, 1
; RV64I-NEXT: slli a1, a1, 32 ; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: addi a1, a1, 1 ; RV64I-NEXT: addi a1, a1, 1
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: or_i64_large:
; RV64B: # %bb.0:
; RV64B-NEXT: bseti a0, a0, 0
; RV64B-NEXT: bseti a0, a0, 32
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: or_i64_large: ; RV64ZBS-LABEL: or_i64_large:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 0 ; RV64ZBS-NEXT: bseti a0, a0, 0
; RV64ZBS-NEXT: bseti a0, a0, 32 ; RV64ZBS-NEXT: bseti a0, a0, 32
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%or = or i64 %a, 4294967297 %or = or i64 %a, 4294967297
ret i64 %or ret i64 %or
} }
define i64 @xor_i64_66901(i64 %a) nounwind { define i64 @xor_i64_66901(i64 %a) nounwind {
; RV64I-LABEL: xor_i64_66901: ; RV64I-LABEL: xor_i64_66901:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, 1365 ; RV64I-NEXT: addiw a1, a1, 1365
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: xor_i64_66901:
; RV64B: # %bb.0:
; RV64B-NEXT: xori a0, a0, 1365
; RV64B-NEXT: binvi a0, a0, 16
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: xor_i64_66901: ; RV64ZBS-LABEL: xor_i64_66901:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: xori a0, a0, 1365 ; RV64ZBS-NEXT: xori a0, a0, 1365
; RV64ZBS-NEXT: binvi a0, a0, 16 ; RV64ZBS-NEXT: binvi a0, a0, 16
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 66901 %xor = xor i64 %a, 66901
ret i64 %xor ret i64 %xor
} }
define i64 @or_i64_4099(i64 %a) nounwind { define i64 @or_i64_4099(i64 %a) nounwind {
; RV64I-LABEL: or_i64_4099: ; RV64I-LABEL: or_i64_4099:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1 ; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, 3 ; RV64I-NEXT: addiw a1, a1, 3
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: or_i64_4099:
; RV64B: # %bb.0:
; RV64B-NEXT: ori a0, a0, 3
; RV64B-NEXT: bseti a0, a0, 12
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: or_i64_4099: ; RV64ZBS-LABEL: or_i64_4099:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: ori a0, a0, 3 ; RV64ZBS-NEXT: ori a0, a0, 3
; RV64ZBS-NEXT: bseti a0, a0, 12 ; RV64ZBS-NEXT: bseti a0, a0, 12
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%or = or i64 %a, 4099 %or = or i64 %a, 4099
ret i64 %or ret i64 %or
} }
define i64 @or_i64_96(i64 %a) nounwind { define i64 @or_i64_96(i64 %a) nounwind {
; RV64I-LABEL: or_i64_96: ; RV64I-LABEL: or_i64_96:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: ori a0, a0, 96 ; RV64I-NEXT: ori a0, a0, 96
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: or_i64_96:
; RV64B: # %bb.0:
; RV64B-NEXT: ori a0, a0, 96
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: or_i64_96: ; RV64ZBS-LABEL: or_i64_96:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: ori a0, a0, 96 ; RV64ZBS-NEXT: ori a0, a0, 96
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%or = or i64 %a, 96 %or = or i64 %a, 96
ret i64 %or ret i64 %or
} }
define i64 @or_i64_66901(i64 %a) nounwind { define i64 @or_i64_66901(i64 %a) nounwind {
; RV64I-LABEL: or_i64_66901: ; RV64I-LABEL: or_i64_66901:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, 1365 ; RV64I-NEXT: addiw a1, a1, 1365
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: or_i64_66901:
; RV64B: # %bb.0:
; RV64B-NEXT: ori a0, a0, 1365
; RV64B-NEXT: bseti a0, a0, 16
; RV64B-NEXT: ret
;
; RV64ZBS-LABEL: or_i64_66901: ; RV64ZBS-LABEL: or_i64_66901:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: ori a0, a0, 1365 ; RV64ZBS-NEXT: ori a0, a0, 1365
; RV64ZBS-NEXT: bseti a0, a0, 16 ; RV64ZBS-NEXT: bseti a0, a0, 16
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%or = or i64 %a, 66901 %or = or i64 %a, 66901
ret i64 %or ret i64 %or
} }

llvm/test/CodeGen/RISCV/rv64zbt.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I ; RUN: | FileCheck %s -check-prefix=RV64I
; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64B
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBT ; RUN: | FileCheck %s -check-prefix=RV64ZBT
define signext i32 @cmix_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind { define signext i32 @cmix_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
; RV64I-LABEL: cmix_i32: ; RV64I-LABEL: cmix_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: and a0, a1, a0 ; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: not a1, a1 ; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: cmix_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: cmix a0, a1, a0, a2
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: cmix_i32: ; RV64ZBT-LABEL: cmix_i32:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: cmix a0, a1, a0, a2 ; RV64ZBT-NEXT: cmix a0, a1, a0, a2
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%and = and i32 %b, %a %and = and i32 %b, %a
%neg = xor i32 %b, -1 %neg = xor i32 %b, -1
%and1 = and i32 %neg, %c %and1 = and i32 %neg, %c
%or = or i32 %and1, %and %or = or i32 %and1, %and
ret i32 %or ret i32 %or
} }
define i64 @cmix_i64(i64 %a, i64 %b, i64 %c) nounwind { define i64 @cmix_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmix_i64: ; RV64I-LABEL: cmix_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: and a0, a1, a0 ; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: not a1, a1 ; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: cmix_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: cmix a0, a1, a0, a2
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: cmix_i64: ; RV64ZBT-LABEL: cmix_i64:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: cmix a0, a1, a0, a2 ; RV64ZBT-NEXT: cmix a0, a1, a0, a2
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%and = and i64 %b, %a %and = and i64 %b, %a
%neg = xor i64 %b, -1 %neg = xor i64 %b, -1
%and1 = and i64 %neg, %c %and1 = and i64 %neg, %c
%or = or i64 %and1, %and %or = or i64 %and1, %and
ret i64 %or ret i64 %or
} }
define signext i32 @cmov_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind { define signext i32 @cmov_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
; RV64I-LABEL: cmov_i32: ; RV64I-LABEL: cmov_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: beqz a1, .LBB2_2 ; RV64I-NEXT: beqz a1, .LBB2_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: .LBB2_2: ; RV64I-NEXT: .LBB2_2:
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: cmov_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: cmov a0, a1, a0, a2
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: cmov_i32: ; RV64ZBT-LABEL: cmov_i32:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: cmov a0, a1, a0, a2 ; RV64ZBT-NEXT: cmov a0, a1, a0, a2
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool.not = icmp eq i32 %b, 0 %tobool.not = icmp eq i32 %b, 0
%cond = select i1 %tobool.not, i32 %c, i32 %a %cond = select i1 %tobool.not, i32 %c, i32 %a
ret i32 %cond ret i32 %cond
} }
define signext i32 @cmov_sle_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { define signext i32 @cmov_sle_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
; RV64I-LABEL: cmov_sle_i32: ; RV64I-LABEL: cmov_sle_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bge a2, a1, .LBB3_2 ; RV64I-NEXT: bge a2, a1, .LBB3_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB3_2: ; RV64I-NEXT: .LBB3_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: cmov_sle_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: slt a1, a2, a1
; RV64B-NEXT: cmov a0, a1, a3, a0
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: cmov_sle_i32: ; RV64ZBT-LABEL: cmov_sle_i32:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: slt a1, a2, a1 ; RV64ZBT-NEXT: slt a1, a2, a1
; RV64ZBT-NEXT: cmov a0, a1, a3, a0 ; RV64ZBT-NEXT: cmov a0, a1, a3, a0
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool = icmp sle i32 %b, %c %tobool = icmp sle i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define signext i32 @cmov_sge_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { define signext i32 @cmov_sge_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
; RV64I-LABEL: cmov_sge_i32: ; RV64I-LABEL: cmov_sge_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bge a1, a2, .LBB4_2 ; RV64I-NEXT: bge a1, a2, .LBB4_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB4_2: ; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: cmov_sge_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: slt a1, a1, a2
; RV64B-NEXT: cmov a0, a1, a3, a0
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: cmov_sge_i32: ; RV64ZBT-LABEL: cmov_sge_i32:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: slt a1, a1, a2 ; RV64ZBT-NEXT: slt a1, a1, a2
; RV64ZBT-NEXT: cmov a0, a1, a3, a0 ; RV64ZBT-NEXT: cmov a0, a1, a3, a0
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool = icmp sge i32 %b, %c %tobool = icmp sge i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define signext i32 @cmov_ule_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { define signext i32 @cmov_ule_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
; RV64I-LABEL: cmov_ule_i32: ; RV64I-LABEL: cmov_ule_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bgeu a2, a1, .LBB5_2 ; RV64I-NEXT: bgeu a2, a1, .LBB5_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB5_2: ; RV64I-NEXT: .LBB5_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: cmov_ule_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: sltu a1, a2, a1
; RV64B-NEXT: cmov a0, a1, a3, a0
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: cmov_ule_i32: ; RV64ZBT-LABEL: cmov_ule_i32:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: sltu a1, a2, a1 ; RV64ZBT-NEXT: sltu a1, a2, a1
; RV64ZBT-NEXT: cmov a0, a1, a3, a0 ; RV64ZBT-NEXT: cmov a0, a1, a3, a0
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool = icmp ule i32 %b, %c %tobool = icmp ule i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define signext i32 @cmov_uge_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { define signext i32 @cmov_uge_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
; RV64I-LABEL: cmov_uge_i32: ; RV64I-LABEL: cmov_uge_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bgeu a1, a2, .LBB6_2 ; RV64I-NEXT: bgeu a1, a2, .LBB6_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB6_2: ; RV64I-NEXT: .LBB6_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: cmov_uge_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: sltu a1, a1, a2
; RV64B-NEXT: cmov a0, a1, a3, a0
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: cmov_uge_i32: ; RV64ZBT-LABEL: cmov_uge_i32:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: sltu a1, a1, a2 ; RV64ZBT-NEXT: sltu a1, a1, a2
; RV64ZBT-NEXT: cmov a0, a1, a3, a0 ; RV64ZBT-NEXT: cmov a0, a1, a3, a0
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool = icmp uge i32 %b, %c %tobool = icmp uge i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind { define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmov_i64: ; RV64I-LABEL: cmov_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: beqz a1, .LBB7_2 ; RV64I-NEXT: beqz a1, .LBB7_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: .LBB7_2: ; RV64I-NEXT: .LBB7_2:
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: cmov_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: cmov a0, a1, a0, a2
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: cmov_i64: ; RV64ZBT-LABEL: cmov_i64:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: cmov a0, a1, a0, a2 ; RV64ZBT-NEXT: cmov a0, a1, a0, a2
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool.not = icmp eq i64 %b, 0 %tobool.not = icmp eq i64 %b, 0
%cond = select i1 %tobool.not, i64 %c, i64 %a %cond = select i1 %tobool.not, i64 %c, i64 %a
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_sle_i64: ; RV64I-LABEL: cmov_sle_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bge a2, a1, .LBB8_2 ; RV64I-NEXT: bge a2, a1, .LBB8_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB8_2: ; RV64I-NEXT: .LBB8_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: cmov_sle_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: slt a1, a2, a1
; RV64B-NEXT: cmov a0, a1, a3, a0
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: cmov_sle_i64: ; RV64ZBT-LABEL: cmov_sle_i64:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: slt a1, a2, a1 ; RV64ZBT-NEXT: slt a1, a2, a1
; RV64ZBT-NEXT: cmov a0, a1, a3, a0 ; RV64ZBT-NEXT: cmov a0, a1, a3, a0
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool = icmp sle i64 %b, %c %tobool = icmp sle i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_sge_i64: ; RV64I-LABEL: cmov_sge_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bge a1, a2, .LBB9_2 ; RV64I-NEXT: bge a1, a2, .LBB9_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB9_2: ; RV64I-NEXT: .LBB9_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: cmov_sge_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: slt a1, a1, a2
; RV64B-NEXT: cmov a0, a1, a3, a0
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: cmov_sge_i64: ; RV64ZBT-LABEL: cmov_sge_i64:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: slt a1, a1, a2 ; RV64ZBT-NEXT: slt a1, a1, a2
; RV64ZBT-NEXT: cmov a0, a1, a3, a0 ; RV64ZBT-NEXT: cmov a0, a1, a3, a0
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool = icmp sge i64 %b, %c %tobool = icmp sge i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_ule_i64: ; RV64I-LABEL: cmov_ule_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bgeu a2, a1, .LBB10_2 ; RV64I-NEXT: bgeu a2, a1, .LBB10_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB10_2: ; RV64I-NEXT: .LBB10_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: cmov_ule_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: sltu a1, a2, a1
; RV64B-NEXT: cmov a0, a1, a3, a0
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: cmov_ule_i64: ; RV64ZBT-LABEL: cmov_ule_i64:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: sltu a1, a2, a1 ; RV64ZBT-NEXT: sltu a1, a2, a1
; RV64ZBT-NEXT: cmov a0, a1, a3, a0 ; RV64ZBT-NEXT: cmov a0, a1, a3, a0
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool = icmp ule i64 %b, %c %tobool = icmp ule i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_uge_i64: ; RV64I-LABEL: cmov_uge_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bgeu a1, a2, .LBB11_2 ; RV64I-NEXT: bgeu a1, a2, .LBB11_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB11_2: ; RV64I-NEXT: .LBB11_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: cmov_uge_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: sltu a1, a1, a2
; RV64B-NEXT: cmov a0, a1, a3, a0
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: cmov_uge_i64: ; RV64ZBT-LABEL: cmov_uge_i64:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: sltu a1, a1, a2 ; RV64ZBT-NEXT: sltu a1, a1, a2
; RV64ZBT-NEXT: cmov a0, a1, a3, a0 ; RV64ZBT-NEXT: cmov a0, a1, a3, a0
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool = icmp uge i64 %b, %c %tobool = icmp uge i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
declare i32 @llvm.fshl.i32(i32, i32, i32) declare i32 @llvm.fshl.i32(i32, i32, i32)
define signext i32 @fshl_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind { define signext i32 @fshl_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
; RV64I-LABEL: fshl_i32: ; RV64I-LABEL: fshl_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: slli a1, a1, 32 ; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a1, a1, 32 ; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: andi a1, a2, 31 ; RV64I-NEXT: andi a1, a2, 31
; RV64I-NEXT: sll a0, a0, a1 ; RV64I-NEXT: sll a0, a0, a1
; RV64I-NEXT: srai a0, a0, 32 ; RV64I-NEXT: srai a0, a0, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: fshl_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: andi a2, a2, 31
; RV64B-NEXT: fslw a0, a0, a1, a2
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: fshl_i32: ; RV64ZBT-LABEL: fshl_i32:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: andi a2, a2, 31 ; RV64ZBT-NEXT: andi a2, a2, 31
; RV64ZBT-NEXT: fslw a0, a0, a1, a2 ; RV64ZBT-NEXT: fslw a0, a0, a1, a2
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c) %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c)
ret i32 %1 ret i32 %1
} }
; Similar to fshl_i32 but result is not sign extended. ; Similar to fshl_i32 but result is not sign extended.
define void @fshl_i32_nosext(i32 signext %a, i32 signext %b, i32 signext %c, i32* %x) nounwind { define void @fshl_i32_nosext(i32 signext %a, i32 signext %b, i32 signext %c, i32* %x) nounwind {
; RV64I-LABEL: fshl_i32_nosext: ; RV64I-LABEL: fshl_i32_nosext:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: slli a1, a1, 32 ; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a1, a1, 32 ; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: andi a1, a2, 31 ; RV64I-NEXT: andi a1, a2, 31
; RV64I-NEXT: sll a0, a0, a1 ; RV64I-NEXT: sll a0, a0, a1
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sw a0, 0(a3) ; RV64I-NEXT: sw a0, 0(a3)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: fshl_i32_nosext:
; RV64B: # %bb.0:
; RV64B-NEXT: andi a2, a2, 31
; RV64B-NEXT: fslw a0, a0, a1, a2
; RV64B-NEXT: sw a0, 0(a3)
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: fshl_i32_nosext: ; RV64ZBT-LABEL: fshl_i32_nosext:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: andi a2, a2, 31 ; RV64ZBT-NEXT: andi a2, a2, 31
; RV64ZBT-NEXT: fslw a0, a0, a1, a2 ; RV64ZBT-NEXT: fslw a0, a0, a1, a2
; RV64ZBT-NEXT: sw a0, 0(a3) ; RV64ZBT-NEXT: sw a0, 0(a3)
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c) %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c)
store i32 %1, i32* %x store i32 %1, i32* %x
ret void ret void
} }
declare i64 @llvm.fshl.i64(i64, i64, i64) declare i64 @llvm.fshl.i64(i64, i64, i64)
define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind { define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: fshl_i64: ; RV64I-LABEL: fshl_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sll a0, a0, a2 ; RV64I-NEXT: sll a0, a0, a2
; RV64I-NEXT: not a2, a2 ; RV64I-NEXT: not a2, a2
; RV64I-NEXT: srli a1, a1, 1 ; RV64I-NEXT: srli a1, a1, 1
; RV64I-NEXT: srl a1, a1, a2 ; RV64I-NEXT: srl a1, a1, a2
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: fshl_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: andi a2, a2, 63
; RV64B-NEXT: fsl a0, a0, a1, a2
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: fshl_i64: ; RV64ZBT-LABEL: fshl_i64:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: andi a2, a2, 63 ; RV64ZBT-NEXT: andi a2, a2, 63
; RV64ZBT-NEXT: fsl a0, a0, a1, a2 ; RV64ZBT-NEXT: fsl a0, a0, a1, a2
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 %c) %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 %c)
ret i64 %1 ret i64 %1
} }
declare i32 @llvm.fshr.i32(i32, i32, i32) declare i32 @llvm.fshr.i32(i32, i32, i32)
define signext i32 @fshr_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind { define signext i32 @fshr_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
; RV64I-LABEL: fshr_i32: ; RV64I-LABEL: fshr_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: slli a1, a1, 32 ; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a1, a1, 32 ; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: andi a1, a2, 31 ; RV64I-NEXT: andi a1, a2, 31
; RV64I-NEXT: srl a0, a0, a1 ; RV64I-NEXT: srl a0, a0, a1
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: fshr_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: andi a2, a2, 31
; RV64B-NEXT: fsrw a0, a1, a0, a2
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: fshr_i32: ; RV64ZBT-LABEL: fshr_i32:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: andi a2, a2, 31 ; RV64ZBT-NEXT: andi a2, a2, 31
; RV64ZBT-NEXT: fsrw a0, a1, a0, a2 ; RV64ZBT-NEXT: fsrw a0, a1, a0, a2
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c) %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)
ret i32 %1 ret i32 %1
} }
; Similar to fshr_i32 but result is not sign extended. ; Similar to fshr_i32 but result is not sign extended.
define void @fshr_i32_nosext(i32 signext %a, i32 signext %b, i32 signext %c, i32* %x) nounwind { define void @fshr_i32_nosext(i32 signext %a, i32 signext %b, i32 signext %c, i32* %x) nounwind {
; RV64I-LABEL: fshr_i32_nosext: ; RV64I-LABEL: fshr_i32_nosext:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: slli a1, a1, 32 ; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a1, a1, 32 ; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: andi a1, a2, 31 ; RV64I-NEXT: andi a1, a2, 31
; RV64I-NEXT: srl a0, a0, a1 ; RV64I-NEXT: srl a0, a0, a1
; RV64I-NEXT: sw a0, 0(a3) ; RV64I-NEXT: sw a0, 0(a3)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: fshr_i32_nosext:
; RV64B: # %bb.0:
; RV64B-NEXT: andi a2, a2, 31
; RV64B-NEXT: fsrw a0, a1, a0, a2
; RV64B-NEXT: sw a0, 0(a3)
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: fshr_i32_nosext: ; RV64ZBT-LABEL: fshr_i32_nosext:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: andi a2, a2, 31 ; RV64ZBT-NEXT: andi a2, a2, 31
; RV64ZBT-NEXT: fsrw a0, a1, a0, a2 ; RV64ZBT-NEXT: fsrw a0, a1, a0, a2
; RV64ZBT-NEXT: sw a0, 0(a3) ; RV64ZBT-NEXT: sw a0, 0(a3)
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c) %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)
store i32 %1, i32* %x store i32 %1, i32* %x
ret void ret void
} }
declare i64 @llvm.fshr.i64(i64, i64, i64) declare i64 @llvm.fshr.i64(i64, i64, i64)
define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind { define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: fshr_i64: ; RV64I-LABEL: fshr_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srl a1, a1, a2 ; RV64I-NEXT: srl a1, a1, a2
; RV64I-NEXT: not a2, a2 ; RV64I-NEXT: not a2, a2
; RV64I-NEXT: slli a0, a0, 1 ; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: sll a0, a0, a2 ; RV64I-NEXT: sll a0, a0, a2
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: fshr_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: andi a2, a2, 63
; RV64B-NEXT: fsr a0, a1, a0, a2
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: fshr_i64: ; RV64ZBT-LABEL: fshr_i64:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: andi a2, a2, 63 ; RV64ZBT-NEXT: andi a2, a2, 63
; RV64ZBT-NEXT: fsr a0, a1, a0, a2 ; RV64ZBT-NEXT: fsr a0, a1, a0, a2
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 %c) %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 %c)
ret i64 %1 ret i64 %1
} }
define signext i32 @fshri_i32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @fshri_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: fshri_i32: ; RV64I-LABEL: fshri_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a1, 5 ; RV64I-NEXT: srliw a1, a1, 5
; RV64I-NEXT: slli a0, a0, 27 ; RV64I-NEXT: slli a0, a0, 27
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: fshri_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: fsriw a0, a1, a0, 5
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: fshri_i32: ; RV64ZBT-LABEL: fshri_i32:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: fsriw a0, a1, a0, 5 ; RV64ZBT-NEXT: fsriw a0, a1, a0, 5
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 5) %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 5)
ret i32 %1 ret i32 %1
} }
; Similar to fshr_i32 but result is not sign extended. ; Similar to fshr_i32 but result is not sign extended.
define void @fshri_i32_nosext(i32 signext %a, i32 signext %b, i32* %x) nounwind { define void @fshri_i32_nosext(i32 signext %a, i32 signext %b, i32* %x) nounwind {
; RV64I-LABEL: fshri_i32_nosext: ; RV64I-LABEL: fshri_i32_nosext:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a1, 5 ; RV64I-NEXT: srliw a1, a1, 5
; RV64I-NEXT: slli a0, a0, 27 ; RV64I-NEXT: slli a0, a0, 27
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: sw a0, 0(a2) ; RV64I-NEXT: sw a0, 0(a2)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: fshri_i32_nosext:
; RV64B: # %bb.0:
; RV64B-NEXT: fsriw a0, a1, a0, 5
; RV64B-NEXT: sw a0, 0(a2)
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: fshri_i32_nosext: ; RV64ZBT-LABEL: fshri_i32_nosext:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: fsriw a0, a1, a0, 5 ; RV64ZBT-NEXT: fsriw a0, a1, a0, 5
; RV64ZBT-NEXT: sw a0, 0(a2) ; RV64ZBT-NEXT: sw a0, 0(a2)
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 5) %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 5)
store i32 %1, i32* %x store i32 %1, i32* %x
ret void ret void
} }
define i64 @fshri_i64(i64 %a, i64 %b) nounwind { define i64 @fshri_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: fshri_i64: ; RV64I-LABEL: fshri_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a1, 5 ; RV64I-NEXT: srli a1, a1, 5
; RV64I-NEXT: slli a0, a0, 59 ; RV64I-NEXT: slli a0, a0, 59
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: fshri_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: fsri a0, a1, a0, 5
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: fshri_i64: ; RV64ZBT-LABEL: fshri_i64:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: fsri a0, a1, a0, 5 ; RV64ZBT-NEXT: fsri a0, a1, a0, 5
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 5) %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 5)
ret i64 %1 ret i64 %1
} }
define signext i32 @fshli_i32(i32 signext %a, i32 signext %b) nounwind { define signext i32 @fshli_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: fshli_i32: ; RV64I-LABEL: fshli_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a1, 27 ; RV64I-NEXT: srliw a1, a1, 27
; RV64I-NEXT: slli a0, a0, 5 ; RV64I-NEXT: slli a0, a0, 5
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: fshli_i32:
; RV64B: # %bb.0:
; RV64B-NEXT: fsriw a0, a1, a0, 27
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: fshli_i32: ; RV64ZBT-LABEL: fshli_i32:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: fsriw a0, a1, a0, 27 ; RV64ZBT-NEXT: fsriw a0, a1, a0, 27
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 5) %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 5)
ret i32 %1 ret i32 %1
} }
; Similar to fshl_i32 but result is not sign extended. ; Similar to fshl_i32 but result is not sign extended.
define void @fshli_i32_nosext(i32 signext %a, i32 signext %b, i32* %x) nounwind { define void @fshli_i32_nosext(i32 signext %a, i32 signext %b, i32* %x) nounwind {
; RV64I-LABEL: fshli_i32_nosext: ; RV64I-LABEL: fshli_i32_nosext:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a1, 27 ; RV64I-NEXT: srliw a1, a1, 27
; RV64I-NEXT: slli a0, a0, 5 ; RV64I-NEXT: slli a0, a0, 5
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: sw a0, 0(a2) ; RV64I-NEXT: sw a0, 0(a2)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: fshli_i32_nosext:
; RV64B: # %bb.0:
; RV64B-NEXT: fsriw a0, a1, a0, 27
; RV64B-NEXT: sw a0, 0(a2)
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: fshli_i32_nosext: ; RV64ZBT-LABEL: fshli_i32_nosext:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: fsriw a0, a1, a0, 27 ; RV64ZBT-NEXT: fsriw a0, a1, a0, 27
; RV64ZBT-NEXT: sw a0, 0(a2) ; RV64ZBT-NEXT: sw a0, 0(a2)
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 5) %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 5)
store i32 %1, i32* %x store i32 %1, i32* %x
ret void ret void
} }
define i64 @fshli_i64(i64 %a, i64 %b) nounwind { define i64 @fshli_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: fshli_i64: ; RV64I-LABEL: fshli_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a1, 59 ; RV64I-NEXT: srli a1, a1, 59
; RV64I-NEXT: slli a0, a0, 5 ; RV64I-NEXT: slli a0, a0, 5
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64B-LABEL: fshli_i64:
; RV64B: # %bb.0:
; RV64B-NEXT: fsri a0, a1, a0, 59
; RV64B-NEXT: ret
;
; RV64ZBT-LABEL: fshli_i64: ; RV64ZBT-LABEL: fshli_i64:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: fsri a0, a1, a0, 59 ; RV64ZBT-NEXT: fsri a0, a1, a0, 59
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 5) %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 5)
ret i64 %1 ret i64 %1
} }

llvm/test/MC/RISCV/attribute-arch.s

Show All 30 Lines
# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0" # CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
.attribute arch, "rv32ima2p0_fdc" .attribute arch, "rv32ima2p0_fdc"
# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0" # CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
.attribute arch, "rv32ima2p_fdc" .attribute arch, "rv32ima2p_fdc"
# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0" # CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
.attribute arch, "rv32ib"
# CHECK: attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
.attribute arch, "rv32iv" .attribute arch, "rv32iv"
# CHECK: attribute 5, "rv32i2p0_v0p10" # CHECK: attribute 5, "rv32i2p0_v0p10"
.attribute arch, "rv32izba" .attribute arch, "rv32izba"
# CHECK: attribute 5, "rv32i2p0_zba0p93" # CHECK: attribute 5, "rv32i2p0_zba0p93"
.attribute arch, "rv32izbb" .attribute arch, "rv32izbb"
# CHECK: attribute 5, "rv32i2p0_zbb0p93" # CHECK: attribute 5, "rv32i2p0_zbb0p93"
Show All 33 Lines

llvm/test/MC/RISCV/rv32b-aliases-valid.s

  • This file was moved to llvm/test/MC/RISCV/rv32zbp-aliases-valid.s.

llvm/test/MC/RISCV/rv32zba-valid.s

# With B extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip base extension: # With Bitmanip base extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zba -show-encoding \ # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zba -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zba -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zba -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zba < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zba < %s \
# RUN: | llvm-objdump --mattr=+experimental-zba -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zba -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
Show All 13 Lines

llvm/test/MC/RISCV/rv32zbb-aliases-valid.s

  • This file was added.
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbb -riscv-no-aliases \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbb \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zbb < %s \
# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbb - \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zbb < %s \
# RUN: | llvm-objdump -d -r --mattr=+experimental-zbb - \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
# The following check prefixes are used in this test:
# CHECK-S-OBJ Match both the .s and objdumped object output with
# aliases enabled
# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
# aliases disabled
# CHECK-S-OBJ-NOALIAS: zext.h t0, t1
# CHECK-S-OBJ: zext.h t0, t1
zext.h x5, x6
# CHECK-S-OBJ-NOALIAS: rev8 t0, t1
# CHECK-S-OBJ: rev8 t0, t1
rev8 x5, x6
# CHECK-S-OBJ-NOALIAS: orc.b t0, t1
# CHECK-S-OBJ: orc.b t0, t1
orc.b x5, x6
# CHECK-S-OBJ-NOALIAS: rori t0, t1, 8
# CHECK-S-OBJ: rori t0, t1, 8
ror x5, x6, 8

llvm/test/MC/RISCV/rv32zbb-valid.s

# With B extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip base extension: # With Bitmanip base extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbb -riscv-no-aliases -show-encoding \ # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbb -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -riscv-no-aliases -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbb < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbb < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbb -M no-aliases -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zbb -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
Show All 31 Lines

llvm/test/MC/RISCV/rv32zbbp-only-valid.s

# With B extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip base extension: # With Bitmanip base extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbb -riscv-no-aliases -show-encoding \ # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbb -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbb < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbb < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbb -M no-aliases -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zbb -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip permutation extension: # With Bitmanip permutation extension:
Show All 12 Lines

llvm/test/MC/RISCV/rv32zbbp-valid.s

# With B extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip base extension: # With Bitmanip base extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbb < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbb < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbb -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zbb -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
Show All 40 Lines

llvm/test/MC/RISCV/rv32zbc-valid.s

# With B extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip carry-less multiply extension: # With Bitmanip carry-less multiply extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbc -show-encoding \ # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbc -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbc -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbc -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbc < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbc < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbc -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zbc -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
Show All 13 Lines

llvm/test/MC/RISCV/rv32zbe-valid.s

# With B extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip extract/deposit extension: # With Bitmanip extract/deposit extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbe -show-encoding \ # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbe -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbe -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbe -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbe < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbe < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbe -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zbe -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
Show All 10 Lines

llvm/test/MC/RISCV/rv32zbf-valid.s

# With B extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bit-Field extension: # With Bit-Field extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbf -show-encoding \ # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbf -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbf -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbf -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbf < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbf < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbf -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zbf -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbf < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbf < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbf -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zbf -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: bfp t0, t1, t2 # CHECK-ASM-AND-OBJ: bfp t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x48] # CHECK-ASM: encoding: [0xb3,0x72,0x73,0x48]
bfp t0, t1, t2 bfp t0, t1, t2

llvm/test/MC/RISCV/rv32zbp-aliases-valid.s

  • This file was moved from llvm/test/MC/RISCV/rv32b-aliases-valid.s.
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -riscv-no-aliases \ # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbp -riscv-no-aliases \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s # RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b \ # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbp \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-b < %s \ # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zbp < %s \
# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-b - \ # RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbp - \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s # RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-b < %s \ # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zbp < %s \
# RUN: | llvm-objdump -d -r --mattr=+experimental-b - \ # RUN: | llvm-objdump -d -r --mattr=+experimental-zbp - \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
# The following check prefixes are used in this test: # The following check prefixes are used in this test:
# CHECK-S-OBJ Match both the .s and objdumped object output with # CHECK-S-OBJ Match both the .s and objdumped object output with
# aliases enabled # aliases enabled
# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with # CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
# aliases disabled # aliases disabled
# CHECK-S-OBJ-NOALIAS: andi t0, t1, 255
# CHECK-S-OBJ: andi t0, t1, 255
zext.b x5, x6
# CHECK-S-OBJ-NOALIAS: zext.h t0, t1 # CHECK-S-OBJ-NOALIAS: zext.h t0, t1
# CHECK-S-OBJ: zext.h t0, t1 # CHECK-S-OBJ: zext.h t0, t1
zext.h x5, x6 zext.h x5, x6
# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 1 # CHECK-S-OBJ-NOALIAS: grevi t0, t1, 1
# CHECK-S-OBJ: rev.p t0, t1 # CHECK-S-OBJ: rev.p t0, t1
rev.p x5, x6 rev.p x5, x6
▲ Show 20 Lines • Show All 192 Lines • ▼ Show 20 Lines
# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 31 # CHECK-S-OBJ-NOALIAS: gorci t0, t1, 31
# CHECK-S-OBJ: orc t0, t1 # CHECK-S-OBJ: orc t0, t1
orc x5, x6 orc x5, x6
# CHECK-S-OBJ-NOALIAS: rori t0, t1, 8 # CHECK-S-OBJ-NOALIAS: rori t0, t1, 8
# CHECK-S-OBJ: rori t0, t1, 8 # CHECK-S-OBJ: rori t0, t1, 8
ror x5, x6, 8 ror x5, x6, 8
# CHECK-S-OBJ-NOALIAS: bseti t0, t1, 8
# CHECK-S-OBJ: bseti t0, t1, 8
bset x5, x6, 8
# CHECK-S-OBJ-NOALIAS: bclri t0, t1, 8
# CHECK-S-OBJ: bclri t0, t1, 8
bclr x5, x6, 8
# CHECK-S-OBJ-NOALIAS: binvi t0, t1, 8
# CHECK-S-OBJ: binvi t0, t1, 8
binv x5, x6, 8
# CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
# CHECK-S-OBJ: bexti t0, t1, 8
bext x5, x6, 8
# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 13 # CHECK-S-OBJ-NOALIAS: grevi t0, t1, 13
# CHECK-S-OBJ: grevi t0, t1, 13 # CHECK-S-OBJ: grevi t0, t1, 13
grev x5, x6, 13 grev x5, x6, 13
# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 13 # CHECK-S-OBJ-NOALIAS: gorci t0, t1, 13
# CHECK-S-OBJ: gorci t0, t1, 13 # CHECK-S-OBJ: gorci t0, t1, 13
gorc x5, x6, 13 gorc x5, x6, 13
# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 13 # CHECK-S-OBJ-NOALIAS: shfli t0, t1, 13
# CHECK-S-OBJ: shfli t0, t1, 13 # CHECK-S-OBJ: shfli t0, t1, 13
shfl x5, x6, 13 shfl x5, x6, 13
# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 13 # CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 13
# CHECK-S-OBJ: unshfli t0, t1, 13 # CHECK-S-OBJ: unshfli t0, t1, 13
unshfl x5, x6, 13 unshfl x5, x6, 13

llvm/test/MC/RISCV/rv32zbp-only-valid.s

# With B extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefix=CHECK-ASM %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-OBJ %s
# With Bitmanip permutation extension: # With Bitmanip permutation extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbp -show-encoding \ # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbp -show-encoding \
# RUN: | FileCheck -check-prefix=CHECK-ASM %s # RUN: | FileCheck -check-prefix=CHECK-ASM %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbp < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbp < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbp -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zbp -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-OBJ %s
# CHECK-ASM: pack t0, t1, zero # CHECK-ASM: pack t0, t1, zero
# CHECK-OBJ: zext.h t0, t1 # CHECK-OBJ: zext.h t0, t1
# CHECK-ASM: encoding: [0xb3,0x42,0x03,0x08] # CHECK-ASM: encoding: [0xb3,0x42,0x03,0x08]
pack t0, t1, x0 pack t0, t1, x0
# CHECK-ASM: grevi t0, t1, 24 # CHECK-ASM: grevi t0, t1, 24
# CHECK-OBJ: rev8 t0, t1 # CHECK-OBJ: rev8 t0, t1
# CHECK-ASM: encoding: [0x93,0x52,0x83,0x69] # CHECK-ASM: encoding: [0x93,0x52,0x83,0x69]
grevi t0, t1, 24 grevi t0, t1, 24

llvm/test/MC/RISCV/rv32zbp-valid.s

# With B extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
# With Bitmanip permutation extension: # With Bitmanip permutation extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbp -show-encoding \ # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbp -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbp -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbp -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbp < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbp < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbp -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zbp -d -r - \
# RUN: | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
▲ Show 20 Lines • Show All 50 Lines • Show Last 20 Lines

llvm/test/MC/RISCV/rv32zbr-valid.s

# With B extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip CRC extension: # With Bitmanip CRC extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbr -show-encoding \ # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbr -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbr < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbr < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbr -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zbr -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: crc32.b t0, t1 # CHECK-ASM-AND-OBJ: crc32.b t0, t1
Show All 17 Lines

llvm/test/MC/RISCV/rv32zbs-aliases-valid.s

  • This file was added.
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbs -riscv-no-aliases \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbs \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zbs < %s \
# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbs - \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zbs < %s \
# RUN: | llvm-objdump -d -r --mattr=+experimental-zbs - \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
# The following check prefixes are used in this test:
# CHECK-S-OBJ Match both the .s and objdumped object output with
# aliases enabled
# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
# aliases disabled
# CHECK-S-OBJ-NOALIAS: bseti t0, t1, 8
# CHECK-S-OBJ: bseti t0, t1, 8
bset x5, x6, 8
# CHECK-S-OBJ-NOALIAS: bclri t0, t1, 8
# CHECK-S-OBJ: bclri t0, t1, 8
bclr x5, x6, 8
# CHECK-S-OBJ-NOALIAS: binvi t0, t1, 8
# CHECK-S-OBJ: binvi t0, t1, 8
binv x5, x6, 8
# CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
# CHECK-S-OBJ: bexti t0, t1, 8
bext x5, x6, 8

llvm/test/MC/RISCV/rv32zbs-invalid.s

Show All 22 Lines
# Immediate operand out of range # Immediate operand out of range
binvi t0, t1, 32 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31] binvi t0, t1, 32 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
binvi t0, t1, -1 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31] binvi t0, t1, -1 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
# Too few operands # Too few operands
bexti t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction bexti t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Immediate operand out of range # Immediate operand out of range
bexti t0, t1, 32 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31] bexti t0, t1, 32 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
bexti t0, t1, -1 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31] bexti t0, t1, -1 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
bclrw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
bsetw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
binvw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
bextw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
bclriw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
bsetiw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
binviw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set

llvm/test/MC/RISCV/rv32zbs-valid.s

# With B extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip single bit extension: # With Bitmanip single bit extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbs -show-encoding \ # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbs -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbs -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbs -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbs < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbs < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbs -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zbs -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
Show All 28 Lines

llvm/test/MC/RISCV/rv32zbt-valid.s

# With B extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip ternary extension: # With Bitmanip ternary extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbt -show-encoding \ # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbt -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbt -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbt -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbt < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbt < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbt -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zbt -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
Show All 19 Lines

llvm/test/MC/RISCV/rv64b-aliases-valid.s

  • This file was moved to llvm/test/MC/RISCV/rv64zbp-aliases-valid.s.

llvm/test/MC/RISCV/rv64zba-aliases-valid.s

  • This file was added.
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zba -riscv-no-aliases \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zba \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zba < %s \
# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zba - \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zba < %s \
# RUN: | llvm-objdump -d -r --mattr=+experimental-zba - \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
# The following check prefixes are used in this test:
# CHECK-S-OBJ Match both the .s and objdumped object output with
# aliases enabled
# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
# aliases disabled
# CHECK-S-OBJ-NOALIAS: add.uw t0, t1, zero
# CHECK-S-OBJ: zext.w t0, t1
zext.w x5, x6
# CHECK-S-OBJ-NOALIAS: addi t1, zero, -2
# CHECK-S-OBJ-NOALIAS-NEXT: add.uw t1, t1, zero
# CHECK-S-OBJ: addi t1, zero, -2
# CHECK-S-OBJ-NEXT: zext.w t1, t1
li x6, 0xfffffffe
# CHECK-S-OBJ-NOALIAS: lui t2, 699051
# CHECK-S-OBJ-NOALIAS-NEXT: addiw t2, t2, -1366
# CHECK-S-OBJ-NOALIAS-NEXT: add.uw t2, t2, zero
# CHECK-S-OBJ: lui t2, 699051
# CHECK-S-OBJ-NEXT: addiw t2, t2, -1366
# CHECK-S-OBJ-NEXT: zext.w t2, t2
li x7, 0xaaaaaaaa

llvm/test/MC/RISCV/rv64zba-valid.s

# With B extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip base extension: # With Bitmanip base extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zba -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zba -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zba < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zba < %s \
# RUN: | llvm-objdump --mattr=+experimental-zba -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zba -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: slli.uw t0, t1, 0 # CHECK-ASM-AND-OBJ: slli.uw t0, t1, 0
Show All 14 Lines

llvm/test/MC/RISCV/rv64zbb-aliases-valid.s

  • This file was added.
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -riscv-no-aliases \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbb < %s \
# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbb - \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbb < %s \
# RUN: | llvm-objdump -d -r --mattr=+experimental-zbb - \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
# The following check prefixes are used in this test:
# CHECK-S-OBJ Match both the .s and objdumped object output with
# aliases enabled
# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
# aliases disabled
# CHECK-S-OBJ-NOALIAS: zext.h t0, t1
# CHECK-S-OBJ: zext.h t0, t1
zext.h x5, x6
# CHECK-S-OBJ-NOALIAS: rev8 t0, t1
# CHECK-S-OBJ: rev8 t0, t1
rev8 x5, x6
# CHECK-S-OBJ-NOALIAS: orc.b t0, t1
# CHECK-S-OBJ: orc.b t0, t1
orc.b x5, x6
# CHECK-S-OBJ-NOALIAS: rori t0, t1, 8
# CHECK-S-OBJ: rori t0, t1, 8
ror x5, x6, 8
# CHECK-S-OBJ-NOALIAS: roriw t0, t1, 8
# CHECK-S-OBJ: roriw t0, t1, 8
rorw x5, x6, 8

llvm/test/MC/RISCV/rv64zbb-valid.s

# With B extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip base extension: # With Bitmanip base extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -riscv-no-aliases -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbb < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbb < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbb -M no-aliases -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zbb -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: clzw t0, t1 # CHECK-ASM-AND-OBJ: clzw t0, t1
# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x60] # CHECK-ASM: encoding: [0x9b,0x12,0x03,0x60]
clzw t0, t1 clzw t0, t1
# CHECK-ASM-AND-OBJ: ctzw t0, t1 # CHECK-ASM-AND-OBJ: ctzw t0, t1
# CHECK-ASM: encoding: [0x9b,0x12,0x13,0x60] # CHECK-ASM: encoding: [0x9b,0x12,0x13,0x60]
ctzw t0, t1 ctzw t0, t1
# CHECK-ASM-AND-OBJ: cpopw t0, t1 # CHECK-ASM-AND-OBJ: cpopw t0, t1
# CHECK-ASM: encoding: [0x9b,0x12,0x23,0x60] # CHECK-ASM: encoding: [0x9b,0x12,0x23,0x60]
cpopw t0, t1 cpopw t0, t1

llvm/test/MC/RISCV/rv64zbbp-valid.s

# With B extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip base extension: # With Bitmanip base extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbb < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbb < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbb -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zbb -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip permutation extension: # With Bitmanip permutation extension:
Show All 24 Lines

llvm/test/MC/RISCV/rv64zbe-valid.s

# With B extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip extract/deposit extension: # With Bitmanip extract/deposit extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbe -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbe -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbe < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbe < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbe -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zbe -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: bdecompressw t0, t1, t2 # CHECK-ASM-AND-OBJ: bdecompressw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x62,0x73,0x48] # CHECK-ASM: encoding: [0xbb,0x62,0x73,0x48]
bdecompressw t0, t1, t2 bdecompressw t0, t1, t2
# CHECK-ASM-AND-OBJ: bcompressw t0, t1, t2 # CHECK-ASM-AND-OBJ: bcompressw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x62,0x73,0x08] # CHECK-ASM: encoding: [0xbb,0x62,0x73,0x08]
bcompressw t0, t1, t2 bcompressw t0, t1, t2

llvm/test/MC/RISCV/rv64zbf-valid.s

# With B extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bit-Field extension: # With Bit-Field extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbf -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbf -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbf < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbf < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbf -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zbf -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: bfpw t0, t1, t2 # CHECK-ASM-AND-OBJ: bfpw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x72,0x73,0x48] # CHECK-ASM: encoding: [0xbb,0x72,0x73,0x48]
bfpw t0, t1, t2 bfpw t0, t1, t2

llvm/test/MC/RISCV/rv64zbm-valid.s

# With B extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip matix extension: # With Bitmanip matix extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbm -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbm -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbm < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbm < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbm -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zbm -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: bmatflip t0, t1 # CHECK-ASM-AND-OBJ: bmatflip t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x33,0x60] # CHECK-ASM: encoding: [0x93,0x12,0x33,0x60]
bmatflip t0, t1 bmatflip t0, t1
# CHECK-ASM-AND-OBJ: bmator t0, t1, t2 # CHECK-ASM-AND-OBJ: bmator t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x32,0x73,0x08] # CHECK-ASM: encoding: [0xb3,0x32,0x73,0x08]
bmator t0, t1, t2 bmator t0, t1, t2
# CHECK-ASM-AND-OBJ: bmatxor t0, t1, t2 # CHECK-ASM-AND-OBJ: bmatxor t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x32,0x73,0x48] # CHECK-ASM: encoding: [0xb3,0x32,0x73,0x48]
bmatxor t0, t1, t2 bmatxor t0, t1, t2

llvm/test/MC/RISCV/rv64zbp-aliases-valid.s

  • This file was moved from llvm/test/MC/RISCV/rv64b-aliases-valid.s.
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -riscv-no-aliases \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbp -riscv-no-aliases \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s # RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbp \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-b < %s \ # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbp < %s \
# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-b - \ # RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbp - \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s # RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-b < %s \ # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbp < %s \
# RUN: | llvm-objdump -d -r --mattr=+experimental-b - \ # RUN: | llvm-objdump -d -r --mattr=+experimental-zbp - \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
# The following check prefixes are used in this test: # The following check prefixes are used in this test:
# CHECK-S-OBJ Match both the .s and objdumped object output with # CHECK-S-OBJ Match both the .s and objdumped object output with
# aliases enabled # aliases enabled
# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with # CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
# aliases disabled # aliases disabled
# CHECK-S-OBJ-NOALIAS: andi t0, t1, 255
# CHECK-S-OBJ: andi t0, t1, 255
zext.b x5, x6
# CHECK-S-OBJ-NOALIAS: zext.h t0, t1 # CHECK-S-OBJ-NOALIAS: zext.h t0, t1
# CHECK-S-OBJ: zext.h t0, t1 # CHECK-S-OBJ: zext.h t0, t1
zext.h x5, x6 zext.h x5, x6
# CHECK-S-OBJ-NOALIAS: add.uw t0, t1, zero
# CHECK-S-OBJ: zext.w t0, t1
zext.w x5, x6
# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 1 # CHECK-S-OBJ-NOALIAS: grevi t0, t1, 1
# CHECK-S-OBJ: rev.p t0, t1 # CHECK-S-OBJ: rev.p t0, t1
rev.p x5, x6 rev.p x5, x6
# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 2 # CHECK-S-OBJ-NOALIAS: grevi t0, t1, 2
# CHECK-S-OBJ: rev2.n t0, t1 # CHECK-S-OBJ: rev2.n t0, t1
rev2.n x5, x6 rev2.n x5, x6
▲ Show 20 Lines • Show All 280 Lines • ▼ Show 20 Lines
# CHECK-S-OBJ-NOALIAS: rori t0, t1, 8 # CHECK-S-OBJ-NOALIAS: rori t0, t1, 8
# CHECK-S-OBJ: rori t0, t1, 8 # CHECK-S-OBJ: rori t0, t1, 8
ror x5, x6, 8 ror x5, x6, 8
# CHECK-S-OBJ-NOALIAS: roriw t0, t1, 8 # CHECK-S-OBJ-NOALIAS: roriw t0, t1, 8
# CHECK-S-OBJ: roriw t0, t1, 8 # CHECK-S-OBJ: roriw t0, t1, 8
rorw x5, x6, 8 rorw x5, x6, 8
# CHECK-S-OBJ-NOALIAS: bseti t0, t1, 8
# CHECK-S-OBJ: bseti t0, t1, 8
bset x5, x6, 8
# CHECK-S-OBJ-NOALIAS: bclri t0, t1, 8
# CHECK-S-OBJ: bclri t0, t1, 8
bclr x5, x6, 8
# CHECK-S-OBJ-NOALIAS: binvi t0, t1, 8
# CHECK-S-OBJ: binvi t0, t1, 8
binv x5, x6, 8
# CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
# CHECK-S-OBJ: bexti t0, t1, 8
bext x5, x6, 8
# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 13 # CHECK-S-OBJ-NOALIAS: grevi t0, t1, 13
# CHECK-S-OBJ: grevi t0, t1, 13 # CHECK-S-OBJ: grevi t0, t1, 13
grev x5, x6, 13 grev x5, x6, 13
# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 13 # CHECK-S-OBJ-NOALIAS: gorci t0, t1, 13
# CHECK-S-OBJ: gorci t0, t1, 13 # CHECK-S-OBJ: gorci t0, t1, 13
gorc x5, x6, 13 gorc x5, x6, 13
# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 13 # CHECK-S-OBJ-NOALIAS: shfli t0, t1, 13
# CHECK-S-OBJ: shfli t0, t1, 13 # CHECK-S-OBJ: shfli t0, t1, 13
shfl x5, x6, 13 shfl x5, x6, 13
# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 13 # CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 13
# CHECK-S-OBJ: unshfli t0, t1, 13 # CHECK-S-OBJ: unshfli t0, t1, 13
unshfl x5, x6, 13 unshfl x5, x6, 13
# CHECK-S-OBJ-NOALIAS: greviw t0, t1, 13 # CHECK-S-OBJ-NOALIAS: greviw t0, t1, 13
# CHECK-S-OBJ: greviw t0, t1, 13 # CHECK-S-OBJ: greviw t0, t1, 13
grevw x5, x6, 13 grevw x5, x6, 13
# CHECK-S-OBJ-NOALIAS: gorciw t0, t1, 13 # CHECK-S-OBJ-NOALIAS: gorciw t0, t1, 13
# CHECK-S-OBJ: gorciw t0, t1, 13 # CHECK-S-OBJ: gorciw t0, t1, 13
gorcw x5, x6, 13 gorcw x5, x6, 13
# CHECK-S-OBJ-NOALIAS: addi t1, zero, -2
# CHECK-S-OBJ-NOALIAS-NEXT: add.uw t1, t1, zero
# CHECK-S-OBJ: addi t1, zero, -2
# CHECK-S-OBJ-NEXT: zext.w t1, t1
li x6, 0xfffffffe
# CHECK-S-OBJ-NOALIAS: lui t2, 699051
# CHECK-S-OBJ-NOALIAS-NEXT: addiw t2, t2, -1366
# CHECK-S-OBJ-NOALIAS-NEXT: add.uw t2, t2, zero
# CHECK-S-OBJ: lui t2, 699051
# CHECK-S-OBJ-NEXT: addiw t2, t2, -1366
# CHECK-S-OBJ-NEXT: zext.w t2, t2
li x7, 0xaaaaaaaa

llvm/test/MC/RISCV/rv64zbp-valid.s

# With B extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
# With Bitmanip permutation extension: # With Bitmanip permutation extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbp -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbp -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbp < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbp < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbp -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zbp -d -r - \
# RUN: | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: gorcw t0, t1, t2 # CHECK-ASM-AND-OBJ: gorcw t0, t1, t2
Show All 34 Lines

llvm/test/MC/RISCV/rv64zbr-valid.s

# With B extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip CRC extension: # With Bitmanip CRC extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbr -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbr -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbr < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbr < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbr -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zbr -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: crc32.b t0, t1 # CHECK-ASM-AND-OBJ: crc32.b t0, t1
Show All 23 Lines

llvm/test/MC/RISCV/rv64zbs-aliases-valid.s

  • This file was added.
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbs -riscv-no-aliases \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbs \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbs < %s \
# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbs - \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbs < %s \
# RUN: | llvm-objdump -d -r --mattr=+experimental-zbs - \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
# The following check prefixes are used in this test:
# CHECK-S-OBJ Match both the .s and objdumped object output with
# aliases enabled
# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
# aliases disabled
# CHECK-S-OBJ-NOALIAS: bseti t0, t1, 8
# CHECK-S-OBJ: bseti t0, t1, 8
bset x5, x6, 8
# CHECK-S-OBJ-NOALIAS: bclri t0, t1, 8
# CHECK-S-OBJ: bclri t0, t1, 8
bclr x5, x6, 8
# CHECK-S-OBJ-NOALIAS: binvi t0, t1, 8
# CHECK-S-OBJ: binvi t0, t1, 8
binv x5, x6, 8
# CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
# CHECK-S-OBJ: bexti t0, t1, 8
bext x5, x6, 8

llvm/test/MC/RISCV/rv64zbs-invalid.s

  • This file was deleted.
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbs < %s 2>&1 | FileCheck %s
# Too few operands
bclrw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands
bsetw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands
binvw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands
bextw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands
bclriw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Immediate operand out of range
bclriw t0, t1, 32 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
bclriw t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
# Too few operands
bsetiw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Immediate operand out of range
bsetiw t0, t1, 32 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
bsetiw t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
# Too few operands
binviw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Immediate operand out of range
binviw t0, t1, 32 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
binviw t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]

llvm/test/MC/RISCV/rv64zbs-valid.s

  • This file was deleted.
# With B extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip single bit extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbs -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbs < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbs -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: bclrw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x48]
bclrw t0, t1, t2
# CHECK-ASM-AND-OBJ: bsetw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x28]
bsetw t0, t1, t2
# CHECK-ASM-AND-OBJ: binvw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x68]
binvw t0, t1, t2
# CHECK-ASM-AND-OBJ: bextw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x48]
bextw t0, t1, t2
# CHECK-ASM-AND-OBJ: bclriw t0, t1, 0
# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x48]
bclriw t0, t1, 0
# CHECK-ASM-AND-OBJ: bsetiw t0, t1, 0
# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x28]
bsetiw t0, t1, 0
# CHECK-ASM-AND-OBJ: binviw t0, t1, 0
# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x68]
binviw t0, t1, 0

llvm/test/MC/RISCV/rv64zbt-valid.s

# With B extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip ternary extension: # With Bitmanip ternary extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbt -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbt -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbt < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbt < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbt -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zbt -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: fslw t0, t1, t2, t3 # CHECK-ASM-AND-OBJ: fslw t0, t1, t2, t3
# CHECK-ASM: encoding: [0xbb,0x12,0xc3,0x3d] # CHECK-ASM: encoding: [0xbb,0x12,0xc3,0x3d]
fslw t0, t1, t2, t3 fslw t0, t1, t2, t3
# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3 # CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3
# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d] # CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
fsrw t0, t1, t2, t3 fsrw t0, t1, t2, t3
# CHECK-ASM-AND-OBJ: fsriw t0, t1, t2, 0 # CHECK-ASM-AND-OBJ: fsriw t0, t1, t2, 0
# CHECK-ASM: encoding: [0x9b,0x52,0x03,0x3c] # CHECK-ASM: encoding: [0x9b,0x52,0x03,0x3c]
fsriw t0, t1, t2, 0 fsriw t0, t1, t2, 0

llvm/test/Transforms/LoopIdiom/RISCV/popcnt.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -loop-idiom -mtriple=riscv32 -mattr=+experimental-zbb -S < %s | FileCheck %s --check-prefixes=CPOP ; RUN: opt -loop-idiom -mtriple=riscv32 -mattr=+experimental-zbb -S < %s | FileCheck %s --check-prefixes=CPOP
; RUN: opt -loop-idiom -mtriple=riscv64 -mattr=+experimental-zbb -S < %s | FileCheck %s --check-prefixes=CPOP ; RUN: opt -loop-idiom -mtriple=riscv64 -mattr=+experimental-zbb -S < %s | FileCheck %s --check-prefixes=CPOP
; RUN: opt -loop-idiom -mtriple=riscv32 -mattr=+experimental-b -S < %s | FileCheck %s --check-prefixes=CPOP
; RUN: opt -loop-idiom -mtriple=riscv64 -mattr=+experimental-b -S < %s | FileCheck %s --check-prefixes=CPOP
; RUN: opt -loop-idiom -mtriple=riscv32 -S < %s | FileCheck %s --check-prefixes=NOCPOP ; RUN: opt -loop-idiom -mtriple=riscv32 -S < %s | FileCheck %s --check-prefixes=NOCPOP
; RUN: opt -loop-idiom -mtriple=riscv64 -S < %s | FileCheck %s --check-prefixes=NOCPOP ; RUN: opt -loop-idiom -mtriple=riscv64 -S < %s | FileCheck %s --check-prefixes=NOCPOP
; Mostly copied from AMDGPU version. ; Mostly copied from AMDGPU version.
;To recognize this pattern: ;To recognize this pattern:
;int popcount(unsigned long long a) { ;int popcount(unsigned long long a) {
; int c = 0; ; int c = 0;
▲ Show 20 Lines • Show All 309 Lines • Show Last 20 Lines
llvm/test/MC/RISCV/rv64zbs-aliases-valid.s