[RISCV] Let lowerSELECT merge SETCC into SELECT_CC for floats

[jrtc27]

Summary

We already perform this optimisation later in PerformDAGCombine for both
integers and floats, but try to perform it early for integers during
lowering rather than deferring to optimising combines. Using the
optimised lowering works for floats too so we might as well make the two
have matching behaviours rather than adding an unnecessary condition. We
just need to be careful when checking for selects of two constant
integers.

[craig.topper]

Do we have test coverage for fp selects with integer conditions? The DAG combine was added in https://reviews.llvm.org/D98132 but I don't see any FP related test changes in there. I'm not sure I realized I was changing the behavior of FP selects at the time.

[craig.topper]

I think this patch is obsolete.

[jrtc27]

In D108220#3987294, @craig.topper wrote:

I think this patch is obsolete.

Indeed; d27c147aaa8fea0d3b438ba9e51b497a621ecf1e (and the XLEN check isn't needed since ConstantSDNode is specifically for integers)

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
   if (VT.isVector()) {
     MVT SplatCondVT = VT.changeVectorElementType(MVT::i1);
     SDValue CondSplat = VT.isScalableVector()
                             ? DAG.getSplatVector(SplatCondVT, DL, CondV)
                             : DAG.getSplatBuildVector(SplatCondVT, DL, CondV);
     return DAG.getNode(ISD::VSELECT, DL, VT, CondSplat, TrueV, FalseV);
   }
 
-  // If the result type is XLenVT and CondV is the output of a SETCC node
-  // which also operated on XLenVT inputs, then merge the SETCC node into the
-  // lowered RISCVISD::SELECT_CC to take advantage of the integer
-  // compare+branch instructions. i.e.:
+  // If CondV is the output of a SETCC node which operates on XLenVT
+  // inputs, then merge the SETCC node into the lowered RISCVISD::SELECT_CC to
+  // take advantage of the integer compare+branch instructions. i.e.:
   // (select (setcc lhs, rhs, cc), truev, falsev)
   // -> (riscvisd::select_cc lhs, rhs, cc, truev, falsev)
-  if (VT == XLenVT && CondV.getOpcode() == ISD::SETCC &&
+  if (CondV.getOpcode() == ISD::SETCC &&
       CondV.getOperand(0).getSimpleValueType() == XLenVT) {
     SDValue LHS = CondV.getOperand(0);
     SDValue RHS = CondV.getOperand(1);
     const auto *CC = cast<CondCodeSDNode>(CondV.getOperand(2));
     ISD::CondCode CCVal = CC->get();
 
-    // Special case for a select of 2 constants that have a diffence of 1.
+    // Special case for a select of 2 int constants that have a diffence of 1.
     // Normally this is done by DAGCombine, but if the select is introduced by
     // type legalization or op legalization, we miss it. Restricting to SETLT
     // case for now because that is what signed saturating add/sub need.
     // FIXME: We don't need the condition to be SETLT or even a SETCC,
     // but we would probably want to swap the true/false values if the condition
     // is SETGE/SETLE to avoid an XORI.
     if (isa<ConstantSDNode>(TrueV) && isa<ConstantSDNode>(FalseV) &&
-        CCVal == ISD::SETLT) {
+        CCVal == ISD::SETLT && VT == XLenVT) {
       const APInt &TrueVal = cast<ConstantSDNode>(TrueV)->getAPIntValue();
       const APInt &FalseVal = cast<ConstantSDNode>(FalseV)->getAPIntValue();
       if (TrueVal - 1 == FalseVal)
         return DAG.getNode(ISD::ADD, DL, Op.getValueType(), CondV, FalseV);
       if (TrueVal + 1 == FalseVal)
         return DAG.getNode(ISD::SUB, DL, Op.getValueType(), FalseV, CondV);
     }