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[RISCV] Restrict performANY_EXTENDCombine to prevent an infinite loop.
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Authored by craig.topper on Jul 24 2021, 11:48 AM.

Details

Summary

The sign_extend we insert here can get turned into a zero_extend if
the sign bit is known zero. This can enable a setcc combine that
shrinks compares with zero_extend. This reduces the use count of
the zero_extend allowing other combines to turn it back into an
any_extend.

This restricts the combine to only cases where the result is used
by a CopyToReg. This works for my original motivating case. I
hope the CopyToReg use will prevent any converted extends from
turning back into an any_extend.

Diff Detail

Event Timeline

craig.topper created this revision.Jul 24 2021, 11:48 AM
craig.topper requested review of this revision.Jul 24 2021, 11:48 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 24 2021, 11:48 AM
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I can confirm that an ARCH=riscv allmodconfig Linux kernel can now successfully build.

frasercrmck added inline comments.Jul 26 2021, 4:01 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
5820

I'd probably suggest

if (!any_of(N->uses(),
            [](SDNode *User) { return User->getOpcode() == ISD::CopyToReg; }))
  return SDValue();

which I believe is equivalent.

luismarques accepted this revision.Jul 28 2021, 2:03 AM

I don't really know if this is the appropriate solution or not for the long term. It at least sounds reasonable for now.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp
5817

Nit: grammar. Missing period?

This revision is now accepted and ready to land.Jul 28 2021, 2:03 AM
This revision was landed with ongoing or failed builds.Jul 28 2021, 9:06 AM
This revision was automatically updated to reflect the committed changes.

Can this be cherry-picked to release/13.x?

Can this be cherry-picked to release/13.x?

Filed in bugzilla here https://bugs.llvm.org/show_bug.cgi?id=51206