[RISCV] Add support for BSWAP and BITREVERSE for RVP

[Jim]

Summary

Use swap8, swap16 and pkbt32 to swap bytes for XLenVT and
customized lower BITREVERSE to bitrevi.

[jrtc27]

llvm/test/CodeGen/RISCV/rvp/bswap.ll

21–24

This is not a code size win. This has also introduced more instruction dependencies; previously 1 and 2 were independent, as were 1 and 3, but now every instruction is dependent on the previous, forming a slow chain that will hurt out-of-order cores, or simple in-order cores that can't execute back-to-back P instructions with forwarding.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoP.td

1266

What if Zbb is enabled. Who gets priority?

llvm/test/CodeGen/RISCV/rvp/bswap.ll

21–24

You probably want to catch i8/i16 on RV32/RV64 and i32 on RV64 in ReplaceNodeResults and map them to the minimum swap instruction you need before they get promoted.

[Jim]

Merge https://reviews.llvm.org/D103691 into this patch.
Add the codegen of RVB for testcases.

[Jim]

clang-foramt

[Jim]

format td file.

[Jim]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4925

catch i8/i16 on RV32/RV64 and i32 on RV64

6190

I have the concern about correctness here.

llvm/lib/Target/RISCV/RISCVInstrInfoP.td

1266

Zbb would be first. Zbb only emit one grev instructions. That is better I think.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Subtarget.is64Bit()) {
       addTypeForP(MVT::v8i8, MVT::i64);
       addTypeForP(MVT::v4i16, MVT::i64);
       addTypeForP(MVT::v2i32, MVT::i64);
     } else {
       addTypeForP(MVT::v4i8, MVT::i32);
       addTypeForP(MVT::v2i16, MVT::i32);
     }
 
+    setOperationAction(ISD::BSWAP, XLenVT, Legal);
+
     // Expand all truncating stores and extending loads.
     for (MVT VT0 : MVT::vector_valuetypes()) {
       for (MVT VT1 : MVT::vector_valuetypes()) {
         setTruncStoreAction(VT0, VT1, Expand);
         setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand);
         setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand);
         setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand);
       }
assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
            Subtarget.hasStdExtZbp() && "Unexpected custom legalisation");
     SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64,
                                  N->getOperand(0));
     unsigned Imm = N->getOpcode() == ISD::BITREVERSE ? 31 : 24;
     SDValue GREVIW = DAG.getNode(RISCVISD::GREVW, DL, MVT::i64, NewOp0,
                                  DAG.getConstant(Imm, DL, MVT::i64));
     // ReplaceNodeResults requires we maintain the same type for the return
     // value.
     Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, GREVIW));
     break;
   }
   case ISD::FSHL:
   case ISD::FSHR: {
     assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
            Subtarget.hasStdExtZbt() && "Unexpected custom legalisation");
     SDValue NewOp0 =
         DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0));
void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
   }
   case RISCVISD::READ_VLENB:
     // We assume VLENB is at least 16 bytes.
     Known.Zero.setLowBits(4);
     break;
   case ISD::INTRINSIC_W_CHAIN: {
     unsigned IntNo = Op.getConstantOperandVal(1);
     switch (IntNo) {
     default:
       // We can't do anything for most intrinsics.
       break;
     case Intrinsic::riscv_vsetvli:
     case Intrinsic::riscv_vsetvlimax:
       // Assume that VL output is positive and would fit in an int32_t.
       // TODO: VLEN might be capped at 16 bits in a future V spec update.
       if (BitWidth >= 32)
         Known.Zero.setBitsFrom(31);

llvm/lib/Target/RISCV/RISCVInstrInfoP.td

 
 let Predicates = [HasStdExtZpn, IsRV64] in {
 def : PatALU32<add, ADD32>;
 def : PatALU32<sub, SUB32>;
 def : PatALU32<and, AND>;
 def : PatALU32<or, OR>;
 def : PatALU32<xor, XOR>;
 } // [HasStdExtZpn, IsRV64]
+
+// bswap
+let Predicates = [HasStdExtZpn] in
+def : Pat<(bswap i32:$rs1), (SWAP16 (SWAP8 GPR:$rs1))>;
+let Predicates = [HasStdExtZpn, IsRV64] in
+def : Pat<(bswap i64:$rs1), (PKBT32 (SWAP16 (SWAP8 GPR:$rs1)),
+                                    (SWAP16 (SWAP8 GPR:$rs1)))>;

llvm/test/CodeGen/RISCV/rvp/bswap.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-p -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s --check-prefixes=RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s --check-prefixes=RV64
 
 declare i16 @llvm.bswap.i16(i16)
 declare i32 @llvm.bswap.i32(i32)
 declare i64 @llvm.bswap.i64(i64)
 
 define i16 @bswap16(i16 %x) nounwind {
 ; RV32-LABEL: bswap16:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    slli a1, a0, 8
-; RV32-NEXT:    slli a0, a0, 16
-; RV32-NEXT:    srli a0, a0, 24
-; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    swap8 a0, a0
+; RV32-NEXT:    swap16 a0, a0
+; RV32-NEXT:    srli a0, a0, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bswap16:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    slli a1, a0, 8
-; RV64-NEXT:    slli a0, a0, 48
-; RV64-NEXT:    srli a0, a0, 56
-; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    swap8 a0, a0
+; RV64-NEXT:    swap16 a0, a0
+; RV64-NEXT:    pkbt32 a0, a0, a0
+; RV64-NEXT:    srli a0, a0, 48
 ; RV64-NEXT:    ret
   %ret = call i16 @llvm.bswap.i16(i16 %x)
   ret i16 %ret
 }
 
 define i32 @bswap32(i32 %x) nounwind {
 ; RV32-LABEL: bswap32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    srli a1, a0, 8
-; RV32-NEXT:    lui a2, 16
-; RV32-NEXT:    addi a2, a2, -256
-; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:    srli a2, a0, 24
-; RV32-NEXT:    or a1, a1, a2
-; RV32-NEXT:    slli a2, a0, 8
-; RV32-NEXT:    lui a3, 4080
-; RV32-NEXT:    and a2, a2, a3
-; RV32-NEXT:    slli a0, a0, 24
-; RV32-NEXT:    or a0, a0, a2
-; RV32-NEXT:    or a0, a0, a1
+; RV32-NEXT:    swap8 a0, a0
+; RV32-NEXT:    swap16 a0, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bswap32:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    srliw a1, a0, 8
-; RV64-NEXT:    lui a2, 16
-; RV64-NEXT:    addiw a2, a2, -256
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    srliw a2, a0, 24
-; RV64-NEXT:    or a1, a1, a2
-; RV64-NEXT:    slli a2, a0, 8
-; RV64-NEXT:    lui a3, 4080
-; RV64-NEXT:    and a2, a2, a3
-; RV64-NEXT:    slli a0, a0, 24
-; RV64-NEXT:    or a0, a0, a2
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    swap8 a0, a0
+; RV64-NEXT:    swap16 a0, a0
+; RV64-NEXT:    pkbt32 a0, a0, a0
+; RV64-NEXT:    srli a0, a0, 32
 ; RV64-NEXT:    ret
   %ret = call i32 @llvm.bswap.i32(i32 %x)
   ret i32 %ret
 }
 
 define i64 @bswap64(i64 %x) nounwind {
 ; RV32-LABEL: bswap64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    srli a2, a1, 8
-; RV32-NEXT:    lui a3, 16
-; RV32-NEXT:    addi a3, a3, -256
-; RV32-NEXT:    and a2, a2, a3
-; RV32-NEXT:    srli a4, a1, 24
-; RV32-NEXT:    or a2, a2, a4
-; RV32-NEXT:    slli a4, a1, 8
-; RV32-NEXT:    lui a5, 4080
-; RV32-NEXT:    and a4, a4, a5
-; RV32-NEXT:    slli a1, a1, 24
-; RV32-NEXT:    or a1, a1, a4
-; RV32-NEXT:    or a2, a1, a2
-; RV32-NEXT:    srli a1, a0, 8
-; RV32-NEXT:    and a1, a1, a3
-; RV32-NEXT:    srli a3, a0, 24
-; RV32-NEXT:    or a1, a1, a3
-; RV32-NEXT:    slli a3, a0, 8
-; RV32-NEXT:    and a3, a3, a5
-; RV32-NEXT:    slli a0, a0, 24
-; RV32-NEXT:    or a0, a0, a3
-; RV32-NEXT:    or a1, a0, a1
+; RV32-NEXT:    swap8 a1, a1
+; RV32-NEXT:    swap16 a2, a1
+; RV32-NEXT:    swap8 a0, a0
+; RV32-NEXT:    swap16 a1, a0
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bswap64:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    srli a1, a0, 24
-; RV64-NEXT:    lui a2, 4080
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    srli a2, a0, 8
-; RV64-NEXT:    addi a3, zero, 255
-; RV64-NEXT:    slli a4, a3, 24
-; RV64-NEXT:    and a2, a2, a4
-; RV64-NEXT:    or a1, a2, a1
-; RV64-NEXT:    srli a2, a0, 40
-; RV64-NEXT:    lui a4, 16
-; RV64-NEXT:    addiw a4, a4, -256
-; RV64-NEXT:    and a2, a2, a4
-; RV64-NEXT:    srli a4, a0, 56
-; RV64-NEXT:    or a2, a2, a4
-; RV64-NEXT:    or a1, a1, a2
-; RV64-NEXT:    slli a2, a0, 8
-; RV64-NEXT:    slli a4, a3, 32
-; RV64-NEXT:    and a2, a2, a4
-; RV64-NEXT:    slli a4, a0, 24
-; RV64-NEXT:    slli a5, a3, 40
-; RV64-NEXT:    and a4, a4, a5
-; RV64-NEXT:    or a2, a4, a2
-; RV64-NEXT:    slli a4, a0, 40
-; RV64-NEXT:    slli a3, a3, 48
-; RV64-NEXT:    and a3, a4, a3
-; RV64-NEXT:    slli a0, a0, 56
-; RV64-NEXT:    or a0, a0, a3
-; RV64-NEXT:    or a0, a0, a2
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    swap8 a0, a0
+; RV64-NEXT:    swap16 a0, a0
+; RV64-NEXT:    pkbt32 a0, a0, a0
 ; RV64-NEXT:    ret
   %ret = call i64 @llvm.bswap.i64(i64 %x)
   ret i64 %ret
 }