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Differential D103687

[RISCV] Pre-commit test for D102467
Needs ReviewPublic

Authored by Jim on Jun 4 2021, 5:00 AM.
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Diff Detail

Unit TestsFailed

TimeTest
200 msx64 debian > LLVM.CodeGen/RISCV::rv32zpn-alu.ll
240 msx64 debian > LLVM.CodeGen/RISCV::rv64zpn-alu.ll
190 msx64 windows > LLVM.CodeGen/RISCV::rv32zpn-alu.ll
180 msx64 windows > LLVM.CodeGen/RISCV::rv64zpn-alu.ll

Event Timeline

Jim created this revision.Jun 4 2021, 5:00 AM
Herald added subscribers: vkmr, frasercrmck, evandro and 23 others. · View Herald TranscriptJun 4 2021, 5:00 AM
Jim requested review of this revision.Jun 4 2021, 5:00 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 4 2021, 5:00 AM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
Jim added a child revision: D102467: [RISCV] Implement codegen patterns for RVP ALU operations.Jun 4 2021, 5:04 AM
Harbormaster completed remote builds in B107650: Diff 349824.Jun 4 2021, 5:33 AM
Jim updated this revision to Diff 350220.Jun 7 2021, 3:05 AM

Add tests for logic operations with immediate.

Harbormaster completed remote builds in B107940: Diff 350220.Jun 7 2021, 4:05 AM
Jim updated this revision to Diff 352114.Jun 15 2021, 6:23 AM

Move tests out of rvp directory.

Harbormaster completed remote builds in B109274: Diff 352114.Jun 15 2021, 6:56 AM

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
2269 lines
2493 lines

Diff 352114

llvm/test/CodeGen/RISCV/rv32zpn-alu.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-p -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IP
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zpn -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IPN
define i32 @addv4i8(i32 %a, i32 %b) nounwind {
; RV32IP-LABEL: addv4i8:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a1, 8(sp)
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lb a0, 11(sp)
; RV32IP-NEXT: lb a1, 7(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lb a0, 10(sp)
; RV32IP-NEXT: lb a1, 6(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lb a0, 9(sp)
; RV32IP-NEXT: lb a1, 5(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lb a0, 8(sp)
; RV32IP-NEXT: lb a1, 4(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: addv4i8:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a1, 8(sp)
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lb a0, 11(sp)
; RV32IPN-NEXT: lb a1, 7(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lb a0, 10(sp)
; RV32IPN-NEXT: lb a1, 6(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lb a0, 9(sp)
; RV32IPN-NEXT: lb a1, 5(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lb a0, 8(sp)
; RV32IPN-NEXT: lb a1, 4(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <4 x i8>
%tmp2 = bitcast i32 %b to <4 x i8>
%add = add <4 x i8> %tmp1, %tmp2
%res = bitcast <4 x i8> %add to i32
ret i32 %res
}
define i32 @addv2i16(i32 %a, i32 %b) nounwind {
; RV32IP-LABEL: addv2i16:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a1, 8(sp)
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lh a0, 10(sp)
; RV32IP-NEXT: lh a1, 6(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sh a0, 14(sp)
; RV32IP-NEXT: lh a0, 8(sp)
; RV32IP-NEXT: lh a1, 4(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: addv2i16:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a1, 8(sp)
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lh a0, 10(sp)
; RV32IPN-NEXT: lh a1, 6(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sh a0, 14(sp)
; RV32IPN-NEXT: lh a0, 8(sp)
; RV32IPN-NEXT: lh a1, 4(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <2 x i16>
%tmp2 = bitcast i32 %b to <2 x i16>
%add = add <2 x i16> %tmp1, %tmp2
%res = bitcast <2 x i16> %add to i32
ret i32 %res
}
define i64 @addv8i8(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: addv8i8:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -32
; RV32IP-NEXT: sw a2, 16(sp)
; RV32IP-NEXT: sw a0, 8(sp)
; RV32IP-NEXT: sw a3, 20(sp)
; RV32IP-NEXT: sw a1, 12(sp)
; RV32IP-NEXT: lb a0, 19(sp)
; RV32IP-NEXT: lb a1, 11(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 27(sp)
; RV32IP-NEXT: lb a0, 18(sp)
; RV32IP-NEXT: lb a1, 10(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 26(sp)
; RV32IP-NEXT: lb a0, 17(sp)
; RV32IP-NEXT: lb a1, 9(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 25(sp)
; RV32IP-NEXT: lb a0, 16(sp)
; RV32IP-NEXT: lb a1, 8(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 24(sp)
; RV32IP-NEXT: lb a0, 23(sp)
; RV32IP-NEXT: lb a1, 15(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 31(sp)
; RV32IP-NEXT: lb a0, 22(sp)
; RV32IP-NEXT: lb a1, 14(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 30(sp)
; RV32IP-NEXT: lb a0, 21(sp)
; RV32IP-NEXT: lb a1, 13(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 29(sp)
; RV32IP-NEXT: lb a0, 20(sp)
; RV32IP-NEXT: lb a1, 12(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 28(sp)
; RV32IP-NEXT: lw a0, 24(sp)
; RV32IP-NEXT: lw a1, 28(sp)
; RV32IP-NEXT: addi sp, sp, 32
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: addv8i8:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -32
; RV32IPN-NEXT: sw a2, 16(sp)
; RV32IPN-NEXT: sw a0, 8(sp)
; RV32IPN-NEXT: sw a3, 20(sp)
; RV32IPN-NEXT: sw a1, 12(sp)
; RV32IPN-NEXT: lb a0, 19(sp)
; RV32IPN-NEXT: lb a1, 11(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 27(sp)
; RV32IPN-NEXT: lb a0, 18(sp)
; RV32IPN-NEXT: lb a1, 10(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 26(sp)
; RV32IPN-NEXT: lb a0, 17(sp)
; RV32IPN-NEXT: lb a1, 9(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 25(sp)
; RV32IPN-NEXT: lb a0, 16(sp)
; RV32IPN-NEXT: lb a1, 8(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 24(sp)
; RV32IPN-NEXT: lb a0, 23(sp)
; RV32IPN-NEXT: lb a1, 15(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 31(sp)
; RV32IPN-NEXT: lb a0, 22(sp)
; RV32IPN-NEXT: lb a1, 14(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 30(sp)
; RV32IPN-NEXT: lb a0, 21(sp)
; RV32IPN-NEXT: lb a1, 13(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 29(sp)
; RV32IPN-NEXT: lb a0, 20(sp)
; RV32IPN-NEXT: lb a1, 12(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 28(sp)
; RV32IPN-NEXT: lw a0, 24(sp)
; RV32IPN-NEXT: lw a1, 28(sp)
; RV32IPN-NEXT: addi sp, sp, 32
; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <8 x i8>
%tmp2 = bitcast i64 %b to <8 x i8>
%add = add <8 x i8> %tmp1, %tmp2
%res = bitcast <8 x i8> %add to i64
ret i64 %res
}
define i64 @addv4i16(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: addv4i16:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -32
; RV32IP-NEXT: sw a2, 16(sp)
; RV32IP-NEXT: sw a0, 8(sp)
; RV32IP-NEXT: sw a3, 20(sp)
; RV32IP-NEXT: sw a1, 12(sp)
; RV32IP-NEXT: lh a0, 18(sp)
; RV32IP-NEXT: lh a1, 10(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sh a0, 26(sp)
; RV32IP-NEXT: lh a0, 16(sp)
; RV32IP-NEXT: lh a1, 8(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sh a0, 24(sp)
; RV32IP-NEXT: lh a0, 22(sp)
; RV32IP-NEXT: lh a1, 14(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sh a0, 30(sp)
; RV32IP-NEXT: lh a0, 20(sp)
; RV32IP-NEXT: lh a1, 12(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sh a0, 28(sp)
; RV32IP-NEXT: lw a0, 24(sp)
; RV32IP-NEXT: lw a1, 28(sp)
; RV32IP-NEXT: addi sp, sp, 32
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: addv4i16:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -32
; RV32IPN-NEXT: sw a2, 16(sp)
; RV32IPN-NEXT: sw a0, 8(sp)
; RV32IPN-NEXT: sw a3, 20(sp)
; RV32IPN-NEXT: sw a1, 12(sp)
; RV32IPN-NEXT: lh a0, 18(sp)
; RV32IPN-NEXT: lh a1, 10(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sh a0, 26(sp)
; RV32IPN-NEXT: lh a0, 16(sp)
; RV32IPN-NEXT: lh a1, 8(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sh a0, 24(sp)
; RV32IPN-NEXT: lh a0, 22(sp)
; RV32IPN-NEXT: lh a1, 14(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sh a0, 30(sp)
; RV32IPN-NEXT: lh a0, 20(sp)
; RV32IPN-NEXT: lh a1, 12(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sh a0, 28(sp)
; RV32IPN-NEXT: lw a0, 24(sp)
; RV32IPN-NEXT: lw a1, 28(sp)
; RV32IPN-NEXT: addi sp, sp, 32
; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <4 x i16>
%tmp2 = bitcast i64 %b to <4 x i16>
%add = add <4 x i16> %tmp1, %tmp2
%res = bitcast <4 x i16> %add to i64
ret i64 %res
}
define i64 @addv2i32(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: addv2i32:
; RV32IP: # %bb.0:
; RV32IP-NEXT: add a0, a0, a2
; RV32IP-NEXT: add a1, a1, a3
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: addv2i32:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: add a0, a0, a2
; RV32IPN-NEXT: add a1, a1, a3
; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <2 x i32>
%tmp2 = bitcast i64 %b to <2 x i32>
%add = add <2 x i32> %tmp1, %tmp2
%res = bitcast <2 x i32> %add to i64
ret i64 %res
}
define i32 @subv4i8(i32 %a, i32 %b) nounwind {
; RV32IP-LABEL: subv4i8:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a1, 8(sp)
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lb a0, 11(sp)
; RV32IP-NEXT: lb a1, 7(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lb a0, 10(sp)
; RV32IP-NEXT: lb a1, 6(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lb a0, 9(sp)
; RV32IP-NEXT: lb a1, 5(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lb a0, 8(sp)
; RV32IP-NEXT: lb a1, 4(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: subv4i8:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a1, 8(sp)
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lb a0, 11(sp)
; RV32IPN-NEXT: lb a1, 7(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lb a0, 10(sp)
; RV32IPN-NEXT: lb a1, 6(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lb a0, 9(sp)
; RV32IPN-NEXT: lb a1, 5(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lb a0, 8(sp)
; RV32IPN-NEXT: lb a1, 4(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <4 x i8>
%tmp2 = bitcast i32 %b to <4 x i8>
%sub = sub <4 x i8> %tmp1, %tmp2
%res = bitcast <4 x i8> %sub to i32
ret i32 %res
}
define i32 @subv2i16(i32 %a, i32 %b) nounwind {
; RV32IP-LABEL: subv2i16:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a1, 8(sp)
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lh a0, 10(sp)
; RV32IP-NEXT: lh a1, 6(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sh a0, 14(sp)
; RV32IP-NEXT: lh a0, 8(sp)
; RV32IP-NEXT: lh a1, 4(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: subv2i16:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a1, 8(sp)
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lh a0, 10(sp)
; RV32IPN-NEXT: lh a1, 6(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sh a0, 14(sp)
; RV32IPN-NEXT: lh a0, 8(sp)
; RV32IPN-NEXT: lh a1, 4(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <2 x i16>
%tmp2 = bitcast i32 %b to <2 x i16>
%sub = sub <2 x i16> %tmp1, %tmp2
%res = bitcast <2 x i16> %sub to i32
ret i32 %res
}
define i64 @subv8i8(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: subv8i8:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -32
; RV32IP-NEXT: sw a2, 16(sp)
; RV32IP-NEXT: sw a0, 8(sp)
; RV32IP-NEXT: sw a3, 20(sp)
; RV32IP-NEXT: sw a1, 12(sp)
; RV32IP-NEXT: lb a0, 19(sp)
; RV32IP-NEXT: lb a1, 11(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 27(sp)
; RV32IP-NEXT: lb a0, 18(sp)
; RV32IP-NEXT: lb a1, 10(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 26(sp)
; RV32IP-NEXT: lb a0, 17(sp)
; RV32IP-NEXT: lb a1, 9(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 25(sp)
; RV32IP-NEXT: lb a0, 16(sp)
; RV32IP-NEXT: lb a1, 8(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 24(sp)
; RV32IP-NEXT: lb a0, 23(sp)
; RV32IP-NEXT: lb a1, 15(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 31(sp)
; RV32IP-NEXT: lb a0, 22(sp)
; RV32IP-NEXT: lb a1, 14(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 30(sp)
; RV32IP-NEXT: lb a0, 21(sp)
; RV32IP-NEXT: lb a1, 13(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 29(sp)
; RV32IP-NEXT: lb a0, 20(sp)
; RV32IP-NEXT: lb a1, 12(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 28(sp)
; RV32IP-NEXT: lw a0, 24(sp)
; RV32IP-NEXT: lw a1, 28(sp)
; RV32IP-NEXT: addi sp, sp, 32
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: subv8i8:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -32
; RV32IPN-NEXT: sw a2, 16(sp)
; RV32IPN-NEXT: sw a0, 8(sp)
; RV32IPN-NEXT: sw a3, 20(sp)
; RV32IPN-NEXT: sw a1, 12(sp)
; RV32IPN-NEXT: lb a0, 19(sp)
; RV32IPN-NEXT: lb a1, 11(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 27(sp)
; RV32IPN-NEXT: lb a0, 18(sp)
; RV32IPN-NEXT: lb a1, 10(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 26(sp)
; RV32IPN-NEXT: lb a0, 17(sp)
; RV32IPN-NEXT: lb a1, 9(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 25(sp)
; RV32IPN-NEXT: lb a0, 16(sp)
; RV32IPN-NEXT: lb a1, 8(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 24(sp)
; RV32IPN-NEXT: lb a0, 23(sp)
; RV32IPN-NEXT: lb a1, 15(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 31(sp)
; RV32IPN-NEXT: lb a0, 22(sp)
; RV32IPN-NEXT: lb a1, 14(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 30(sp)
; RV32IPN-NEXT: lb a0, 21(sp)
; RV32IPN-NEXT: lb a1, 13(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 29(sp)
; RV32IPN-NEXT: lb a0, 20(sp)
; RV32IPN-NEXT: lb a1, 12(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 28(sp)
; RV32IPN-NEXT: lw a0, 24(sp)
; RV32IPN-NEXT: lw a1, 28(sp)
; RV32IPN-NEXT: addi sp, sp, 32
; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <8 x i8>
%tmp2 = bitcast i64 %b to <8 x i8>
%sub = sub <8 x i8> %tmp1, %tmp2
%res = bitcast <8 x i8> %sub to i64
ret i64 %res
}
define i64 @subv4i16(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: subv4i16:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -32
; RV32IP-NEXT: sw a2, 16(sp)
; RV32IP-NEXT: sw a0, 8(sp)
; RV32IP-NEXT: sw a3, 20(sp)
; RV32IP-NEXT: sw a1, 12(sp)
; RV32IP-NEXT: lh a0, 18(sp)
; RV32IP-NEXT: lh a1, 10(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sh a0, 26(sp)
; RV32IP-NEXT: lh a0, 16(sp)
; RV32IP-NEXT: lh a1, 8(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sh a0, 24(sp)
; RV32IP-NEXT: lh a0, 22(sp)
; RV32IP-NEXT: lh a1, 14(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sh a0, 30(sp)
; RV32IP-NEXT: lh a0, 20(sp)
; RV32IP-NEXT: lh a1, 12(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sh a0, 28(sp)
; RV32IP-NEXT: lw a0, 24(sp)
; RV32IP-NEXT: lw a1, 28(sp)
; RV32IP-NEXT: addi sp, sp, 32
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: subv4i16:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -32
; RV32IPN-NEXT: sw a2, 16(sp)
; RV32IPN-NEXT: sw a0, 8(sp)
; RV32IPN-NEXT: sw a3, 20(sp)
; RV32IPN-NEXT: sw a1, 12(sp)
; RV32IPN-NEXT: lh a0, 18(sp)
; RV32IPN-NEXT: lh a1, 10(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sh a0, 26(sp)
; RV32IPN-NEXT: lh a0, 16(sp)
; RV32IPN-NEXT: lh a1, 8(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sh a0, 24(sp)
; RV32IPN-NEXT: lh a0, 22(sp)
; RV32IPN-NEXT: lh a1, 14(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sh a0, 30(sp)
; RV32IPN-NEXT: lh a0, 20(sp)
; RV32IPN-NEXT: lh a1, 12(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sh a0, 28(sp)
; RV32IPN-NEXT: lw a0, 24(sp)
; RV32IPN-NEXT: lw a1, 28(sp)
; RV32IPN-NEXT: addi sp, sp, 32
; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <4 x i16>
%tmp2 = bitcast i64 %b to <4 x i16>
%sub = sub <4 x i16> %tmp1, %tmp2
%res = bitcast <4 x i16> %sub to i64
ret i64 %res
}
define i64 @subv2i32(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: subv2i32:
; RV32IP: # %bb.0:
; RV32IP-NEXT: sub a0, a0, a2
; RV32IP-NEXT: sub a1, a1, a3
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: subv2i32:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: sub a0, a0, a2
; RV32IPN-NEXT: sub a1, a1, a3
; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <2 x i32>
%tmp2 = bitcast i64 %b to <2 x i32>
%add = sub <2 x i32> %tmp1, %tmp2
%res = bitcast <2 x i32> %add to i64
ret i64 %res
}
define i32 @andv4i8(i32 %a) nounwind {
; RV32IP-LABEL: andv4i8:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a0, 8(sp)
; RV32IP-NEXT: lbu a0, 11(sp)
; RV32IP-NEXT: andi a0, a0, 4
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lbu a0, 10(sp)
; RV32IP-NEXT: andi a0, a0, 3
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lbu a0, 9(sp)
; RV32IP-NEXT: andi a0, a0, 2
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lbu a0, 8(sp)
; RV32IP-NEXT: andi a0, a0, 1
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: andv4i8:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a0, 8(sp)
; RV32IPN-NEXT: lbu a0, 11(sp)
; RV32IPN-NEXT: andi a0, a0, 4
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lbu a0, 10(sp)
; RV32IPN-NEXT: andi a0, a0, 3
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lbu a0, 9(sp)
; RV32IPN-NEXT: andi a0, a0, 2
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lbu a0, 8(sp)
; RV32IPN-NEXT: andi a0, a0, 1
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp = bitcast i32 %a to <4 x i8>
%and = and <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4>
%res = bitcast <4 x i8> %and to i32
ret i32 %res
}
define i32 @andv2i16(i32 %a) nounwind {
; RV32IP-LABEL: andv2i16:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a0, 8(sp)
; RV32IP-NEXT: lhu a0, 10(sp)
; RV32IP-NEXT: andi a0, a0, 2
; RV32IP-NEXT: sh a0, 14(sp)
; RV32IP-NEXT: lhu a0, 8(sp)
; RV32IP-NEXT: andi a0, a0, 1
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: andv2i16:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a0, 8(sp)
; RV32IPN-NEXT: lhu a0, 10(sp)
; RV32IPN-NEXT: andi a0, a0, 2
; RV32IPN-NEXT: sh a0, 14(sp)
; RV32IPN-NEXT: lhu a0, 8(sp)
; RV32IPN-NEXT: andi a0, a0, 1
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp = bitcast i32 %a to <2 x i16>
%and = and <2 x i16> %tmp, <i16 1, i16 2>
%res = bitcast <2 x i16> %and to i32
ret i32 %res
}
define i64 @andv8i8(i64 %a) nounwind {
; RV32IP-LABEL: andv8i8:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a0, 0(sp)
; RV32IP-NEXT: sw a1, 4(sp)
; RV32IP-NEXT: lbu a0, 3(sp)
; RV32IP-NEXT: andi a0, a0, 4
; RV32IP-NEXT: sb a0, 11(sp)
; RV32IP-NEXT: lbu a0, 2(sp)
; RV32IP-NEXT: andi a0, a0, 3
; RV32IP-NEXT: sb a0, 10(sp)
; RV32IP-NEXT: lbu a0, 1(sp)
; RV32IP-NEXT: andi a0, a0, 2
; RV32IP-NEXT: sb a0, 9(sp)
; RV32IP-NEXT: lbu a0, 0(sp)
; RV32IP-NEXT: andi a0, a0, 1
; RV32IP-NEXT: sb a0, 8(sp)
; RV32IP-NEXT: lbu a0, 7(sp)
; RV32IP-NEXT: andi a0, a0, 8
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lbu a0, 6(sp)
; RV32IP-NEXT: andi a0, a0, 7
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lbu a0, 5(sp)
; RV32IP-NEXT: andi a0, a0, 6
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lbu a0, 4(sp)
; RV32IP-NEXT: andi a0, a0, 5
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 8(sp)
; RV32IP-NEXT: lw a1, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: andv8i8:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a0, 0(sp)
; RV32IPN-NEXT: sw a1, 4(sp)
; RV32IPN-NEXT: lbu a0, 3(sp)
; RV32IPN-NEXT: andi a0, a0, 4
; RV32IPN-NEXT: sb a0, 11(sp)
; RV32IPN-NEXT: lbu a0, 2(sp)
; RV32IPN-NEXT: andi a0, a0, 3
; RV32IPN-NEXT: sb a0, 10(sp)
; RV32IPN-NEXT: lbu a0, 1(sp)
; RV32IPN-NEXT: andi a0, a0, 2
; RV32IPN-NEXT: sb a0, 9(sp)
; RV32IPN-NEXT: lbu a0, 0(sp)
; RV32IPN-NEXT: andi a0, a0, 1
; RV32IPN-NEXT: sb a0, 8(sp)
; RV32IPN-NEXT: lbu a0, 7(sp)
; RV32IPN-NEXT: andi a0, a0, 8
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lbu a0, 6(sp)
; RV32IPN-NEXT: andi a0, a0, 7
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lbu a0, 5(sp)
; RV32IPN-NEXT: andi a0, a0, 6
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lbu a0, 4(sp)
; RV32IPN-NEXT: andi a0, a0, 5
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 8(sp)
; RV32IPN-NEXT: lw a1, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp = bitcast i64 %a to <8 x i8>
%and = and <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
%res = bitcast <8 x i8> %and to i64
ret i64 %res
}
define i64 @andv4i16(i64 %a) nounwind {
; RV32IP-LABEL: andv4i16:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a0, 0(sp)
; RV32IP-NEXT: sw a1, 4(sp)
; RV32IP-NEXT: lhu a0, 2(sp)
; RV32IP-NEXT: andi a0, a0, 2
; RV32IP-NEXT: sh a0, 10(sp)
; RV32IP-NEXT: lhu a0, 0(sp)
; RV32IP-NEXT: andi a0, a0, 1
; RV32IP-NEXT: sh a0, 8(sp)
; RV32IP-NEXT: lhu a0, 6(sp)
; RV32IP-NEXT: andi a0, a0, 4
; RV32IP-NEXT: sh a0, 14(sp)
; RV32IP-NEXT: lhu a0, 4(sp)
; RV32IP-NEXT: andi a0, a0, 3
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 8(sp)
; RV32IP-NEXT: lw a1, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: andv4i16:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a0, 0(sp)
; RV32IPN-NEXT: sw a1, 4(sp)
; RV32IPN-NEXT: lhu a0, 2(sp)
; RV32IPN-NEXT: andi a0, a0, 2
; RV32IPN-NEXT: sh a0, 10(sp)
; RV32IPN-NEXT: lhu a0, 0(sp)
; RV32IPN-NEXT: andi a0, a0, 1
; RV32IPN-NEXT: sh a0, 8(sp)
; RV32IPN-NEXT: lhu a0, 6(sp)
; RV32IPN-NEXT: andi a0, a0, 4
; RV32IPN-NEXT: sh a0, 14(sp)
; RV32IPN-NEXT: lhu a0, 4(sp)
; RV32IPN-NEXT: andi a0, a0, 3
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 8(sp)
; RV32IPN-NEXT: lw a1, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp = bitcast i64 %a to <4 x i16>
%and = and <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4>
%res = bitcast <4 x i16> %and to i64
ret i64 %res
}
define i64 @andv2i32(i64 %a) nounwind {
; RV32IP-LABEL: andv2i32:
; RV32IP: # %bb.0:
; RV32IP-NEXT: andi a0, a0, 1
; RV32IP-NEXT: andi a1, a1, 2
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: andv2i32:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: andi a0, a0, 1
; RV32IPN-NEXT: andi a1, a1, 2
; RV32IPN-NEXT: ret
%tmp = bitcast i64 %a to <2 x i32>
%and = and <2 x i32> %tmp, <i32 1, i32 2>
%res = bitcast <2 x i32> %and to i64
ret i64 %res
}
define i32 @orv4i8(i32 %a) nounwind {
; RV32IP-LABEL: orv4i8:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a0, 8(sp)
; RV32IP-NEXT: lb a0, 11(sp)
; RV32IP-NEXT: ori a0, a0, 4
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lb a0, 10(sp)
; RV32IP-NEXT: ori a0, a0, 3
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lb a0, 9(sp)
; RV32IP-NEXT: ori a0, a0, 2
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lb a0, 8(sp)
; RV32IP-NEXT: ori a0, a0, 1
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: orv4i8:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a0, 8(sp)
; RV32IPN-NEXT: lb a0, 11(sp)
; RV32IPN-NEXT: ori a0, a0, 4
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lb a0, 10(sp)
; RV32IPN-NEXT: ori a0, a0, 3
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lb a0, 9(sp)
; RV32IPN-NEXT: ori a0, a0, 2
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lb a0, 8(sp)
; RV32IPN-NEXT: ori a0, a0, 1
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp = bitcast i32 %a to <4 x i8>
%or = or <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4>
%res = bitcast <4 x i8> %or to i32
ret i32 %res
}
define i32 @orv2i16(i32 %a) nounwind {
; RV32IP-LABEL: orv2i16:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a0, 8(sp)
; RV32IP-NEXT: lh a0, 10(sp)
; RV32IP-NEXT: ori a0, a0, 2
; RV32IP-NEXT: sh a0, 14(sp)
; RV32IP-NEXT: lh a0, 8(sp)
; RV32IP-NEXT: ori a0, a0, 1
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: orv2i16:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a0, 8(sp)
; RV32IPN-NEXT: lh a0, 10(sp)
; RV32IPN-NEXT: ori a0, a0, 2
; RV32IPN-NEXT: sh a0, 14(sp)
; RV32IPN-NEXT: lh a0, 8(sp)
; RV32IPN-NEXT: ori a0, a0, 1
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp = bitcast i32 %a to <2 x i16>
%or = or <2 x i16> %tmp, <i16 1, i16 2>
%res = bitcast <2 x i16> %or to i32
ret i32 %res
}
define i64 @orv8i8(i64 %a) nounwind {
; RV32IP-LABEL: orv8i8:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a0, 0(sp)
; RV32IP-NEXT: sw a1, 4(sp)
; RV32IP-NEXT: lb a0, 3(sp)
; RV32IP-NEXT: ori a0, a0, 4
; RV32IP-NEXT: sb a0, 11(sp)
; RV32IP-NEXT: lb a0, 2(sp)
; RV32IP-NEXT: ori a0, a0, 3
; RV32IP-NEXT: sb a0, 10(sp)
; RV32IP-NEXT: lb a0, 1(sp)
; RV32IP-NEXT: ori a0, a0, 2
; RV32IP-NEXT: sb a0, 9(sp)
; RV32IP-NEXT: lb a0, 0(sp)
; RV32IP-NEXT: ori a0, a0, 1
; RV32IP-NEXT: sb a0, 8(sp)
; RV32IP-NEXT: lb a0, 7(sp)
; RV32IP-NEXT: ori a0, a0, 8
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lb a0, 6(sp)
; RV32IP-NEXT: ori a0, a0, 7
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lb a0, 5(sp)
; RV32IP-NEXT: ori a0, a0, 6
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lb a0, 4(sp)
; RV32IP-NEXT: ori a0, a0, 5
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 8(sp)
; RV32IP-NEXT: lw a1, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: orv8i8:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a0, 0(sp)
; RV32IPN-NEXT: sw a1, 4(sp)
; RV32IPN-NEXT: lb a0, 3(sp)
; RV32IPN-NEXT: ori a0, a0, 4
; RV32IPN-NEXT: sb a0, 11(sp)
; RV32IPN-NEXT: lb a0, 2(sp)
; RV32IPN-NEXT: ori a0, a0, 3
; RV32IPN-NEXT: sb a0, 10(sp)
; RV32IPN-NEXT: lb a0, 1(sp)
; RV32IPN-NEXT: ori a0, a0, 2
; RV32IPN-NEXT: sb a0, 9(sp)
; RV32IPN-NEXT: lb a0, 0(sp)
; RV32IPN-NEXT: ori a0, a0, 1
; RV32IPN-NEXT: sb a0, 8(sp)
; RV32IPN-NEXT: lb a0, 7(sp)
; RV32IPN-NEXT: ori a0, a0, 8
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lb a0, 6(sp)
; RV32IPN-NEXT: ori a0, a0, 7
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lb a0, 5(sp)
; RV32IPN-NEXT: ori a0, a0, 6
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lb a0, 4(sp)
; RV32IPN-NEXT: ori a0, a0, 5
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 8(sp)
; RV32IPN-NEXT: lw a1, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp = bitcast i64 %a to <8 x i8>
%or = or <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
%res = bitcast <8 x i8> %or to i64
ret i64 %res
}
define i64 @orv4i16(i64 %a) nounwind {
; RV32IP-LABEL: orv4i16:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a0, 0(sp)
; RV32IP-NEXT: sw a1, 4(sp)
; RV32IP-NEXT: lh a0, 2(sp)
; RV32IP-NEXT: ori a0, a0, 2
; RV32IP-NEXT: sh a0, 10(sp)
; RV32IP-NEXT: lh a0, 0(sp)
; RV32IP-NEXT: ori a0, a0, 1
; RV32IP-NEXT: sh a0, 8(sp)
; RV32IP-NEXT: lh a0, 6(sp)
; RV32IP-NEXT: ori a0, a0, 4
; RV32IP-NEXT: sh a0, 14(sp)
; RV32IP-NEXT: lh a0, 4(sp)
; RV32IP-NEXT: ori a0, a0, 3
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 8(sp)
; RV32IP-NEXT: lw a1, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: orv4i16:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a0, 0(sp)
; RV32IPN-NEXT: sw a1, 4(sp)
; RV32IPN-NEXT: lh a0, 2(sp)
; RV32IPN-NEXT: ori a0, a0, 2
; RV32IPN-NEXT: sh a0, 10(sp)
; RV32IPN-NEXT: lh a0, 0(sp)
; RV32IPN-NEXT: ori a0, a0, 1
; RV32IPN-NEXT: sh a0, 8(sp)
; RV32IPN-NEXT: lh a0, 6(sp)
; RV32IPN-NEXT: ori a0, a0, 4
; RV32IPN-NEXT: sh a0, 14(sp)
; RV32IPN-NEXT: lh a0, 4(sp)
; RV32IPN-NEXT: ori a0, a0, 3
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 8(sp)
; RV32IPN-NEXT: lw a1, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp = bitcast i64 %a to <4 x i16>
%or = or <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4>
%res = bitcast <4 x i16> %or to i64
ret i64 %res
}
define i64 @orv2i32(i64 %a) nounwind {
; RV32IP-LABEL: orv2i32:
; RV32IP: # %bb.0:
; RV32IP-NEXT: ori a0, a0, 1
; RV32IP-NEXT: ori a1, a1, 2
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: orv2i32:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: ori a0, a0, 1
; RV32IPN-NEXT: ori a1, a1, 2
; RV32IPN-NEXT: ret
%tmp = bitcast i64 %a to <2 x i32>
%or = or <2 x i32> %tmp, <i32 1, i32 2>
%res = bitcast <2 x i32> %or to i64
ret i64 %res
}
define i32 @xorv4i8(i32 %a) nounwind {
; RV32IP-LABEL: xorv4i8:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a0, 8(sp)
; RV32IP-NEXT: lb a0, 11(sp)
; RV32IP-NEXT: xori a0, a0, 4
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lb a0, 10(sp)
; RV32IP-NEXT: xori a0, a0, 3
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lb a0, 9(sp)
; RV32IP-NEXT: xori a0, a0, 2
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lb a0, 8(sp)
; RV32IP-NEXT: xori a0, a0, 1
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: xorv4i8:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a0, 8(sp)
; RV32IPN-NEXT: lb a0, 11(sp)
; RV32IPN-NEXT: xori a0, a0, 4
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lb a0, 10(sp)
; RV32IPN-NEXT: xori a0, a0, 3
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lb a0, 9(sp)
; RV32IPN-NEXT: xori a0, a0, 2
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lb a0, 8(sp)
; RV32IPN-NEXT: xori a0, a0, 1
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp = bitcast i32 %a to <4 x i8>
%xor = xor <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4>
%res = bitcast <4 x i8> %xor to i32
ret i32 %res
}
define i32 @xorv2i16(i32 %a) nounwind {
; RV32IP-LABEL: xorv2i16:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a0, 8(sp)
; RV32IP-NEXT: lh a0, 10(sp)
; RV32IP-NEXT: xori a0, a0, 2
; RV32IP-NEXT: sh a0, 14(sp)
; RV32IP-NEXT: lh a0, 8(sp)
; RV32IP-NEXT: xori a0, a0, 1
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: xorv2i16:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a0, 8(sp)
; RV32IPN-NEXT: lh a0, 10(sp)
; RV32IPN-NEXT: xori a0, a0, 2
; RV32IPN-NEXT: sh a0, 14(sp)
; RV32IPN-NEXT: lh a0, 8(sp)
; RV32IPN-NEXT: xori a0, a0, 1
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp = bitcast i32 %a to <2 x i16>
%xor = xor <2 x i16> %tmp, <i16 1, i16 2>
%res = bitcast <2 x i16> %xor to i32
ret i32 %res
}
define i64 @xorv8i8(i64 %a) nounwind {
; RV32IP-LABEL: xorv8i8:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a0, 0(sp)
; RV32IP-NEXT: sw a1, 4(sp)
; RV32IP-NEXT: lb a0, 3(sp)
; RV32IP-NEXT: xori a0, a0, 4
; RV32IP-NEXT: sb a0, 11(sp)
; RV32IP-NEXT: lb a0, 2(sp)
; RV32IP-NEXT: xori a0, a0, 3
; RV32IP-NEXT: sb a0, 10(sp)
; RV32IP-NEXT: lb a0, 1(sp)
; RV32IP-NEXT: xori a0, a0, 2
; RV32IP-NEXT: sb a0, 9(sp)
; RV32IP-NEXT: lb a0, 0(sp)
; RV32IP-NEXT: xori a0, a0, 1
; RV32IP-NEXT: sb a0, 8(sp)
; RV32IP-NEXT: lb a0, 7(sp)
; RV32IP-NEXT: xori a0, a0, 8
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lb a0, 6(sp)
; RV32IP-NEXT: xori a0, a0, 7
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lb a0, 5(sp)
; RV32IP-NEXT: xori a0, a0, 6
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lb a0, 4(sp)
; RV32IP-NEXT: xori a0, a0, 5
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 8(sp)
; RV32IP-NEXT: lw a1, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: xorv8i8:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a0, 0(sp)
; RV32IPN-NEXT: sw a1, 4(sp)
; RV32IPN-NEXT: lb a0, 3(sp)
; RV32IPN-NEXT: xori a0, a0, 4
; RV32IPN-NEXT: sb a0, 11(sp)
; RV32IPN-NEXT: lb a0, 2(sp)
; RV32IPN-NEXT: xori a0, a0, 3
; RV32IPN-NEXT: sb a0, 10(sp)
; RV32IPN-NEXT: lb a0, 1(sp)
; RV32IPN-NEXT: xori a0, a0, 2
; RV32IPN-NEXT: sb a0, 9(sp)
; RV32IPN-NEXT: lb a0, 0(sp)
; RV32IPN-NEXT: xori a0, a0, 1
; RV32IPN-NEXT: sb a0, 8(sp)
; RV32IPN-NEXT: lb a0, 7(sp)
; RV32IPN-NEXT: xori a0, a0, 8
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lb a0, 6(sp)
; RV32IPN-NEXT: xori a0, a0, 7
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lb a0, 5(sp)
; RV32IPN-NEXT: xori a0, a0, 6
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lb a0, 4(sp)
; RV32IPN-NEXT: xori a0, a0, 5
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 8(sp)
; RV32IPN-NEXT: lw a1, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp = bitcast i64 %a to <8 x i8>
%xor = xor <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
%res = bitcast <8 x i8> %xor to i64
ret i64 %res
}
define i64 @xorv4i16(i64 %a) nounwind {
; RV32IP-LABEL: xorv4i16:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a0, 0(sp)
; RV32IP-NEXT: sw a1, 4(sp)
; RV32IP-NEXT: lh a0, 2(sp)
; RV32IP-NEXT: xori a0, a0, 2
; RV32IP-NEXT: sh a0, 10(sp)
; RV32IP-NEXT: lh a0, 0(sp)
; RV32IP-NEXT: xori a0, a0, 1
; RV32IP-NEXT: sh a0, 8(sp)
; RV32IP-NEXT: lh a0, 6(sp)
; RV32IP-NEXT: xori a0, a0, 4
; RV32IP-NEXT: sh a0, 14(sp)
; RV32IP-NEXT: lh a0, 4(sp)
; RV32IP-NEXT: xori a0, a0, 3
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 8(sp)
; RV32IP-NEXT: lw a1, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: xorv4i16:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a0, 0(sp)
; RV32IPN-NEXT: sw a1, 4(sp)
; RV32IPN-NEXT: lh a0, 2(sp)
; RV32IPN-NEXT: xori a0, a0, 2
; RV32IPN-NEXT: sh a0, 10(sp)
; RV32IPN-NEXT: lh a0, 0(sp)
; RV32IPN-NEXT: xori a0, a0, 1
; RV32IPN-NEXT: sh a0, 8(sp)
; RV32IPN-NEXT: lh a0, 6(sp)
; RV32IPN-NEXT: xori a0, a0, 4
; RV32IPN-NEXT: sh a0, 14(sp)
; RV32IPN-NEXT: lh a0, 4(sp)
; RV32IPN-NEXT: xori a0, a0, 3
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 8(sp)
; RV32IPN-NEXT: lw a1, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp = bitcast i64 %a to <4 x i16>
%xor = xor <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4>
%res = bitcast <4 x i16> %xor to i64
ret i64 %res
}
define i64 @xorv2i32(i64 %a) nounwind {
; RV32IP-LABEL: xorv2i32:
; RV32IP: # %bb.0:
; RV32IP-NEXT: xori a0, a0, 1
; RV32IP-NEXT: xori a1, a1, 2
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: xorv2i32:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: xori a0, a0, 1
; RV32IPN-NEXT: xori a1, a1, 2
; RV32IPN-NEXT: ret
%tmp = bitcast i64 %a to <2 x i32>
%xor = xor <2 x i32> %tmp, <i32 1, i32 2>
%res = bitcast <2 x i32> %xor to i64
ret i64 %res
}
; Logic operation with immediate.
; It has the input from the result of a vector operation to avoid
; it bitcasted to a scalar operation.
define i32 @andiv4i8(i32 %a, i32 %b) nounwind {
; RV32IP-LABEL: andiv4i8:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a1, 8(sp)
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lb a6, 8(sp)
; RV32IP-NEXT: lb a7, 4(sp)
; RV32IP-NEXT: lb t0, 9(sp)
; RV32IP-NEXT: lb a3, 5(sp)
; RV32IP-NEXT: lb a4, 10(sp)
; RV32IP-NEXT: lb a5, 6(sp)
; RV32IP-NEXT: lb a0, 11(sp)
; RV32IP-NEXT: lb a1, 7(sp)
; RV32IP-NEXT: addi a2, zero, 1
; RV32IP-NEXT: sw a2, 0(sp)
; RV32IP-NEXT: lb a2, 3(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: and a0, a0, a2
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lb a0, 2(sp)
; RV32IP-NEXT: add a1, a5, a4
; RV32IP-NEXT: and a0, a1, a0
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lb a0, 1(sp)
; RV32IP-NEXT: add a1, a3, t0
; RV32IP-NEXT: and a0, a1, a0
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lb a0, 0(sp)
; RV32IP-NEXT: add a1, a7, a6
; RV32IP-NEXT: and a0, a1, a0
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: andiv4i8:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a1, 8(sp)
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lb a6, 8(sp)
; RV32IPN-NEXT: lb a7, 4(sp)
; RV32IPN-NEXT: lb t0, 9(sp)
; RV32IPN-NEXT: lb a3, 5(sp)
; RV32IPN-NEXT: lb a4, 10(sp)
; RV32IPN-NEXT: lb a5, 6(sp)
; RV32IPN-NEXT: lb a0, 11(sp)
; RV32IPN-NEXT: lb a1, 7(sp)
; RV32IPN-NEXT: addi a2, zero, 1
; RV32IPN-NEXT: sw a2, 0(sp)
; RV32IPN-NEXT: lb a2, 3(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: and a0, a0, a2
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lb a0, 2(sp)
; RV32IPN-NEXT: add a1, a5, a4
; RV32IPN-NEXT: and a0, a1, a0
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lb a0, 1(sp)
; RV32IPN-NEXT: add a1, a3, t0
; RV32IPN-NEXT: and a0, a1, a0
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lb a0, 0(sp)
; RV32IPN-NEXT: add a1, a7, a6
; RV32IPN-NEXT: and a0, a1, a0
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <4 x i8>
%tmp2 = bitcast i32 %b to <4 x i8>
%imm = bitcast i32 1 to <4 x i8>
%add = add <4 x i8> %tmp1, %tmp2
%and = and <4 x i8> %add, %imm
%res = bitcast <4 x i8> %and to i32
ret i32 %res
}
define i32 @andiv2i16(i32 %a, i32 %b) nounwind {
; RV32IP-LABEL: andiv2i16:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a1, 8(sp)
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lh a0, 8(sp)
; RV32IP-NEXT: lh a1, 4(sp)
; RV32IP-NEXT: lh a2, 10(sp)
; RV32IP-NEXT: lh a3, 6(sp)
; RV32IP-NEXT: addi a4, zero, -2
; RV32IP-NEXT: sw a4, 0(sp)
; RV32IP-NEXT: lh a4, 2(sp)
; RV32IP-NEXT: add a2, a3, a2
; RV32IP-NEXT: and a2, a2, a4
; RV32IP-NEXT: sh a2, 14(sp)
; RV32IP-NEXT: lh a2, 0(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: and a0, a0, a2
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: andiv2i16:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a1, 8(sp)
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lh a0, 8(sp)
; RV32IPN-NEXT: lh a1, 4(sp)
; RV32IPN-NEXT: lh a2, 10(sp)
; RV32IPN-NEXT: lh a3, 6(sp)
; RV32IPN-NEXT: addi a4, zero, -2
; RV32IPN-NEXT: sw a4, 0(sp)
; RV32IPN-NEXT: lh a4, 2(sp)
; RV32IPN-NEXT: add a2, a3, a2
; RV32IPN-NEXT: and a2, a2, a4
; RV32IPN-NEXT: sh a2, 14(sp)
; RV32IPN-NEXT: lh a2, 0(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: and a0, a0, a2
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <2 x i16>
%tmp2 = bitcast i32 %b to <2 x i16>
%imm = bitcast i32 -2 to <2 x i16>
%add = add <2 x i16> %tmp1, %tmp2
%and = and <2 x i16> %add, %imm
%res = bitcast <2 x i16> %and to i32
ret i32 %res
}
define i64 @andiv8i8(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: andiv8i8:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -32
; RV32IP-NEXT: sw a3, 20(sp)
; RV32IP-NEXT: sw a1, 12(sp)
; RV32IP-NEXT: sw a2, 16(sp)
; RV32IP-NEXT: sw a0, 8(sp)
; RV32IP-NEXT: lb a0, 23(sp)
; RV32IP-NEXT: lb a1, 15(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 27(sp)
; RV32IP-NEXT: lb a0, 22(sp)
; RV32IP-NEXT: lb a1, 14(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 26(sp)
; RV32IP-NEXT: lb a0, 21(sp)
; RV32IP-NEXT: lb a1, 13(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 25(sp)
; RV32IP-NEXT: lb a0, 20(sp)
; RV32IP-NEXT: lb a1, 12(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 24(sp)
; RV32IP-NEXT: lb a6, 16(sp)
; RV32IP-NEXT: lb a7, 8(sp)
; RV32IP-NEXT: lb t0, 17(sp)
; RV32IP-NEXT: lb t1, 9(sp)
; RV32IP-NEXT: lb a5, 18(sp)
; RV32IP-NEXT: lb a0, 10(sp)
; RV32IP-NEXT: lb a2, 19(sp)
; RV32IP-NEXT: lb a3, 11(sp)
; RV32IP-NEXT: lw a1, 24(sp)
; RV32IP-NEXT: addi a4, zero, -3
; RV32IP-NEXT: sw a4, 4(sp)
; RV32IP-NEXT: lb a4, 7(sp)
; RV32IP-NEXT: add a2, a3, a2
; RV32IP-NEXT: and a2, a2, a4
; RV32IP-NEXT: sb a2, 31(sp)
; RV32IP-NEXT: lb a2, 6(sp)
; RV32IP-NEXT: add a0, a0, a5
; RV32IP-NEXT: and a0, a0, a2
; RV32IP-NEXT: sb a0, 30(sp)
; RV32IP-NEXT: lb a0, 5(sp)
; RV32IP-NEXT: add a2, t1, t0
; RV32IP-NEXT: and a0, a2, a0
; RV32IP-NEXT: sb a0, 29(sp)
; RV32IP-NEXT: lb a0, 4(sp)
; RV32IP-NEXT: add a2, a7, a6
; RV32IP-NEXT: and a0, a2, a0
; RV32IP-NEXT: sb a0, 28(sp)
; RV32IP-NEXT: lw a0, 28(sp)
; RV32IP-NEXT: addi sp, sp, 32
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: andiv8i8:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -32
; RV32IPN-NEXT: sw a3, 20(sp)
; RV32IPN-NEXT: sw a1, 12(sp)
; RV32IPN-NEXT: sw a2, 16(sp)
; RV32IPN-NEXT: sw a0, 8(sp)
; RV32IPN-NEXT: lb a0, 23(sp)
; RV32IPN-NEXT: lb a1, 15(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 27(sp)
; RV32IPN-NEXT: lb a0, 22(sp)
; RV32IPN-NEXT: lb a1, 14(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 26(sp)
; RV32IPN-NEXT: lb a0, 21(sp)
; RV32IPN-NEXT: lb a1, 13(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 25(sp)
; RV32IPN-NEXT: lb a0, 20(sp)
; RV32IPN-NEXT: lb a1, 12(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 24(sp)
; RV32IPN-NEXT: lb a6, 16(sp)
; RV32IPN-NEXT: lb a7, 8(sp)
; RV32IPN-NEXT: lb t0, 17(sp)
; RV32IPN-NEXT: lb t1, 9(sp)
; RV32IPN-NEXT: lb a5, 18(sp)
; RV32IPN-NEXT: lb a0, 10(sp)
; RV32IPN-NEXT: lb a2, 19(sp)
; RV32IPN-NEXT: lb a3, 11(sp)
; RV32IPN-NEXT: lw a1, 24(sp)
; RV32IPN-NEXT: addi a4, zero, -3
; RV32IPN-NEXT: sw a4, 4(sp)
; RV32IPN-NEXT: lb a4, 7(sp)
; RV32IPN-NEXT: add a2, a3, a2
; RV32IPN-NEXT: and a2, a2, a4
; RV32IPN-NEXT: sb a2, 31(sp)
; RV32IPN-NEXT: lb a2, 6(sp)
; RV32IPN-NEXT: add a0, a0, a5
; RV32IPN-NEXT: and a0, a0, a2
; RV32IPN-NEXT: sb a0, 30(sp)
; RV32IPN-NEXT: lb a0, 5(sp)
; RV32IPN-NEXT: add a2, t1, t0
; RV32IPN-NEXT: and a0, a2, a0
; RV32IPN-NEXT: sb a0, 29(sp)
; RV32IPN-NEXT: lb a0, 4(sp)
; RV32IPN-NEXT: add a2, a7, a6
; RV32IPN-NEXT: and a0, a2, a0
; RV32IPN-NEXT: sb a0, 28(sp)
; RV32IPN-NEXT: lw a0, 28(sp)
; RV32IPN-NEXT: addi sp, sp, 32
; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <8 x i8>
%tmp2 = bitcast i64 %b to <8 x i8>
%imm = bitcast i64 -3 to <8 x i8>
%add = add <8 x i8> %tmp1, %tmp2
%and = and <8 x i8> %add, %imm
%res = bitcast <8 x i8> %and to i64
ret i64 %res
}
define i64 @andvi4i16(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: andvi4i16:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -32
; RV32IP-NEXT: sw a3, 20(sp)
; RV32IP-NEXT: sw a1, 12(sp)
; RV32IP-NEXT: sw a2, 16(sp)
; RV32IP-NEXT: sw a0, 8(sp)
; RV32IP-NEXT: lh a0, 22(sp)
; RV32IP-NEXT: lh a1, 14(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sh a0, 26(sp)
; RV32IP-NEXT: lh a0, 20(sp)
; RV32IP-NEXT: lh a1, 12(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sh a0, 24(sp)
; RV32IP-NEXT: lh a0, 16(sp)
; RV32IP-NEXT: lh a2, 8(sp)
; RV32IP-NEXT: lh a3, 18(sp)
; RV32IP-NEXT: lh a4, 10(sp)
; RV32IP-NEXT: lw a1, 24(sp)
; RV32IP-NEXT: addi a5, zero, -4
; RV32IP-NEXT: sw a5, 4(sp)
; RV32IP-NEXT: lh a5, 6(sp)
; RV32IP-NEXT: add a3, a4, a3
; RV32IP-NEXT: and a3, a3, a5
; RV32IP-NEXT: sh a3, 30(sp)
; RV32IP-NEXT: lh a3, 4(sp)
; RV32IP-NEXT: add a0, a2, a0
; RV32IP-NEXT: and a0, a0, a3
; RV32IP-NEXT: sh a0, 28(sp)
; RV32IP-NEXT: lw a0, 28(sp)
; RV32IP-NEXT: addi sp, sp, 32
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: andvi4i16:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -32
; RV32IPN-NEXT: sw a3, 20(sp)
; RV32IPN-NEXT: sw a1, 12(sp)
; RV32IPN-NEXT: sw a2, 16(sp)
; RV32IPN-NEXT: sw a0, 8(sp)
; RV32IPN-NEXT: lh a0, 22(sp)
; RV32IPN-NEXT: lh a1, 14(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sh a0, 26(sp)
; RV32IPN-NEXT: lh a0, 20(sp)
; RV32IPN-NEXT: lh a1, 12(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sh a0, 24(sp)
; RV32IPN-NEXT: lh a0, 16(sp)
; RV32IPN-NEXT: lh a2, 8(sp)
; RV32IPN-NEXT: lh a3, 18(sp)
; RV32IPN-NEXT: lh a4, 10(sp)
; RV32IPN-NEXT: lw a1, 24(sp)
; RV32IPN-NEXT: addi a5, zero, -4
; RV32IPN-NEXT: sw a5, 4(sp)
; RV32IPN-NEXT: lh a5, 6(sp)
; RV32IPN-NEXT: add a3, a4, a3
; RV32IPN-NEXT: and a3, a3, a5
; RV32IPN-NEXT: sh a3, 30(sp)
; RV32IPN-NEXT: lh a3, 4(sp)
; RV32IPN-NEXT: add a0, a2, a0
; RV32IPN-NEXT: and a0, a0, a3
; RV32IPN-NEXT: sh a0, 28(sp)
; RV32IPN-NEXT: lw a0, 28(sp)
; RV32IPN-NEXT: addi sp, sp, 32
; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <4 x i16>
%tmp2 = bitcast i64 %b to <4 x i16>
%imm = bitcast i64 -4 to <4 x i16>
%add = add <4 x i16> %tmp1, %tmp2
%and = and <4 x i16> %add, %imm
%res = bitcast <4 x i16> %and to i64
ret i64 %res
}
define i64 @andiv2i32(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: andiv2i32:
; RV32IP: # %bb.0:
; RV32IP-NEXT: add a1, a1, a3
; RV32IP-NEXT: add a0, a0, a2
; RV32IP-NEXT: andi a0, a0, -5
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: andiv2i32:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: add a1, a1, a3
; RV32IPN-NEXT: add a0, a0, a2
; RV32IPN-NEXT: andi a0, a0, -5
; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <2 x i32>
%tmp2 = bitcast i64 %b to <2 x i32>
%imm = bitcast i64 -5 to <2 x i32>
%add = add <2 x i32> %tmp1, %tmp2
%and = and <2 x i32> %add, %imm
%res = bitcast <2 x i32> %and to i64
ret i64 %res
}
define i32 @oriv4i8(i32 %a, i32 %b) nounwind {
; RV32IP-LABEL: oriv4i8:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a1, 8(sp)
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lb a6, 8(sp)
; RV32IP-NEXT: lb a7, 4(sp)
; RV32IP-NEXT: lb t0, 9(sp)
; RV32IP-NEXT: lb a3, 5(sp)
; RV32IP-NEXT: lb a4, 10(sp)
; RV32IP-NEXT: lb a5, 6(sp)
; RV32IP-NEXT: lb a0, 11(sp)
; RV32IP-NEXT: lb a1, 7(sp)
; RV32IP-NEXT: addi a2, zero, 1
; RV32IP-NEXT: sw a2, 0(sp)
; RV32IP-NEXT: lb a2, 3(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: or a0, a0, a2
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lb a0, 2(sp)
; RV32IP-NEXT: add a1, a5, a4
; RV32IP-NEXT: or a0, a1, a0
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lb a0, 1(sp)
; RV32IP-NEXT: add a1, a3, t0
; RV32IP-NEXT: or a0, a1, a0
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lb a0, 0(sp)
; RV32IP-NEXT: add a1, a7, a6
; RV32IP-NEXT: or a0, a1, a0
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: oriv4i8:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a1, 8(sp)
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lb a6, 8(sp)
; RV32IPN-NEXT: lb a7, 4(sp)
; RV32IPN-NEXT: lb t0, 9(sp)
; RV32IPN-NEXT: lb a3, 5(sp)
; RV32IPN-NEXT: lb a4, 10(sp)
; RV32IPN-NEXT: lb a5, 6(sp)
; RV32IPN-NEXT: lb a0, 11(sp)
; RV32IPN-NEXT: lb a1, 7(sp)
; RV32IPN-NEXT: addi a2, zero, 1
; RV32IPN-NEXT: sw a2, 0(sp)
; RV32IPN-NEXT: lb a2, 3(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: or a0, a0, a2
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lb a0, 2(sp)
; RV32IPN-NEXT: add a1, a5, a4
; RV32IPN-NEXT: or a0, a1, a0
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lb a0, 1(sp)
; RV32IPN-NEXT: add a1, a3, t0
; RV32IPN-NEXT: or a0, a1, a0
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lb a0, 0(sp)
; RV32IPN-NEXT: add a1, a7, a6
; RV32IPN-NEXT: or a0, a1, a0
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <4 x i8>
%tmp2 = bitcast i32 %b to <4 x i8>
%imm = bitcast i32 1 to <4 x i8>
%add = add <4 x i8> %tmp1, %tmp2
%or = or <4 x i8> %add, %imm
%res = bitcast <4 x i8> %or to i32
ret i32 %res
}
define i32 @oriv2i16(i32 %a, i32 %b) nounwind {
; RV32IP-LABEL: oriv2i16:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a1, 8(sp)
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lh a0, 8(sp)
; RV32IP-NEXT: lh a1, 4(sp)
; RV32IP-NEXT: lh a2, 10(sp)
; RV32IP-NEXT: lh a3, 6(sp)
; RV32IP-NEXT: addi a4, zero, -2
; RV32IP-NEXT: sw a4, 0(sp)
; RV32IP-NEXT: lh a4, 2(sp)
; RV32IP-NEXT: add a2, a3, a2
; RV32IP-NEXT: or a2, a2, a4
; RV32IP-NEXT: sh a2, 14(sp)
; RV32IP-NEXT: lh a2, 0(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: or a0, a0, a2
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: oriv2i16:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a1, 8(sp)
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lh a0, 8(sp)
; RV32IPN-NEXT: lh a1, 4(sp)
; RV32IPN-NEXT: lh a2, 10(sp)
; RV32IPN-NEXT: lh a3, 6(sp)
; RV32IPN-NEXT: addi a4, zero, -2
; RV32IPN-NEXT: sw a4, 0(sp)
; RV32IPN-NEXT: lh a4, 2(sp)
; RV32IPN-NEXT: add a2, a3, a2
; RV32IPN-NEXT: or a2, a2, a4
; RV32IPN-NEXT: sh a2, 14(sp)
; RV32IPN-NEXT: lh a2, 0(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: or a0, a0, a2
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <2 x i16>
%tmp2 = bitcast i32 %b to <2 x i16>
%imm = bitcast i32 -2 to <2 x i16>
%add = add <2 x i16> %tmp1, %tmp2
%or = or <2 x i16> %add, %imm
%res = bitcast <2 x i16> %or to i32
ret i32 %res
}
define i64 @oriv8i8(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: oriv8i8:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a2, 8(sp)
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lb a6, 8(sp)
; RV32IP-NEXT: lb a7, 4(sp)
; RV32IP-NEXT: lb t0, 9(sp)
; RV32IP-NEXT: lb a3, 5(sp)
; RV32IP-NEXT: lb a4, 10(sp)
; RV32IP-NEXT: lb a5, 6(sp)
; RV32IP-NEXT: lb a0, 11(sp)
; RV32IP-NEXT: lb a1, 7(sp)
; RV32IP-NEXT: addi a2, zero, -3
; RV32IP-NEXT: sw a2, 0(sp)
; RV32IP-NEXT: lb a2, 3(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: or a0, a0, a2
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lb a0, 2(sp)
; RV32IP-NEXT: add a1, a5, a4
; RV32IP-NEXT: or a0, a1, a0
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lb a0, 1(sp)
; RV32IP-NEXT: add a1, a3, t0
; RV32IP-NEXT: or a0, a1, a0
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lb a0, 0(sp)
; RV32IP-NEXT: add a1, a7, a6
; RV32IP-NEXT: or a0, a1, a0
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lui a0, %hi(.LCPI32_0)
; RV32IP-NEXT: lw a1, %lo(.LCPI32_0)(a0)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: oriv8i8:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a2, 8(sp)
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lb a6, 8(sp)
; RV32IPN-NEXT: lb a7, 4(sp)
; RV32IPN-NEXT: lb t0, 9(sp)
; RV32IPN-NEXT: lb a3, 5(sp)
; RV32IPN-NEXT: lb a4, 10(sp)
; RV32IPN-NEXT: lb a5, 6(sp)
; RV32IPN-NEXT: lb a0, 11(sp)
; RV32IPN-NEXT: lb a1, 7(sp)
; RV32IPN-NEXT: addi a2, zero, -3
; RV32IPN-NEXT: sw a2, 0(sp)
; RV32IPN-NEXT: lb a2, 3(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: or a0, a0, a2
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lb a0, 2(sp)
; RV32IPN-NEXT: add a1, a5, a4
; RV32IPN-NEXT: or a0, a1, a0
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lb a0, 1(sp)
; RV32IPN-NEXT: add a1, a3, t0
; RV32IPN-NEXT: or a0, a1, a0
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lb a0, 0(sp)
; RV32IPN-NEXT: add a1, a7, a6
; RV32IPN-NEXT: or a0, a1, a0
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lui a0, %hi(.LCPI32_0)
; RV32IPN-NEXT: lw a1, %lo(.LCPI32_0)(a0)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <8 x i8>
%tmp2 = bitcast i64 %b to <8 x i8>
%imm = bitcast i64 -3 to <8 x i8>
%add = add <8 x i8> %tmp1, %tmp2
%or = or <8 x i8> %add, %imm
%res = bitcast <8 x i8> %or to i64
ret i64 %res
}
define i64 @orvi4i16(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: orvi4i16:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a2, 8(sp)
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lh a0, 8(sp)
; RV32IP-NEXT: lh a1, 4(sp)
; RV32IP-NEXT: lh a2, 10(sp)
; RV32IP-NEXT: lh a3, 6(sp)
; RV32IP-NEXT: addi a4, zero, -4
; RV32IP-NEXT: sw a4, 0(sp)
; RV32IP-NEXT: lh a4, 2(sp)
; RV32IP-NEXT: add a2, a3, a2
; RV32IP-NEXT: or a2, a2, a4
; RV32IP-NEXT: sh a2, 14(sp)
; RV32IP-NEXT: lh a2, 0(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: or a0, a0, a2
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lui a0, %hi(.LCPI33_0)
; RV32IP-NEXT: lw a1, %lo(.LCPI33_0)(a0)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: orvi4i16:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a2, 8(sp)
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lh a0, 8(sp)
; RV32IPN-NEXT: lh a1, 4(sp)
; RV32IPN-NEXT: lh a2, 10(sp)
; RV32IPN-NEXT: lh a3, 6(sp)
; RV32IPN-NEXT: addi a4, zero, -4
; RV32IPN-NEXT: sw a4, 0(sp)
; RV32IPN-NEXT: lh a4, 2(sp)
; RV32IPN-NEXT: add a2, a3, a2
; RV32IPN-NEXT: or a2, a2, a4
; RV32IPN-NEXT: sh a2, 14(sp)
; RV32IPN-NEXT: lh a2, 0(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: or a0, a0, a2
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lui a0, %hi(.LCPI33_0)
; RV32IPN-NEXT: lw a1, %lo(.LCPI33_0)(a0)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <4 x i16>
%tmp2 = bitcast i64 %b to <4 x i16>
%imm = bitcast i64 -4 to <4 x i16>
%add = add <4 x i16> %tmp1, %tmp2
%or = or <4 x i16> %add, %imm
%res = bitcast <4 x i16> %or to i64
ret i64 %res
}
define i64 @oriv2i32(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: oriv2i32:
; RV32IP: # %bb.0:
; RV32IP-NEXT: add a0, a0, a2
; RV32IP-NEXT: ori a0, a0, -5
; RV32IP-NEXT: addi a1, zero, -1
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: oriv2i32:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: add a0, a0, a2
; RV32IPN-NEXT: ori a0, a0, -5
; RV32IPN-NEXT: addi a1, zero, -1
; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <2 x i32>
%tmp2 = bitcast i64 %b to <2 x i32>
%imm = bitcast i64 -5 to <2 x i32>
%add = add <2 x i32> %tmp1, %tmp2
%or = or <2 x i32> %add, %imm
%res = bitcast <2 x i32> %or to i64
ret i64 %res
}
define i32 @xoriv4i8(i32 %a, i32 %b) nounwind {
; RV32IP-LABEL: xoriv4i8:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a1, 8(sp)
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lb a6, 8(sp)
; RV32IP-NEXT: lb a7, 4(sp)
; RV32IP-NEXT: lb t0, 9(sp)
; RV32IP-NEXT: lb a3, 5(sp)
; RV32IP-NEXT: lb a4, 10(sp)
; RV32IP-NEXT: lb a5, 6(sp)
; RV32IP-NEXT: lb a0, 11(sp)
; RV32IP-NEXT: lb a1, 7(sp)
; RV32IP-NEXT: addi a2, zero, -1
; RV32IP-NEXT: sw a2, 0(sp)
; RV32IP-NEXT: lb a2, 3(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: xor a0, a0, a2
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lb a0, 2(sp)
; RV32IP-NEXT: add a1, a5, a4
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lb a0, 1(sp)
; RV32IP-NEXT: add a1, a3, t0
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lb a0, 0(sp)
; RV32IP-NEXT: add a1, a7, a6
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: xoriv4i8:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a1, 8(sp)
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lb a6, 8(sp)
; RV32IPN-NEXT: lb a7, 4(sp)
; RV32IPN-NEXT: lb t0, 9(sp)
; RV32IPN-NEXT: lb a3, 5(sp)
; RV32IPN-NEXT: lb a4, 10(sp)
; RV32IPN-NEXT: lb a5, 6(sp)
; RV32IPN-NEXT: lb a0, 11(sp)
; RV32IPN-NEXT: lb a1, 7(sp)
; RV32IPN-NEXT: addi a2, zero, -1
; RV32IPN-NEXT: sw a2, 0(sp)
; RV32IPN-NEXT: lb a2, 3(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: xor a0, a0, a2
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lb a0, 2(sp)
; RV32IPN-NEXT: add a1, a5, a4
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lb a0, 1(sp)
; RV32IPN-NEXT: add a1, a3, t0
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lb a0, 0(sp)
; RV32IPN-NEXT: add a1, a7, a6
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <4 x i8>
%tmp2 = bitcast i32 %b to <4 x i8>
%imm = bitcast i32 -1 to <4 x i8>
%add = add <4 x i8> %tmp1, %tmp2
%xor = xor <4 x i8> %add, %imm
%res = bitcast <4 x i8> %xor to i32
ret i32 %res
}
define i32 @xoriv2i16(i32 %a, i32 %b) nounwind {
; RV32IP-LABEL: xoriv2i16:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16
; RV32IP-NEXT: sw a1, 8(sp)
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lh a0, 8(sp)
; RV32IP-NEXT: lh a1, 4(sp)
; RV32IP-NEXT: lh a2, 10(sp)
; RV32IP-NEXT: lh a3, 6(sp)
; RV32IP-NEXT: addi a4, zero, -2
; RV32IP-NEXT: sw a4, 0(sp)
; RV32IP-NEXT: lh a4, 2(sp)
; RV32IP-NEXT: add a2, a3, a2
; RV32IP-NEXT: xor a2, a2, a4
; RV32IP-NEXT: sh a2, 14(sp)
; RV32IP-NEXT: lh a2, 0(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: xor a0, a0, a2
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: xoriv2i16:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16
; RV32IPN-NEXT: sw a1, 8(sp)
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lh a0, 8(sp)
; RV32IPN-NEXT: lh a1, 4(sp)
; RV32IPN-NEXT: lh a2, 10(sp)
; RV32IPN-NEXT: lh a3, 6(sp)
; RV32IPN-NEXT: addi a4, zero, -2
; RV32IPN-NEXT: sw a4, 0(sp)
; RV32IPN-NEXT: lh a4, 2(sp)
; RV32IPN-NEXT: add a2, a3, a2
; RV32IPN-NEXT: xor a2, a2, a4
; RV32IPN-NEXT: sh a2, 14(sp)
; RV32IPN-NEXT: lh a2, 0(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: xor a0, a0, a2
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <2 x i16>
%tmp2 = bitcast i32 %b to <2 x i16>
%imm = bitcast i32 -2 to <2 x i16>
%add = add <2 x i16> %tmp1, %tmp2
%xor = xor <2 x i16> %add, %imm
%res = bitcast <2 x i16> %xor to i32
ret i32 %res
}
define i64 @xoriv8i8(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: xoriv8i8:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -48
; RV32IP-NEXT: sw s0, 44(sp) # 4-byte Folded Spill
; RV32IP-NEXT: sw s1, 40(sp) # 4-byte Folded Spill
; RV32IP-NEXT: sw a3, 28(sp)
; RV32IP-NEXT: sw a1, 20(sp)
; RV32IP-NEXT: sw a2, 24(sp)
; RV32IP-NEXT: sw a0, 16(sp)
; RV32IP-NEXT: lb a6, 28(sp)
; RV32IP-NEXT: lb a7, 20(sp)
; RV32IP-NEXT: lb t0, 29(sp)
; RV32IP-NEXT: lb t1, 21(sp)
; RV32IP-NEXT: lb t2, 30(sp)
; RV32IP-NEXT: lb t3, 22(sp)
; RV32IP-NEXT: lb t4, 31(sp)
; RV32IP-NEXT: lb t5, 23(sp)
; RV32IP-NEXT: lb t6, 24(sp)
; RV32IP-NEXT: lb a3, 16(sp)
; RV32IP-NEXT: lb a4, 25(sp)
; RV32IP-NEXT: lb a5, 17(sp)
; RV32IP-NEXT: lb a0, 26(sp)
; RV32IP-NEXT: lb a1, 18(sp)
; RV32IP-NEXT: lb a2, 27(sp)
; RV32IP-NEXT: lb s0, 19(sp)
; RV32IP-NEXT: addi s1, zero, -3
; RV32IP-NEXT: sw s1, 8(sp)
; RV32IP-NEXT: addi s1, zero, -1
; RV32IP-NEXT: sw s1, 12(sp)
; RV32IP-NEXT: lb s1, 11(sp)
; RV32IP-NEXT: add a2, s0, a2
; RV32IP-NEXT: xor a2, a2, s1
; RV32IP-NEXT: sb a2, 35(sp)
; RV32IP-NEXT: lb a2, 10(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: xor a0, a0, a2
; RV32IP-NEXT: sb a0, 34(sp)
; RV32IP-NEXT: lb a0, 9(sp)
; RV32IP-NEXT: add a1, a5, a4
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sb a0, 33(sp)
; RV32IP-NEXT: lb a0, 8(sp)
; RV32IP-NEXT: add a1, a3, t6
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sb a0, 32(sp)
; RV32IP-NEXT: lb a0, 15(sp)
; RV32IP-NEXT: add a1, t5, t4
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sb a0, 39(sp)
; RV32IP-NEXT: lb a0, 14(sp)
; RV32IP-NEXT: add a1, t3, t2
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sb a0, 38(sp)
; RV32IP-NEXT: lb a0, 13(sp)
; RV32IP-NEXT: add a1, t1, t0
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sb a0, 37(sp)
; RV32IP-NEXT: lb a0, 12(sp)
; RV32IP-NEXT: add a1, a7, a6
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sb a0, 36(sp)
; RV32IP-NEXT: lw a0, 32(sp)
; RV32IP-NEXT: lw a1, 36(sp)
; RV32IP-NEXT: lw s1, 40(sp) # 4-byte Folded Reload
; RV32IP-NEXT: lw s0, 44(sp) # 4-byte Folded Reload
; RV32IP-NEXT: addi sp, sp, 48
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: xoriv8i8:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -48
; RV32IPN-NEXT: sw s0, 44(sp) # 4-byte Folded Spill
; RV32IPN-NEXT: sw s1, 40(sp) # 4-byte Folded Spill
; RV32IPN-NEXT: sw a3, 28(sp)
; RV32IPN-NEXT: sw a1, 20(sp)
; RV32IPN-NEXT: sw a2, 24(sp)
; RV32IPN-NEXT: sw a0, 16(sp)
; RV32IPN-NEXT: lb a6, 28(sp)
; RV32IPN-NEXT: lb a7, 20(sp)
; RV32IPN-NEXT: lb t0, 29(sp)
; RV32IPN-NEXT: lb t1, 21(sp)
; RV32IPN-NEXT: lb t2, 30(sp)
; RV32IPN-NEXT: lb t3, 22(sp)
; RV32IPN-NEXT: lb t4, 31(sp)
; RV32IPN-NEXT: lb t5, 23(sp)
; RV32IPN-NEXT: lb t6, 24(sp)
; RV32IPN-NEXT: lb a3, 16(sp)
; RV32IPN-NEXT: lb a4, 25(sp)
; RV32IPN-NEXT: lb a5, 17(sp)
; RV32IPN-NEXT: lb a0, 26(sp)
; RV32IPN-NEXT: lb a1, 18(sp)
; RV32IPN-NEXT: lb a2, 27(sp)
; RV32IPN-NEXT: lb s0, 19(sp)
; RV32IPN-NEXT: addi s1, zero, -3
; RV32IPN-NEXT: sw s1, 8(sp)
; RV32IPN-NEXT: addi s1, zero, -1
; RV32IPN-NEXT: sw s1, 12(sp)
; RV32IPN-NEXT: lb s1, 11(sp)
; RV32IPN-NEXT: add a2, s0, a2
; RV32IPN-NEXT: xor a2, a2, s1
; RV32IPN-NEXT: sb a2, 35(sp)
; RV32IPN-NEXT: lb a2, 10(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: xor a0, a0, a2
; RV32IPN-NEXT: sb a0, 34(sp)
; RV32IPN-NEXT: lb a0, 9(sp)
; RV32IPN-NEXT: add a1, a5, a4
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sb a0, 33(sp)
; RV32IPN-NEXT: lb a0, 8(sp)
; RV32IPN-NEXT: add a1, a3, t6
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sb a0, 32(sp)
; RV32IPN-NEXT: lb a0, 15(sp)
; RV32IPN-NEXT: add a1, t5, t4
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sb a0, 39(sp)
; RV32IPN-NEXT: lb a0, 14(sp)
; RV32IPN-NEXT: add a1, t3, t2
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sb a0, 38(sp)
; RV32IPN-NEXT: lb a0, 13(sp)
; RV32IPN-NEXT: add a1, t1, t0
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sb a0, 37(sp)
; RV32IPN-NEXT: lb a0, 12(sp)
; RV32IPN-NEXT: add a1, a7, a6
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sb a0, 36(sp)
; RV32IPN-NEXT: lw a0, 32(sp)
; RV32IPN-NEXT: lw a1, 36(sp)
; RV32IPN-NEXT: lw s1, 40(sp) # 4-byte Folded Reload
; RV32IPN-NEXT: lw s0, 44(sp) # 4-byte Folded Reload
; RV32IPN-NEXT: addi sp, sp, 48
; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <8 x i8>
%tmp2 = bitcast i64 %b to <8 x i8>
%imm = bitcast i64 -3 to <8 x i8>
%add = add <8 x i8> %tmp1, %tmp2
%xor = xor <8 x i8> %add, %imm
%res = bitcast <8 x i8> %xor to i64
ret i64 %res
}
define i64 @xorvi4i16(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: xorvi4i16:
; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -32
; RV32IP-NEXT: sw a3, 20(sp)
; RV32IP-NEXT: sw a1, 12(sp)
; RV32IP-NEXT: sw a2, 16(sp)
; RV32IP-NEXT: sw a0, 8(sp)
; RV32IP-NEXT: lh a6, 20(sp)
; RV32IP-NEXT: lh a7, 12(sp)
; RV32IP-NEXT: lh t0, 22(sp)
; RV32IP-NEXT: lh a3, 14(sp)
; RV32IP-NEXT: lh a4, 16(sp)
; RV32IP-NEXT: lh a5, 8(sp)
; RV32IP-NEXT: lh a0, 18(sp)
; RV32IP-NEXT: lh a1, 10(sp)
; RV32IP-NEXT: addi a2, zero, -4
; RV32IP-NEXT: sw a2, 0(sp)
; RV32IP-NEXT: addi a2, zero, -1
; RV32IP-NEXT: sw a2, 4(sp)
; RV32IP-NEXT: lh a2, 2(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: xor a0, a0, a2
; RV32IP-NEXT: sh a0, 26(sp)
; RV32IP-NEXT: lh a0, 0(sp)
; RV32IP-NEXT: add a1, a5, a4
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sh a0, 24(sp)
; RV32IP-NEXT: lh a0, 6(sp)
; RV32IP-NEXT: add a1, a3, t0
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sh a0, 30(sp)
; RV32IP-NEXT: lh a0, 4(sp)
; RV32IP-NEXT: add a1, a7, a6
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sh a0, 28(sp)
; RV32IP-NEXT: lw a0, 24(sp)
; RV32IP-NEXT: lw a1, 28(sp)
; RV32IP-NEXT: addi sp, sp, 32
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: xorvi4i16:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -32
; RV32IPN-NEXT: sw a3, 20(sp)
; RV32IPN-NEXT: sw a1, 12(sp)
; RV32IPN-NEXT: sw a2, 16(sp)
; RV32IPN-NEXT: sw a0, 8(sp)
; RV32IPN-NEXT: lh a6, 20(sp)
; RV32IPN-NEXT: lh a7, 12(sp)
; RV32IPN-NEXT: lh t0, 22(sp)
; RV32IPN-NEXT: lh a3, 14(sp)
; RV32IPN-NEXT: lh a4, 16(sp)
; RV32IPN-NEXT: lh a5, 8(sp)
; RV32IPN-NEXT: lh a0, 18(sp)
; RV32IPN-NEXT: lh a1, 10(sp)
; RV32IPN-NEXT: addi a2, zero, -4
; RV32IPN-NEXT: sw a2, 0(sp)
; RV32IPN-NEXT: addi a2, zero, -1
; RV32IPN-NEXT: sw a2, 4(sp)
; RV32IPN-NEXT: lh a2, 2(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: xor a0, a0, a2
; RV32IPN-NEXT: sh a0, 26(sp)
; RV32IPN-NEXT: lh a0, 0(sp)
; RV32IPN-NEXT: add a1, a5, a4
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sh a0, 24(sp)
; RV32IPN-NEXT: lh a0, 6(sp)
; RV32IPN-NEXT: add a1, a3, t0
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sh a0, 30(sp)
; RV32IPN-NEXT: lh a0, 4(sp)
; RV32IPN-NEXT: add a1, a7, a6
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sh a0, 28(sp)
; RV32IPN-NEXT: lw a0, 24(sp)
; RV32IPN-NEXT: lw a1, 28(sp)
; RV32IPN-NEXT: addi sp, sp, 32
; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <4 x i16>
%tmp2 = bitcast i64 %b to <4 x i16>
%imm = bitcast i64 -4 to <4 x i16>
%add = add <4 x i16> %tmp1, %tmp2
%xor = xor <4 x i16> %add, %imm
%res = bitcast <4 x i16> %xor to i64
ret i64 %res
}
define i64 @xoriv2i32(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: xoriv2i32:
; RV32IP: # %bb.0:
; RV32IP-NEXT: add a1, a1, a3
; RV32IP-NEXT: add a0, a0, a2
; RV32IP-NEXT: xori a0, a0, -5
; RV32IP-NEXT: not a1, a1
; RV32IP-NEXT: ret
;
; RV32IPN-LABEL: xoriv2i32:
; RV32IPN: # %bb.0:
; RV32IPN-NEXT: add a1, a1, a3
; RV32IPN-NEXT: add a0, a0, a2
; RV32IPN-NEXT: xori a0, a0, -5
; RV32IPN-NEXT: not a1, a1
; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <2 x i32>
%tmp2 = bitcast i64 %b to <2 x i32>
%imm = bitcast i64 -5 to <2 x i32>
%add = add <2 x i32> %tmp1, %tmp2
%xor = xor <2 x i32> %add, %imm
%res = bitcast <2 x i32> %xor to i64
ret i64 %res
}

llvm/test/CodeGen/RISCV/rv64zpn-alu.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV64IP
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zpn -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV64IPN
define signext i32 @addv4i8(i32 signext %a, i32 signext %b) nounwind {
; RV64IP-LABEL: addv4i8:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sw a1, 8(sp)
; RV64IP-NEXT: sw a0, 12(sp)
; RV64IP-NEXT: lb a6, 8(sp)
; RV64IP-NEXT: lb a7, 12(sp)
; RV64IP-NEXT: lb a2, 9(sp)
; RV64IP-NEXT: lb a3, 11(sp)
; RV64IP-NEXT: lb a4, 15(sp)
; RV64IP-NEXT: lb a5, 10(sp)
; RV64IP-NEXT: lb a0, 14(sp)
; RV64IP-NEXT: lb a1, 13(sp)
; RV64IP-NEXT: add a3, a4, a3
; RV64IP-NEXT: sb a3, 7(sp)
; RV64IP-NEXT: add a0, a0, a5
; RV64IP-NEXT: sb a0, 6(sp)
; RV64IP-NEXT: add a0, a1, a2
; RV64IP-NEXT: sb a0, 5(sp)
; RV64IP-NEXT: add a0, a7, a6
; RV64IP-NEXT: sb a0, 4(sp)
; RV64IP-NEXT: lw a0, 4(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: addv4i8:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sw a1, 8(sp)
; RV64IPN-NEXT: sw a0, 12(sp)
; RV64IPN-NEXT: lb a6, 8(sp)
; RV64IPN-NEXT: lb a7, 12(sp)
; RV64IPN-NEXT: lb a2, 9(sp)
; RV64IPN-NEXT: lb a3, 11(sp)
; RV64IPN-NEXT: lb a4, 15(sp)
; RV64IPN-NEXT: lb a5, 10(sp)
; RV64IPN-NEXT: lb a0, 14(sp)
; RV64IPN-NEXT: lb a1, 13(sp)
; RV64IPN-NEXT: add a3, a4, a3
; RV64IPN-NEXT: sb a3, 7(sp)
; RV64IPN-NEXT: add a0, a0, a5
; RV64IPN-NEXT: sb a0, 6(sp)
; RV64IPN-NEXT: add a0, a1, a2
; RV64IPN-NEXT: sb a0, 5(sp)
; RV64IPN-NEXT: add a0, a7, a6
; RV64IPN-NEXT: sb a0, 4(sp)
; RV64IPN-NEXT: lw a0, 4(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <4 x i8>
%tmp2 = bitcast i32 %b to <4 x i8>
%add = add <4 x i8> %tmp1, %tmp2
%res = bitcast <4 x i8> %add to i32
ret i32 %res
}
define signext i32 @addv2i16(i32 signext %a, i32 signext %b) nounwind {
; RV64IP-LABEL: addv2i16:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sw a1, 8(sp)
; RV64IP-NEXT: sw a0, 12(sp)
; RV64IP-NEXT: lh a0, 10(sp)
; RV64IP-NEXT: lh a1, 14(sp)
; RV64IP-NEXT: lh a2, 8(sp)
; RV64IP-NEXT: lh a3, 12(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sh a0, 6(sp)
; RV64IP-NEXT: add a0, a3, a2
; RV64IP-NEXT: sh a0, 4(sp)
; RV64IP-NEXT: lw a0, 4(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: addv2i16:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sw a1, 8(sp)
; RV64IPN-NEXT: sw a0, 12(sp)
; RV64IPN-NEXT: lh a0, 10(sp)
; RV64IPN-NEXT: lh a1, 14(sp)
; RV64IPN-NEXT: lh a2, 8(sp)
; RV64IPN-NEXT: lh a3, 12(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sh a0, 6(sp)
; RV64IPN-NEXT: add a0, a3, a2
; RV64IPN-NEXT: sh a0, 4(sp)
; RV64IPN-NEXT: lw a0, 4(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <2 x i16>
%tmp2 = bitcast i32 %b to <2 x i16>
%add = add <2 x i16> %tmp1, %tmp2
%res = bitcast <2 x i16> %add to i32
ret i32 %res
}
define i64 @addv8i8(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: addv8i8:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lb a0, 23(sp)
; RV64IP-NEXT: lb a1, 15(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sb a0, 31(sp)
; RV64IP-NEXT: lb a0, 22(sp)
; RV64IP-NEXT: lb a1, 14(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sb a0, 30(sp)
; RV64IP-NEXT: lb a0, 21(sp)
; RV64IP-NEXT: lb a1, 13(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sb a0, 29(sp)
; RV64IP-NEXT: lb a0, 20(sp)
; RV64IP-NEXT: lb a1, 12(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sb a0, 28(sp)
; RV64IP-NEXT: lb a0, 19(sp)
; RV64IP-NEXT: lb a1, 11(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sb a0, 27(sp)
; RV64IP-NEXT: lb a0, 18(sp)
; RV64IP-NEXT: lb a1, 10(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sb a0, 26(sp)
; RV64IP-NEXT: lb a0, 17(sp)
; RV64IP-NEXT: lb a1, 9(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sb a0, 25(sp)
; RV64IP-NEXT: lb a0, 16(sp)
; RV64IP-NEXT: lb a1, 8(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sb a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: addv8i8:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lb a0, 23(sp)
; RV64IPN-NEXT: lb a1, 15(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sb a0, 31(sp)
; RV64IPN-NEXT: lb a0, 22(sp)
; RV64IPN-NEXT: lb a1, 14(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sb a0, 30(sp)
; RV64IPN-NEXT: lb a0, 21(sp)
; RV64IPN-NEXT: lb a1, 13(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sb a0, 29(sp)
; RV64IPN-NEXT: lb a0, 20(sp)
; RV64IPN-NEXT: lb a1, 12(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sb a0, 28(sp)
; RV64IPN-NEXT: lb a0, 19(sp)
; RV64IPN-NEXT: lb a1, 11(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sb a0, 27(sp)
; RV64IPN-NEXT: lb a0, 18(sp)
; RV64IPN-NEXT: lb a1, 10(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sb a0, 26(sp)
; RV64IPN-NEXT: lb a0, 17(sp)
; RV64IPN-NEXT: lb a1, 9(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sb a0, 25(sp)
; RV64IPN-NEXT: lb a0, 16(sp)
; RV64IPN-NEXT: lb a1, 8(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sb a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <8 x i8>
%tmp2 = bitcast i64 %b to <8 x i8>
%add = add <8 x i8> %tmp1, %tmp2
%res = bitcast <8 x i8> %add to i64
ret i64 %res
}
define i64 @addv4i16(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: addv4i16:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lh a0, 22(sp)
; RV64IP-NEXT: lh a1, 14(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sh a0, 30(sp)
; RV64IP-NEXT: lh a0, 20(sp)
; RV64IP-NEXT: lh a1, 12(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sh a0, 28(sp)
; RV64IP-NEXT: lh a0, 18(sp)
; RV64IP-NEXT: lh a1, 10(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sh a0, 26(sp)
; RV64IP-NEXT: lh a0, 16(sp)
; RV64IP-NEXT: lh a1, 8(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sh a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: addv4i16:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lh a0, 22(sp)
; RV64IPN-NEXT: lh a1, 14(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sh a0, 30(sp)
; RV64IPN-NEXT: lh a0, 20(sp)
; RV64IPN-NEXT: lh a1, 12(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sh a0, 28(sp)
; RV64IPN-NEXT: lh a0, 18(sp)
; RV64IPN-NEXT: lh a1, 10(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sh a0, 26(sp)
; RV64IPN-NEXT: lh a0, 16(sp)
; RV64IPN-NEXT: lh a1, 8(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sh a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <4 x i16>
%tmp2 = bitcast i64 %b to <4 x i16>
%add = add <4 x i16> %tmp1, %tmp2
%res = bitcast <4 x i16> %add to i64
ret i64 %res
}
define i64 @addv2i32(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: addv2i32:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lw a0, 20(sp)
; RV64IP-NEXT: lw a1, 12(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sw a0, 28(sp)
; RV64IP-NEXT: lw a0, 16(sp)
; RV64IP-NEXT: lw a1, 8(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sw a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: addv2i32:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lw a0, 20(sp)
; RV64IPN-NEXT: lw a1, 12(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sw a0, 28(sp)
; RV64IPN-NEXT: lw a0, 16(sp)
; RV64IPN-NEXT: lw a1, 8(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sw a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <2 x i32>
%tmp2 = bitcast i64 %b to <2 x i32>
%add = add <2 x i32> %tmp1, %tmp2
%res = bitcast <2 x i32> %add to i64
ret i64 %res
}
define signext i32 @subv4i8(i32 signext %a, i32 signext %b) nounwind {
; RV64IP-LABEL: subv4i8:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sw a1, 8(sp)
; RV64IP-NEXT: sw a0, 12(sp)
; RV64IP-NEXT: lb a6, 8(sp)
; RV64IP-NEXT: lb a7, 12(sp)
; RV64IP-NEXT: lb a2, 9(sp)
; RV64IP-NEXT: lb a3, 11(sp)
; RV64IP-NEXT: lb a4, 15(sp)
; RV64IP-NEXT: lb a5, 10(sp)
; RV64IP-NEXT: lb a0, 14(sp)
; RV64IP-NEXT: lb a1, 13(sp)
; RV64IP-NEXT: sub a3, a4, a3
; RV64IP-NEXT: sb a3, 7(sp)
; RV64IP-NEXT: sub a0, a0, a5
; RV64IP-NEXT: sb a0, 6(sp)
; RV64IP-NEXT: sub a0, a1, a2
; RV64IP-NEXT: sb a0, 5(sp)
; RV64IP-NEXT: sub a0, a7, a6
; RV64IP-NEXT: sb a0, 4(sp)
; RV64IP-NEXT: lw a0, 4(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: subv4i8:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sw a1, 8(sp)
; RV64IPN-NEXT: sw a0, 12(sp)
; RV64IPN-NEXT: lb a6, 8(sp)
; RV64IPN-NEXT: lb a7, 12(sp)
; RV64IPN-NEXT: lb a2, 9(sp)
; RV64IPN-NEXT: lb a3, 11(sp)
; RV64IPN-NEXT: lb a4, 15(sp)
; RV64IPN-NEXT: lb a5, 10(sp)
; RV64IPN-NEXT: lb a0, 14(sp)
; RV64IPN-NEXT: lb a1, 13(sp)
; RV64IPN-NEXT: sub a3, a4, a3
; RV64IPN-NEXT: sb a3, 7(sp)
; RV64IPN-NEXT: sub a0, a0, a5
; RV64IPN-NEXT: sb a0, 6(sp)
; RV64IPN-NEXT: sub a0, a1, a2
; RV64IPN-NEXT: sb a0, 5(sp)
; RV64IPN-NEXT: sub a0, a7, a6
; RV64IPN-NEXT: sb a0, 4(sp)
; RV64IPN-NEXT: lw a0, 4(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <4 x i8>
%tmp2 = bitcast i32 %b to <4 x i8>
%sub = sub <4 x i8> %tmp1, %tmp2
%res = bitcast <4 x i8> %sub to i32
ret i32 %res
}
define signext i32 @subv2i16(i32 signext %a, i32 signext %b) nounwind {
; RV64IP-LABEL: subv2i16:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sw a1, 8(sp)
; RV64IP-NEXT: sw a0, 12(sp)
; RV64IP-NEXT: lh a0, 10(sp)
; RV64IP-NEXT: lh a1, 14(sp)
; RV64IP-NEXT: lh a2, 8(sp)
; RV64IP-NEXT: lh a3, 12(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sh a0, 6(sp)
; RV64IP-NEXT: sub a0, a3, a2
; RV64IP-NEXT: sh a0, 4(sp)
; RV64IP-NEXT: lw a0, 4(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: subv2i16:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sw a1, 8(sp)
; RV64IPN-NEXT: sw a0, 12(sp)
; RV64IPN-NEXT: lh a0, 10(sp)
; RV64IPN-NEXT: lh a1, 14(sp)
; RV64IPN-NEXT: lh a2, 8(sp)
; RV64IPN-NEXT: lh a3, 12(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sh a0, 6(sp)
; RV64IPN-NEXT: sub a0, a3, a2
; RV64IPN-NEXT: sh a0, 4(sp)
; RV64IPN-NEXT: lw a0, 4(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <2 x i16>
%tmp2 = bitcast i32 %b to <2 x i16>
%sub = sub <2 x i16> %tmp1, %tmp2
%res = bitcast <2 x i16> %sub to i32
ret i32 %res
}
define i64 @subv8i8(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: subv8i8:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lb a0, 23(sp)
; RV64IP-NEXT: lb a1, 15(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sb a0, 31(sp)
; RV64IP-NEXT: lb a0, 22(sp)
; RV64IP-NEXT: lb a1, 14(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sb a0, 30(sp)
; RV64IP-NEXT: lb a0, 21(sp)
; RV64IP-NEXT: lb a1, 13(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sb a0, 29(sp)
; RV64IP-NEXT: lb a0, 20(sp)
; RV64IP-NEXT: lb a1, 12(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sb a0, 28(sp)
; RV64IP-NEXT: lb a0, 19(sp)
; RV64IP-NEXT: lb a1, 11(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sb a0, 27(sp)
; RV64IP-NEXT: lb a0, 18(sp)
; RV64IP-NEXT: lb a1, 10(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sb a0, 26(sp)
; RV64IP-NEXT: lb a0, 17(sp)
; RV64IP-NEXT: lb a1, 9(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sb a0, 25(sp)
; RV64IP-NEXT: lb a0, 16(sp)
; RV64IP-NEXT: lb a1, 8(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sb a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: subv8i8:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lb a0, 23(sp)
; RV64IPN-NEXT: lb a1, 15(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sb a0, 31(sp)
; RV64IPN-NEXT: lb a0, 22(sp)
; RV64IPN-NEXT: lb a1, 14(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sb a0, 30(sp)
; RV64IPN-NEXT: lb a0, 21(sp)
; RV64IPN-NEXT: lb a1, 13(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sb a0, 29(sp)
; RV64IPN-NEXT: lb a0, 20(sp)
; RV64IPN-NEXT: lb a1, 12(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sb a0, 28(sp)
; RV64IPN-NEXT: lb a0, 19(sp)
; RV64IPN-NEXT: lb a1, 11(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sb a0, 27(sp)
; RV64IPN-NEXT: lb a0, 18(sp)
; RV64IPN-NEXT: lb a1, 10(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sb a0, 26(sp)
; RV64IPN-NEXT: lb a0, 17(sp)
; RV64IPN-NEXT: lb a1, 9(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sb a0, 25(sp)
; RV64IPN-NEXT: lb a0, 16(sp)
; RV64IPN-NEXT: lb a1, 8(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sb a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <8 x i8>
%tmp2 = bitcast i64 %b to <8 x i8>
%sub = sub <8 x i8> %tmp1, %tmp2
%res = bitcast <8 x i8> %sub to i64
ret i64 %res
}
define i64 @subv4i16(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: subv4i16:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lh a0, 22(sp)
; RV64IP-NEXT: lh a1, 14(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sh a0, 30(sp)
; RV64IP-NEXT: lh a0, 20(sp)
; RV64IP-NEXT: lh a1, 12(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sh a0, 28(sp)
; RV64IP-NEXT: lh a0, 18(sp)
; RV64IP-NEXT: lh a1, 10(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sh a0, 26(sp)
; RV64IP-NEXT: lh a0, 16(sp)
; RV64IP-NEXT: lh a1, 8(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sh a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: subv4i16:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lh a0, 22(sp)
; RV64IPN-NEXT: lh a1, 14(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sh a0, 30(sp)
; RV64IPN-NEXT: lh a0, 20(sp)
; RV64IPN-NEXT: lh a1, 12(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sh a0, 28(sp)
; RV64IPN-NEXT: lh a0, 18(sp)
; RV64IPN-NEXT: lh a1, 10(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sh a0, 26(sp)
; RV64IPN-NEXT: lh a0, 16(sp)
; RV64IPN-NEXT: lh a1, 8(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sh a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <4 x i16>
%tmp2 = bitcast i64 %b to <4 x i16>
%sub = sub <4 x i16> %tmp1, %tmp2
%res = bitcast <4 x i16> %sub to i64
ret i64 %res
}
define i64 @subv2i32(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: subv2i32:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lw a0, 20(sp)
; RV64IP-NEXT: lw a1, 12(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sw a0, 28(sp)
; RV64IP-NEXT: lw a0, 16(sp)
; RV64IP-NEXT: lw a1, 8(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sw a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: subv2i32:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lw a0, 20(sp)
; RV64IPN-NEXT: lw a1, 12(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sw a0, 28(sp)
; RV64IPN-NEXT: lw a0, 16(sp)
; RV64IPN-NEXT: lw a1, 8(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sw a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <2 x i32>
%tmp2 = bitcast i64 %b to <2 x i32>
%add = sub <2 x i32> %tmp1, %tmp2
%res = bitcast <2 x i32> %add to i64
ret i64 %res
}
define signext i32 @andv4i8(i32 signext %a) nounwind {
; RV64IP-LABEL: andv4i8:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sw a0, 12(sp)
; RV64IP-NEXT: lbu a0, 15(sp)
; RV64IP-NEXT: lbu a1, 12(sp)
; RV64IP-NEXT: lbu a2, 14(sp)
; RV64IP-NEXT: lbu a3, 13(sp)
; RV64IP-NEXT: andi a0, a0, 4
; RV64IP-NEXT: sb a0, 11(sp)
; RV64IP-NEXT: andi a0, a2, 3
; RV64IP-NEXT: sb a0, 10(sp)
; RV64IP-NEXT: andi a0, a3, 2
; RV64IP-NEXT: sb a0, 9(sp)
; RV64IP-NEXT: andi a0, a1, 1
; RV64IP-NEXT: sb a0, 8(sp)
; RV64IP-NEXT: lwu a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: andv4i8:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sw a0, 12(sp)
; RV64IPN-NEXT: lbu a0, 15(sp)
; RV64IPN-NEXT: lbu a1, 12(sp)
; RV64IPN-NEXT: lbu a2, 14(sp)
; RV64IPN-NEXT: lbu a3, 13(sp)
; RV64IPN-NEXT: andi a0, a0, 4
; RV64IPN-NEXT: sb a0, 11(sp)
; RV64IPN-NEXT: andi a0, a2, 3
; RV64IPN-NEXT: sb a0, 10(sp)
; RV64IPN-NEXT: andi a0, a3, 2
; RV64IPN-NEXT: sb a0, 9(sp)
; RV64IPN-NEXT: andi a0, a1, 1
; RV64IPN-NEXT: sb a0, 8(sp)
; RV64IPN-NEXT: lwu a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp = bitcast i32 %a to <4 x i8>
%and = and <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4>
%res = bitcast <4 x i8> %and to i32
ret i32 %res
}
define signext i32 @andv2i16(i32 signext %a) nounwind {
; RV64IP-LABEL: andv2i16:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sw a0, 12(sp)
; RV64IP-NEXT: lhu a0, 14(sp)
; RV64IP-NEXT: lhu a1, 12(sp)
; RV64IP-NEXT: andi a0, a0, 2
; RV64IP-NEXT: sh a0, 10(sp)
; RV64IP-NEXT: andi a0, a1, 1
; RV64IP-NEXT: sh a0, 8(sp)
; RV64IP-NEXT: lwu a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: andv2i16:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sw a0, 12(sp)
; RV64IPN-NEXT: lhu a0, 14(sp)
; RV64IPN-NEXT: lhu a1, 12(sp)
; RV64IPN-NEXT: andi a0, a0, 2
; RV64IPN-NEXT: sh a0, 10(sp)
; RV64IPN-NEXT: andi a0, a1, 1
; RV64IPN-NEXT: sh a0, 8(sp)
; RV64IPN-NEXT: lwu a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp = bitcast i32 %a to <2 x i16>
%and = and <2 x i16> %tmp, <i16 1, i16 2>
%res = bitcast <2 x i16> %and to i32
ret i32 %res
}
define i64 @andv8i8(i64 %a) nounwind {
; RV64IP-LABEL: andv8i8:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sd a0, 0(sp)
; RV64IP-NEXT: lbu a0, 7(sp)
; RV64IP-NEXT: andi a0, a0, 8
; RV64IP-NEXT: sb a0, 15(sp)
; RV64IP-NEXT: lbu a0, 6(sp)
; RV64IP-NEXT: andi a0, a0, 7
; RV64IP-NEXT: sb a0, 14(sp)
; RV64IP-NEXT: lbu a0, 5(sp)
; RV64IP-NEXT: andi a0, a0, 6
; RV64IP-NEXT: sb a0, 13(sp)
; RV64IP-NEXT: lbu a0, 4(sp)
; RV64IP-NEXT: andi a0, a0, 5
; RV64IP-NEXT: sb a0, 12(sp)
; RV64IP-NEXT: lbu a0, 3(sp)
; RV64IP-NEXT: andi a0, a0, 4
; RV64IP-NEXT: sb a0, 11(sp)
; RV64IP-NEXT: lbu a0, 2(sp)
; RV64IP-NEXT: andi a0, a0, 3
; RV64IP-NEXT: sb a0, 10(sp)
; RV64IP-NEXT: lbu a0, 1(sp)
; RV64IP-NEXT: andi a0, a0, 2
; RV64IP-NEXT: sb a0, 9(sp)
; RV64IP-NEXT: lbu a0, 0(sp)
; RV64IP-NEXT: andi a0, a0, 1
; RV64IP-NEXT: sb a0, 8(sp)
; RV64IP-NEXT: ld a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: andv8i8:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sd a0, 0(sp)
; RV64IPN-NEXT: lbu a0, 7(sp)
; RV64IPN-NEXT: andi a0, a0, 8
; RV64IPN-NEXT: sb a0, 15(sp)
; RV64IPN-NEXT: lbu a0, 6(sp)
; RV64IPN-NEXT: andi a0, a0, 7
; RV64IPN-NEXT: sb a0, 14(sp)
; RV64IPN-NEXT: lbu a0, 5(sp)
; RV64IPN-NEXT: andi a0, a0, 6
; RV64IPN-NEXT: sb a0, 13(sp)
; RV64IPN-NEXT: lbu a0, 4(sp)
; RV64IPN-NEXT: andi a0, a0, 5
; RV64IPN-NEXT: sb a0, 12(sp)
; RV64IPN-NEXT: lbu a0, 3(sp)
; RV64IPN-NEXT: andi a0, a0, 4
; RV64IPN-NEXT: sb a0, 11(sp)
; RV64IPN-NEXT: lbu a0, 2(sp)
; RV64IPN-NEXT: andi a0, a0, 3
; RV64IPN-NEXT: sb a0, 10(sp)
; RV64IPN-NEXT: lbu a0, 1(sp)
; RV64IPN-NEXT: andi a0, a0, 2
; RV64IPN-NEXT: sb a0, 9(sp)
; RV64IPN-NEXT: lbu a0, 0(sp)
; RV64IPN-NEXT: andi a0, a0, 1
; RV64IPN-NEXT: sb a0, 8(sp)
; RV64IPN-NEXT: ld a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp = bitcast i64 %a to <8 x i8>
%and = and <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
%res = bitcast <8 x i8> %and to i64
ret i64 %res
}
define i64 @andv4i16(i64 %a) nounwind {
; RV64IP-LABEL: andv4i16:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sd a0, 0(sp)
; RV64IP-NEXT: lhu a0, 6(sp)
; RV64IP-NEXT: andi a0, a0, 4
; RV64IP-NEXT: sh a0, 14(sp)
; RV64IP-NEXT: lhu a0, 4(sp)
; RV64IP-NEXT: andi a0, a0, 3
; RV64IP-NEXT: sh a0, 12(sp)
; RV64IP-NEXT: lhu a0, 2(sp)
; RV64IP-NEXT: andi a0, a0, 2
; RV64IP-NEXT: sh a0, 10(sp)
; RV64IP-NEXT: lhu a0, 0(sp)
; RV64IP-NEXT: andi a0, a0, 1
; RV64IP-NEXT: sh a0, 8(sp)
; RV64IP-NEXT: ld a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: andv4i16:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sd a0, 0(sp)
; RV64IPN-NEXT: lhu a0, 6(sp)
; RV64IPN-NEXT: andi a0, a0, 4
; RV64IPN-NEXT: sh a0, 14(sp)
; RV64IPN-NEXT: lhu a0, 4(sp)
; RV64IPN-NEXT: andi a0, a0, 3
; RV64IPN-NEXT: sh a0, 12(sp)
; RV64IPN-NEXT: lhu a0, 2(sp)
; RV64IPN-NEXT: andi a0, a0, 2
; RV64IPN-NEXT: sh a0, 10(sp)
; RV64IPN-NEXT: lhu a0, 0(sp)
; RV64IPN-NEXT: andi a0, a0, 1
; RV64IPN-NEXT: sh a0, 8(sp)
; RV64IPN-NEXT: ld a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp = bitcast i64 %a to <4 x i16>
%and = and <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4>
%res = bitcast <4 x i16> %and to i64
ret i64 %res
}
define i64 @andv2i32(i64 %a) nounwind {
; RV64IP-LABEL: andv2i32:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sd a0, 0(sp)
; RV64IP-NEXT: lwu a0, 4(sp)
; RV64IP-NEXT: andi a0, a0, 2
; RV64IP-NEXT: sw a0, 12(sp)
; RV64IP-NEXT: lwu a0, 0(sp)
; RV64IP-NEXT: andi a0, a0, 1
; RV64IP-NEXT: sw a0, 8(sp)
; RV64IP-NEXT: ld a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: andv2i32:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sd a0, 0(sp)
; RV64IPN-NEXT: lwu a0, 4(sp)
; RV64IPN-NEXT: andi a0, a0, 2
; RV64IPN-NEXT: sw a0, 12(sp)
; RV64IPN-NEXT: lwu a0, 0(sp)
; RV64IPN-NEXT: andi a0, a0, 1
; RV64IPN-NEXT: sw a0, 8(sp)
; RV64IPN-NEXT: ld a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp = bitcast i64 %a to <2 x i32>
%and = and <2 x i32> %tmp, <i32 1, i32 2>
%res = bitcast <2 x i32> %and to i64
ret i64 %res
}
define signext i32 @orv4i8(i32 signext %a) nounwind {
; RV64IP-LABEL: orv4i8:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sw a0, 12(sp)
; RV64IP-NEXT: lb a0, 15(sp)
; RV64IP-NEXT: lb a1, 12(sp)
; RV64IP-NEXT: lb a2, 14(sp)
; RV64IP-NEXT: lb a3, 13(sp)
; RV64IP-NEXT: ori a0, a0, 4
; RV64IP-NEXT: sb a0, 11(sp)
; RV64IP-NEXT: ori a0, a2, 3
; RV64IP-NEXT: sb a0, 10(sp)
; RV64IP-NEXT: ori a0, a3, 2
; RV64IP-NEXT: sb a0, 9(sp)
; RV64IP-NEXT: ori a0, a1, 1
; RV64IP-NEXT: sb a0, 8(sp)
; RV64IP-NEXT: lw a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: orv4i8:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sw a0, 12(sp)
; RV64IPN-NEXT: lb a0, 15(sp)
; RV64IPN-NEXT: lb a1, 12(sp)
; RV64IPN-NEXT: lb a2, 14(sp)
; RV64IPN-NEXT: lb a3, 13(sp)
; RV64IPN-NEXT: ori a0, a0, 4
; RV64IPN-NEXT: sb a0, 11(sp)
; RV64IPN-NEXT: ori a0, a2, 3
; RV64IPN-NEXT: sb a0, 10(sp)
; RV64IPN-NEXT: ori a0, a3, 2
; RV64IPN-NEXT: sb a0, 9(sp)
; RV64IPN-NEXT: ori a0, a1, 1
; RV64IPN-NEXT: sb a0, 8(sp)
; RV64IPN-NEXT: lw a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp = bitcast i32 %a to <4 x i8>
%or = or <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4>
%res = bitcast <4 x i8> %or to i32
ret i32 %res
}
define signext i32 @orv2i16(i32 signext %a) nounwind {
; RV64IP-LABEL: orv2i16:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sw a0, 12(sp)
; RV64IP-NEXT: lh a0, 14(sp)
; RV64IP-NEXT: lh a1, 12(sp)
; RV64IP-NEXT: ori a0, a0, 2
; RV64IP-NEXT: sh a0, 10(sp)
; RV64IP-NEXT: ori a0, a1, 1
; RV64IP-NEXT: sh a0, 8(sp)
; RV64IP-NEXT: lw a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: orv2i16:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sw a0, 12(sp)
; RV64IPN-NEXT: lh a0, 14(sp)
; RV64IPN-NEXT: lh a1, 12(sp)
; RV64IPN-NEXT: ori a0, a0, 2
; RV64IPN-NEXT: sh a0, 10(sp)
; RV64IPN-NEXT: ori a0, a1, 1
; RV64IPN-NEXT: sh a0, 8(sp)
; RV64IPN-NEXT: lw a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp = bitcast i32 %a to <2 x i16>
%or = or <2 x i16> %tmp, <i16 1, i16 2>
%res = bitcast <2 x i16> %or to i32
ret i32 %res
}
define i64 @orv8i8(i64 %a) nounwind {
; RV64IP-LABEL: orv8i8:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sd a0, 0(sp)
; RV64IP-NEXT: lb a0, 7(sp)
; RV64IP-NEXT: ori a0, a0, 8
; RV64IP-NEXT: sb a0, 15(sp)
; RV64IP-NEXT: lb a0, 6(sp)
; RV64IP-NEXT: ori a0, a0, 7
; RV64IP-NEXT: sb a0, 14(sp)
; RV64IP-NEXT: lb a0, 5(sp)
; RV64IP-NEXT: ori a0, a0, 6
; RV64IP-NEXT: sb a0, 13(sp)
; RV64IP-NEXT: lb a0, 4(sp)
; RV64IP-NEXT: ori a0, a0, 5
; RV64IP-NEXT: sb a0, 12(sp)
; RV64IP-NEXT: lb a0, 3(sp)
; RV64IP-NEXT: ori a0, a0, 4
; RV64IP-NEXT: sb a0, 11(sp)
; RV64IP-NEXT: lb a0, 2(sp)
; RV64IP-NEXT: ori a0, a0, 3
; RV64IP-NEXT: sb a0, 10(sp)
; RV64IP-NEXT: lb a0, 1(sp)
; RV64IP-NEXT: ori a0, a0, 2
; RV64IP-NEXT: sb a0, 9(sp)
; RV64IP-NEXT: lb a0, 0(sp)
; RV64IP-NEXT: ori a0, a0, 1
; RV64IP-NEXT: sb a0, 8(sp)
; RV64IP-NEXT: ld a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: orv8i8:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sd a0, 0(sp)
; RV64IPN-NEXT: lb a0, 7(sp)
; RV64IPN-NEXT: ori a0, a0, 8
; RV64IPN-NEXT: sb a0, 15(sp)
; RV64IPN-NEXT: lb a0, 6(sp)
; RV64IPN-NEXT: ori a0, a0, 7
; RV64IPN-NEXT: sb a0, 14(sp)
; RV64IPN-NEXT: lb a0, 5(sp)
; RV64IPN-NEXT: ori a0, a0, 6
; RV64IPN-NEXT: sb a0, 13(sp)
; RV64IPN-NEXT: lb a0, 4(sp)
; RV64IPN-NEXT: ori a0, a0, 5
; RV64IPN-NEXT: sb a0, 12(sp)
; RV64IPN-NEXT: lb a0, 3(sp)
; RV64IPN-NEXT: ori a0, a0, 4
; RV64IPN-NEXT: sb a0, 11(sp)
; RV64IPN-NEXT: lb a0, 2(sp)
; RV64IPN-NEXT: ori a0, a0, 3
; RV64IPN-NEXT: sb a0, 10(sp)
; RV64IPN-NEXT: lb a0, 1(sp)
; RV64IPN-NEXT: ori a0, a0, 2
; RV64IPN-NEXT: sb a0, 9(sp)
; RV64IPN-NEXT: lb a0, 0(sp)
; RV64IPN-NEXT: ori a0, a0, 1
; RV64IPN-NEXT: sb a0, 8(sp)
; RV64IPN-NEXT: ld a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp = bitcast i64 %a to <8 x i8>
%or = or <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
%res = bitcast <8 x i8> %or to i64
ret i64 %res
}
define i64 @orv4i16(i64 %a) nounwind {
; RV64IP-LABEL: orv4i16:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sd a0, 0(sp)
; RV64IP-NEXT: lh a0, 6(sp)
; RV64IP-NEXT: ori a0, a0, 4
; RV64IP-NEXT: sh a0, 14(sp)
; RV64IP-NEXT: lh a0, 4(sp)
; RV64IP-NEXT: ori a0, a0, 3
; RV64IP-NEXT: sh a0, 12(sp)
; RV64IP-NEXT: lh a0, 2(sp)
; RV64IP-NEXT: ori a0, a0, 2
; RV64IP-NEXT: sh a0, 10(sp)
; RV64IP-NEXT: lh a0, 0(sp)
; RV64IP-NEXT: ori a0, a0, 1
; RV64IP-NEXT: sh a0, 8(sp)
; RV64IP-NEXT: ld a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: orv4i16:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sd a0, 0(sp)
; RV64IPN-NEXT: lh a0, 6(sp)
; RV64IPN-NEXT: ori a0, a0, 4
; RV64IPN-NEXT: sh a0, 14(sp)
; RV64IPN-NEXT: lh a0, 4(sp)
; RV64IPN-NEXT: ori a0, a0, 3
; RV64IPN-NEXT: sh a0, 12(sp)
; RV64IPN-NEXT: lh a0, 2(sp)
; RV64IPN-NEXT: ori a0, a0, 2
; RV64IPN-NEXT: sh a0, 10(sp)
; RV64IPN-NEXT: lh a0, 0(sp)
; RV64IPN-NEXT: ori a0, a0, 1
; RV64IPN-NEXT: sh a0, 8(sp)
; RV64IPN-NEXT: ld a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp = bitcast i64 %a to <4 x i16>
%or = or <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4>
%res = bitcast <4 x i16> %or to i64
ret i64 %res
}
define i64 @orv2i32(i64 %a) nounwind {
; RV64IP-LABEL: orv2i32:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sd a0, 0(sp)
; RV64IP-NEXT: lw a0, 4(sp)
; RV64IP-NEXT: ori a0, a0, 2
; RV64IP-NEXT: sw a0, 12(sp)
; RV64IP-NEXT: lw a0, 0(sp)
; RV64IP-NEXT: ori a0, a0, 1
; RV64IP-NEXT: sw a0, 8(sp)
; RV64IP-NEXT: ld a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: orv2i32:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sd a0, 0(sp)
; RV64IPN-NEXT: lw a0, 4(sp)
; RV64IPN-NEXT: ori a0, a0, 2
; RV64IPN-NEXT: sw a0, 12(sp)
; RV64IPN-NEXT: lw a0, 0(sp)
; RV64IPN-NEXT: ori a0, a0, 1
; RV64IPN-NEXT: sw a0, 8(sp)
; RV64IPN-NEXT: ld a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp = bitcast i64 %a to <2 x i32>
%or = or <2 x i32> %tmp, <i32 1, i32 2>
%res = bitcast <2 x i32> %or to i64
ret i64 %res
}
define signext i32 @xorv4i8(i32 signext %a) nounwind {
; RV64IP-LABEL: xorv4i8:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sw a0, 12(sp)
; RV64IP-NEXT: lb a0, 15(sp)
; RV64IP-NEXT: lb a1, 12(sp)
; RV64IP-NEXT: lb a2, 14(sp)
; RV64IP-NEXT: lb a3, 13(sp)
; RV64IP-NEXT: xori a0, a0, 4
; RV64IP-NEXT: sb a0, 11(sp)
; RV64IP-NEXT: xori a0, a2, 3
; RV64IP-NEXT: sb a0, 10(sp)
; RV64IP-NEXT: xori a0, a3, 2
; RV64IP-NEXT: sb a0, 9(sp)
; RV64IP-NEXT: xori a0, a1, 1
; RV64IP-NEXT: sb a0, 8(sp)
; RV64IP-NEXT: lw a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: xorv4i8:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sw a0, 12(sp)
; RV64IPN-NEXT: lb a0, 15(sp)
; RV64IPN-NEXT: lb a1, 12(sp)
; RV64IPN-NEXT: lb a2, 14(sp)
; RV64IPN-NEXT: lb a3, 13(sp)
; RV64IPN-NEXT: xori a0, a0, 4
; RV64IPN-NEXT: sb a0, 11(sp)
; RV64IPN-NEXT: xori a0, a2, 3
; RV64IPN-NEXT: sb a0, 10(sp)
; RV64IPN-NEXT: xori a0, a3, 2
; RV64IPN-NEXT: sb a0, 9(sp)
; RV64IPN-NEXT: xori a0, a1, 1
; RV64IPN-NEXT: sb a0, 8(sp)
; RV64IPN-NEXT: lw a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp = bitcast i32 %a to <4 x i8>
%xor = xor <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4>
%res = bitcast <4 x i8> %xor to i32
ret i32 %res
}
define signext i32 @xorv2i16(i32 signext %a) nounwind {
; RV64IP-LABEL: xorv2i16:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sw a0, 12(sp)
; RV64IP-NEXT: lh a0, 14(sp)
; RV64IP-NEXT: lh a1, 12(sp)
; RV64IP-NEXT: xori a0, a0, 2
; RV64IP-NEXT: sh a0, 10(sp)
; RV64IP-NEXT: xori a0, a1, 1
; RV64IP-NEXT: sh a0, 8(sp)
; RV64IP-NEXT: lw a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: xorv2i16:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sw a0, 12(sp)
; RV64IPN-NEXT: lh a0, 14(sp)
; RV64IPN-NEXT: lh a1, 12(sp)
; RV64IPN-NEXT: xori a0, a0, 2
; RV64IPN-NEXT: sh a0, 10(sp)
; RV64IPN-NEXT: xori a0, a1, 1
; RV64IPN-NEXT: sh a0, 8(sp)
; RV64IPN-NEXT: lw a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp = bitcast i32 %a to <2 x i16>
%xor = xor <2 x i16> %tmp, <i16 1, i16 2>
%res = bitcast <2 x i16> %xor to i32
ret i32 %res
}
define i64 @xorv8i8(i64 %a) nounwind {
; RV64IP-LABEL: xorv8i8:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sd a0, 0(sp)
; RV64IP-NEXT: lb a0, 7(sp)
; RV64IP-NEXT: xori a0, a0, 8
; RV64IP-NEXT: sb a0, 15(sp)
; RV64IP-NEXT: lb a0, 6(sp)
; RV64IP-NEXT: xori a0, a0, 7
; RV64IP-NEXT: sb a0, 14(sp)
; RV64IP-NEXT: lb a0, 5(sp)
; RV64IP-NEXT: xori a0, a0, 6
; RV64IP-NEXT: sb a0, 13(sp)
; RV64IP-NEXT: lb a0, 4(sp)
; RV64IP-NEXT: xori a0, a0, 5
; RV64IP-NEXT: sb a0, 12(sp)
; RV64IP-NEXT: lb a0, 3(sp)
; RV64IP-NEXT: xori a0, a0, 4
; RV64IP-NEXT: sb a0, 11(sp)
; RV64IP-NEXT: lb a0, 2(sp)
; RV64IP-NEXT: xori a0, a0, 3
; RV64IP-NEXT: sb a0, 10(sp)
; RV64IP-NEXT: lb a0, 1(sp)
; RV64IP-NEXT: xori a0, a0, 2
; RV64IP-NEXT: sb a0, 9(sp)
; RV64IP-NEXT: lb a0, 0(sp)
; RV64IP-NEXT: xori a0, a0, 1
; RV64IP-NEXT: sb a0, 8(sp)
; RV64IP-NEXT: ld a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: xorv8i8:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sd a0, 0(sp)
; RV64IPN-NEXT: lb a0, 7(sp)
; RV64IPN-NEXT: xori a0, a0, 8
; RV64IPN-NEXT: sb a0, 15(sp)
; RV64IPN-NEXT: lb a0, 6(sp)
; RV64IPN-NEXT: xori a0, a0, 7
; RV64IPN-NEXT: sb a0, 14(sp)
; RV64IPN-NEXT: lb a0, 5(sp)
; RV64IPN-NEXT: xori a0, a0, 6
; RV64IPN-NEXT: sb a0, 13(sp)
; RV64IPN-NEXT: lb a0, 4(sp)
; RV64IPN-NEXT: xori a0, a0, 5
; RV64IPN-NEXT: sb a0, 12(sp)
; RV64IPN-NEXT: lb a0, 3(sp)
; RV64IPN-NEXT: xori a0, a0, 4
; RV64IPN-NEXT: sb a0, 11(sp)
; RV64IPN-NEXT: lb a0, 2(sp)
; RV64IPN-NEXT: xori a0, a0, 3
; RV64IPN-NEXT: sb a0, 10(sp)
; RV64IPN-NEXT: lb a0, 1(sp)
; RV64IPN-NEXT: xori a0, a0, 2
; RV64IPN-NEXT: sb a0, 9(sp)
; RV64IPN-NEXT: lb a0, 0(sp)
; RV64IPN-NEXT: xori a0, a0, 1
; RV64IPN-NEXT: sb a0, 8(sp)
; RV64IPN-NEXT: ld a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp = bitcast i64 %a to <8 x i8>
%xor = xor <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
%res = bitcast <8 x i8> %xor to i64
ret i64 %res
}
define i64 @xorv4i16(i64 %a) nounwind {
; RV64IP-LABEL: xorv4i16:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sd a0, 0(sp)
; RV64IP-NEXT: lh a0, 6(sp)
; RV64IP-NEXT: xori a0, a0, 4
; RV64IP-NEXT: sh a0, 14(sp)
; RV64IP-NEXT: lh a0, 4(sp)
; RV64IP-NEXT: xori a0, a0, 3
; RV64IP-NEXT: sh a0, 12(sp)
; RV64IP-NEXT: lh a0, 2(sp)
; RV64IP-NEXT: xori a0, a0, 2
; RV64IP-NEXT: sh a0, 10(sp)
; RV64IP-NEXT: lh a0, 0(sp)
; RV64IP-NEXT: xori a0, a0, 1
; RV64IP-NEXT: sh a0, 8(sp)
; RV64IP-NEXT: ld a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: xorv4i16:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sd a0, 0(sp)
; RV64IPN-NEXT: lh a0, 6(sp)
; RV64IPN-NEXT: xori a0, a0, 4
; RV64IPN-NEXT: sh a0, 14(sp)
; RV64IPN-NEXT: lh a0, 4(sp)
; RV64IPN-NEXT: xori a0, a0, 3
; RV64IPN-NEXT: sh a0, 12(sp)
; RV64IPN-NEXT: lh a0, 2(sp)
; RV64IPN-NEXT: xori a0, a0, 2
; RV64IPN-NEXT: sh a0, 10(sp)
; RV64IPN-NEXT: lh a0, 0(sp)
; RV64IPN-NEXT: xori a0, a0, 1
; RV64IPN-NEXT: sh a0, 8(sp)
; RV64IPN-NEXT: ld a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp = bitcast i64 %a to <4 x i16>
%xor = xor <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4>
%res = bitcast <4 x i16> %xor to i64
ret i64 %res
}
define i64 @xorv2i32(i64 %a) nounwind {
; RV64IP-LABEL: xorv2i32:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sd a0, 0(sp)
; RV64IP-NEXT: lw a0, 4(sp)
; RV64IP-NEXT: xori a0, a0, 2
; RV64IP-NEXT: sw a0, 12(sp)
; RV64IP-NEXT: lw a0, 0(sp)
; RV64IP-NEXT: xori a0, a0, 1
; RV64IP-NEXT: sw a0, 8(sp)
; RV64IP-NEXT: ld a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: xorv2i32:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sd a0, 0(sp)
; RV64IPN-NEXT: lw a0, 4(sp)
; RV64IPN-NEXT: xori a0, a0, 2
; RV64IPN-NEXT: sw a0, 12(sp)
; RV64IPN-NEXT: lw a0, 0(sp)
; RV64IPN-NEXT: xori a0, a0, 1
; RV64IPN-NEXT: sw a0, 8(sp)
; RV64IPN-NEXT: ld a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp = bitcast i64 %a to <2 x i32>
%xor = xor <2 x i32> %tmp, <i32 1, i32 2>
%res = bitcast <2 x i32> %xor to i64
ret i64 %res
}
; Logic operation with immediate.
; It has the input from the result of a vector operation to avoid
; it bitcasted to a scalar operation.
define signext i32 @andiv4i8(i32 signext %a, i32 signext %b) nounwind {
; RV64IP-LABEL: andiv4i8:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sw a1, 4(sp)
; RV64IP-NEXT: sw a0, 8(sp)
; RV64IP-NEXT: lb a0, 7(sp)
; RV64IP-NEXT: lb a1, 11(sp)
; RV64IP-NEXT: lb a2, 6(sp)
; RV64IP-NEXT: lb a3, 10(sp)
; RV64IP-NEXT: lb t0, 5(sp)
; RV64IP-NEXT: lb a5, 9(sp)
; RV64IP-NEXT: lb a6, 4(sp)
; RV64IP-NEXT: lb a7, 8(sp)
; RV64IP-NEXT: addi a4, zero, 1
; RV64IP-NEXT: sw a4, 12(sp)
; RV64IP-NEXT: lb a4, 15(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: and a0, a0, a4
; RV64IP-NEXT: sb a0, 3(sp)
; RV64IP-NEXT: lb a0, 14(sp)
; RV64IP-NEXT: add a1, a3, a2
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sb a0, 2(sp)
; RV64IP-NEXT: lb a0, 13(sp)
; RV64IP-NEXT: add a1, a5, t0
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sb a0, 1(sp)
; RV64IP-NEXT: lb a0, 12(sp)
; RV64IP-NEXT: add a1, a7, a6
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sb a0, 0(sp)
; RV64IP-NEXT: lwu a0, 0(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: andiv4i8:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sw a1, 4(sp)
; RV64IPN-NEXT: sw a0, 8(sp)
; RV64IPN-NEXT: lb a0, 7(sp)
; RV64IPN-NEXT: lb a1, 11(sp)
; RV64IPN-NEXT: lb a2, 6(sp)
; RV64IPN-NEXT: lb a3, 10(sp)
; RV64IPN-NEXT: lb t0, 5(sp)
; RV64IPN-NEXT: lb a5, 9(sp)
; RV64IPN-NEXT: lb a6, 4(sp)
; RV64IPN-NEXT: lb a7, 8(sp)
; RV64IPN-NEXT: addi a4, zero, 1
; RV64IPN-NEXT: sw a4, 12(sp)
; RV64IPN-NEXT: lb a4, 15(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: and a0, a0, a4
; RV64IPN-NEXT: sb a0, 3(sp)
; RV64IPN-NEXT: lb a0, 14(sp)
; RV64IPN-NEXT: add a1, a3, a2
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sb a0, 2(sp)
; RV64IPN-NEXT: lb a0, 13(sp)
; RV64IPN-NEXT: add a1, a5, t0
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sb a0, 1(sp)
; RV64IPN-NEXT: lb a0, 12(sp)
; RV64IPN-NEXT: add a1, a7, a6
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sb a0, 0(sp)
; RV64IPN-NEXT: lwu a0, 0(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <4 x i8>
%tmp2 = bitcast i32 %b to <4 x i8>
%imm = bitcast i32 1 to <4 x i8>
%add = add <4 x i8> %tmp1, %tmp2
%and = and <4 x i8> %add, %imm
%res = bitcast <4 x i8> %and to i32
ret i32 %res
}
define signext i32 @andiv2i16(i32 signext %a, i32 signext %b) nounwind {
; RV64IP-LABEL: andiv2i16:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sw a1, 4(sp)
; RV64IP-NEXT: sw a0, 8(sp)
; RV64IP-NEXT: lh a0, 6(sp)
; RV64IP-NEXT: lh a1, 10(sp)
; RV64IP-NEXT: lh a2, 4(sp)
; RV64IP-NEXT: lh a3, 8(sp)
; RV64IP-NEXT: addi a4, zero, 1
; RV64IP-NEXT: slli a4, a4, 32
; RV64IP-NEXT: addi a4, a4, -2
; RV64IP-NEXT: sw a4, 12(sp)
; RV64IP-NEXT: lh a4, 14(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: and a0, a0, a4
; RV64IP-NEXT: sh a0, 2(sp)
; RV64IP-NEXT: lh a0, 12(sp)
; RV64IP-NEXT: add a1, a3, a2
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sh a0, 0(sp)
; RV64IP-NEXT: lw a0, 0(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: andiv2i16:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sw a1, 4(sp)
; RV64IPN-NEXT: sw a0, 8(sp)
; RV64IPN-NEXT: lh a0, 6(sp)
; RV64IPN-NEXT: lh a1, 10(sp)
; RV64IPN-NEXT: lh a2, 4(sp)
; RV64IPN-NEXT: lh a3, 8(sp)
; RV64IPN-NEXT: addi a4, zero, 1
; RV64IPN-NEXT: slli a4, a4, 32
; RV64IPN-NEXT: addi a4, a4, -2
; RV64IPN-NEXT: sw a4, 12(sp)
; RV64IPN-NEXT: lh a4, 14(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: and a0, a0, a4
; RV64IPN-NEXT: sh a0, 2(sp)
; RV64IPN-NEXT: lh a0, 12(sp)
; RV64IPN-NEXT: add a1, a3, a2
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sh a0, 0(sp)
; RV64IPN-NEXT: lw a0, 0(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <2 x i16>
%tmp2 = bitcast i32 %b to <2 x i16>
%imm = bitcast i32 -2 to <2 x i16>
%add = add <2 x i16> %tmp1, %tmp2
%and = and <2 x i16> %add, %imm
%res = bitcast <2 x i16> %and to i32
ret i32 %res
}
define i64 @andiv8i8(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: andiv8i8:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -48
; RV64IP-NEXT: sd s0, 40(sp) # 8-byte Folded Spill
; RV64IP-NEXT: sd s1, 32(sp) # 8-byte Folded Spill
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lb a6, 16(sp)
; RV64IP-NEXT: lb a7, 8(sp)
; RV64IP-NEXT: lb t0, 17(sp)
; RV64IP-NEXT: lb t1, 9(sp)
; RV64IP-NEXT: lb t2, 18(sp)
; RV64IP-NEXT: lb t3, 10(sp)
; RV64IP-NEXT: lb t4, 19(sp)
; RV64IP-NEXT: lb t5, 11(sp)
; RV64IP-NEXT: lb t6, 20(sp)
; RV64IP-NEXT: lb a3, 12(sp)
; RV64IP-NEXT: lb a4, 21(sp)
; RV64IP-NEXT: lb a5, 13(sp)
; RV64IP-NEXT: lb a0, 22(sp)
; RV64IP-NEXT: lb a1, 14(sp)
; RV64IP-NEXT: lb a2, 23(sp)
; RV64IP-NEXT: lb s0, 15(sp)
; RV64IP-NEXT: addi s1, zero, -3
; RV64IP-NEXT: sd s1, 0(sp)
; RV64IP-NEXT: lb s1, 7(sp)
; RV64IP-NEXT: add a2, s0, a2
; RV64IP-NEXT: and a2, a2, s1
; RV64IP-NEXT: sb a2, 31(sp)
; RV64IP-NEXT: lb a2, 6(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: and a0, a0, a2
; RV64IP-NEXT: sb a0, 30(sp)
; RV64IP-NEXT: lb a0, 5(sp)
; RV64IP-NEXT: add a1, a5, a4
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sb a0, 29(sp)
; RV64IP-NEXT: lb a0, 4(sp)
; RV64IP-NEXT: add a1, a3, t6
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sb a0, 28(sp)
; RV64IP-NEXT: lb a0, 3(sp)
; RV64IP-NEXT: add a1, t5, t4
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sb a0, 27(sp)
; RV64IP-NEXT: lb a0, 2(sp)
; RV64IP-NEXT: add a1, t3, t2
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sb a0, 26(sp)
; RV64IP-NEXT: lb a0, 1(sp)
; RV64IP-NEXT: add a1, t1, t0
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sb a0, 25(sp)
; RV64IP-NEXT: lb a0, 0(sp)
; RV64IP-NEXT: add a1, a7, a6
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sb a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: ld s1, 32(sp) # 8-byte Folded Reload
; RV64IP-NEXT: ld s0, 40(sp) # 8-byte Folded Reload
; RV64IP-NEXT: addi sp, sp, 48
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: andiv8i8:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -48
; RV64IPN-NEXT: sd s0, 40(sp) # 8-byte Folded Spill
; RV64IPN-NEXT: sd s1, 32(sp) # 8-byte Folded Spill
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lb a6, 16(sp)
; RV64IPN-NEXT: lb a7, 8(sp)
; RV64IPN-NEXT: lb t0, 17(sp)
; RV64IPN-NEXT: lb t1, 9(sp)
; RV64IPN-NEXT: lb t2, 18(sp)
; RV64IPN-NEXT: lb t3, 10(sp)
; RV64IPN-NEXT: lb t4, 19(sp)
; RV64IPN-NEXT: lb t5, 11(sp)
; RV64IPN-NEXT: lb t6, 20(sp)
; RV64IPN-NEXT: lb a3, 12(sp)
; RV64IPN-NEXT: lb a4, 21(sp)
; RV64IPN-NEXT: lb a5, 13(sp)
; RV64IPN-NEXT: lb a0, 22(sp)
; RV64IPN-NEXT: lb a1, 14(sp)
; RV64IPN-NEXT: lb a2, 23(sp)
; RV64IPN-NEXT: lb s0, 15(sp)
; RV64IPN-NEXT: addi s1, zero, -3
; RV64IPN-NEXT: sd s1, 0(sp)
; RV64IPN-NEXT: lb s1, 7(sp)
; RV64IPN-NEXT: add a2, s0, a2
; RV64IPN-NEXT: and a2, a2, s1
; RV64IPN-NEXT: sb a2, 31(sp)
; RV64IPN-NEXT: lb a2, 6(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: and a0, a0, a2
; RV64IPN-NEXT: sb a0, 30(sp)
; RV64IPN-NEXT: lb a0, 5(sp)
; RV64IPN-NEXT: add a1, a5, a4
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sb a0, 29(sp)
; RV64IPN-NEXT: lb a0, 4(sp)
; RV64IPN-NEXT: add a1, a3, t6
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sb a0, 28(sp)
; RV64IPN-NEXT: lb a0, 3(sp)
; RV64IPN-NEXT: add a1, t5, t4
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sb a0, 27(sp)
; RV64IPN-NEXT: lb a0, 2(sp)
; RV64IPN-NEXT: add a1, t3, t2
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sb a0, 26(sp)
; RV64IPN-NEXT: lb a0, 1(sp)
; RV64IPN-NEXT: add a1, t1, t0
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sb a0, 25(sp)
; RV64IPN-NEXT: lb a0, 0(sp)
; RV64IPN-NEXT: add a1, a7, a6
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sb a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: ld s1, 32(sp) # 8-byte Folded Reload
; RV64IPN-NEXT: ld s0, 40(sp) # 8-byte Folded Reload
; RV64IPN-NEXT: addi sp, sp, 48
; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <8 x i8>
%tmp2 = bitcast i64 %b to <8 x i8>
%imm = bitcast i64 -3 to <8 x i8>
%add = add <8 x i8> %tmp1, %tmp2
%and = and <8 x i8> %add, %imm
%res = bitcast <8 x i8> %and to i64
ret i64 %res
}
define i64 @andvi4i16(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: andvi4i16:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lh a6, 16(sp)
; RV64IP-NEXT: lh a7, 8(sp)
; RV64IP-NEXT: lh t0, 18(sp)
; RV64IP-NEXT: lh a3, 10(sp)
; RV64IP-NEXT: lh a4, 20(sp)
; RV64IP-NEXT: lh a5, 12(sp)
; RV64IP-NEXT: lh a0, 22(sp)
; RV64IP-NEXT: lh a1, 14(sp)
; RV64IP-NEXT: addi a2, zero, -4
; RV64IP-NEXT: sd a2, 0(sp)
; RV64IP-NEXT: lh a2, 6(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: and a0, a0, a2
; RV64IP-NEXT: sh a0, 30(sp)
; RV64IP-NEXT: lh a0, 4(sp)
; RV64IP-NEXT: add a1, a5, a4
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sh a0, 28(sp)
; RV64IP-NEXT: lh a0, 2(sp)
; RV64IP-NEXT: add a1, a3, t0
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sh a0, 26(sp)
; RV64IP-NEXT: lh a0, 0(sp)
; RV64IP-NEXT: add a1, a7, a6
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sh a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: andvi4i16:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lh a6, 16(sp)
; RV64IPN-NEXT: lh a7, 8(sp)
; RV64IPN-NEXT: lh t0, 18(sp)
; RV64IPN-NEXT: lh a3, 10(sp)
; RV64IPN-NEXT: lh a4, 20(sp)
; RV64IPN-NEXT: lh a5, 12(sp)
; RV64IPN-NEXT: lh a0, 22(sp)
; RV64IPN-NEXT: lh a1, 14(sp)
; RV64IPN-NEXT: addi a2, zero, -4
; RV64IPN-NEXT: sd a2, 0(sp)
; RV64IPN-NEXT: lh a2, 6(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: and a0, a0, a2
; RV64IPN-NEXT: sh a0, 30(sp)
; RV64IPN-NEXT: lh a0, 4(sp)
; RV64IPN-NEXT: add a1, a5, a4
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sh a0, 28(sp)
; RV64IPN-NEXT: lh a0, 2(sp)
; RV64IPN-NEXT: add a1, a3, t0
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sh a0, 26(sp)
; RV64IPN-NEXT: lh a0, 0(sp)
; RV64IPN-NEXT: add a1, a7, a6
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sh a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <4 x i16>
%tmp2 = bitcast i64 %b to <4 x i16>
%imm = bitcast i64 -4 to <4 x i16>
%add = add <4 x i16> %tmp1, %tmp2
%and = and <4 x i16> %add, %imm
%res = bitcast <4 x i16> %and to i64
ret i64 %res
}
define i64 @andiv2i32(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: andiv2i32:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lw a0, 16(sp)
; RV64IP-NEXT: lw a1, 8(sp)
; RV64IP-NEXT: lw a2, 20(sp)
; RV64IP-NEXT: lw a3, 12(sp)
; RV64IP-NEXT: addi a4, zero, -5
; RV64IP-NEXT: sd a4, 0(sp)
; RV64IP-NEXT: lw a4, 4(sp)
; RV64IP-NEXT: add a2, a3, a2
; RV64IP-NEXT: and a2, a2, a4
; RV64IP-NEXT: sw a2, 28(sp)
; RV64IP-NEXT: lw a2, 0(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: and a0, a0, a2
; RV64IP-NEXT: sw a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: andiv2i32:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lw a0, 16(sp)
; RV64IPN-NEXT: lw a1, 8(sp)
; RV64IPN-NEXT: lw a2, 20(sp)
; RV64IPN-NEXT: lw a3, 12(sp)
; RV64IPN-NEXT: addi a4, zero, -5
; RV64IPN-NEXT: sd a4, 0(sp)
; RV64IPN-NEXT: lw a4, 4(sp)
; RV64IPN-NEXT: add a2, a3, a2
; RV64IPN-NEXT: and a2, a2, a4
; RV64IPN-NEXT: sw a2, 28(sp)
; RV64IPN-NEXT: lw a2, 0(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: and a0, a0, a2
; RV64IPN-NEXT: sw a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <2 x i32>
%tmp2 = bitcast i64 %b to <2 x i32>
%imm = bitcast i64 -5 to <2 x i32>
%add = add <2 x i32> %tmp1, %tmp2
%and = and <2 x i32> %add, %imm
%res = bitcast <2 x i32> %and to i64
ret i64 %res
}
define signext i32 @oriv4i8(i32 signext %a, i32 signext %b) nounwind {
; RV64IP-LABEL: oriv4i8:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sw a1, 4(sp)
; RV64IP-NEXT: sw a0, 8(sp)
; RV64IP-NEXT: lb a0, 7(sp)
; RV64IP-NEXT: lb a1, 11(sp)
; RV64IP-NEXT: lb a2, 6(sp)
; RV64IP-NEXT: lb a3, 10(sp)
; RV64IP-NEXT: lb t0, 5(sp)
; RV64IP-NEXT: lb a5, 9(sp)
; RV64IP-NEXT: lb a6, 4(sp)
; RV64IP-NEXT: lb a7, 8(sp)
; RV64IP-NEXT: addi a4, zero, 1
; RV64IP-NEXT: sw a4, 12(sp)
; RV64IP-NEXT: lb a4, 15(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: or a0, a0, a4
; RV64IP-NEXT: sb a0, 3(sp)
; RV64IP-NEXT: lb a0, 14(sp)
; RV64IP-NEXT: add a1, a3, a2
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sb a0, 2(sp)
; RV64IP-NEXT: lb a0, 13(sp)
; RV64IP-NEXT: add a1, a5, t0
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sb a0, 1(sp)
; RV64IP-NEXT: lb a0, 12(sp)
; RV64IP-NEXT: add a1, a7, a6
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sb a0, 0(sp)
; RV64IP-NEXT: lw a0, 0(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: oriv4i8:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sw a1, 4(sp)
; RV64IPN-NEXT: sw a0, 8(sp)
; RV64IPN-NEXT: lb a0, 7(sp)
; RV64IPN-NEXT: lb a1, 11(sp)
; RV64IPN-NEXT: lb a2, 6(sp)
; RV64IPN-NEXT: lb a3, 10(sp)
; RV64IPN-NEXT: lb t0, 5(sp)
; RV64IPN-NEXT: lb a5, 9(sp)
; RV64IPN-NEXT: lb a6, 4(sp)
; RV64IPN-NEXT: lb a7, 8(sp)
; RV64IPN-NEXT: addi a4, zero, 1
; RV64IPN-NEXT: sw a4, 12(sp)
; RV64IPN-NEXT: lb a4, 15(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: or a0, a0, a4
; RV64IPN-NEXT: sb a0, 3(sp)
; RV64IPN-NEXT: lb a0, 14(sp)
; RV64IPN-NEXT: add a1, a3, a2
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sb a0, 2(sp)
; RV64IPN-NEXT: lb a0, 13(sp)
; RV64IPN-NEXT: add a1, a5, t0
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sb a0, 1(sp)
; RV64IPN-NEXT: lb a0, 12(sp)
; RV64IPN-NEXT: add a1, a7, a6
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sb a0, 0(sp)
; RV64IPN-NEXT: lw a0, 0(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <4 x i8>
%tmp2 = bitcast i32 %b to <4 x i8>
%imm = bitcast i32 1 to <4 x i8>
%add = add <4 x i8> %tmp1, %tmp2
%or = or <4 x i8> %add, %imm
%res = bitcast <4 x i8> %or to i32
ret i32 %res
}
define signext i32 @oriv2i16(i32 signext %a, i32 signext %b) nounwind {
; RV64IP-LABEL: oriv2i16:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sw a1, 4(sp)
; RV64IP-NEXT: sw a0, 8(sp)
; RV64IP-NEXT: lh a0, 6(sp)
; RV64IP-NEXT: lh a1, 10(sp)
; RV64IP-NEXT: lh a2, 4(sp)
; RV64IP-NEXT: lh a3, 8(sp)
; RV64IP-NEXT: addi a4, zero, 1
; RV64IP-NEXT: slli a4, a4, 32
; RV64IP-NEXT: addi a4, a4, -2
; RV64IP-NEXT: sw a4, 12(sp)
; RV64IP-NEXT: lh a4, 14(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: or a0, a0, a4
; RV64IP-NEXT: sh a0, 2(sp)
; RV64IP-NEXT: lh a0, 12(sp)
; RV64IP-NEXT: add a1, a3, a2
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sh a0, 0(sp)
; RV64IP-NEXT: lw a0, 0(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: oriv2i16:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sw a1, 4(sp)
; RV64IPN-NEXT: sw a0, 8(sp)
; RV64IPN-NEXT: lh a0, 6(sp)
; RV64IPN-NEXT: lh a1, 10(sp)
; RV64IPN-NEXT: lh a2, 4(sp)
; RV64IPN-NEXT: lh a3, 8(sp)
; RV64IPN-NEXT: addi a4, zero, 1
; RV64IPN-NEXT: slli a4, a4, 32
; RV64IPN-NEXT: addi a4, a4, -2
; RV64IPN-NEXT: sw a4, 12(sp)
; RV64IPN-NEXT: lh a4, 14(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: or a0, a0, a4
; RV64IPN-NEXT: sh a0, 2(sp)
; RV64IPN-NEXT: lh a0, 12(sp)
; RV64IPN-NEXT: add a1, a3, a2
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sh a0, 0(sp)
; RV64IPN-NEXT: lw a0, 0(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <2 x i16>
%tmp2 = bitcast i32 %b to <2 x i16>
%imm = bitcast i32 -2 to <2 x i16>
%add = add <2 x i16> %tmp1, %tmp2
%or = or <2 x i16> %add, %imm
%res = bitcast <2 x i16> %or to i32
ret i32 %res
}
define i64 @oriv8i8(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: oriv8i8:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -48
; RV64IP-NEXT: sd s0, 40(sp) # 8-byte Folded Spill
; RV64IP-NEXT: sd s1, 32(sp) # 8-byte Folded Spill
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lb a6, 16(sp)
; RV64IP-NEXT: lb a7, 8(sp)
; RV64IP-NEXT: lb t0, 17(sp)
; RV64IP-NEXT: lb t1, 9(sp)
; RV64IP-NEXT: lb t2, 18(sp)
; RV64IP-NEXT: lb t3, 10(sp)
; RV64IP-NEXT: lb t4, 19(sp)
; RV64IP-NEXT: lb t5, 11(sp)
; RV64IP-NEXT: lb t6, 20(sp)
; RV64IP-NEXT: lb a3, 12(sp)
; RV64IP-NEXT: lb a4, 21(sp)
; RV64IP-NEXT: lb a5, 13(sp)
; RV64IP-NEXT: lb a0, 22(sp)
; RV64IP-NEXT: lb a1, 14(sp)
; RV64IP-NEXT: lb a2, 23(sp)
; RV64IP-NEXT: lb s0, 15(sp)
; RV64IP-NEXT: addi s1, zero, -3
; RV64IP-NEXT: sd s1, 0(sp)
; RV64IP-NEXT: lb s1, 7(sp)
; RV64IP-NEXT: add a2, s0, a2
; RV64IP-NEXT: or a2, a2, s1
; RV64IP-NEXT: sb a2, 31(sp)
; RV64IP-NEXT: lb a2, 6(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: or a0, a0, a2
; RV64IP-NEXT: sb a0, 30(sp)
; RV64IP-NEXT: lb a0, 5(sp)
; RV64IP-NEXT: add a1, a5, a4
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sb a0, 29(sp)
; RV64IP-NEXT: lb a0, 4(sp)
; RV64IP-NEXT: add a1, a3, t6
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sb a0, 28(sp)
; RV64IP-NEXT: lb a0, 3(sp)
; RV64IP-NEXT: add a1, t5, t4
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sb a0, 27(sp)
; RV64IP-NEXT: lb a0, 2(sp)
; RV64IP-NEXT: add a1, t3, t2
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sb a0, 26(sp)
; RV64IP-NEXT: lb a0, 1(sp)
; RV64IP-NEXT: add a1, t1, t0
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sb a0, 25(sp)
; RV64IP-NEXT: lb a0, 0(sp)
; RV64IP-NEXT: add a1, a7, a6
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sb a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: ld s1, 32(sp) # 8-byte Folded Reload
; RV64IP-NEXT: ld s0, 40(sp) # 8-byte Folded Reload
; RV64IP-NEXT: addi sp, sp, 48
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: oriv8i8:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -48
; RV64IPN-NEXT: sd s0, 40(sp) # 8-byte Folded Spill
; RV64IPN-NEXT: sd s1, 32(sp) # 8-byte Folded Spill
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lb a6, 16(sp)
; RV64IPN-NEXT: lb a7, 8(sp)
; RV64IPN-NEXT: lb t0, 17(sp)
; RV64IPN-NEXT: lb t1, 9(sp)
; RV64IPN-NEXT: lb t2, 18(sp)
; RV64IPN-NEXT: lb t3, 10(sp)
; RV64IPN-NEXT: lb t4, 19(sp)
; RV64IPN-NEXT: lb t5, 11(sp)
; RV64IPN-NEXT: lb t6, 20(sp)
; RV64IPN-NEXT: lb a3, 12(sp)
; RV64IPN-NEXT: lb a4, 21(sp)
; RV64IPN-NEXT: lb a5, 13(sp)
; RV64IPN-NEXT: lb a0, 22(sp)
; RV64IPN-NEXT: lb a1, 14(sp)
; RV64IPN-NEXT: lb a2, 23(sp)
; RV64IPN-NEXT: lb s0, 15(sp)
; RV64IPN-NEXT: addi s1, zero, -3
; RV64IPN-NEXT: sd s1, 0(sp)
; RV64IPN-NEXT: lb s1, 7(sp)
; RV64IPN-NEXT: add a2, s0, a2
; RV64IPN-NEXT: or a2, a2, s1
; RV64IPN-NEXT: sb a2, 31(sp)
; RV64IPN-NEXT: lb a2, 6(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: or a0, a0, a2
; RV64IPN-NEXT: sb a0, 30(sp)
; RV64IPN-NEXT: lb a0, 5(sp)
; RV64IPN-NEXT: add a1, a5, a4
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sb a0, 29(sp)
; RV64IPN-NEXT: lb a0, 4(sp)
; RV64IPN-NEXT: add a1, a3, t6
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sb a0, 28(sp)
; RV64IPN-NEXT: lb a0, 3(sp)
; RV64IPN-NEXT: add a1, t5, t4
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sb a0, 27(sp)
; RV64IPN-NEXT: lb a0, 2(sp)
; RV64IPN-NEXT: add a1, t3, t2
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sb a0, 26(sp)
; RV64IPN-NEXT: lb a0, 1(sp)
; RV64IPN-NEXT: add a1, t1, t0
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sb a0, 25(sp)
; RV64IPN-NEXT: lb a0, 0(sp)
; RV64IPN-NEXT: add a1, a7, a6
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sb a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: ld s1, 32(sp) # 8-byte Folded Reload
; RV64IPN-NEXT: ld s0, 40(sp) # 8-byte Folded Reload
; RV64IPN-NEXT: addi sp, sp, 48
; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <8 x i8>
%tmp2 = bitcast i64 %b to <8 x i8>
%imm = bitcast i64 -3 to <8 x i8>
%add = add <8 x i8> %tmp1, %tmp2
%or = or <8 x i8> %add, %imm
%res = bitcast <8 x i8> %or to i64
ret i64 %res
}
define i64 @orvi4i16(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: orvi4i16:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lh a6, 16(sp)
; RV64IP-NEXT: lh a7, 8(sp)
; RV64IP-NEXT: lh t0, 18(sp)
; RV64IP-NEXT: lh a3, 10(sp)
; RV64IP-NEXT: lh a4, 20(sp)
; RV64IP-NEXT: lh a5, 12(sp)
; RV64IP-NEXT: lh a0, 22(sp)
; RV64IP-NEXT: lh a1, 14(sp)
; RV64IP-NEXT: addi a2, zero, -4
; RV64IP-NEXT: sd a2, 0(sp)
; RV64IP-NEXT: lh a2, 6(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: or a0, a0, a2
; RV64IP-NEXT: sh a0, 30(sp)
; RV64IP-NEXT: lh a0, 4(sp)
; RV64IP-NEXT: add a1, a5, a4
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sh a0, 28(sp)
; RV64IP-NEXT: lh a0, 2(sp)
; RV64IP-NEXT: add a1, a3, t0
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sh a0, 26(sp)
; RV64IP-NEXT: lh a0, 0(sp)
; RV64IP-NEXT: add a1, a7, a6
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sh a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: orvi4i16:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lh a6, 16(sp)
; RV64IPN-NEXT: lh a7, 8(sp)
; RV64IPN-NEXT: lh t0, 18(sp)
; RV64IPN-NEXT: lh a3, 10(sp)
; RV64IPN-NEXT: lh a4, 20(sp)
; RV64IPN-NEXT: lh a5, 12(sp)
; RV64IPN-NEXT: lh a0, 22(sp)
; RV64IPN-NEXT: lh a1, 14(sp)
; RV64IPN-NEXT: addi a2, zero, -4
; RV64IPN-NEXT: sd a2, 0(sp)
; RV64IPN-NEXT: lh a2, 6(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: or a0, a0, a2
; RV64IPN-NEXT: sh a0, 30(sp)
; RV64IPN-NEXT: lh a0, 4(sp)
; RV64IPN-NEXT: add a1, a5, a4
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sh a0, 28(sp)
; RV64IPN-NEXT: lh a0, 2(sp)
; RV64IPN-NEXT: add a1, a3, t0
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sh a0, 26(sp)
; RV64IPN-NEXT: lh a0, 0(sp)
; RV64IPN-NEXT: add a1, a7, a6
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sh a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <4 x i16>
%tmp2 = bitcast i64 %b to <4 x i16>
%imm = bitcast i64 -4 to <4 x i16>
%add = add <4 x i16> %tmp1, %tmp2
%or = or <4 x i16> %add, %imm
%res = bitcast <4 x i16> %or to i64
ret i64 %res
}
define i64 @oriv2i32(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: oriv2i32:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lw a0, 16(sp)
; RV64IP-NEXT: lw a1, 8(sp)
; RV64IP-NEXT: lw a2, 20(sp)
; RV64IP-NEXT: lw a3, 12(sp)
; RV64IP-NEXT: addi a4, zero, -5
; RV64IP-NEXT: sd a4, 0(sp)
; RV64IP-NEXT: lw a4, 4(sp)
; RV64IP-NEXT: add a2, a3, a2
; RV64IP-NEXT: or a2, a2, a4
; RV64IP-NEXT: sw a2, 28(sp)
; RV64IP-NEXT: lw a2, 0(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: or a0, a0, a2
; RV64IP-NEXT: sw a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: oriv2i32:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lw a0, 16(sp)
; RV64IPN-NEXT: lw a1, 8(sp)
; RV64IPN-NEXT: lw a2, 20(sp)
; RV64IPN-NEXT: lw a3, 12(sp)
; RV64IPN-NEXT: addi a4, zero, -5
; RV64IPN-NEXT: sd a4, 0(sp)
; RV64IPN-NEXT: lw a4, 4(sp)
; RV64IPN-NEXT: add a2, a3, a2
; RV64IPN-NEXT: or a2, a2, a4
; RV64IPN-NEXT: sw a2, 28(sp)
; RV64IPN-NEXT: lw a2, 0(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: or a0, a0, a2
; RV64IPN-NEXT: sw a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <2 x i32>
%tmp2 = bitcast i64 %b to <2 x i32>
%imm = bitcast i64 -5 to <2 x i32>
%add = add <2 x i32> %tmp1, %tmp2
%or = or <2 x i32> %add, %imm
%res = bitcast <2 x i32> %or to i64
ret i64 %res
}
define signext i32 @xoriv4i8(i32 signext %a, i32 signext %b) nounwind {
; RV64IP-LABEL: xoriv4i8:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sw a1, 4(sp)
; RV64IP-NEXT: sw a0, 8(sp)
; RV64IP-NEXT: lb a0, 7(sp)
; RV64IP-NEXT: lb a1, 11(sp)
; RV64IP-NEXT: lb a2, 6(sp)
; RV64IP-NEXT: lb a3, 10(sp)
; RV64IP-NEXT: lb t0, 5(sp)
; RV64IP-NEXT: lb a5, 9(sp)
; RV64IP-NEXT: lb a6, 4(sp)
; RV64IP-NEXT: lb a7, 8(sp)
; RV64IP-NEXT: addi a4, zero, -1
; RV64IP-NEXT: srli a4, a4, 32
; RV64IP-NEXT: sw a4, 12(sp)
; RV64IP-NEXT: lb a4, 15(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: xor a0, a0, a4
; RV64IP-NEXT: sb a0, 3(sp)
; RV64IP-NEXT: lb a0, 14(sp)
; RV64IP-NEXT: add a1, a3, a2
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sb a0, 2(sp)
; RV64IP-NEXT: lb a0, 13(sp)
; RV64IP-NEXT: add a1, a5, t0
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sb a0, 1(sp)
; RV64IP-NEXT: lb a0, 12(sp)
; RV64IP-NEXT: add a1, a7, a6
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sb a0, 0(sp)
; RV64IP-NEXT: lw a0, 0(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: xoriv4i8:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sw a1, 4(sp)
; RV64IPN-NEXT: sw a0, 8(sp)
; RV64IPN-NEXT: lb a0, 7(sp)
; RV64IPN-NEXT: lb a1, 11(sp)
; RV64IPN-NEXT: lb a2, 6(sp)
; RV64IPN-NEXT: lb a3, 10(sp)
; RV64IPN-NEXT: lb t0, 5(sp)
; RV64IPN-NEXT: lb a5, 9(sp)
; RV64IPN-NEXT: lb a6, 4(sp)
; RV64IPN-NEXT: lb a7, 8(sp)
; RV64IPN-NEXT: addi a4, zero, -1
; RV64IPN-NEXT: srli a4, a4, 32
; RV64IPN-NEXT: sw a4, 12(sp)
; RV64IPN-NEXT: lb a4, 15(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: xor a0, a0, a4
; RV64IPN-NEXT: sb a0, 3(sp)
; RV64IPN-NEXT: lb a0, 14(sp)
; RV64IPN-NEXT: add a1, a3, a2
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sb a0, 2(sp)
; RV64IPN-NEXT: lb a0, 13(sp)
; RV64IPN-NEXT: add a1, a5, t0
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sb a0, 1(sp)
; RV64IPN-NEXT: lb a0, 12(sp)
; RV64IPN-NEXT: add a1, a7, a6
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sb a0, 0(sp)
; RV64IPN-NEXT: lw a0, 0(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <4 x i8>
%tmp2 = bitcast i32 %b to <4 x i8>
%imm = bitcast i32 -1 to <4 x i8>
%add = add <4 x i8> %tmp1, %tmp2
%xor = xor <4 x i8> %add, %imm
%res = bitcast <4 x i8> %xor to i32
ret i32 %res
}
define signext i32 @xoriv2i16(i32 signext %a, i32 signext %b) nounwind {
; RV64IP-LABEL: xoriv2i16:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16
; RV64IP-NEXT: sw a1, 4(sp)
; RV64IP-NEXT: sw a0, 8(sp)
; RV64IP-NEXT: lh a0, 6(sp)
; RV64IP-NEXT: lh a1, 10(sp)
; RV64IP-NEXT: lh a2, 4(sp)
; RV64IP-NEXT: lh a3, 8(sp)
; RV64IP-NEXT: addi a4, zero, 1
; RV64IP-NEXT: slli a4, a4, 32
; RV64IP-NEXT: addi a4, a4, -2
; RV64IP-NEXT: sw a4, 12(sp)
; RV64IP-NEXT: lh a4, 14(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: xor a0, a0, a4
; RV64IP-NEXT: sh a0, 2(sp)
; RV64IP-NEXT: lh a0, 12(sp)
; RV64IP-NEXT: add a1, a3, a2
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sh a0, 0(sp)
; RV64IP-NEXT: lw a0, 0(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: xoriv2i16:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16
; RV64IPN-NEXT: sw a1, 4(sp)
; RV64IPN-NEXT: sw a0, 8(sp)
; RV64IPN-NEXT: lh a0, 6(sp)
; RV64IPN-NEXT: lh a1, 10(sp)
; RV64IPN-NEXT: lh a2, 4(sp)
; RV64IPN-NEXT: lh a3, 8(sp)
; RV64IPN-NEXT: addi a4, zero, 1
; RV64IPN-NEXT: slli a4, a4, 32
; RV64IPN-NEXT: addi a4, a4, -2
; RV64IPN-NEXT: sw a4, 12(sp)
; RV64IPN-NEXT: lh a4, 14(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: xor a0, a0, a4
; RV64IPN-NEXT: sh a0, 2(sp)
; RV64IPN-NEXT: lh a0, 12(sp)
; RV64IPN-NEXT: add a1, a3, a2
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sh a0, 0(sp)
; RV64IPN-NEXT: lw a0, 0(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <2 x i16>
%tmp2 = bitcast i32 %b to <2 x i16>
%imm = bitcast i32 -2 to <2 x i16>
%add = add <2 x i16> %tmp1, %tmp2
%xor = xor <2 x i16> %add, %imm
%res = bitcast <2 x i16> %xor to i32
ret i32 %res
}
define i64 @xoriv8i8(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: xoriv8i8:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -48
; RV64IP-NEXT: sd s0, 40(sp) # 8-byte Folded Spill
; RV64IP-NEXT: sd s1, 32(sp) # 8-byte Folded Spill
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lb a6, 16(sp)
; RV64IP-NEXT: lb a7, 8(sp)
; RV64IP-NEXT: lb t0, 17(sp)
; RV64IP-NEXT: lb t1, 9(sp)
; RV64IP-NEXT: lb t2, 18(sp)
; RV64IP-NEXT: lb t3, 10(sp)
; RV64IP-NEXT: lb t4, 19(sp)
; RV64IP-NEXT: lb t5, 11(sp)
; RV64IP-NEXT: lb t6, 20(sp)
; RV64IP-NEXT: lb a3, 12(sp)
; RV64IP-NEXT: lb a4, 21(sp)
; RV64IP-NEXT: lb a5, 13(sp)
; RV64IP-NEXT: lb a0, 22(sp)
; RV64IP-NEXT: lb a1, 14(sp)
; RV64IP-NEXT: lb a2, 23(sp)
; RV64IP-NEXT: lb s0, 15(sp)
; RV64IP-NEXT: addi s1, zero, -3
; RV64IP-NEXT: sd s1, 0(sp)
; RV64IP-NEXT: lb s1, 7(sp)
; RV64IP-NEXT: add a2, s0, a2
; RV64IP-NEXT: xor a2, a2, s1
; RV64IP-NEXT: sb a2, 31(sp)
; RV64IP-NEXT: lb a2, 6(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: xor a0, a0, a2
; RV64IP-NEXT: sb a0, 30(sp)
; RV64IP-NEXT: lb a0, 5(sp)
; RV64IP-NEXT: add a1, a5, a4
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sb a0, 29(sp)
; RV64IP-NEXT: lb a0, 4(sp)
; RV64IP-NEXT: add a1, a3, t6
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sb a0, 28(sp)
; RV64IP-NEXT: lb a0, 3(sp)
; RV64IP-NEXT: add a1, t5, t4
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sb a0, 27(sp)
; RV64IP-NEXT: lb a0, 2(sp)
; RV64IP-NEXT: add a1, t3, t2
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sb a0, 26(sp)
; RV64IP-NEXT: lb a0, 1(sp)
; RV64IP-NEXT: add a1, t1, t0
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sb a0, 25(sp)
; RV64IP-NEXT: lb a0, 0(sp)
; RV64IP-NEXT: add a1, a7, a6
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sb a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: ld s1, 32(sp) # 8-byte Folded Reload
; RV64IP-NEXT: ld s0, 40(sp) # 8-byte Folded Reload
; RV64IP-NEXT: addi sp, sp, 48
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: xoriv8i8:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -48
; RV64IPN-NEXT: sd s0, 40(sp) # 8-byte Folded Spill
; RV64IPN-NEXT: sd s1, 32(sp) # 8-byte Folded Spill
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lb a6, 16(sp)
; RV64IPN-NEXT: lb a7, 8(sp)
; RV64IPN-NEXT: lb t0, 17(sp)
; RV64IPN-NEXT: lb t1, 9(sp)
; RV64IPN-NEXT: lb t2, 18(sp)
; RV64IPN-NEXT: lb t3, 10(sp)
; RV64IPN-NEXT: lb t4, 19(sp)
; RV64IPN-NEXT: lb t5, 11(sp)
; RV64IPN-NEXT: lb t6, 20(sp)
; RV64IPN-NEXT: lb a3, 12(sp)
; RV64IPN-NEXT: lb a4, 21(sp)
; RV64IPN-NEXT: lb a5, 13(sp)
; RV64IPN-NEXT: lb a0, 22(sp)
; RV64IPN-NEXT: lb a1, 14(sp)
; RV64IPN-NEXT: lb a2, 23(sp)
; RV64IPN-NEXT: lb s0, 15(sp)
; RV64IPN-NEXT: addi s1, zero, -3
; RV64IPN-NEXT: sd s1, 0(sp)
; RV64IPN-NEXT: lb s1, 7(sp)
; RV64IPN-NEXT: add a2, s0, a2
; RV64IPN-NEXT: xor a2, a2, s1
; RV64IPN-NEXT: sb a2, 31(sp)
; RV64IPN-NEXT: lb a2, 6(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: xor a0, a0, a2
; RV64IPN-NEXT: sb a0, 30(sp)
; RV64IPN-NEXT: lb a0, 5(sp)
; RV64IPN-NEXT: add a1, a5, a4
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sb a0, 29(sp)
; RV64IPN-NEXT: lb a0, 4(sp)
; RV64IPN-NEXT: add a1, a3, t6
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sb a0, 28(sp)
; RV64IPN-NEXT: lb a0, 3(sp)
; RV64IPN-NEXT: add a1, t5, t4
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sb a0, 27(sp)
; RV64IPN-NEXT: lb a0, 2(sp)
; RV64IPN-NEXT: add a1, t3, t2
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sb a0, 26(sp)
; RV64IPN-NEXT: lb a0, 1(sp)
; RV64IPN-NEXT: add a1, t1, t0
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sb a0, 25(sp)
; RV64IPN-NEXT: lb a0, 0(sp)
; RV64IPN-NEXT: add a1, a7, a6
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sb a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: ld s1, 32(sp) # 8-byte Folded Reload
; RV64IPN-NEXT: ld s0, 40(sp) # 8-byte Folded Reload
; RV64IPN-NEXT: addi sp, sp, 48
; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <8 x i8>
%tmp2 = bitcast i64 %b to <8 x i8>
%imm = bitcast i64 -3 to <8 x i8>
%add = add <8 x i8> %tmp1, %tmp2
%xor = xor <8 x i8> %add, %imm
%res = bitcast <8 x i8> %xor to i64
ret i64 %res
}
define i64 @xorvi4i16(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: xorvi4i16:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lh a6, 16(sp)
; RV64IP-NEXT: lh a7, 8(sp)
; RV64IP-NEXT: lh t0, 18(sp)
; RV64IP-NEXT: lh a3, 10(sp)
; RV64IP-NEXT: lh a4, 20(sp)
; RV64IP-NEXT: lh a5, 12(sp)
; RV64IP-NEXT: lh a0, 22(sp)
; RV64IP-NEXT: lh a1, 14(sp)
; RV64IP-NEXT: addi a2, zero, -4
; RV64IP-NEXT: sd a2, 0(sp)
; RV64IP-NEXT: lh a2, 6(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: xor a0, a0, a2
; RV64IP-NEXT: sh a0, 30(sp)
; RV64IP-NEXT: lh a0, 4(sp)
; RV64IP-NEXT: add a1, a5, a4
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sh a0, 28(sp)
; RV64IP-NEXT: lh a0, 2(sp)
; RV64IP-NEXT: add a1, a3, t0
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sh a0, 26(sp)
; RV64IP-NEXT: lh a0, 0(sp)
; RV64IP-NEXT: add a1, a7, a6
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sh a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: xorvi4i16:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lh a6, 16(sp)
; RV64IPN-NEXT: lh a7, 8(sp)
; RV64IPN-NEXT: lh t0, 18(sp)
; RV64IPN-NEXT: lh a3, 10(sp)
; RV64IPN-NEXT: lh a4, 20(sp)
; RV64IPN-NEXT: lh a5, 12(sp)
; RV64IPN-NEXT: lh a0, 22(sp)
; RV64IPN-NEXT: lh a1, 14(sp)
; RV64IPN-NEXT: addi a2, zero, -4
; RV64IPN-NEXT: sd a2, 0(sp)
; RV64IPN-NEXT: lh a2, 6(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: xor a0, a0, a2
; RV64IPN-NEXT: sh a0, 30(sp)
; RV64IPN-NEXT: lh a0, 4(sp)
; RV64IPN-NEXT: add a1, a5, a4
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sh a0, 28(sp)
; RV64IPN-NEXT: lh a0, 2(sp)
; RV64IPN-NEXT: add a1, a3, t0
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sh a0, 26(sp)
; RV64IPN-NEXT: lh a0, 0(sp)
; RV64IPN-NEXT: add a1, a7, a6
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sh a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <4 x i16>
%tmp2 = bitcast i64 %b to <4 x i16>
%imm = bitcast i64 -4 to <4 x i16>
%add = add <4 x i16> %tmp1, %tmp2
%xor = xor <4 x i16> %add, %imm
%res = bitcast <4 x i16> %xor to i64
ret i64 %res
}
define i64 @xoriv2i32(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: xoriv2i32:
; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lw a0, 16(sp)
; RV64IP-NEXT: lw a1, 8(sp)
; RV64IP-NEXT: lw a2, 20(sp)
; RV64IP-NEXT: lw a3, 12(sp)
; RV64IP-NEXT: addi a4, zero, -5
; RV64IP-NEXT: sd a4, 0(sp)
; RV64IP-NEXT: lw a4, 4(sp)
; RV64IP-NEXT: add a2, a3, a2
; RV64IP-NEXT: xor a2, a2, a4
; RV64IP-NEXT: sw a2, 28(sp)
; RV64IP-NEXT: lw a2, 0(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: xor a0, a0, a2
; RV64IP-NEXT: sw a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret
;
; RV64IPN-LABEL: xoriv2i32:
; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lw a0, 16(sp)
; RV64IPN-NEXT: lw a1, 8(sp)
; RV64IPN-NEXT: lw a2, 20(sp)
; RV64IPN-NEXT: lw a3, 12(sp)
; RV64IPN-NEXT: addi a4, zero, -5
; RV64IPN-NEXT: sd a4, 0(sp)
; RV64IPN-NEXT: lw a4, 4(sp)
; RV64IPN-NEXT: add a2, a3, a2
; RV64IPN-NEXT: xor a2, a2, a4
; RV64IPN-NEXT: sw a2, 28(sp)
; RV64IPN-NEXT: lw a2, 0(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: xor a0, a0, a2
; RV64IPN-NEXT: sw a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <2 x i32>
%tmp2 = bitcast i64 %b to <2 x i32>
%imm = bitcast i64 -5 to <2 x i32>
%add = add <2 x i32> %tmp1, %tmp2
%xor = xor <2 x i32> %add, %imm
%res = bitcast <2 x i32> %xor to i64
ret i64 %res
}