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Differential D102467

[RISCV] Implement codegen patterns for RVP ALU operations
Needs ReviewPublic

Authored by Jim on May 13 2021, 10:14 PM.

Details

Reviewers
craig.topper
khchen
frasercrmck
HsiangKai
jrtc27
Summary

Add codegen patterns for vector add, sub, and, or and xor operations.

Diff Detail

Event Timeline

Jim created this revision.May 13 2021, 10:14 PM
Herald added subscribers: vkmr, frasercrmck, evandro and 24 others. · View Herald TranscriptMay 13 2021, 10:14 PM
Jim requested review of this revision.May 13 2021, 10:14 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 13 2021, 10:14 PM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B104435: Diff 345354.May 13 2021, 10:15 PM
Jim added reviewers: craig.topper, khchen, frasercrmck, HsiangKai, jrtc27.May 13 2021, 10:17 PM
Jim added a parent revision: D102466: [RISCV] Support RVP vectors in the calling convention.
Jim updated this revision to Diff 349825.Jun 4 2021, 5:03 AM

Add support for vector and, or and xor operations and
implement getPreferredVectorAction hook to widen v4i8 and v2i16 to v8i8 and v4i16 for RV64P.

Harbormaster completed remote builds in B107651: Diff 349825.Jun 4 2021, 5:04 AM
Jim edited parent revisions, added: D103687: [RISCV] Pre-commit test for D102467; removed: D102466: [RISCV] Support RVP vectors in the calling convention.Jun 4 2021, 5:04 AM
Jim retitled this revision from [RISCV] Implement codegen patterns for add8, add16, sub8 and sub16 to [RISCV] Implement codegen patterns for RVP ALU operations.Jun 4 2021, 5:07 AM
Jim edited the summary of this revision. (Show Details)
Jim added a child revision: D103688: [RISCV] Pre-commit test for D103689.Jun 4 2021, 5:20 AM
Jim updated this revision to Diff 350222.Jun 7 2021, 3:07 AM

Add codegen patterns for logic operation with immediate.

Harbormaster completed remote builds in B107941: Diff 350222.Jun 7 2021, 3:08 AM
Jim updated this revision to Diff 352116.Jun 15 2021, 6:25 AM

Move tests out of rvp directory.

Harbormaster completed remote builds in B109275: Diff 352116.Jun 15 2021, 6:26 AM

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
3 lines
14 lines
56 lines
test/
CodeGen/
RISCV/
1804 lines
2074 lines

Diff 352116

llvm/lib/Target/RISCV/RISCVISelLowering.h

Show First 20 Lines • Show All 312 Lines • ▼ Show 20 Linespublic:
/// should be stack expanded. /// should be stack expanded.
bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
bool hasBitPreservingFPLogic(EVT VT) const override; bool hasBitPreservingFPLogic(EVT VT) const override;
bool bool
shouldExpandBuildVectorWithShuffles(EVT VT, shouldExpandBuildVectorWithShuffles(EVT VT,
unsigned DefinedValues) const override; unsigned DefinedValues) const override;
TargetLoweringBase::LegalizeTypeAction
getPreferredVectorAction(MVT VT) const override;
// Provide custom lowering hooks for some operations. // Provide custom lowering hooks for some operations.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const override; SelectionDAG &DAG) const override;
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
▲ Show 20 Lines • Show All 284 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 821 Lines • ▼ Show 20 LinesRISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
} }
if (Subtarget.hasStdExtZpn()) { if (Subtarget.hasStdExtZpn()) {
const auto addTypeForP = [&](MVT VT, MVT PromotedBitwiseVT) { const auto addTypeForP = [&](MVT VT, MVT PromotedBitwiseVT) {
// Expand all builtin opcodes. // Expand all builtin opcodes.
for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
setOperationAction(Opc, VT, Expand); setOperationAction(Opc, VT, Expand);
setOperationAction(ISD::ADD, VT, Legal);
setOperationAction(ISD::SUB, VT, Legal);
setOperationAction(ISD::AND, VT, Legal);
setOperationAction(ISD::OR, VT, Legal);
setOperationAction(ISD::XOR, VT, Legal);
setOperationAction(ISD::BITCAST, VT, Legal); setOperationAction(ISD::BITCAST, VT, Legal);
// Promote load and store operations. // Promote load and store operations.
setOperationAction(ISD::LOAD, VT, Promote); setOperationAction(ISD::LOAD, VT, Promote);
AddPromotedToType(ISD::LOAD, VT, PromotedBitwiseVT); AddPromotedToType(ISD::LOAD, VT, PromotedBitwiseVT);
setOperationAction(ISD::STORE, VT, Promote); setOperationAction(ISD::STORE, VT, Promote);
AddPromotedToType(ISD::STORE, VT, PromotedBitwiseVT); AddPromotedToType(ISD::STORE, VT, PromotedBitwiseVT);
}; };
▲ Show 20 Lines • Show All 7,896 Lines • ▼ Show 20 Lines if (PartVTBitSize % ValueVTBitSize == 0) {
if (ValueEltVT != PartEltVT) if (ValueEltVT != PartEltVT)
Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
return Val; return Val;
} }
} }
return SDValue(); return SDValue();
} }
TargetLoweringBase::LegalizeTypeAction
RISCVTargetLowering::getPreferredVectorAction(MVT VT) const {
// For RV64P, v4i8 and v2i16 can be widened to v8i8 and v4i16 as legal types.
if (Subtarget.hasStdExtZpn() && (VT == MVT::v4i8 || VT == MVT::v2i16))
return TypeWidenVector;
return TargetLoweringBase::getPreferredVectorAction(VT);
}
#define GET_REGISTER_MATCHER #define GET_REGISTER_MATCHER
#include "RISCVGenAsmMatcher.inc" #include "RISCVGenAsmMatcher.inc"
Register Register
RISCVTargetLowering::getRegisterByName(const char *RegName, LLT VT, RISCVTargetLowering::getRegisterByName(const char *RegName, LLT VT,
const MachineFunction &MF) const { const MachineFunction &MF) const {
Register Reg = MatchRegisterAltName(RegName); Register Reg = MatchRegisterAltName(RegName);
if (Reg == RISCV::NoRegister) if (Reg == RISCV::NoRegister)
Show All 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoP.td

Show First 20 Lines • Show All 1,220 Lines • ▼ Show 20 Lines
class RVPTernaryINSBPat<RVInst Inst, string IntID> class RVPTernaryINSBPat<RVInst Inst, string IntID>
: Pat<(XLenVT (!cast<Intrinsic>("int_riscv_" # IntID) : Pat<(XLenVT (!cast<Intrinsic>("int_riscv_" # IntID)
XLenVT:$rs1, XLenVT:$rs2, uimmlog2xlenbytes:$rs3)), XLenVT:$rs1, XLenVT:$rs2, uimmlog2xlenbytes:$rs3)),
(Inst GPR:$rs1, GPR:$rs2, uimmlog2xlenbytes:$rs3)>; (Inst GPR:$rs1, GPR:$rs2, uimmlog2xlenbytes:$rs3)>;
let Predicates = [HasStdExtZpn] in let Predicates = [HasStdExtZpn] in
def : RVPTernaryINSBPat<INSB, "insb">; def : RVPTernaryINSBPat<INSB, "insb">;
//===----------------------------------------------------------------------===//
// Codegen patterns
//===----------------------------------------------------------------------===//
class PatALU8<SDPatternOperator OpNode, RVInst Inst>
: Pat<(XVEI8VT (OpNode GPR:$rs1, GPR:$rs2)),
(Inst GPR:$rs1, GPR:$rs2)>;
class PatALU16<SDPatternOperator OpNode, RVInst Inst>
: Pat<(XVEI16VT (OpNode GPR:$rs1, GPR:$rs2)),
(Inst GPR:$rs1, GPR:$rs2)>;
class PatALU32<SDPatternOperator OpNode, RVInst Inst>
: Pat<(XVEI32VT (OpNode GPR:$rs1, GPR:$rs2)),
(Inst GPR:$rs1, GPR:$rs2)>;
class PatALU8I<SDPatternOperator OpNode, RVInst Inst>
: Pat<(XVEI8VT (OpNode GPR:$rs1, (bitconvert simm12:$imm))),
(Inst GPR:$rs1, simm12:$imm)>;
class PatALU16I<SDPatternOperator OpNode, RVInst Inst>
: Pat<(XVEI16VT (OpNode GPR:$rs1, (bitconvert simm12:$imm))),
(Inst GPR:$rs1, simm12:$imm)>;
class PatALU32I<SDPatternOperator OpNode, RVInst Inst>
: Pat<(XVEI32VT (OpNode GPR:$rs1, (bitconvert simm12:$imm))),
(Inst GPR:$rs1, simm12:$imm)>;
// ALU operations
let Predicates = [HasStdExtZpn] in {
def : PatALU8<add, ADD8>;
def : PatALU8<sub, SUB8>;
def : PatALU8<and, AND>;
def : PatALU8<or, OR>;
def : PatALU8<xor, XOR>;
def : PatALU16<add, ADD16>;
def : PatALU16<sub, SUB16>;
def : PatALU16<and, AND>;
def : PatALU16<or, OR>;
def : PatALU16<xor, XOR>;
def : PatALU8I<and, ANDI>;
def : PatALU8I<or, ORI>;
def : PatALU8I<xor, XORI>;
def : PatALU16I<and, ANDI>;
def : PatALU16I<or, ORI>;
def : PatALU16I<xor, XORI>;
} // Predicates = [HasStdExtZpn]
let Predicates = [HasStdExtZpn, IsRV64] in {
def : PatALU32<add, ADD32>;
def : PatALU32<sub, SUB32>;
def : PatALU32<and, AND>;
def : PatALU32<or, OR>;
def : PatALU32<xor, XOR>;
def : PatALU32I<and, ANDI>;
def : PatALU32I<or, ORI>;
def : PatALU32I<xor, XORI>;
} // [HasStdExtZpn, IsRV64]

llvm/test/CodeGen/RISCV/rv32zpn-alu.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-p -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-p -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IP ; RUN: | FileCheck %s --check-prefixes=RV32IP
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zpn -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zpn -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IPN ; RUN: | FileCheck %s --check-prefixes=RV32IPN
define i32 @addv4i8(i32 %a, i32 %b) nounwind { define i32 @addv4i8(i32 %a, i32 %b) nounwind {
; RV32IP-LABEL: addv4i8: ; RV32IP-LABEL: addv4i8:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: add8 a0, a0, a1
; RV32IP-NEXT: sw a1, 8(sp)
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lb a0, 11(sp)
; RV32IP-NEXT: lb a1, 7(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lb a0, 10(sp)
; RV32IP-NEXT: lb a1, 6(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lb a0, 9(sp)
; RV32IP-NEXT: lb a1, 5(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lb a0, 8(sp)
; RV32IP-NEXT: lb a1, 4(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: addv4i8: ; RV32IPN-LABEL: addv4i8:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: add8 a0, a0, a1
; RV32IPN-NEXT: sw a1, 8(sp)
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lb a0, 11(sp)
; RV32IPN-NEXT: lb a1, 7(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lb a0, 10(sp)
; RV32IPN-NEXT: lb a1, 6(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lb a0, 9(sp)
; RV32IPN-NEXT: lb a1, 5(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lb a0, 8(sp)
; RV32IPN-NEXT: lb a1, 4(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <4 x i8> %tmp1 = bitcast i32 %a to <4 x i8>
%tmp2 = bitcast i32 %b to <4 x i8> %tmp2 = bitcast i32 %b to <4 x i8>
%add = add <4 x i8> %tmp1, %tmp2 %add = add <4 x i8> %tmp1, %tmp2
%res = bitcast <4 x i8> %add to i32 %res = bitcast <4 x i8> %add to i32
ret i32 %res ret i32 %res
} }
define i32 @addv2i16(i32 %a, i32 %b) nounwind { define i32 @addv2i16(i32 %a, i32 %b) nounwind {
; RV32IP-LABEL: addv2i16: ; RV32IP-LABEL: addv2i16:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: add16 a0, a0, a1
; RV32IP-NEXT: sw a1, 8(sp)
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lh a0, 10(sp)
; RV32IP-NEXT: lh a1, 6(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sh a0, 14(sp)
; RV32IP-NEXT: lh a0, 8(sp)
; RV32IP-NEXT: lh a1, 4(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: addv2i16: ; RV32IPN-LABEL: addv2i16:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: add16 a0, a0, a1
; RV32IPN-NEXT: sw a1, 8(sp)
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lh a0, 10(sp)
; RV32IPN-NEXT: lh a1, 6(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sh a0, 14(sp)
; RV32IPN-NEXT: lh a0, 8(sp)
; RV32IPN-NEXT: lh a1, 4(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <2 x i16> %tmp1 = bitcast i32 %a to <2 x i16>
%tmp2 = bitcast i32 %b to <2 x i16> %tmp2 = bitcast i32 %b to <2 x i16>
%add = add <2 x i16> %tmp1, %tmp2 %add = add <2 x i16> %tmp1, %tmp2
%res = bitcast <2 x i16> %add to i32 %res = bitcast <2 x i16> %add to i32
ret i32 %res ret i32 %res
} }
define i64 @addv8i8(i64 %a, i64 %b) nounwind { define i64 @addv8i8(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: addv8i8: ; RV32IP-LABEL: addv8i8:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -32 ; RV32IP-NEXT: add8 a1, a1, a3
; RV32IP-NEXT: sw a2, 16(sp) ; RV32IP-NEXT: add8 a0, a0, a2
; RV32IP-NEXT: sw a0, 8(sp)
; RV32IP-NEXT: sw a3, 20(sp)
; RV32IP-NEXT: sw a1, 12(sp)
; RV32IP-NEXT: lb a0, 19(sp)
; RV32IP-NEXT: lb a1, 11(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 27(sp)
; RV32IP-NEXT: lb a0, 18(sp)
; RV32IP-NEXT: lb a1, 10(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 26(sp)
; RV32IP-NEXT: lb a0, 17(sp)
; RV32IP-NEXT: lb a1, 9(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 25(sp)
; RV32IP-NEXT: lb a0, 16(sp)
; RV32IP-NEXT: lb a1, 8(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 24(sp)
; RV32IP-NEXT: lb a0, 23(sp)
; RV32IP-NEXT: lb a1, 15(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 31(sp)
; RV32IP-NEXT: lb a0, 22(sp)
; RV32IP-NEXT: lb a1, 14(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 30(sp)
; RV32IP-NEXT: lb a0, 21(sp)
; RV32IP-NEXT: lb a1, 13(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 29(sp)
; RV32IP-NEXT: lb a0, 20(sp)
; RV32IP-NEXT: lb a1, 12(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 28(sp)
; RV32IP-NEXT: lw a0, 24(sp)
; RV32IP-NEXT: lw a1, 28(sp)
; RV32IP-NEXT: addi sp, sp, 32
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: addv8i8: ; RV32IPN-LABEL: addv8i8:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -32 ; RV32IPN-NEXT: add8 a1, a1, a3
; RV32IPN-NEXT: sw a2, 16(sp) ; RV32IPN-NEXT: add8 a0, a0, a2
; RV32IPN-NEXT: sw a0, 8(sp)
; RV32IPN-NEXT: sw a3, 20(sp)
; RV32IPN-NEXT: sw a1, 12(sp)
; RV32IPN-NEXT: lb a0, 19(sp)
; RV32IPN-NEXT: lb a1, 11(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 27(sp)
; RV32IPN-NEXT: lb a0, 18(sp)
; RV32IPN-NEXT: lb a1, 10(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 26(sp)
; RV32IPN-NEXT: lb a0, 17(sp)
; RV32IPN-NEXT: lb a1, 9(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 25(sp)
; RV32IPN-NEXT: lb a0, 16(sp)
; RV32IPN-NEXT: lb a1, 8(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 24(sp)
; RV32IPN-NEXT: lb a0, 23(sp)
; RV32IPN-NEXT: lb a1, 15(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 31(sp)
; RV32IPN-NEXT: lb a0, 22(sp)
; RV32IPN-NEXT: lb a1, 14(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 30(sp)
; RV32IPN-NEXT: lb a0, 21(sp)
; RV32IPN-NEXT: lb a1, 13(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 29(sp)
; RV32IPN-NEXT: lb a0, 20(sp)
; RV32IPN-NEXT: lb a1, 12(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 28(sp)
; RV32IPN-NEXT: lw a0, 24(sp)
; RV32IPN-NEXT: lw a1, 28(sp)
; RV32IPN-NEXT: addi sp, sp, 32
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <8 x i8> %tmp1 = bitcast i64 %a to <8 x i8>
%tmp2 = bitcast i64 %b to <8 x i8> %tmp2 = bitcast i64 %b to <8 x i8>
%add = add <8 x i8> %tmp1, %tmp2 %add = add <8 x i8> %tmp1, %tmp2
%res = bitcast <8 x i8> %add to i64 %res = bitcast <8 x i8> %add to i64
ret i64 %res ret i64 %res
} }
define i64 @addv4i16(i64 %a, i64 %b) nounwind { define i64 @addv4i16(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: addv4i16: ; RV32IP-LABEL: addv4i16:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -32 ; RV32IP-NEXT: add16 a1, a1, a3
; RV32IP-NEXT: sw a2, 16(sp) ; RV32IP-NEXT: add16 a0, a0, a2
; RV32IP-NEXT: sw a0, 8(sp)
; RV32IP-NEXT: sw a3, 20(sp)
; RV32IP-NEXT: sw a1, 12(sp)
; RV32IP-NEXT: lh a0, 18(sp)
; RV32IP-NEXT: lh a1, 10(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sh a0, 26(sp)
; RV32IP-NEXT: lh a0, 16(sp)
; RV32IP-NEXT: lh a1, 8(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sh a0, 24(sp)
; RV32IP-NEXT: lh a0, 22(sp)
; RV32IP-NEXT: lh a1, 14(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sh a0, 30(sp)
; RV32IP-NEXT: lh a0, 20(sp)
; RV32IP-NEXT: lh a1, 12(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sh a0, 28(sp)
; RV32IP-NEXT: lw a0, 24(sp)
; RV32IP-NEXT: lw a1, 28(sp)
; RV32IP-NEXT: addi sp, sp, 32
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: addv4i16: ; RV32IPN-LABEL: addv4i16:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -32 ; RV32IPN-NEXT: add16 a1, a1, a3
; RV32IPN-NEXT: sw a2, 16(sp) ; RV32IPN-NEXT: add16 a0, a0, a2
; RV32IPN-NEXT: sw a0, 8(sp)
; RV32IPN-NEXT: sw a3, 20(sp)
; RV32IPN-NEXT: sw a1, 12(sp)
; RV32IPN-NEXT: lh a0, 18(sp)
; RV32IPN-NEXT: lh a1, 10(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sh a0, 26(sp)
; RV32IPN-NEXT: lh a0, 16(sp)
; RV32IPN-NEXT: lh a1, 8(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sh a0, 24(sp)
; RV32IPN-NEXT: lh a0, 22(sp)
; RV32IPN-NEXT: lh a1, 14(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sh a0, 30(sp)
; RV32IPN-NEXT: lh a0, 20(sp)
; RV32IPN-NEXT: lh a1, 12(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sh a0, 28(sp)
; RV32IPN-NEXT: lw a0, 24(sp)
; RV32IPN-NEXT: lw a1, 28(sp)
; RV32IPN-NEXT: addi sp, sp, 32
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <4 x i16> %tmp1 = bitcast i64 %a to <4 x i16>
%tmp2 = bitcast i64 %b to <4 x i16> %tmp2 = bitcast i64 %b to <4 x i16>
%add = add <4 x i16> %tmp1, %tmp2 %add = add <4 x i16> %tmp1, %tmp2
%res = bitcast <4 x i16> %add to i64 %res = bitcast <4 x i16> %add to i64
ret i64 %res ret i64 %res
} }
Show All 14 Lines; RV32IPN-NEXT: ret
%add = add <2 x i32> %tmp1, %tmp2 %add = add <2 x i32> %tmp1, %tmp2
%res = bitcast <2 x i32> %add to i64 %res = bitcast <2 x i32> %add to i64
ret i64 %res ret i64 %res
} }
define i32 @subv4i8(i32 %a, i32 %b) nounwind { define i32 @subv4i8(i32 %a, i32 %b) nounwind {
; RV32IP-LABEL: subv4i8: ; RV32IP-LABEL: subv4i8:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: sub8 a0, a0, a1
; RV32IP-NEXT: sw a1, 8(sp)
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lb a0, 11(sp)
; RV32IP-NEXT: lb a1, 7(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lb a0, 10(sp)
; RV32IP-NEXT: lb a1, 6(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lb a0, 9(sp)
; RV32IP-NEXT: lb a1, 5(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lb a0, 8(sp)
; RV32IP-NEXT: lb a1, 4(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: subv4i8: ; RV32IPN-LABEL: subv4i8:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: sub8 a0, a0, a1
; RV32IPN-NEXT: sw a1, 8(sp)
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lb a0, 11(sp)
; RV32IPN-NEXT: lb a1, 7(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lb a0, 10(sp)
; RV32IPN-NEXT: lb a1, 6(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lb a0, 9(sp)
; RV32IPN-NEXT: lb a1, 5(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lb a0, 8(sp)
; RV32IPN-NEXT: lb a1, 4(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <4 x i8> %tmp1 = bitcast i32 %a to <4 x i8>
%tmp2 = bitcast i32 %b to <4 x i8> %tmp2 = bitcast i32 %b to <4 x i8>
%sub = sub <4 x i8> %tmp1, %tmp2 %sub = sub <4 x i8> %tmp1, %tmp2
%res = bitcast <4 x i8> %sub to i32 %res = bitcast <4 x i8> %sub to i32
ret i32 %res ret i32 %res
} }
define i32 @subv2i16(i32 %a, i32 %b) nounwind { define i32 @subv2i16(i32 %a, i32 %b) nounwind {
; RV32IP-LABEL: subv2i16: ; RV32IP-LABEL: subv2i16:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: sub16 a0, a0, a1
; RV32IP-NEXT: sw a1, 8(sp)
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lh a0, 10(sp)
; RV32IP-NEXT: lh a1, 6(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sh a0, 14(sp)
; RV32IP-NEXT: lh a0, 8(sp)
; RV32IP-NEXT: lh a1, 4(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: subv2i16: ; RV32IPN-LABEL: subv2i16:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: sub16 a0, a0, a1
; RV32IPN-NEXT: sw a1, 8(sp)
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lh a0, 10(sp)
; RV32IPN-NEXT: lh a1, 6(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sh a0, 14(sp)
; RV32IPN-NEXT: lh a0, 8(sp)
; RV32IPN-NEXT: lh a1, 4(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <2 x i16> %tmp1 = bitcast i32 %a to <2 x i16>
%tmp2 = bitcast i32 %b to <2 x i16> %tmp2 = bitcast i32 %b to <2 x i16>
%sub = sub <2 x i16> %tmp1, %tmp2 %sub = sub <2 x i16> %tmp1, %tmp2
%res = bitcast <2 x i16> %sub to i32 %res = bitcast <2 x i16> %sub to i32
ret i32 %res ret i32 %res
} }
define i64 @subv8i8(i64 %a, i64 %b) nounwind { define i64 @subv8i8(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: subv8i8: ; RV32IP-LABEL: subv8i8:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -32 ; RV32IP-NEXT: sub8 a1, a1, a3
; RV32IP-NEXT: sw a2, 16(sp) ; RV32IP-NEXT: sub8 a0, a0, a2
; RV32IP-NEXT: sw a0, 8(sp)
; RV32IP-NEXT: sw a3, 20(sp)
; RV32IP-NEXT: sw a1, 12(sp)
; RV32IP-NEXT: lb a0, 19(sp)
; RV32IP-NEXT: lb a1, 11(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 27(sp)
; RV32IP-NEXT: lb a0, 18(sp)
; RV32IP-NEXT: lb a1, 10(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 26(sp)
; RV32IP-NEXT: lb a0, 17(sp)
; RV32IP-NEXT: lb a1, 9(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 25(sp)
; RV32IP-NEXT: lb a0, 16(sp)
; RV32IP-NEXT: lb a1, 8(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 24(sp)
; RV32IP-NEXT: lb a0, 23(sp)
; RV32IP-NEXT: lb a1, 15(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 31(sp)
; RV32IP-NEXT: lb a0, 22(sp)
; RV32IP-NEXT: lb a1, 14(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 30(sp)
; RV32IP-NEXT: lb a0, 21(sp)
; RV32IP-NEXT: lb a1, 13(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 29(sp)
; RV32IP-NEXT: lb a0, 20(sp)
; RV32IP-NEXT: lb a1, 12(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sb a0, 28(sp)
; RV32IP-NEXT: lw a0, 24(sp)
; RV32IP-NEXT: lw a1, 28(sp)
; RV32IP-NEXT: addi sp, sp, 32
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: subv8i8: ; RV32IPN-LABEL: subv8i8:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -32 ; RV32IPN-NEXT: sub8 a1, a1, a3
; RV32IPN-NEXT: sw a2, 16(sp) ; RV32IPN-NEXT: sub8 a0, a0, a2
; RV32IPN-NEXT: sw a0, 8(sp)
; RV32IPN-NEXT: sw a3, 20(sp)
; RV32IPN-NEXT: sw a1, 12(sp)
; RV32IPN-NEXT: lb a0, 19(sp)
; RV32IPN-NEXT: lb a1, 11(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 27(sp)
; RV32IPN-NEXT: lb a0, 18(sp)
; RV32IPN-NEXT: lb a1, 10(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 26(sp)
; RV32IPN-NEXT: lb a0, 17(sp)
; RV32IPN-NEXT: lb a1, 9(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 25(sp)
; RV32IPN-NEXT: lb a0, 16(sp)
; RV32IPN-NEXT: lb a1, 8(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 24(sp)
; RV32IPN-NEXT: lb a0, 23(sp)
; RV32IPN-NEXT: lb a1, 15(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 31(sp)
; RV32IPN-NEXT: lb a0, 22(sp)
; RV32IPN-NEXT: lb a1, 14(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 30(sp)
; RV32IPN-NEXT: lb a0, 21(sp)
; RV32IPN-NEXT: lb a1, 13(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 29(sp)
; RV32IPN-NEXT: lb a0, 20(sp)
; RV32IPN-NEXT: lb a1, 12(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sb a0, 28(sp)
; RV32IPN-NEXT: lw a0, 24(sp)
; RV32IPN-NEXT: lw a1, 28(sp)
; RV32IPN-NEXT: addi sp, sp, 32
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <8 x i8> %tmp1 = bitcast i64 %a to <8 x i8>
%tmp2 = bitcast i64 %b to <8 x i8> %tmp2 = bitcast i64 %b to <8 x i8>
%sub = sub <8 x i8> %tmp1, %tmp2 %sub = sub <8 x i8> %tmp1, %tmp2
%res = bitcast <8 x i8> %sub to i64 %res = bitcast <8 x i8> %sub to i64
ret i64 %res ret i64 %res
} }
define i64 @subv4i16(i64 %a, i64 %b) nounwind { define i64 @subv4i16(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: subv4i16: ; RV32IP-LABEL: subv4i16:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -32 ; RV32IP-NEXT: sub16 a1, a1, a3
; RV32IP-NEXT: sw a2, 16(sp) ; RV32IP-NEXT: sub16 a0, a0, a2
; RV32IP-NEXT: sw a0, 8(sp)
; RV32IP-NEXT: sw a3, 20(sp)
; RV32IP-NEXT: sw a1, 12(sp)
; RV32IP-NEXT: lh a0, 18(sp)
; RV32IP-NEXT: lh a1, 10(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sh a0, 26(sp)
; RV32IP-NEXT: lh a0, 16(sp)
; RV32IP-NEXT: lh a1, 8(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sh a0, 24(sp)
; RV32IP-NEXT: lh a0, 22(sp)
; RV32IP-NEXT: lh a1, 14(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sh a0, 30(sp)
; RV32IP-NEXT: lh a0, 20(sp)
; RV32IP-NEXT: lh a1, 12(sp)
; RV32IP-NEXT: sub a0, a1, a0
; RV32IP-NEXT: sh a0, 28(sp)
; RV32IP-NEXT: lw a0, 24(sp)
; RV32IP-NEXT: lw a1, 28(sp)
; RV32IP-NEXT: addi sp, sp, 32
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: subv4i16: ; RV32IPN-LABEL: subv4i16:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -32 ; RV32IPN-NEXT: sub16 a1, a1, a3
; RV32IPN-NEXT: sw a2, 16(sp) ; RV32IPN-NEXT: sub16 a0, a0, a2
; RV32IPN-NEXT: sw a0, 8(sp)
; RV32IPN-NEXT: sw a3, 20(sp)
; RV32IPN-NEXT: sw a1, 12(sp)
; RV32IPN-NEXT: lh a0, 18(sp)
; RV32IPN-NEXT: lh a1, 10(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sh a0, 26(sp)
; RV32IPN-NEXT: lh a0, 16(sp)
; RV32IPN-NEXT: lh a1, 8(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sh a0, 24(sp)
; RV32IPN-NEXT: lh a0, 22(sp)
; RV32IPN-NEXT: lh a1, 14(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sh a0, 30(sp)
; RV32IPN-NEXT: lh a0, 20(sp)
; RV32IPN-NEXT: lh a1, 12(sp)
; RV32IPN-NEXT: sub a0, a1, a0
; RV32IPN-NEXT: sh a0, 28(sp)
; RV32IPN-NEXT: lw a0, 24(sp)
; RV32IPN-NEXT: lw a1, 28(sp)
; RV32IPN-NEXT: addi sp, sp, 32
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <4 x i16> %tmp1 = bitcast i64 %a to <4 x i16>
%tmp2 = bitcast i64 %b to <4 x i16> %tmp2 = bitcast i64 %b to <4 x i16>
%sub = sub <4 x i16> %tmp1, %tmp2 %sub = sub <4 x i16> %tmp1, %tmp2
%res = bitcast <4 x i16> %sub to i64 %res = bitcast <4 x i16> %sub to i64
ret i64 %res ret i64 %res
} }
Show All 14 Lines; RV32IPN-NEXT: ret
%add = sub <2 x i32> %tmp1, %tmp2 %add = sub <2 x i32> %tmp1, %tmp2
%res = bitcast <2 x i32> %add to i64 %res = bitcast <2 x i32> %add to i64
ret i64 %res ret i64 %res
} }
define i32 @andv4i8(i32 %a) nounwind { define i32 @andv4i8(i32 %a) nounwind {
; RV32IP-LABEL: andv4i8: ; RV32IP-LABEL: andv4i8:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: lui a1, %hi(.LCPI10_0)
; RV32IP-NEXT: sw a0, 8(sp) ; RV32IP-NEXT: lw a1, %lo(.LCPI10_0)(a1)
; RV32IP-NEXT: lbu a0, 11(sp) ; RV32IP-NEXT: and a0, a0, a1
; RV32IP-NEXT: andi a0, a0, 4
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lbu a0, 10(sp)
; RV32IP-NEXT: andi a0, a0, 3
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lbu a0, 9(sp)
; RV32IP-NEXT: andi a0, a0, 2
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lbu a0, 8(sp)
; RV32IP-NEXT: andi a0, a0, 1
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: andv4i8: ; RV32IPN-LABEL: andv4i8:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: lui a1, %hi(.LCPI10_0)
; RV32IPN-NEXT: sw a0, 8(sp) ; RV32IPN-NEXT: lw a1, %lo(.LCPI10_0)(a1)
; RV32IPN-NEXT: lbu a0, 11(sp) ; RV32IPN-NEXT: and a0, a0, a1
; RV32IPN-NEXT: andi a0, a0, 4
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lbu a0, 10(sp)
; RV32IPN-NEXT: andi a0, a0, 3
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lbu a0, 9(sp)
; RV32IPN-NEXT: andi a0, a0, 2
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lbu a0, 8(sp)
; RV32IPN-NEXT: andi a0, a0, 1
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp = bitcast i32 %a to <4 x i8> %tmp = bitcast i32 %a to <4 x i8>
%and = and <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4> %and = and <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4>
%res = bitcast <4 x i8> %and to i32 %res = bitcast <4 x i8> %and to i32
ret i32 %res ret i32 %res
} }
define i32 @andv2i16(i32 %a) nounwind { define i32 @andv2i16(i32 %a) nounwind {
; RV32IP-LABEL: andv2i16: ; RV32IP-LABEL: andv2i16:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: lui a1, %hi(.LCPI11_0)
; RV32IP-NEXT: sw a0, 8(sp) ; RV32IP-NEXT: lw a1, %lo(.LCPI11_0)(a1)
; RV32IP-NEXT: lhu a0, 10(sp) ; RV32IP-NEXT: and a0, a0, a1
; RV32IP-NEXT: andi a0, a0, 2
; RV32IP-NEXT: sh a0, 14(sp)
; RV32IP-NEXT: lhu a0, 8(sp)
; RV32IP-NEXT: andi a0, a0, 1
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: andv2i16: ; RV32IPN-LABEL: andv2i16:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: lui a1, %hi(.LCPI11_0)
; RV32IPN-NEXT: sw a0, 8(sp) ; RV32IPN-NEXT: lw a1, %lo(.LCPI11_0)(a1)
; RV32IPN-NEXT: lhu a0, 10(sp) ; RV32IPN-NEXT: and a0, a0, a1
; RV32IPN-NEXT: andi a0, a0, 2
; RV32IPN-NEXT: sh a0, 14(sp)
; RV32IPN-NEXT: lhu a0, 8(sp)
; RV32IPN-NEXT: andi a0, a0, 1
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp = bitcast i32 %a to <2 x i16> %tmp = bitcast i32 %a to <2 x i16>
%and = and <2 x i16> %tmp, <i16 1, i16 2> %and = and <2 x i16> %tmp, <i16 1, i16 2>
%res = bitcast <2 x i16> %and to i32 %res = bitcast <2 x i16> %and to i32
ret i32 %res ret i32 %res
} }
define i64 @andv8i8(i64 %a) nounwind { define i64 @andv8i8(i64 %a) nounwind {
; RV32IP-LABEL: andv8i8: ; RV32IP-LABEL: andv8i8:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: lui a2, %hi(.LCPI12_0)
; RV32IP-NEXT: sw a0, 0(sp) ; RV32IP-NEXT: lw a2, %lo(.LCPI12_0)(a2)
; RV32IP-NEXT: sw a1, 4(sp) ; RV32IP-NEXT: lui a3, %hi(.LCPI12_1)
; RV32IP-NEXT: lbu a0, 3(sp) ; RV32IP-NEXT: lw a3, %lo(.LCPI12_1)(a3)
; RV32IP-NEXT: andi a0, a0, 4 ; RV32IP-NEXT: and a1, a1, a2
; RV32IP-NEXT: sb a0, 11(sp) ; RV32IP-NEXT: and a0, a0, a3
; RV32IP-NEXT: lbu a0, 2(sp)
; RV32IP-NEXT: andi a0, a0, 3
; RV32IP-NEXT: sb a0, 10(sp)
; RV32IP-NEXT: lbu a0, 1(sp)
; RV32IP-NEXT: andi a0, a0, 2
; RV32IP-NEXT: sb a0, 9(sp)
; RV32IP-NEXT: lbu a0, 0(sp)
; RV32IP-NEXT: andi a0, a0, 1
; RV32IP-NEXT: sb a0, 8(sp)
; RV32IP-NEXT: lbu a0, 7(sp)
; RV32IP-NEXT: andi a0, a0, 8
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lbu a0, 6(sp)
; RV32IP-NEXT: andi a0, a0, 7
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lbu a0, 5(sp)
; RV32IP-NEXT: andi a0, a0, 6
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lbu a0, 4(sp)
; RV32IP-NEXT: andi a0, a0, 5
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 8(sp)
; RV32IP-NEXT: lw a1, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: andv8i8: ; RV32IPN-LABEL: andv8i8:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: lui a2, %hi(.LCPI12_0)
; RV32IPN-NEXT: sw a0, 0(sp) ; RV32IPN-NEXT: lw a2, %lo(.LCPI12_0)(a2)
; RV32IPN-NEXT: sw a1, 4(sp) ; RV32IPN-NEXT: lui a3, %hi(.LCPI12_1)
; RV32IPN-NEXT: lbu a0, 3(sp) ; RV32IPN-NEXT: lw a3, %lo(.LCPI12_1)(a3)
; RV32IPN-NEXT: andi a0, a0, 4 ; RV32IPN-NEXT: and a1, a1, a2
; RV32IPN-NEXT: sb a0, 11(sp) ; RV32IPN-NEXT: and a0, a0, a3
; RV32IPN-NEXT: lbu a0, 2(sp)
; RV32IPN-NEXT: andi a0, a0, 3
; RV32IPN-NEXT: sb a0, 10(sp)
; RV32IPN-NEXT: lbu a0, 1(sp)
; RV32IPN-NEXT: andi a0, a0, 2
; RV32IPN-NEXT: sb a0, 9(sp)
; RV32IPN-NEXT: lbu a0, 0(sp)
; RV32IPN-NEXT: andi a0, a0, 1
; RV32IPN-NEXT: sb a0, 8(sp)
; RV32IPN-NEXT: lbu a0, 7(sp)
; RV32IPN-NEXT: andi a0, a0, 8
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lbu a0, 6(sp)
; RV32IPN-NEXT: andi a0, a0, 7
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lbu a0, 5(sp)
; RV32IPN-NEXT: andi a0, a0, 6
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lbu a0, 4(sp)
; RV32IPN-NEXT: andi a0, a0, 5
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 8(sp)
; RV32IPN-NEXT: lw a1, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp = bitcast i64 %a to <8 x i8> %tmp = bitcast i64 %a to <8 x i8>
%and = and <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8> %and = and <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
%res = bitcast <8 x i8> %and to i64 %res = bitcast <8 x i8> %and to i64
ret i64 %res ret i64 %res
} }
define i64 @andv4i16(i64 %a) nounwind { define i64 @andv4i16(i64 %a) nounwind {
; RV32IP-LABEL: andv4i16: ; RV32IP-LABEL: andv4i16:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: lui a2, %hi(.LCPI13_0)
; RV32IP-NEXT: sw a0, 0(sp) ; RV32IP-NEXT: lw a2, %lo(.LCPI13_0)(a2)
; RV32IP-NEXT: sw a1, 4(sp) ; RV32IP-NEXT: lui a3, %hi(.LCPI13_1)
; RV32IP-NEXT: lhu a0, 2(sp) ; RV32IP-NEXT: lw a3, %lo(.LCPI13_1)(a3)
; RV32IP-NEXT: andi a0, a0, 2 ; RV32IP-NEXT: and a1, a1, a2
; RV32IP-NEXT: sh a0, 10(sp) ; RV32IP-NEXT: and a0, a0, a3
; RV32IP-NEXT: lhu a0, 0(sp)
; RV32IP-NEXT: andi a0, a0, 1
; RV32IP-NEXT: sh a0, 8(sp)
; RV32IP-NEXT: lhu a0, 6(sp)
; RV32IP-NEXT: andi a0, a0, 4
; RV32IP-NEXT: sh a0, 14(sp)
; RV32IP-NEXT: lhu a0, 4(sp)
; RV32IP-NEXT: andi a0, a0, 3
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 8(sp)
; RV32IP-NEXT: lw a1, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: andv4i16: ; RV32IPN-LABEL: andv4i16:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: lui a2, %hi(.LCPI13_0)
; RV32IPN-NEXT: sw a0, 0(sp) ; RV32IPN-NEXT: lw a2, %lo(.LCPI13_0)(a2)
; RV32IPN-NEXT: sw a1, 4(sp) ; RV32IPN-NEXT: lui a3, %hi(.LCPI13_1)
; RV32IPN-NEXT: lhu a0, 2(sp) ; RV32IPN-NEXT: lw a3, %lo(.LCPI13_1)(a3)
; RV32IPN-NEXT: andi a0, a0, 2 ; RV32IPN-NEXT: and a1, a1, a2
; RV32IPN-NEXT: sh a0, 10(sp) ; RV32IPN-NEXT: and a0, a0, a3
; RV32IPN-NEXT: lhu a0, 0(sp)
; RV32IPN-NEXT: andi a0, a0, 1
; RV32IPN-NEXT: sh a0, 8(sp)
; RV32IPN-NEXT: lhu a0, 6(sp)
; RV32IPN-NEXT: andi a0, a0, 4
; RV32IPN-NEXT: sh a0, 14(sp)
; RV32IPN-NEXT: lhu a0, 4(sp)
; RV32IPN-NEXT: andi a0, a0, 3
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 8(sp)
; RV32IPN-NEXT: lw a1, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp = bitcast i64 %a to <4 x i16> %tmp = bitcast i64 %a to <4 x i16>
%and = and <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4> %and = and <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4>
%res = bitcast <4 x i16> %and to i64 %res = bitcast <4 x i16> %and to i64
ret i64 %res ret i64 %res
} }
define i64 @andv2i32(i64 %a) nounwind { define i64 @andv2i32(i64 %a) nounwind {
Show All 12 Lines; RV32IPN-NEXT: ret
%and = and <2 x i32> %tmp, <i32 1, i32 2> %and = and <2 x i32> %tmp, <i32 1, i32 2>
%res = bitcast <2 x i32> %and to i64 %res = bitcast <2 x i32> %and to i64
ret i64 %res ret i64 %res
} }
define i32 @orv4i8(i32 %a) nounwind { define i32 @orv4i8(i32 %a) nounwind {
; RV32IP-LABEL: orv4i8: ; RV32IP-LABEL: orv4i8:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: lui a1, %hi(.LCPI15_0)
; RV32IP-NEXT: sw a0, 8(sp) ; RV32IP-NEXT: lw a1, %lo(.LCPI15_0)(a1)
; RV32IP-NEXT: lb a0, 11(sp) ; RV32IP-NEXT: or a0, a0, a1
; RV32IP-NEXT: ori a0, a0, 4
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lb a0, 10(sp)
; RV32IP-NEXT: ori a0, a0, 3
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lb a0, 9(sp)
; RV32IP-NEXT: ori a0, a0, 2
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lb a0, 8(sp)
; RV32IP-NEXT: ori a0, a0, 1
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: orv4i8: ; RV32IPN-LABEL: orv4i8:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: lui a1, %hi(.LCPI15_0)
; RV32IPN-NEXT: sw a0, 8(sp) ; RV32IPN-NEXT: lw a1, %lo(.LCPI15_0)(a1)
; RV32IPN-NEXT: lb a0, 11(sp) ; RV32IPN-NEXT: or a0, a0, a1
; RV32IPN-NEXT: ori a0, a0, 4
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lb a0, 10(sp)
; RV32IPN-NEXT: ori a0, a0, 3
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lb a0, 9(sp)
; RV32IPN-NEXT: ori a0, a0, 2
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lb a0, 8(sp)
; RV32IPN-NEXT: ori a0, a0, 1
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp = bitcast i32 %a to <4 x i8> %tmp = bitcast i32 %a to <4 x i8>
%or = or <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4> %or = or <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4>
%res = bitcast <4 x i8> %or to i32 %res = bitcast <4 x i8> %or to i32
ret i32 %res ret i32 %res
} }
define i32 @orv2i16(i32 %a) nounwind { define i32 @orv2i16(i32 %a) nounwind {
; RV32IP-LABEL: orv2i16: ; RV32IP-LABEL: orv2i16:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: lui a1, %hi(.LCPI16_0)
; RV32IP-NEXT: sw a0, 8(sp) ; RV32IP-NEXT: lw a1, %lo(.LCPI16_0)(a1)
; RV32IP-NEXT: lh a0, 10(sp) ; RV32IP-NEXT: or a0, a0, a1
; RV32IP-NEXT: ori a0, a0, 2
; RV32IP-NEXT: sh a0, 14(sp)
; RV32IP-NEXT: lh a0, 8(sp)
; RV32IP-NEXT: ori a0, a0, 1
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: orv2i16: ; RV32IPN-LABEL: orv2i16:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: lui a1, %hi(.LCPI16_0)
; RV32IPN-NEXT: sw a0, 8(sp) ; RV32IPN-NEXT: lw a1, %lo(.LCPI16_0)(a1)
; RV32IPN-NEXT: lh a0, 10(sp) ; RV32IPN-NEXT: or a0, a0, a1
; RV32IPN-NEXT: ori a0, a0, 2
; RV32IPN-NEXT: sh a0, 14(sp)
; RV32IPN-NEXT: lh a0, 8(sp)
; RV32IPN-NEXT: ori a0, a0, 1
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp = bitcast i32 %a to <2 x i16> %tmp = bitcast i32 %a to <2 x i16>
%or = or <2 x i16> %tmp, <i16 1, i16 2> %or = or <2 x i16> %tmp, <i16 1, i16 2>
%res = bitcast <2 x i16> %or to i32 %res = bitcast <2 x i16> %or to i32
ret i32 %res ret i32 %res
} }
define i64 @orv8i8(i64 %a) nounwind { define i64 @orv8i8(i64 %a) nounwind {
; RV32IP-LABEL: orv8i8: ; RV32IP-LABEL: orv8i8:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: lui a2, %hi(.LCPI17_0)
; RV32IP-NEXT: sw a0, 0(sp) ; RV32IP-NEXT: lw a2, %lo(.LCPI17_0)(a2)
; RV32IP-NEXT: sw a1, 4(sp) ; RV32IP-NEXT: lui a3, %hi(.LCPI17_1)
; RV32IP-NEXT: lb a0, 3(sp) ; RV32IP-NEXT: lw a3, %lo(.LCPI17_1)(a3)
; RV32IP-NEXT: ori a0, a0, 4 ; RV32IP-NEXT: or a1, a1, a2
; RV32IP-NEXT: sb a0, 11(sp) ; RV32IP-NEXT: or a0, a0, a3
; RV32IP-NEXT: lb a0, 2(sp)
; RV32IP-NEXT: ori a0, a0, 3
; RV32IP-NEXT: sb a0, 10(sp)
; RV32IP-NEXT: lb a0, 1(sp)
; RV32IP-NEXT: ori a0, a0, 2
; RV32IP-NEXT: sb a0, 9(sp)
; RV32IP-NEXT: lb a0, 0(sp)
; RV32IP-NEXT: ori a0, a0, 1
; RV32IP-NEXT: sb a0, 8(sp)
; RV32IP-NEXT: lb a0, 7(sp)
; RV32IP-NEXT: ori a0, a0, 8
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lb a0, 6(sp)
; RV32IP-NEXT: ori a0, a0, 7
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lb a0, 5(sp)
; RV32IP-NEXT: ori a0, a0, 6
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lb a0, 4(sp)
; RV32IP-NEXT: ori a0, a0, 5
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 8(sp)
; RV32IP-NEXT: lw a1, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: orv8i8: ; RV32IPN-LABEL: orv8i8:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: lui a2, %hi(.LCPI17_0)
; RV32IPN-NEXT: sw a0, 0(sp) ; RV32IPN-NEXT: lw a2, %lo(.LCPI17_0)(a2)
; RV32IPN-NEXT: sw a1, 4(sp) ; RV32IPN-NEXT: lui a3, %hi(.LCPI17_1)
; RV32IPN-NEXT: lb a0, 3(sp) ; RV32IPN-NEXT: lw a3, %lo(.LCPI17_1)(a3)
; RV32IPN-NEXT: ori a0, a0, 4 ; RV32IPN-NEXT: or a1, a1, a2
; RV32IPN-NEXT: sb a0, 11(sp) ; RV32IPN-NEXT: or a0, a0, a3
; RV32IPN-NEXT: lb a0, 2(sp)
; RV32IPN-NEXT: ori a0, a0, 3
; RV32IPN-NEXT: sb a0, 10(sp)
; RV32IPN-NEXT: lb a0, 1(sp)
; RV32IPN-NEXT: ori a0, a0, 2
; RV32IPN-NEXT: sb a0, 9(sp)
; RV32IPN-NEXT: lb a0, 0(sp)
; RV32IPN-NEXT: ori a0, a0, 1
; RV32IPN-NEXT: sb a0, 8(sp)
; RV32IPN-NEXT: lb a0, 7(sp)
; RV32IPN-NEXT: ori a0, a0, 8
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lb a0, 6(sp)
; RV32IPN-NEXT: ori a0, a0, 7
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lb a0, 5(sp)
; RV32IPN-NEXT: ori a0, a0, 6
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lb a0, 4(sp)
; RV32IPN-NEXT: ori a0, a0, 5
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 8(sp)
; RV32IPN-NEXT: lw a1, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp = bitcast i64 %a to <8 x i8> %tmp = bitcast i64 %a to <8 x i8>
%or = or <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8> %or = or <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
%res = bitcast <8 x i8> %or to i64 %res = bitcast <8 x i8> %or to i64
ret i64 %res ret i64 %res
} }
define i64 @orv4i16(i64 %a) nounwind { define i64 @orv4i16(i64 %a) nounwind {
; RV32IP-LABEL: orv4i16: ; RV32IP-LABEL: orv4i16:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: lui a2, %hi(.LCPI18_0)
; RV32IP-NEXT: sw a0, 0(sp) ; RV32IP-NEXT: lw a2, %lo(.LCPI18_0)(a2)
; RV32IP-NEXT: sw a1, 4(sp) ; RV32IP-NEXT: lui a3, %hi(.LCPI18_1)
; RV32IP-NEXT: lh a0, 2(sp) ; RV32IP-NEXT: lw a3, %lo(.LCPI18_1)(a3)
; RV32IP-NEXT: ori a0, a0, 2 ; RV32IP-NEXT: or a1, a1, a2
; RV32IP-NEXT: sh a0, 10(sp) ; RV32IP-NEXT: or a0, a0, a3
; RV32IP-NEXT: lh a0, 0(sp)
; RV32IP-NEXT: ori a0, a0, 1
; RV32IP-NEXT: sh a0, 8(sp)
; RV32IP-NEXT: lh a0, 6(sp)
; RV32IP-NEXT: ori a0, a0, 4
; RV32IP-NEXT: sh a0, 14(sp)
; RV32IP-NEXT: lh a0, 4(sp)
; RV32IP-NEXT: ori a0, a0, 3
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 8(sp)
; RV32IP-NEXT: lw a1, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: orv4i16: ; RV32IPN-LABEL: orv4i16:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: lui a2, %hi(.LCPI18_0)
; RV32IPN-NEXT: sw a0, 0(sp) ; RV32IPN-NEXT: lw a2, %lo(.LCPI18_0)(a2)
; RV32IPN-NEXT: sw a1, 4(sp) ; RV32IPN-NEXT: lui a3, %hi(.LCPI18_1)
; RV32IPN-NEXT: lh a0, 2(sp) ; RV32IPN-NEXT: lw a3, %lo(.LCPI18_1)(a3)
; RV32IPN-NEXT: ori a0, a0, 2 ; RV32IPN-NEXT: or a1, a1, a2
; RV32IPN-NEXT: sh a0, 10(sp) ; RV32IPN-NEXT: or a0, a0, a3
; RV32IPN-NEXT: lh a0, 0(sp)
; RV32IPN-NEXT: ori a0, a0, 1
; RV32IPN-NEXT: sh a0, 8(sp)
; RV32IPN-NEXT: lh a0, 6(sp)
; RV32IPN-NEXT: ori a0, a0, 4
; RV32IPN-NEXT: sh a0, 14(sp)
; RV32IPN-NEXT: lh a0, 4(sp)
; RV32IPN-NEXT: ori a0, a0, 3
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 8(sp)
; RV32IPN-NEXT: lw a1, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp = bitcast i64 %a to <4 x i16> %tmp = bitcast i64 %a to <4 x i16>
%or = or <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4> %or = or <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4>
%res = bitcast <4 x i16> %or to i64 %res = bitcast <4 x i16> %or to i64
ret i64 %res ret i64 %res
} }
define i64 @orv2i32(i64 %a) nounwind { define i64 @orv2i32(i64 %a) nounwind {
Show All 12 Lines; RV32IPN-NEXT: ret
%or = or <2 x i32> %tmp, <i32 1, i32 2> %or = or <2 x i32> %tmp, <i32 1, i32 2>
%res = bitcast <2 x i32> %or to i64 %res = bitcast <2 x i32> %or to i64
ret i64 %res ret i64 %res
} }
define i32 @xorv4i8(i32 %a) nounwind { define i32 @xorv4i8(i32 %a) nounwind {
; RV32IP-LABEL: xorv4i8: ; RV32IP-LABEL: xorv4i8:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: lui a1, %hi(.LCPI20_0)
; RV32IP-NEXT: sw a0, 8(sp) ; RV32IP-NEXT: lw a1, %lo(.LCPI20_0)(a1)
; RV32IP-NEXT: lb a0, 11(sp) ; RV32IP-NEXT: xor a0, a0, a1
; RV32IP-NEXT: xori a0, a0, 4
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lb a0, 10(sp)
; RV32IP-NEXT: xori a0, a0, 3
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lb a0, 9(sp)
; RV32IP-NEXT: xori a0, a0, 2
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lb a0, 8(sp)
; RV32IP-NEXT: xori a0, a0, 1
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: xorv4i8: ; RV32IPN-LABEL: xorv4i8:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: lui a1, %hi(.LCPI20_0)
; RV32IPN-NEXT: sw a0, 8(sp) ; RV32IPN-NEXT: lw a1, %lo(.LCPI20_0)(a1)
; RV32IPN-NEXT: lb a0, 11(sp) ; RV32IPN-NEXT: xor a0, a0, a1
; RV32IPN-NEXT: xori a0, a0, 4
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lb a0, 10(sp)
; RV32IPN-NEXT: xori a0, a0, 3
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lb a0, 9(sp)
; RV32IPN-NEXT: xori a0, a0, 2
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lb a0, 8(sp)
; RV32IPN-NEXT: xori a0, a0, 1
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp = bitcast i32 %a to <4 x i8> %tmp = bitcast i32 %a to <4 x i8>
%xor = xor <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4> %xor = xor <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4>
%res = bitcast <4 x i8> %xor to i32 %res = bitcast <4 x i8> %xor to i32
ret i32 %res ret i32 %res
} }
define i32 @xorv2i16(i32 %a) nounwind { define i32 @xorv2i16(i32 %a) nounwind {
; RV32IP-LABEL: xorv2i16: ; RV32IP-LABEL: xorv2i16:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: lui a1, %hi(.LCPI21_0)
; RV32IP-NEXT: sw a0, 8(sp) ; RV32IP-NEXT: lw a1, %lo(.LCPI21_0)(a1)
; RV32IP-NEXT: lh a0, 10(sp) ; RV32IP-NEXT: xor a0, a0, a1
; RV32IP-NEXT: xori a0, a0, 2
; RV32IP-NEXT: sh a0, 14(sp)
; RV32IP-NEXT: lh a0, 8(sp)
; RV32IP-NEXT: xori a0, a0, 1
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: xorv2i16: ; RV32IPN-LABEL: xorv2i16:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: lui a1, %hi(.LCPI21_0)
; RV32IPN-NEXT: sw a0, 8(sp) ; RV32IPN-NEXT: lw a1, %lo(.LCPI21_0)(a1)
; RV32IPN-NEXT: lh a0, 10(sp) ; RV32IPN-NEXT: xor a0, a0, a1
; RV32IPN-NEXT: xori a0, a0, 2
; RV32IPN-NEXT: sh a0, 14(sp)
; RV32IPN-NEXT: lh a0, 8(sp)
; RV32IPN-NEXT: xori a0, a0, 1
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp = bitcast i32 %a to <2 x i16> %tmp = bitcast i32 %a to <2 x i16>
%xor = xor <2 x i16> %tmp, <i16 1, i16 2> %xor = xor <2 x i16> %tmp, <i16 1, i16 2>
%res = bitcast <2 x i16> %xor to i32 %res = bitcast <2 x i16> %xor to i32
ret i32 %res ret i32 %res
} }
define i64 @xorv8i8(i64 %a) nounwind { define i64 @xorv8i8(i64 %a) nounwind {
; RV32IP-LABEL: xorv8i8: ; RV32IP-LABEL: xorv8i8:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: lui a2, %hi(.LCPI22_0)
; RV32IP-NEXT: sw a0, 0(sp) ; RV32IP-NEXT: lw a2, %lo(.LCPI22_0)(a2)
; RV32IP-NEXT: sw a1, 4(sp) ; RV32IP-NEXT: lui a3, %hi(.LCPI22_1)
; RV32IP-NEXT: lb a0, 3(sp) ; RV32IP-NEXT: lw a3, %lo(.LCPI22_1)(a3)
; RV32IP-NEXT: xori a0, a0, 4 ; RV32IP-NEXT: xor a1, a1, a2
; RV32IP-NEXT: sb a0, 11(sp) ; RV32IP-NEXT: xor a0, a0, a3
; RV32IP-NEXT: lb a0, 2(sp)
; RV32IP-NEXT: xori a0, a0, 3
; RV32IP-NEXT: sb a0, 10(sp)
; RV32IP-NEXT: lb a0, 1(sp)
; RV32IP-NEXT: xori a0, a0, 2
; RV32IP-NEXT: sb a0, 9(sp)
; RV32IP-NEXT: lb a0, 0(sp)
; RV32IP-NEXT: xori a0, a0, 1
; RV32IP-NEXT: sb a0, 8(sp)
; RV32IP-NEXT: lb a0, 7(sp)
; RV32IP-NEXT: xori a0, a0, 8
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lb a0, 6(sp)
; RV32IP-NEXT: xori a0, a0, 7
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lb a0, 5(sp)
; RV32IP-NEXT: xori a0, a0, 6
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lb a0, 4(sp)
; RV32IP-NEXT: xori a0, a0, 5
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 8(sp)
; RV32IP-NEXT: lw a1, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: xorv8i8: ; RV32IPN-LABEL: xorv8i8:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: lui a2, %hi(.LCPI22_0)
; RV32IPN-NEXT: sw a0, 0(sp) ; RV32IPN-NEXT: lw a2, %lo(.LCPI22_0)(a2)
; RV32IPN-NEXT: sw a1, 4(sp) ; RV32IPN-NEXT: lui a3, %hi(.LCPI22_1)
; RV32IPN-NEXT: lb a0, 3(sp) ; RV32IPN-NEXT: lw a3, %lo(.LCPI22_1)(a3)
; RV32IPN-NEXT: xori a0, a0, 4 ; RV32IPN-NEXT: xor a1, a1, a2
; RV32IPN-NEXT: sb a0, 11(sp) ; RV32IPN-NEXT: xor a0, a0, a3
; RV32IPN-NEXT: lb a0, 2(sp)
; RV32IPN-NEXT: xori a0, a0, 3
; RV32IPN-NEXT: sb a0, 10(sp)
; RV32IPN-NEXT: lb a0, 1(sp)
; RV32IPN-NEXT: xori a0, a0, 2
; RV32IPN-NEXT: sb a0, 9(sp)
; RV32IPN-NEXT: lb a0, 0(sp)
; RV32IPN-NEXT: xori a0, a0, 1
; RV32IPN-NEXT: sb a0, 8(sp)
; RV32IPN-NEXT: lb a0, 7(sp)
; RV32IPN-NEXT: xori a0, a0, 8
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lb a0, 6(sp)
; RV32IPN-NEXT: xori a0, a0, 7
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lb a0, 5(sp)
; RV32IPN-NEXT: xori a0, a0, 6
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lb a0, 4(sp)
; RV32IPN-NEXT: xori a0, a0, 5
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 8(sp)
; RV32IPN-NEXT: lw a1, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp = bitcast i64 %a to <8 x i8> %tmp = bitcast i64 %a to <8 x i8>
%xor = xor <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8> %xor = xor <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
%res = bitcast <8 x i8> %xor to i64 %res = bitcast <8 x i8> %xor to i64
ret i64 %res ret i64 %res
} }
define i64 @xorv4i16(i64 %a) nounwind { define i64 @xorv4i16(i64 %a) nounwind {
; RV32IP-LABEL: xorv4i16: ; RV32IP-LABEL: xorv4i16:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: lui a2, %hi(.LCPI23_0)
; RV32IP-NEXT: sw a0, 0(sp) ; RV32IP-NEXT: lw a2, %lo(.LCPI23_0)(a2)
; RV32IP-NEXT: sw a1, 4(sp) ; RV32IP-NEXT: lui a3, %hi(.LCPI23_1)
; RV32IP-NEXT: lh a0, 2(sp) ; RV32IP-NEXT: lw a3, %lo(.LCPI23_1)(a3)
; RV32IP-NEXT: xori a0, a0, 2 ; RV32IP-NEXT: xor a1, a1, a2
; RV32IP-NEXT: sh a0, 10(sp) ; RV32IP-NEXT: xor a0, a0, a3
; RV32IP-NEXT: lh a0, 0(sp)
; RV32IP-NEXT: xori a0, a0, 1
; RV32IP-NEXT: sh a0, 8(sp)
; RV32IP-NEXT: lh a0, 6(sp)
; RV32IP-NEXT: xori a0, a0, 4
; RV32IP-NEXT: sh a0, 14(sp)
; RV32IP-NEXT: lh a0, 4(sp)
; RV32IP-NEXT: xori a0, a0, 3
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 8(sp)
; RV32IP-NEXT: lw a1, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: xorv4i16: ; RV32IPN-LABEL: xorv4i16:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: lui a2, %hi(.LCPI23_0)
; RV32IPN-NEXT: sw a0, 0(sp) ; RV32IPN-NEXT: lw a2, %lo(.LCPI23_0)(a2)
; RV32IPN-NEXT: sw a1, 4(sp) ; RV32IPN-NEXT: lui a3, %hi(.LCPI23_1)
; RV32IPN-NEXT: lh a0, 2(sp) ; RV32IPN-NEXT: lw a3, %lo(.LCPI23_1)(a3)
; RV32IPN-NEXT: xori a0, a0, 2 ; RV32IPN-NEXT: xor a1, a1, a2
; RV32IPN-NEXT: sh a0, 10(sp) ; RV32IPN-NEXT: xor a0, a0, a3
; RV32IPN-NEXT: lh a0, 0(sp)
; RV32IPN-NEXT: xori a0, a0, 1
; RV32IPN-NEXT: sh a0, 8(sp)
; RV32IPN-NEXT: lh a0, 6(sp)
; RV32IPN-NEXT: xori a0, a0, 4
; RV32IPN-NEXT: sh a0, 14(sp)
; RV32IPN-NEXT: lh a0, 4(sp)
; RV32IPN-NEXT: xori a0, a0, 3
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 8(sp)
; RV32IPN-NEXT: lw a1, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp = bitcast i64 %a to <4 x i16> %tmp = bitcast i64 %a to <4 x i16>
%xor = xor <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4> %xor = xor <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4>
%res = bitcast <4 x i16> %xor to i64 %res = bitcast <4 x i16> %xor to i64
ret i64 %res ret i64 %res
} }
define i64 @xorv2i32(i64 %a) nounwind { define i64 @xorv2i32(i64 %a) nounwind {
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; Logic operation with immediate. ; Logic operation with immediate.
; It has the input from the result of a vector operation to avoid ; It has the input from the result of a vector operation to avoid
; it bitcasted to a scalar operation. ; it bitcasted to a scalar operation.
define i32 @andiv4i8(i32 %a, i32 %b) nounwind { define i32 @andiv4i8(i32 %a, i32 %b) nounwind {
; RV32IP-LABEL: andiv4i8: ; RV32IP-LABEL: andiv4i8:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: add8 a0, a0, a1
; RV32IP-NEXT: sw a1, 8(sp) ; RV32IP-NEXT: andi a0, a0, 1
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lb a6, 8(sp)
; RV32IP-NEXT: lb a7, 4(sp)
; RV32IP-NEXT: lb t0, 9(sp)
; RV32IP-NEXT: lb a3, 5(sp)
; RV32IP-NEXT: lb a4, 10(sp)
; RV32IP-NEXT: lb a5, 6(sp)
; RV32IP-NEXT: lb a0, 11(sp)
; RV32IP-NEXT: lb a1, 7(sp)
; RV32IP-NEXT: addi a2, zero, 1
; RV32IP-NEXT: sw a2, 0(sp)
; RV32IP-NEXT: lb a2, 3(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: and a0, a0, a2
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lb a0, 2(sp)
; RV32IP-NEXT: add a1, a5, a4
; RV32IP-NEXT: and a0, a1, a0
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lb a0, 1(sp)
; RV32IP-NEXT: add a1, a3, t0
; RV32IP-NEXT: and a0, a1, a0
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lb a0, 0(sp)
; RV32IP-NEXT: add a1, a7, a6
; RV32IP-NEXT: and a0, a1, a0
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: andiv4i8: ; RV32IPN-LABEL: andiv4i8:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: add8 a0, a0, a1
; RV32IPN-NEXT: sw a1, 8(sp) ; RV32IPN-NEXT: andi a0, a0, 1
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lb a6, 8(sp)
; RV32IPN-NEXT: lb a7, 4(sp)
; RV32IPN-NEXT: lb t0, 9(sp)
; RV32IPN-NEXT: lb a3, 5(sp)
; RV32IPN-NEXT: lb a4, 10(sp)
; RV32IPN-NEXT: lb a5, 6(sp)
; RV32IPN-NEXT: lb a0, 11(sp)
; RV32IPN-NEXT: lb a1, 7(sp)
; RV32IPN-NEXT: addi a2, zero, 1
; RV32IPN-NEXT: sw a2, 0(sp)
; RV32IPN-NEXT: lb a2, 3(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: and a0, a0, a2
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lb a0, 2(sp)
; RV32IPN-NEXT: add a1, a5, a4
; RV32IPN-NEXT: and a0, a1, a0
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lb a0, 1(sp)
; RV32IPN-NEXT: add a1, a3, t0
; RV32IPN-NEXT: and a0, a1, a0
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lb a0, 0(sp)
; RV32IPN-NEXT: add a1, a7, a6
; RV32IPN-NEXT: and a0, a1, a0
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <4 x i8> %tmp1 = bitcast i32 %a to <4 x i8>
%tmp2 = bitcast i32 %b to <4 x i8> %tmp2 = bitcast i32 %b to <4 x i8>
%imm = bitcast i32 1 to <4 x i8> %imm = bitcast i32 1 to <4 x i8>
%add = add <4 x i8> %tmp1, %tmp2 %add = add <4 x i8> %tmp1, %tmp2
%and = and <4 x i8> %add, %imm %and = and <4 x i8> %add, %imm
%res = bitcast <4 x i8> %and to i32 %res = bitcast <4 x i8> %and to i32
ret i32 %res ret i32 %res
} }
define i32 @andiv2i16(i32 %a, i32 %b) nounwind { define i32 @andiv2i16(i32 %a, i32 %b) nounwind {
; RV32IP-LABEL: andiv2i16: ; RV32IP-LABEL: andiv2i16:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: add16 a0, a0, a1
; RV32IP-NEXT: sw a1, 8(sp) ; RV32IP-NEXT: andi a0, a0, -2
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lh a0, 8(sp)
; RV32IP-NEXT: lh a1, 4(sp)
; RV32IP-NEXT: lh a2, 10(sp)
; RV32IP-NEXT: lh a3, 6(sp)
; RV32IP-NEXT: addi a4, zero, -2
; RV32IP-NEXT: sw a4, 0(sp)
; RV32IP-NEXT: lh a4, 2(sp)
; RV32IP-NEXT: add a2, a3, a2
; RV32IP-NEXT: and a2, a2, a4
; RV32IP-NEXT: sh a2, 14(sp)
; RV32IP-NEXT: lh a2, 0(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: and a0, a0, a2
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: andiv2i16: ; RV32IPN-LABEL: andiv2i16:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: add16 a0, a0, a1
; RV32IPN-NEXT: sw a1, 8(sp) ; RV32IPN-NEXT: andi a0, a0, -2
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lh a0, 8(sp)
; RV32IPN-NEXT: lh a1, 4(sp)
; RV32IPN-NEXT: lh a2, 10(sp)
; RV32IPN-NEXT: lh a3, 6(sp)
; RV32IPN-NEXT: addi a4, zero, -2
; RV32IPN-NEXT: sw a4, 0(sp)
; RV32IPN-NEXT: lh a4, 2(sp)
; RV32IPN-NEXT: add a2, a3, a2
; RV32IPN-NEXT: and a2, a2, a4
; RV32IPN-NEXT: sh a2, 14(sp)
; RV32IPN-NEXT: lh a2, 0(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: and a0, a0, a2
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <2 x i16> %tmp1 = bitcast i32 %a to <2 x i16>
%tmp2 = bitcast i32 %b to <2 x i16> %tmp2 = bitcast i32 %b to <2 x i16>
%imm = bitcast i32 -2 to <2 x i16> %imm = bitcast i32 -2 to <2 x i16>
%add = add <2 x i16> %tmp1, %tmp2 %add = add <2 x i16> %tmp1, %tmp2
%and = and <2 x i16> %add, %imm %and = and <2 x i16> %add, %imm
%res = bitcast <2 x i16> %and to i32 %res = bitcast <2 x i16> %and to i32
ret i32 %res ret i32 %res
} }
define i64 @andiv8i8(i64 %a, i64 %b) nounwind { define i64 @andiv8i8(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: andiv8i8: ; RV32IP-LABEL: andiv8i8:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -32 ; RV32IP-NEXT: add8 a1, a1, a3
; RV32IP-NEXT: sw a3, 20(sp) ; RV32IP-NEXT: add8 a0, a0, a2
; RV32IP-NEXT: sw a1, 12(sp) ; RV32IP-NEXT: andi a0, a0, -3
; RV32IP-NEXT: sw a2, 16(sp)
; RV32IP-NEXT: sw a0, 8(sp)
; RV32IP-NEXT: lb a0, 23(sp)
; RV32IP-NEXT: lb a1, 15(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 27(sp)
; RV32IP-NEXT: lb a0, 22(sp)
; RV32IP-NEXT: lb a1, 14(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 26(sp)
; RV32IP-NEXT: lb a0, 21(sp)
; RV32IP-NEXT: lb a1, 13(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 25(sp)
; RV32IP-NEXT: lb a0, 20(sp)
; RV32IP-NEXT: lb a1, 12(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sb a0, 24(sp)
; RV32IP-NEXT: lb a6, 16(sp)
; RV32IP-NEXT: lb a7, 8(sp)
; RV32IP-NEXT: lb t0, 17(sp)
; RV32IP-NEXT: lb t1, 9(sp)
; RV32IP-NEXT: lb a5, 18(sp)
; RV32IP-NEXT: lb a0, 10(sp)
; RV32IP-NEXT: lb a2, 19(sp)
; RV32IP-NEXT: lb a3, 11(sp)
; RV32IP-NEXT: lw a1, 24(sp)
; RV32IP-NEXT: addi a4, zero, -3
; RV32IP-NEXT: sw a4, 4(sp)
; RV32IP-NEXT: lb a4, 7(sp)
; RV32IP-NEXT: add a2, a3, a2
; RV32IP-NEXT: and a2, a2, a4
; RV32IP-NEXT: sb a2, 31(sp)
; RV32IP-NEXT: lb a2, 6(sp)
; RV32IP-NEXT: add a0, a0, a5
; RV32IP-NEXT: and a0, a0, a2
; RV32IP-NEXT: sb a0, 30(sp)
; RV32IP-NEXT: lb a0, 5(sp)
; RV32IP-NEXT: add a2, t1, t0
; RV32IP-NEXT: and a0, a2, a0
; RV32IP-NEXT: sb a0, 29(sp)
; RV32IP-NEXT: lb a0, 4(sp)
; RV32IP-NEXT: add a2, a7, a6
; RV32IP-NEXT: and a0, a2, a0
; RV32IP-NEXT: sb a0, 28(sp)
; RV32IP-NEXT: lw a0, 28(sp)
; RV32IP-NEXT: addi sp, sp, 32
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: andiv8i8: ; RV32IPN-LABEL: andiv8i8:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -32 ; RV32IPN-NEXT: add8 a1, a1, a3
; RV32IPN-NEXT: sw a3, 20(sp) ; RV32IPN-NEXT: add8 a0, a0, a2
; RV32IPN-NEXT: sw a1, 12(sp) ; RV32IPN-NEXT: andi a0, a0, -3
; RV32IPN-NEXT: sw a2, 16(sp)
; RV32IPN-NEXT: sw a0, 8(sp)
; RV32IPN-NEXT: lb a0, 23(sp)
; RV32IPN-NEXT: lb a1, 15(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 27(sp)
; RV32IPN-NEXT: lb a0, 22(sp)
; RV32IPN-NEXT: lb a1, 14(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 26(sp)
; RV32IPN-NEXT: lb a0, 21(sp)
; RV32IPN-NEXT: lb a1, 13(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 25(sp)
; RV32IPN-NEXT: lb a0, 20(sp)
; RV32IPN-NEXT: lb a1, 12(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sb a0, 24(sp)
; RV32IPN-NEXT: lb a6, 16(sp)
; RV32IPN-NEXT: lb a7, 8(sp)
; RV32IPN-NEXT: lb t0, 17(sp)
; RV32IPN-NEXT: lb t1, 9(sp)
; RV32IPN-NEXT: lb a5, 18(sp)
; RV32IPN-NEXT: lb a0, 10(sp)
; RV32IPN-NEXT: lb a2, 19(sp)
; RV32IPN-NEXT: lb a3, 11(sp)
; RV32IPN-NEXT: lw a1, 24(sp)
; RV32IPN-NEXT: addi a4, zero, -3
; RV32IPN-NEXT: sw a4, 4(sp)
; RV32IPN-NEXT: lb a4, 7(sp)
; RV32IPN-NEXT: add a2, a3, a2
; RV32IPN-NEXT: and a2, a2, a4
; RV32IPN-NEXT: sb a2, 31(sp)
; RV32IPN-NEXT: lb a2, 6(sp)
; RV32IPN-NEXT: add a0, a0, a5
; RV32IPN-NEXT: and a0, a0, a2
; RV32IPN-NEXT: sb a0, 30(sp)
; RV32IPN-NEXT: lb a0, 5(sp)
; RV32IPN-NEXT: add a2, t1, t0
; RV32IPN-NEXT: and a0, a2, a0
; RV32IPN-NEXT: sb a0, 29(sp)
; RV32IPN-NEXT: lb a0, 4(sp)
; RV32IPN-NEXT: add a2, a7, a6
; RV32IPN-NEXT: and a0, a2, a0
; RV32IPN-NEXT: sb a0, 28(sp)
; RV32IPN-NEXT: lw a0, 28(sp)
; RV32IPN-NEXT: addi sp, sp, 32
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <8 x i8> %tmp1 = bitcast i64 %a to <8 x i8>
%tmp2 = bitcast i64 %b to <8 x i8> %tmp2 = bitcast i64 %b to <8 x i8>
%imm = bitcast i64 -3 to <8 x i8> %imm = bitcast i64 -3 to <8 x i8>
%add = add <8 x i8> %tmp1, %tmp2 %add = add <8 x i8> %tmp1, %tmp2
%and = and <8 x i8> %add, %imm %and = and <8 x i8> %add, %imm
%res = bitcast <8 x i8> %and to i64 %res = bitcast <8 x i8> %and to i64
ret i64 %res ret i64 %res
} }
define i64 @andvi4i16(i64 %a, i64 %b) nounwind { define i64 @andvi4i16(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: andvi4i16: ; RV32IP-LABEL: andvi4i16:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -32 ; RV32IP-NEXT: add16 a1, a1, a3
; RV32IP-NEXT: sw a3, 20(sp) ; RV32IP-NEXT: add16 a0, a0, a2
; RV32IP-NEXT: sw a1, 12(sp) ; RV32IP-NEXT: andi a0, a0, -4
; RV32IP-NEXT: sw a2, 16(sp)
; RV32IP-NEXT: sw a0, 8(sp)
; RV32IP-NEXT: lh a0, 22(sp)
; RV32IP-NEXT: lh a1, 14(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sh a0, 26(sp)
; RV32IP-NEXT: lh a0, 20(sp)
; RV32IP-NEXT: lh a1, 12(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: sh a0, 24(sp)
; RV32IP-NEXT: lh a0, 16(sp)
; RV32IP-NEXT: lh a2, 8(sp)
; RV32IP-NEXT: lh a3, 18(sp)
; RV32IP-NEXT: lh a4, 10(sp)
; RV32IP-NEXT: lw a1, 24(sp)
; RV32IP-NEXT: addi a5, zero, -4
; RV32IP-NEXT: sw a5, 4(sp)
; RV32IP-NEXT: lh a5, 6(sp)
; RV32IP-NEXT: add a3, a4, a3
; RV32IP-NEXT: and a3, a3, a5
; RV32IP-NEXT: sh a3, 30(sp)
; RV32IP-NEXT: lh a3, 4(sp)
; RV32IP-NEXT: add a0, a2, a0
; RV32IP-NEXT: and a0, a0, a3
; RV32IP-NEXT: sh a0, 28(sp)
; RV32IP-NEXT: lw a0, 28(sp)
; RV32IP-NEXT: addi sp, sp, 32
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: andvi4i16: ; RV32IPN-LABEL: andvi4i16:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -32 ; RV32IPN-NEXT: add16 a1, a1, a3
; RV32IPN-NEXT: sw a3, 20(sp) ; RV32IPN-NEXT: add16 a0, a0, a2
; RV32IPN-NEXT: sw a1, 12(sp) ; RV32IPN-NEXT: andi a0, a0, -4
; RV32IPN-NEXT: sw a2, 16(sp)
; RV32IPN-NEXT: sw a0, 8(sp)
; RV32IPN-NEXT: lh a0, 22(sp)
; RV32IPN-NEXT: lh a1, 14(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sh a0, 26(sp)
; RV32IPN-NEXT: lh a0, 20(sp)
; RV32IPN-NEXT: lh a1, 12(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: sh a0, 24(sp)
; RV32IPN-NEXT: lh a0, 16(sp)
; RV32IPN-NEXT: lh a2, 8(sp)
; RV32IPN-NEXT: lh a3, 18(sp)
; RV32IPN-NEXT: lh a4, 10(sp)
; RV32IPN-NEXT: lw a1, 24(sp)
; RV32IPN-NEXT: addi a5, zero, -4
; RV32IPN-NEXT: sw a5, 4(sp)
; RV32IPN-NEXT: lh a5, 6(sp)
; RV32IPN-NEXT: add a3, a4, a3
; RV32IPN-NEXT: and a3, a3, a5
; RV32IPN-NEXT: sh a3, 30(sp)
; RV32IPN-NEXT: lh a3, 4(sp)
; RV32IPN-NEXT: add a0, a2, a0
; RV32IPN-NEXT: and a0, a0, a3
; RV32IPN-NEXT: sh a0, 28(sp)
; RV32IPN-NEXT: lw a0, 28(sp)
; RV32IPN-NEXT: addi sp, sp, 32
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <4 x i16> %tmp1 = bitcast i64 %a to <4 x i16>
%tmp2 = bitcast i64 %b to <4 x i16> %tmp2 = bitcast i64 %b to <4 x i16>
%imm = bitcast i64 -4 to <4 x i16> %imm = bitcast i64 -4 to <4 x i16>
%add = add <4 x i16> %tmp1, %tmp2 %add = add <4 x i16> %tmp1, %tmp2
%and = and <4 x i16> %add, %imm %and = and <4 x i16> %add, %imm
%res = bitcast <4 x i16> %and to i64 %res = bitcast <4 x i16> %and to i64
ret i64 %res ret i64 %res
Show All 20 Lines; RV32IPN-NEXT: ret
%and = and <2 x i32> %add, %imm %and = and <2 x i32> %add, %imm
%res = bitcast <2 x i32> %and to i64 %res = bitcast <2 x i32> %and to i64
ret i64 %res ret i64 %res
} }
define i32 @oriv4i8(i32 %a, i32 %b) nounwind { define i32 @oriv4i8(i32 %a, i32 %b) nounwind {
; RV32IP-LABEL: oriv4i8: ; RV32IP-LABEL: oriv4i8:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: add8 a0, a0, a1
; RV32IP-NEXT: sw a1, 8(sp) ; RV32IP-NEXT: ori a0, a0, 1
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lb a6, 8(sp)
; RV32IP-NEXT: lb a7, 4(sp)
; RV32IP-NEXT: lb t0, 9(sp)
; RV32IP-NEXT: lb a3, 5(sp)
; RV32IP-NEXT: lb a4, 10(sp)
; RV32IP-NEXT: lb a5, 6(sp)
; RV32IP-NEXT: lb a0, 11(sp)
; RV32IP-NEXT: lb a1, 7(sp)
; RV32IP-NEXT: addi a2, zero, 1
; RV32IP-NEXT: sw a2, 0(sp)
; RV32IP-NEXT: lb a2, 3(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: or a0, a0, a2
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lb a0, 2(sp)
; RV32IP-NEXT: add a1, a5, a4
; RV32IP-NEXT: or a0, a1, a0
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lb a0, 1(sp)
; RV32IP-NEXT: add a1, a3, t0
; RV32IP-NEXT: or a0, a1, a0
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lb a0, 0(sp)
; RV32IP-NEXT: add a1, a7, a6
; RV32IP-NEXT: or a0, a1, a0
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: oriv4i8: ; RV32IPN-LABEL: oriv4i8:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: add8 a0, a0, a1
; RV32IPN-NEXT: sw a1, 8(sp) ; RV32IPN-NEXT: ori a0, a0, 1
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lb a6, 8(sp)
; RV32IPN-NEXT: lb a7, 4(sp)
; RV32IPN-NEXT: lb t0, 9(sp)
; RV32IPN-NEXT: lb a3, 5(sp)
; RV32IPN-NEXT: lb a4, 10(sp)
; RV32IPN-NEXT: lb a5, 6(sp)
; RV32IPN-NEXT: lb a0, 11(sp)
; RV32IPN-NEXT: lb a1, 7(sp)
; RV32IPN-NEXT: addi a2, zero, 1
; RV32IPN-NEXT: sw a2, 0(sp)
; RV32IPN-NEXT: lb a2, 3(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: or a0, a0, a2
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lb a0, 2(sp)
; RV32IPN-NEXT: add a1, a5, a4
; RV32IPN-NEXT: or a0, a1, a0
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lb a0, 1(sp)
; RV32IPN-NEXT: add a1, a3, t0
; RV32IPN-NEXT: or a0, a1, a0
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lb a0, 0(sp)
; RV32IPN-NEXT: add a1, a7, a6
; RV32IPN-NEXT: or a0, a1, a0
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <4 x i8> %tmp1 = bitcast i32 %a to <4 x i8>
%tmp2 = bitcast i32 %b to <4 x i8> %tmp2 = bitcast i32 %b to <4 x i8>
%imm = bitcast i32 1 to <4 x i8> %imm = bitcast i32 1 to <4 x i8>
%add = add <4 x i8> %tmp1, %tmp2 %add = add <4 x i8> %tmp1, %tmp2
%or = or <4 x i8> %add, %imm %or = or <4 x i8> %add, %imm
%res = bitcast <4 x i8> %or to i32 %res = bitcast <4 x i8> %or to i32
ret i32 %res ret i32 %res
} }
define i32 @oriv2i16(i32 %a, i32 %b) nounwind { define i32 @oriv2i16(i32 %a, i32 %b) nounwind {
; RV32IP-LABEL: oriv2i16: ; RV32IP-LABEL: oriv2i16:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: add16 a0, a0, a1
; RV32IP-NEXT: sw a1, 8(sp) ; RV32IP-NEXT: ori a0, a0, -2
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lh a0, 8(sp)
; RV32IP-NEXT: lh a1, 4(sp)
; RV32IP-NEXT: lh a2, 10(sp)
; RV32IP-NEXT: lh a3, 6(sp)
; RV32IP-NEXT: addi a4, zero, -2
; RV32IP-NEXT: sw a4, 0(sp)
; RV32IP-NEXT: lh a4, 2(sp)
; RV32IP-NEXT: add a2, a3, a2
; RV32IP-NEXT: or a2, a2, a4
; RV32IP-NEXT: sh a2, 14(sp)
; RV32IP-NEXT: lh a2, 0(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: or a0, a0, a2
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: oriv2i16: ; RV32IPN-LABEL: oriv2i16:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: add16 a0, a0, a1
; RV32IPN-NEXT: sw a1, 8(sp) ; RV32IPN-NEXT: ori a0, a0, -2
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lh a0, 8(sp)
; RV32IPN-NEXT: lh a1, 4(sp)
; RV32IPN-NEXT: lh a2, 10(sp)
; RV32IPN-NEXT: lh a3, 6(sp)
; RV32IPN-NEXT: addi a4, zero, -2
; RV32IPN-NEXT: sw a4, 0(sp)
; RV32IPN-NEXT: lh a4, 2(sp)
; RV32IPN-NEXT: add a2, a3, a2
; RV32IPN-NEXT: or a2, a2, a4
; RV32IPN-NEXT: sh a2, 14(sp)
; RV32IPN-NEXT: lh a2, 0(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: or a0, a0, a2
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <2 x i16> %tmp1 = bitcast i32 %a to <2 x i16>
%tmp2 = bitcast i32 %b to <2 x i16> %tmp2 = bitcast i32 %b to <2 x i16>
%imm = bitcast i32 -2 to <2 x i16> %imm = bitcast i32 -2 to <2 x i16>
%add = add <2 x i16> %tmp1, %tmp2 %add = add <2 x i16> %tmp1, %tmp2
%or = or <2 x i16> %add, %imm %or = or <2 x i16> %add, %imm
%res = bitcast <2 x i16> %or to i32 %res = bitcast <2 x i16> %or to i32
ret i32 %res ret i32 %res
} }
define i64 @oriv8i8(i64 %a, i64 %b) nounwind { define i64 @oriv8i8(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: oriv8i8: ; RV32IP-LABEL: oriv8i8:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: lui a1, %hi(.LCPI32_0)
; RV32IP-NEXT: sw a2, 8(sp) ; RV32IP-NEXT: lw a1, %lo(.LCPI32_0)(a1)
; RV32IP-NEXT: sw a0, 4(sp) ; RV32IP-NEXT: add8 a0, a0, a2
; RV32IP-NEXT: lb a6, 8(sp) ; RV32IP-NEXT: ori a0, a0, -3
; RV32IP-NEXT: lb a7, 4(sp)
; RV32IP-NEXT: lb t0, 9(sp)
; RV32IP-NEXT: lb a3, 5(sp)
; RV32IP-NEXT: lb a4, 10(sp)
; RV32IP-NEXT: lb a5, 6(sp)
; RV32IP-NEXT: lb a0, 11(sp)
; RV32IP-NEXT: lb a1, 7(sp)
; RV32IP-NEXT: addi a2, zero, -3
; RV32IP-NEXT: sw a2, 0(sp)
; RV32IP-NEXT: lb a2, 3(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: or a0, a0, a2
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lb a0, 2(sp)
; RV32IP-NEXT: add a1, a5, a4
; RV32IP-NEXT: or a0, a1, a0
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lb a0, 1(sp)
; RV32IP-NEXT: add a1, a3, t0
; RV32IP-NEXT: or a0, a1, a0
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lb a0, 0(sp)
; RV32IP-NEXT: add a1, a7, a6
; RV32IP-NEXT: or a0, a1, a0
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lui a0, %hi(.LCPI32_0)
; RV32IP-NEXT: lw a1, %lo(.LCPI32_0)(a0)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: oriv8i8: ; RV32IPN-LABEL: oriv8i8:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: lui a1, %hi(.LCPI32_0)
; RV32IPN-NEXT: sw a2, 8(sp) ; RV32IPN-NEXT: lw a1, %lo(.LCPI32_0)(a1)
; RV32IPN-NEXT: sw a0, 4(sp) ; RV32IPN-NEXT: add8 a0, a0, a2
; RV32IPN-NEXT: lb a6, 8(sp) ; RV32IPN-NEXT: ori a0, a0, -3
; RV32IPN-NEXT: lb a7, 4(sp)
; RV32IPN-NEXT: lb t0, 9(sp)
; RV32IPN-NEXT: lb a3, 5(sp)
; RV32IPN-NEXT: lb a4, 10(sp)
; RV32IPN-NEXT: lb a5, 6(sp)
; RV32IPN-NEXT: lb a0, 11(sp)
; RV32IPN-NEXT: lb a1, 7(sp)
; RV32IPN-NEXT: addi a2, zero, -3
; RV32IPN-NEXT: sw a2, 0(sp)
; RV32IPN-NEXT: lb a2, 3(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: or a0, a0, a2
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lb a0, 2(sp)
; RV32IPN-NEXT: add a1, a5, a4
; RV32IPN-NEXT: or a0, a1, a0
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lb a0, 1(sp)
; RV32IPN-NEXT: add a1, a3, t0
; RV32IPN-NEXT: or a0, a1, a0
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lb a0, 0(sp)
; RV32IPN-NEXT: add a1, a7, a6
; RV32IPN-NEXT: or a0, a1, a0
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lui a0, %hi(.LCPI32_0)
; RV32IPN-NEXT: lw a1, %lo(.LCPI32_0)(a0)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <8 x i8> %tmp1 = bitcast i64 %a to <8 x i8>
%tmp2 = bitcast i64 %b to <8 x i8> %tmp2 = bitcast i64 %b to <8 x i8>
%imm = bitcast i64 -3 to <8 x i8> %imm = bitcast i64 -3 to <8 x i8>
%add = add <8 x i8> %tmp1, %tmp2 %add = add <8 x i8> %tmp1, %tmp2
%or = or <8 x i8> %add, %imm %or = or <8 x i8> %add, %imm
%res = bitcast <8 x i8> %or to i64 %res = bitcast <8 x i8> %or to i64
ret i64 %res ret i64 %res
} }
define i64 @orvi4i16(i64 %a, i64 %b) nounwind { define i64 @orvi4i16(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: orvi4i16: ; RV32IP-LABEL: orvi4i16:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: lui a1, %hi(.LCPI33_0)
; RV32IP-NEXT: sw a2, 8(sp) ; RV32IP-NEXT: lw a1, %lo(.LCPI33_0)(a1)
; RV32IP-NEXT: sw a0, 4(sp) ; RV32IP-NEXT: add16 a0, a0, a2
; RV32IP-NEXT: lh a0, 8(sp) ; RV32IP-NEXT: ori a0, a0, -4
; RV32IP-NEXT: lh a1, 4(sp)
; RV32IP-NEXT: lh a2, 10(sp)
; RV32IP-NEXT: lh a3, 6(sp)
; RV32IP-NEXT: addi a4, zero, -4
; RV32IP-NEXT: sw a4, 0(sp)
; RV32IP-NEXT: lh a4, 2(sp)
; RV32IP-NEXT: add a2, a3, a2
; RV32IP-NEXT: or a2, a2, a4
; RV32IP-NEXT: sh a2, 14(sp)
; RV32IP-NEXT: lh a2, 0(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: or a0, a0, a2
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lui a0, %hi(.LCPI33_0)
; RV32IP-NEXT: lw a1, %lo(.LCPI33_0)(a0)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: orvi4i16: ; RV32IPN-LABEL: orvi4i16:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: lui a1, %hi(.LCPI33_0)
; RV32IPN-NEXT: sw a2, 8(sp) ; RV32IPN-NEXT: lw a1, %lo(.LCPI33_0)(a1)
; RV32IPN-NEXT: sw a0, 4(sp) ; RV32IPN-NEXT: add16 a0, a0, a2
; RV32IPN-NEXT: lh a0, 8(sp) ; RV32IPN-NEXT: ori a0, a0, -4
; RV32IPN-NEXT: lh a1, 4(sp)
; RV32IPN-NEXT: lh a2, 10(sp)
; RV32IPN-NEXT: lh a3, 6(sp)
; RV32IPN-NEXT: addi a4, zero, -4
; RV32IPN-NEXT: sw a4, 0(sp)
; RV32IPN-NEXT: lh a4, 2(sp)
; RV32IPN-NEXT: add a2, a3, a2
; RV32IPN-NEXT: or a2, a2, a4
; RV32IPN-NEXT: sh a2, 14(sp)
; RV32IPN-NEXT: lh a2, 0(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: or a0, a0, a2
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lui a0, %hi(.LCPI33_0)
; RV32IPN-NEXT: lw a1, %lo(.LCPI33_0)(a0)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <4 x i16> %tmp1 = bitcast i64 %a to <4 x i16>
%tmp2 = bitcast i64 %b to <4 x i16> %tmp2 = bitcast i64 %b to <4 x i16>
%imm = bitcast i64 -4 to <4 x i16> %imm = bitcast i64 -4 to <4 x i16>
%add = add <4 x i16> %tmp1, %tmp2 %add = add <4 x i16> %tmp1, %tmp2
%or = or <4 x i16> %add, %imm %or = or <4 x i16> %add, %imm
%res = bitcast <4 x i16> %or to i64 %res = bitcast <4 x i16> %or to i64
ret i64 %res ret i64 %res
Show All 20 Lines; RV32IPN-NEXT: ret
%or = or <2 x i32> %add, %imm %or = or <2 x i32> %add, %imm
%res = bitcast <2 x i32> %or to i64 %res = bitcast <2 x i32> %or to i64
ret i64 %res ret i64 %res
} }
define i32 @xoriv4i8(i32 %a, i32 %b) nounwind { define i32 @xoriv4i8(i32 %a, i32 %b) nounwind {
; RV32IP-LABEL: xoriv4i8: ; RV32IP-LABEL: xoriv4i8:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: add8 a0, a0, a1
; RV32IP-NEXT: sw a1, 8(sp) ; RV32IP-NEXT: not a0, a0
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lb a6, 8(sp)
; RV32IP-NEXT: lb a7, 4(sp)
; RV32IP-NEXT: lb t0, 9(sp)
; RV32IP-NEXT: lb a3, 5(sp)
; RV32IP-NEXT: lb a4, 10(sp)
; RV32IP-NEXT: lb a5, 6(sp)
; RV32IP-NEXT: lb a0, 11(sp)
; RV32IP-NEXT: lb a1, 7(sp)
; RV32IP-NEXT: addi a2, zero, -1
; RV32IP-NEXT: sw a2, 0(sp)
; RV32IP-NEXT: lb a2, 3(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: xor a0, a0, a2
; RV32IP-NEXT: sb a0, 15(sp)
; RV32IP-NEXT: lb a0, 2(sp)
; RV32IP-NEXT: add a1, a5, a4
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sb a0, 14(sp)
; RV32IP-NEXT: lb a0, 1(sp)
; RV32IP-NEXT: add a1, a3, t0
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sb a0, 13(sp)
; RV32IP-NEXT: lb a0, 0(sp)
; RV32IP-NEXT: add a1, a7, a6
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sb a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: xoriv4i8: ; RV32IPN-LABEL: xoriv4i8:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: add8 a0, a0, a1
; RV32IPN-NEXT: sw a1, 8(sp) ; RV32IPN-NEXT: not a0, a0
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lb a6, 8(sp)
; RV32IPN-NEXT: lb a7, 4(sp)
; RV32IPN-NEXT: lb t0, 9(sp)
; RV32IPN-NEXT: lb a3, 5(sp)
; RV32IPN-NEXT: lb a4, 10(sp)
; RV32IPN-NEXT: lb a5, 6(sp)
; RV32IPN-NEXT: lb a0, 11(sp)
; RV32IPN-NEXT: lb a1, 7(sp)
; RV32IPN-NEXT: addi a2, zero, -1
; RV32IPN-NEXT: sw a2, 0(sp)
; RV32IPN-NEXT: lb a2, 3(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: xor a0, a0, a2
; RV32IPN-NEXT: sb a0, 15(sp)
; RV32IPN-NEXT: lb a0, 2(sp)
; RV32IPN-NEXT: add a1, a5, a4
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sb a0, 14(sp)
; RV32IPN-NEXT: lb a0, 1(sp)
; RV32IPN-NEXT: add a1, a3, t0
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sb a0, 13(sp)
; RV32IPN-NEXT: lb a0, 0(sp)
; RV32IPN-NEXT: add a1, a7, a6
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sb a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <4 x i8> %tmp1 = bitcast i32 %a to <4 x i8>
%tmp2 = bitcast i32 %b to <4 x i8> %tmp2 = bitcast i32 %b to <4 x i8>
%imm = bitcast i32 -1 to <4 x i8> %imm = bitcast i32 -1 to <4 x i8>
%add = add <4 x i8> %tmp1, %tmp2 %add = add <4 x i8> %tmp1, %tmp2
%xor = xor <4 x i8> %add, %imm %xor = xor <4 x i8> %add, %imm
%res = bitcast <4 x i8> %xor to i32 %res = bitcast <4 x i8> %xor to i32
ret i32 %res ret i32 %res
} }
define i32 @xoriv2i16(i32 %a, i32 %b) nounwind { define i32 @xoriv2i16(i32 %a, i32 %b) nounwind {
; RV32IP-LABEL: xoriv2i16: ; RV32IP-LABEL: xoriv2i16:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -16 ; RV32IP-NEXT: add16 a0, a0, a1
; RV32IP-NEXT: sw a1, 8(sp) ; RV32IP-NEXT: xori a0, a0, -2
; RV32IP-NEXT: sw a0, 4(sp)
; RV32IP-NEXT: lh a0, 8(sp)
; RV32IP-NEXT: lh a1, 4(sp)
; RV32IP-NEXT: lh a2, 10(sp)
; RV32IP-NEXT: lh a3, 6(sp)
; RV32IP-NEXT: addi a4, zero, -2
; RV32IP-NEXT: sw a4, 0(sp)
; RV32IP-NEXT: lh a4, 2(sp)
; RV32IP-NEXT: add a2, a3, a2
; RV32IP-NEXT: xor a2, a2, a4
; RV32IP-NEXT: sh a2, 14(sp)
; RV32IP-NEXT: lh a2, 0(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: xor a0, a0, a2
; RV32IP-NEXT: sh a0, 12(sp)
; RV32IP-NEXT: lw a0, 12(sp)
; RV32IP-NEXT: addi sp, sp, 16
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: xoriv2i16: ; RV32IPN-LABEL: xoriv2i16:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -16 ; RV32IPN-NEXT: add16 a0, a0, a1
; RV32IPN-NEXT: sw a1, 8(sp) ; RV32IPN-NEXT: xori a0, a0, -2
; RV32IPN-NEXT: sw a0, 4(sp)
; RV32IPN-NEXT: lh a0, 8(sp)
; RV32IPN-NEXT: lh a1, 4(sp)
; RV32IPN-NEXT: lh a2, 10(sp)
; RV32IPN-NEXT: lh a3, 6(sp)
; RV32IPN-NEXT: addi a4, zero, -2
; RV32IPN-NEXT: sw a4, 0(sp)
; RV32IPN-NEXT: lh a4, 2(sp)
; RV32IPN-NEXT: add a2, a3, a2
; RV32IPN-NEXT: xor a2, a2, a4
; RV32IPN-NEXT: sh a2, 14(sp)
; RV32IPN-NEXT: lh a2, 0(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: xor a0, a0, a2
; RV32IPN-NEXT: sh a0, 12(sp)
; RV32IPN-NEXT: lw a0, 12(sp)
; RV32IPN-NEXT: addi sp, sp, 16
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <2 x i16> %tmp1 = bitcast i32 %a to <2 x i16>
%tmp2 = bitcast i32 %b to <2 x i16> %tmp2 = bitcast i32 %b to <2 x i16>
%imm = bitcast i32 -2 to <2 x i16> %imm = bitcast i32 -2 to <2 x i16>
%add = add <2 x i16> %tmp1, %tmp2 %add = add <2 x i16> %tmp1, %tmp2
%xor = xor <2 x i16> %add, %imm %xor = xor <2 x i16> %add, %imm
%res = bitcast <2 x i16> %xor to i32 %res = bitcast <2 x i16> %xor to i32
ret i32 %res ret i32 %res
} }
define i64 @xoriv8i8(i64 %a, i64 %b) nounwind { define i64 @xoriv8i8(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: xoriv8i8: ; RV32IP-LABEL: xoriv8i8:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -48 ; RV32IP-NEXT: add8 a0, a0, a2
; RV32IP-NEXT: sw s0, 44(sp) # 4-byte Folded Spill ; RV32IP-NEXT: add8 a1, a1, a3
; RV32IP-NEXT: sw s1, 40(sp) # 4-byte Folded Spill ; RV32IP-NEXT: not a1, a1
; RV32IP-NEXT: sw a3, 28(sp) ; RV32IP-NEXT: xori a0, a0, -3
; RV32IP-NEXT: sw a1, 20(sp)
; RV32IP-NEXT: sw a2, 24(sp)
; RV32IP-NEXT: sw a0, 16(sp)
; RV32IP-NEXT: lb a6, 28(sp)
; RV32IP-NEXT: lb a7, 20(sp)
; RV32IP-NEXT: lb t0, 29(sp)
; RV32IP-NEXT: lb t1, 21(sp)
; RV32IP-NEXT: lb t2, 30(sp)
; RV32IP-NEXT: lb t3, 22(sp)
; RV32IP-NEXT: lb t4, 31(sp)
; RV32IP-NEXT: lb t5, 23(sp)
; RV32IP-NEXT: lb t6, 24(sp)
; RV32IP-NEXT: lb a3, 16(sp)
; RV32IP-NEXT: lb a4, 25(sp)
; RV32IP-NEXT: lb a5, 17(sp)
; RV32IP-NEXT: lb a0, 26(sp)
; RV32IP-NEXT: lb a1, 18(sp)
; RV32IP-NEXT: lb a2, 27(sp)
; RV32IP-NEXT: lb s0, 19(sp)
; RV32IP-NEXT: addi s1, zero, -3
; RV32IP-NEXT: sw s1, 8(sp)
; RV32IP-NEXT: addi s1, zero, -1
; RV32IP-NEXT: sw s1, 12(sp)
; RV32IP-NEXT: lb s1, 11(sp)
; RV32IP-NEXT: add a2, s0, a2
; RV32IP-NEXT: xor a2, a2, s1
; RV32IP-NEXT: sb a2, 35(sp)
; RV32IP-NEXT: lb a2, 10(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: xor a0, a0, a2
; RV32IP-NEXT: sb a0, 34(sp)
; RV32IP-NEXT: lb a0, 9(sp)
; RV32IP-NEXT: add a1, a5, a4
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sb a0, 33(sp)
; RV32IP-NEXT: lb a0, 8(sp)
; RV32IP-NEXT: add a1, a3, t6
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sb a0, 32(sp)
; RV32IP-NEXT: lb a0, 15(sp)
; RV32IP-NEXT: add a1, t5, t4
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sb a0, 39(sp)
; RV32IP-NEXT: lb a0, 14(sp)
; RV32IP-NEXT: add a1, t3, t2
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sb a0, 38(sp)
; RV32IP-NEXT: lb a0, 13(sp)
; RV32IP-NEXT: add a1, t1, t0
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sb a0, 37(sp)
; RV32IP-NEXT: lb a0, 12(sp)
; RV32IP-NEXT: add a1, a7, a6
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sb a0, 36(sp)
; RV32IP-NEXT: lw a0, 32(sp)
; RV32IP-NEXT: lw a1, 36(sp)
; RV32IP-NEXT: lw s1, 40(sp) # 4-byte Folded Reload
; RV32IP-NEXT: lw s0, 44(sp) # 4-byte Folded Reload
; RV32IP-NEXT: addi sp, sp, 48
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: xoriv8i8: ; RV32IPN-LABEL: xoriv8i8:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -48 ; RV32IPN-NEXT: add8 a0, a0, a2
; RV32IPN-NEXT: sw s0, 44(sp) # 4-byte Folded Spill ; RV32IPN-NEXT: add8 a1, a1, a3
; RV32IPN-NEXT: sw s1, 40(sp) # 4-byte Folded Spill ; RV32IPN-NEXT: not a1, a1
; RV32IPN-NEXT: sw a3, 28(sp) ; RV32IPN-NEXT: xori a0, a0, -3
; RV32IPN-NEXT: sw a1, 20(sp)
; RV32IPN-NEXT: sw a2, 24(sp)
; RV32IPN-NEXT: sw a0, 16(sp)
; RV32IPN-NEXT: lb a6, 28(sp)
; RV32IPN-NEXT: lb a7, 20(sp)
; RV32IPN-NEXT: lb t0, 29(sp)
; RV32IPN-NEXT: lb t1, 21(sp)
; RV32IPN-NEXT: lb t2, 30(sp)
; RV32IPN-NEXT: lb t3, 22(sp)
; RV32IPN-NEXT: lb t4, 31(sp)
; RV32IPN-NEXT: lb t5, 23(sp)
; RV32IPN-NEXT: lb t6, 24(sp)
; RV32IPN-NEXT: lb a3, 16(sp)
; RV32IPN-NEXT: lb a4, 25(sp)
; RV32IPN-NEXT: lb a5, 17(sp)
; RV32IPN-NEXT: lb a0, 26(sp)
; RV32IPN-NEXT: lb a1, 18(sp)
; RV32IPN-NEXT: lb a2, 27(sp)
; RV32IPN-NEXT: lb s0, 19(sp)
; RV32IPN-NEXT: addi s1, zero, -3
; RV32IPN-NEXT: sw s1, 8(sp)
; RV32IPN-NEXT: addi s1, zero, -1
; RV32IPN-NEXT: sw s1, 12(sp)
; RV32IPN-NEXT: lb s1, 11(sp)
; RV32IPN-NEXT: add a2, s0, a2
; RV32IPN-NEXT: xor a2, a2, s1
; RV32IPN-NEXT: sb a2, 35(sp)
; RV32IPN-NEXT: lb a2, 10(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: xor a0, a0, a2
; RV32IPN-NEXT: sb a0, 34(sp)
; RV32IPN-NEXT: lb a0, 9(sp)
; RV32IPN-NEXT: add a1, a5, a4
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sb a0, 33(sp)
; RV32IPN-NEXT: lb a0, 8(sp)
; RV32IPN-NEXT: add a1, a3, t6
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sb a0, 32(sp)
; RV32IPN-NEXT: lb a0, 15(sp)
; RV32IPN-NEXT: add a1, t5, t4
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sb a0, 39(sp)
; RV32IPN-NEXT: lb a0, 14(sp)
; RV32IPN-NEXT: add a1, t3, t2
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sb a0, 38(sp)
; RV32IPN-NEXT: lb a0, 13(sp)
; RV32IPN-NEXT: add a1, t1, t0
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sb a0, 37(sp)
; RV32IPN-NEXT: lb a0, 12(sp)
; RV32IPN-NEXT: add a1, a7, a6
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sb a0, 36(sp)
; RV32IPN-NEXT: lw a0, 32(sp)
; RV32IPN-NEXT: lw a1, 36(sp)
; RV32IPN-NEXT: lw s1, 40(sp) # 4-byte Folded Reload
; RV32IPN-NEXT: lw s0, 44(sp) # 4-byte Folded Reload
; RV32IPN-NEXT: addi sp, sp, 48
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <8 x i8> %tmp1 = bitcast i64 %a to <8 x i8>
%tmp2 = bitcast i64 %b to <8 x i8> %tmp2 = bitcast i64 %b to <8 x i8>
%imm = bitcast i64 -3 to <8 x i8> %imm = bitcast i64 -3 to <8 x i8>
%add = add <8 x i8> %tmp1, %tmp2 %add = add <8 x i8> %tmp1, %tmp2
%xor = xor <8 x i8> %add, %imm %xor = xor <8 x i8> %add, %imm
%res = bitcast <8 x i8> %xor to i64 %res = bitcast <8 x i8> %xor to i64
ret i64 %res ret i64 %res
} }
define i64 @xorvi4i16(i64 %a, i64 %b) nounwind { define i64 @xorvi4i16(i64 %a, i64 %b) nounwind {
; RV32IP-LABEL: xorvi4i16: ; RV32IP-LABEL: xorvi4i16:
; RV32IP: # %bb.0: ; RV32IP: # %bb.0:
; RV32IP-NEXT: addi sp, sp, -32 ; RV32IP-NEXT: add16 a0, a0, a2
; RV32IP-NEXT: sw a3, 20(sp) ; RV32IP-NEXT: add16 a1, a1, a3
; RV32IP-NEXT: sw a1, 12(sp) ; RV32IP-NEXT: not a1, a1
; RV32IP-NEXT: sw a2, 16(sp) ; RV32IP-NEXT: xori a0, a0, -4
; RV32IP-NEXT: sw a0, 8(sp)
; RV32IP-NEXT: lh a6, 20(sp)
; RV32IP-NEXT: lh a7, 12(sp)
; RV32IP-NEXT: lh t0, 22(sp)
; RV32IP-NEXT: lh a3, 14(sp)
; RV32IP-NEXT: lh a4, 16(sp)
; RV32IP-NEXT: lh a5, 8(sp)
; RV32IP-NEXT: lh a0, 18(sp)
; RV32IP-NEXT: lh a1, 10(sp)
; RV32IP-NEXT: addi a2, zero, -4
; RV32IP-NEXT: sw a2, 0(sp)
; RV32IP-NEXT: addi a2, zero, -1
; RV32IP-NEXT: sw a2, 4(sp)
; RV32IP-NEXT: lh a2, 2(sp)
; RV32IP-NEXT: add a0, a1, a0
; RV32IP-NEXT: xor a0, a0, a2
; RV32IP-NEXT: sh a0, 26(sp)
; RV32IP-NEXT: lh a0, 0(sp)
; RV32IP-NEXT: add a1, a5, a4
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sh a0, 24(sp)
; RV32IP-NEXT: lh a0, 6(sp)
; RV32IP-NEXT: add a1, a3, t0
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sh a0, 30(sp)
; RV32IP-NEXT: lh a0, 4(sp)
; RV32IP-NEXT: add a1, a7, a6
; RV32IP-NEXT: xor a0, a1, a0
; RV32IP-NEXT: sh a0, 28(sp)
; RV32IP-NEXT: lw a0, 24(sp)
; RV32IP-NEXT: lw a1, 28(sp)
; RV32IP-NEXT: addi sp, sp, 32
; RV32IP-NEXT: ret ; RV32IP-NEXT: ret
; ;
; RV32IPN-LABEL: xorvi4i16: ; RV32IPN-LABEL: xorvi4i16:
; RV32IPN: # %bb.0: ; RV32IPN: # %bb.0:
; RV32IPN-NEXT: addi sp, sp, -32 ; RV32IPN-NEXT: add16 a0, a0, a2
; RV32IPN-NEXT: sw a3, 20(sp) ; RV32IPN-NEXT: add16 a1, a1, a3
; RV32IPN-NEXT: sw a1, 12(sp) ; RV32IPN-NEXT: not a1, a1
; RV32IPN-NEXT: sw a2, 16(sp) ; RV32IPN-NEXT: xori a0, a0, -4
; RV32IPN-NEXT: sw a0, 8(sp)
; RV32IPN-NEXT: lh a6, 20(sp)
; RV32IPN-NEXT: lh a7, 12(sp)
; RV32IPN-NEXT: lh t0, 22(sp)
; RV32IPN-NEXT: lh a3, 14(sp)
; RV32IPN-NEXT: lh a4, 16(sp)
; RV32IPN-NEXT: lh a5, 8(sp)
; RV32IPN-NEXT: lh a0, 18(sp)
; RV32IPN-NEXT: lh a1, 10(sp)
; RV32IPN-NEXT: addi a2, zero, -4
; RV32IPN-NEXT: sw a2, 0(sp)
; RV32IPN-NEXT: addi a2, zero, -1
; RV32IPN-NEXT: sw a2, 4(sp)
; RV32IPN-NEXT: lh a2, 2(sp)
; RV32IPN-NEXT: add a0, a1, a0
; RV32IPN-NEXT: xor a0, a0, a2
; RV32IPN-NEXT: sh a0, 26(sp)
; RV32IPN-NEXT: lh a0, 0(sp)
; RV32IPN-NEXT: add a1, a5, a4
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sh a0, 24(sp)
; RV32IPN-NEXT: lh a0, 6(sp)
; RV32IPN-NEXT: add a1, a3, t0
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sh a0, 30(sp)
; RV32IPN-NEXT: lh a0, 4(sp)
; RV32IPN-NEXT: add a1, a7, a6
; RV32IPN-NEXT: xor a0, a1, a0
; RV32IPN-NEXT: sh a0, 28(sp)
; RV32IPN-NEXT: lw a0, 24(sp)
; RV32IPN-NEXT: lw a1, 28(sp)
; RV32IPN-NEXT: addi sp, sp, 32
; RV32IPN-NEXT: ret ; RV32IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <4 x i16> %tmp1 = bitcast i64 %a to <4 x i16>
%tmp2 = bitcast i64 %b to <4 x i16> %tmp2 = bitcast i64 %b to <4 x i16>
%imm = bitcast i64 -4 to <4 x i16> %imm = bitcast i64 -4 to <4 x i16>
%add = add <4 x i16> %tmp1, %tmp2 %add = add <4 x i16> %tmp1, %tmp2
%xor = xor <4 x i16> %add, %imm %xor = xor <4 x i16> %add, %imm
%res = bitcast <4 x i16> %xor to i64 %res = bitcast <4 x i16> %xor to i64
ret i64 %res ret i64 %res
Show All 26 Lines

llvm/test/CodeGen/RISCV/rv64zpn-alu.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV64IP ; RUN: | FileCheck %s --check-prefixes=RV64IP
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zpn -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zpn -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV64IPN ; RUN: | FileCheck %s --check-prefixes=RV64IPN
define signext i32 @addv4i8(i32 signext %a, i32 signext %b) nounwind { define signext i32 @addv4i8(i32 signext %a, i32 signext %b) nounwind {
; RV64IP-LABEL: addv4i8: ; RV64IP-LABEL: addv4i8:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: add8 a0, a0, a1
; RV64IP-NEXT: sw a1, 8(sp) ; RV64IP-NEXT: sext.w a0, a0
; RV64IP-NEXT: sw a0, 12(sp)
; RV64IP-NEXT: lb a6, 8(sp)
; RV64IP-NEXT: lb a7, 12(sp)
; RV64IP-NEXT: lb a2, 9(sp)
; RV64IP-NEXT: lb a3, 11(sp)
; RV64IP-NEXT: lb a4, 15(sp)
; RV64IP-NEXT: lb a5, 10(sp)
; RV64IP-NEXT: lb a0, 14(sp)
; RV64IP-NEXT: lb a1, 13(sp)
; RV64IP-NEXT: add a3, a4, a3
; RV64IP-NEXT: sb a3, 7(sp)
; RV64IP-NEXT: add a0, a0, a5
; RV64IP-NEXT: sb a0, 6(sp)
; RV64IP-NEXT: add a0, a1, a2
; RV64IP-NEXT: sb a0, 5(sp)
; RV64IP-NEXT: add a0, a7, a6
; RV64IP-NEXT: sb a0, 4(sp)
; RV64IP-NEXT: lw a0, 4(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: addv4i8: ; RV64IPN-LABEL: addv4i8:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: add8 a0, a0, a1
; RV64IPN-NEXT: sw a1, 8(sp) ; RV64IPN-NEXT: sext.w a0, a0
; RV64IPN-NEXT: sw a0, 12(sp)
; RV64IPN-NEXT: lb a6, 8(sp)
; RV64IPN-NEXT: lb a7, 12(sp)
; RV64IPN-NEXT: lb a2, 9(sp)
; RV64IPN-NEXT: lb a3, 11(sp)
; RV64IPN-NEXT: lb a4, 15(sp)
; RV64IPN-NEXT: lb a5, 10(sp)
; RV64IPN-NEXT: lb a0, 14(sp)
; RV64IPN-NEXT: lb a1, 13(sp)
; RV64IPN-NEXT: add a3, a4, a3
; RV64IPN-NEXT: sb a3, 7(sp)
; RV64IPN-NEXT: add a0, a0, a5
; RV64IPN-NEXT: sb a0, 6(sp)
; RV64IPN-NEXT: add a0, a1, a2
; RV64IPN-NEXT: sb a0, 5(sp)
; RV64IPN-NEXT: add a0, a7, a6
; RV64IPN-NEXT: sb a0, 4(sp)
; RV64IPN-NEXT: lw a0, 4(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <4 x i8> %tmp1 = bitcast i32 %a to <4 x i8>
%tmp2 = bitcast i32 %b to <4 x i8> %tmp2 = bitcast i32 %b to <4 x i8>
%add = add <4 x i8> %tmp1, %tmp2 %add = add <4 x i8> %tmp1, %tmp2
%res = bitcast <4 x i8> %add to i32 %res = bitcast <4 x i8> %add to i32
ret i32 %res ret i32 %res
} }
define signext i32 @addv2i16(i32 signext %a, i32 signext %b) nounwind { define signext i32 @addv2i16(i32 signext %a, i32 signext %b) nounwind {
; RV64IP-LABEL: addv2i16: ; RV64IP-LABEL: addv2i16:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: add16 a0, a0, a1
; RV64IP-NEXT: sw a1, 8(sp) ; RV64IP-NEXT: sext.w a0, a0
; RV64IP-NEXT: sw a0, 12(sp)
; RV64IP-NEXT: lh a0, 10(sp)
; RV64IP-NEXT: lh a1, 14(sp)
; RV64IP-NEXT: lh a2, 8(sp)
; RV64IP-NEXT: lh a3, 12(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sh a0, 6(sp)
; RV64IP-NEXT: add a0, a3, a2
; RV64IP-NEXT: sh a0, 4(sp)
; RV64IP-NEXT: lw a0, 4(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: addv2i16: ; RV64IPN-LABEL: addv2i16:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: add16 a0, a0, a1
; RV64IPN-NEXT: sw a1, 8(sp) ; RV64IPN-NEXT: sext.w a0, a0
; RV64IPN-NEXT: sw a0, 12(sp)
; RV64IPN-NEXT: lh a0, 10(sp)
; RV64IPN-NEXT: lh a1, 14(sp)
; RV64IPN-NEXT: lh a2, 8(sp)
; RV64IPN-NEXT: lh a3, 12(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sh a0, 6(sp)
; RV64IPN-NEXT: add a0, a3, a2
; RV64IPN-NEXT: sh a0, 4(sp)
; RV64IPN-NEXT: lw a0, 4(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <2 x i16> %tmp1 = bitcast i32 %a to <2 x i16>
%tmp2 = bitcast i32 %b to <2 x i16> %tmp2 = bitcast i32 %b to <2 x i16>
%add = add <2 x i16> %tmp1, %tmp2 %add = add <2 x i16> %tmp1, %tmp2
%res = bitcast <2 x i16> %add to i32 %res = bitcast <2 x i16> %add to i32
ret i32 %res ret i32 %res
} }
define i64 @addv8i8(i64 %a, i64 %b) nounwind { define i64 @addv8i8(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: addv8i8: ; RV64IP-LABEL: addv8i8:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32 ; RV64IP-NEXT: add8 a0, a0, a1
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lb a0, 23(sp)
; RV64IP-NEXT: lb a1, 15(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sb a0, 31(sp)
; RV64IP-NEXT: lb a0, 22(sp)
; RV64IP-NEXT: lb a1, 14(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sb a0, 30(sp)
; RV64IP-NEXT: lb a0, 21(sp)
; RV64IP-NEXT: lb a1, 13(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sb a0, 29(sp)
; RV64IP-NEXT: lb a0, 20(sp)
; RV64IP-NEXT: lb a1, 12(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sb a0, 28(sp)
; RV64IP-NEXT: lb a0, 19(sp)
; RV64IP-NEXT: lb a1, 11(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sb a0, 27(sp)
; RV64IP-NEXT: lb a0, 18(sp)
; RV64IP-NEXT: lb a1, 10(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sb a0, 26(sp)
; RV64IP-NEXT: lb a0, 17(sp)
; RV64IP-NEXT: lb a1, 9(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sb a0, 25(sp)
; RV64IP-NEXT: lb a0, 16(sp)
; RV64IP-NEXT: lb a1, 8(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sb a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: addv8i8: ; RV64IPN-LABEL: addv8i8:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32 ; RV64IPN-NEXT: add8 a0, a0, a1
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lb a0, 23(sp)
; RV64IPN-NEXT: lb a1, 15(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sb a0, 31(sp)
; RV64IPN-NEXT: lb a0, 22(sp)
; RV64IPN-NEXT: lb a1, 14(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sb a0, 30(sp)
; RV64IPN-NEXT: lb a0, 21(sp)
; RV64IPN-NEXT: lb a1, 13(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sb a0, 29(sp)
; RV64IPN-NEXT: lb a0, 20(sp)
; RV64IPN-NEXT: lb a1, 12(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sb a0, 28(sp)
; RV64IPN-NEXT: lb a0, 19(sp)
; RV64IPN-NEXT: lb a1, 11(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sb a0, 27(sp)
; RV64IPN-NEXT: lb a0, 18(sp)
; RV64IPN-NEXT: lb a1, 10(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sb a0, 26(sp)
; RV64IPN-NEXT: lb a0, 17(sp)
; RV64IPN-NEXT: lb a1, 9(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sb a0, 25(sp)
; RV64IPN-NEXT: lb a0, 16(sp)
; RV64IPN-NEXT: lb a1, 8(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sb a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <8 x i8> %tmp1 = bitcast i64 %a to <8 x i8>
%tmp2 = bitcast i64 %b to <8 x i8> %tmp2 = bitcast i64 %b to <8 x i8>
%add = add <8 x i8> %tmp1, %tmp2 %add = add <8 x i8> %tmp1, %tmp2
%res = bitcast <8 x i8> %add to i64 %res = bitcast <8 x i8> %add to i64
ret i64 %res ret i64 %res
} }
define i64 @addv4i16(i64 %a, i64 %b) nounwind { define i64 @addv4i16(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: addv4i16: ; RV64IP-LABEL: addv4i16:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32 ; RV64IP-NEXT: add16 a0, a0, a1
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lh a0, 22(sp)
; RV64IP-NEXT: lh a1, 14(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sh a0, 30(sp)
; RV64IP-NEXT: lh a0, 20(sp)
; RV64IP-NEXT: lh a1, 12(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sh a0, 28(sp)
; RV64IP-NEXT: lh a0, 18(sp)
; RV64IP-NEXT: lh a1, 10(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sh a0, 26(sp)
; RV64IP-NEXT: lh a0, 16(sp)
; RV64IP-NEXT: lh a1, 8(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sh a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: addv4i16: ; RV64IPN-LABEL: addv4i16:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32 ; RV64IPN-NEXT: add16 a0, a0, a1
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lh a0, 22(sp)
; RV64IPN-NEXT: lh a1, 14(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sh a0, 30(sp)
; RV64IPN-NEXT: lh a0, 20(sp)
; RV64IPN-NEXT: lh a1, 12(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sh a0, 28(sp)
; RV64IPN-NEXT: lh a0, 18(sp)
; RV64IPN-NEXT: lh a1, 10(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sh a0, 26(sp)
; RV64IPN-NEXT: lh a0, 16(sp)
; RV64IPN-NEXT: lh a1, 8(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sh a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <4 x i16> %tmp1 = bitcast i64 %a to <4 x i16>
%tmp2 = bitcast i64 %b to <4 x i16> %tmp2 = bitcast i64 %b to <4 x i16>
%add = add <4 x i16> %tmp1, %tmp2 %add = add <4 x i16> %tmp1, %tmp2
%res = bitcast <4 x i16> %add to i64 %res = bitcast <4 x i16> %add to i64
ret i64 %res ret i64 %res
} }
define i64 @addv2i32(i64 %a, i64 %b) nounwind { define i64 @addv2i32(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: addv2i32: ; RV64IP-LABEL: addv2i32:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32 ; RV64IP-NEXT: add32 a0, a0, a1
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lw a0, 20(sp)
; RV64IP-NEXT: lw a1, 12(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sw a0, 28(sp)
; RV64IP-NEXT: lw a0, 16(sp)
; RV64IP-NEXT: lw a1, 8(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: sw a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: addv2i32: ; RV64IPN-LABEL: addv2i32:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32 ; RV64IPN-NEXT: add32 a0, a0, a1
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lw a0, 20(sp)
; RV64IPN-NEXT: lw a1, 12(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sw a0, 28(sp)
; RV64IPN-NEXT: lw a0, 16(sp)
; RV64IPN-NEXT: lw a1, 8(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: sw a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <2 x i32> %tmp1 = bitcast i64 %a to <2 x i32>
%tmp2 = bitcast i64 %b to <2 x i32> %tmp2 = bitcast i64 %b to <2 x i32>
%add = add <2 x i32> %tmp1, %tmp2 %add = add <2 x i32> %tmp1, %tmp2
%res = bitcast <2 x i32> %add to i64 %res = bitcast <2 x i32> %add to i64
ret i64 %res ret i64 %res
} }
define signext i32 @subv4i8(i32 signext %a, i32 signext %b) nounwind { define signext i32 @subv4i8(i32 signext %a, i32 signext %b) nounwind {
; RV64IP-LABEL: subv4i8: ; RV64IP-LABEL: subv4i8:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: sub8 a0, a0, a1
; RV64IP-NEXT: sw a1, 8(sp) ; RV64IP-NEXT: sext.w a0, a0
; RV64IP-NEXT: sw a0, 12(sp)
; RV64IP-NEXT: lb a6, 8(sp)
; RV64IP-NEXT: lb a7, 12(sp)
; RV64IP-NEXT: lb a2, 9(sp)
; RV64IP-NEXT: lb a3, 11(sp)
; RV64IP-NEXT: lb a4, 15(sp)
; RV64IP-NEXT: lb a5, 10(sp)
; RV64IP-NEXT: lb a0, 14(sp)
; RV64IP-NEXT: lb a1, 13(sp)
; RV64IP-NEXT: sub a3, a4, a3
; RV64IP-NEXT: sb a3, 7(sp)
; RV64IP-NEXT: sub a0, a0, a5
; RV64IP-NEXT: sb a0, 6(sp)
; RV64IP-NEXT: sub a0, a1, a2
; RV64IP-NEXT: sb a0, 5(sp)
; RV64IP-NEXT: sub a0, a7, a6
; RV64IP-NEXT: sb a0, 4(sp)
; RV64IP-NEXT: lw a0, 4(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: subv4i8: ; RV64IPN-LABEL: subv4i8:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: sub8 a0, a0, a1
; RV64IPN-NEXT: sw a1, 8(sp) ; RV64IPN-NEXT: sext.w a0, a0
; RV64IPN-NEXT: sw a0, 12(sp)
; RV64IPN-NEXT: lb a6, 8(sp)
; RV64IPN-NEXT: lb a7, 12(sp)
; RV64IPN-NEXT: lb a2, 9(sp)
; RV64IPN-NEXT: lb a3, 11(sp)
; RV64IPN-NEXT: lb a4, 15(sp)
; RV64IPN-NEXT: lb a5, 10(sp)
; RV64IPN-NEXT: lb a0, 14(sp)
; RV64IPN-NEXT: lb a1, 13(sp)
; RV64IPN-NEXT: sub a3, a4, a3
; RV64IPN-NEXT: sb a3, 7(sp)
; RV64IPN-NEXT: sub a0, a0, a5
; RV64IPN-NEXT: sb a0, 6(sp)
; RV64IPN-NEXT: sub a0, a1, a2
; RV64IPN-NEXT: sb a0, 5(sp)
; RV64IPN-NEXT: sub a0, a7, a6
; RV64IPN-NEXT: sb a0, 4(sp)
; RV64IPN-NEXT: lw a0, 4(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <4 x i8> %tmp1 = bitcast i32 %a to <4 x i8>
%tmp2 = bitcast i32 %b to <4 x i8> %tmp2 = bitcast i32 %b to <4 x i8>
%sub = sub <4 x i8> %tmp1, %tmp2 %sub = sub <4 x i8> %tmp1, %tmp2
%res = bitcast <4 x i8> %sub to i32 %res = bitcast <4 x i8> %sub to i32
ret i32 %res ret i32 %res
} }
define signext i32 @subv2i16(i32 signext %a, i32 signext %b) nounwind { define signext i32 @subv2i16(i32 signext %a, i32 signext %b) nounwind {
; RV64IP-LABEL: subv2i16: ; RV64IP-LABEL: subv2i16:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: sub16 a0, a0, a1
; RV64IP-NEXT: sw a1, 8(sp) ; RV64IP-NEXT: sext.w a0, a0
; RV64IP-NEXT: sw a0, 12(sp)
; RV64IP-NEXT: lh a0, 10(sp)
; RV64IP-NEXT: lh a1, 14(sp)
; RV64IP-NEXT: lh a2, 8(sp)
; RV64IP-NEXT: lh a3, 12(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sh a0, 6(sp)
; RV64IP-NEXT: sub a0, a3, a2
; RV64IP-NEXT: sh a0, 4(sp)
; RV64IP-NEXT: lw a0, 4(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: subv2i16: ; RV64IPN-LABEL: subv2i16:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: sub16 a0, a0, a1
; RV64IPN-NEXT: sw a1, 8(sp) ; RV64IPN-NEXT: sext.w a0, a0
; RV64IPN-NEXT: sw a0, 12(sp)
; RV64IPN-NEXT: lh a0, 10(sp)
; RV64IPN-NEXT: lh a1, 14(sp)
; RV64IPN-NEXT: lh a2, 8(sp)
; RV64IPN-NEXT: lh a3, 12(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sh a0, 6(sp)
; RV64IPN-NEXT: sub a0, a3, a2
; RV64IPN-NEXT: sh a0, 4(sp)
; RV64IPN-NEXT: lw a0, 4(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <2 x i16> %tmp1 = bitcast i32 %a to <2 x i16>
%tmp2 = bitcast i32 %b to <2 x i16> %tmp2 = bitcast i32 %b to <2 x i16>
%sub = sub <2 x i16> %tmp1, %tmp2 %sub = sub <2 x i16> %tmp1, %tmp2
%res = bitcast <2 x i16> %sub to i32 %res = bitcast <2 x i16> %sub to i32
ret i32 %res ret i32 %res
} }
define i64 @subv8i8(i64 %a, i64 %b) nounwind { define i64 @subv8i8(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: subv8i8: ; RV64IP-LABEL: subv8i8:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32 ; RV64IP-NEXT: sub8 a0, a0, a1
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lb a0, 23(sp)
; RV64IP-NEXT: lb a1, 15(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sb a0, 31(sp)
; RV64IP-NEXT: lb a0, 22(sp)
; RV64IP-NEXT: lb a1, 14(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sb a0, 30(sp)
; RV64IP-NEXT: lb a0, 21(sp)
; RV64IP-NEXT: lb a1, 13(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sb a0, 29(sp)
; RV64IP-NEXT: lb a0, 20(sp)
; RV64IP-NEXT: lb a1, 12(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sb a0, 28(sp)
; RV64IP-NEXT: lb a0, 19(sp)
; RV64IP-NEXT: lb a1, 11(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sb a0, 27(sp)
; RV64IP-NEXT: lb a0, 18(sp)
; RV64IP-NEXT: lb a1, 10(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sb a0, 26(sp)
; RV64IP-NEXT: lb a0, 17(sp)
; RV64IP-NEXT: lb a1, 9(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sb a0, 25(sp)
; RV64IP-NEXT: lb a0, 16(sp)
; RV64IP-NEXT: lb a1, 8(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sb a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: subv8i8: ; RV64IPN-LABEL: subv8i8:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32 ; RV64IPN-NEXT: sub8 a0, a0, a1
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lb a0, 23(sp)
; RV64IPN-NEXT: lb a1, 15(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sb a0, 31(sp)
; RV64IPN-NEXT: lb a0, 22(sp)
; RV64IPN-NEXT: lb a1, 14(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sb a0, 30(sp)
; RV64IPN-NEXT: lb a0, 21(sp)
; RV64IPN-NEXT: lb a1, 13(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sb a0, 29(sp)
; RV64IPN-NEXT: lb a0, 20(sp)
; RV64IPN-NEXT: lb a1, 12(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sb a0, 28(sp)
; RV64IPN-NEXT: lb a0, 19(sp)
; RV64IPN-NEXT: lb a1, 11(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sb a0, 27(sp)
; RV64IPN-NEXT: lb a0, 18(sp)
; RV64IPN-NEXT: lb a1, 10(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sb a0, 26(sp)
; RV64IPN-NEXT: lb a0, 17(sp)
; RV64IPN-NEXT: lb a1, 9(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sb a0, 25(sp)
; RV64IPN-NEXT: lb a0, 16(sp)
; RV64IPN-NEXT: lb a1, 8(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sb a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <8 x i8> %tmp1 = bitcast i64 %a to <8 x i8>
%tmp2 = bitcast i64 %b to <8 x i8> %tmp2 = bitcast i64 %b to <8 x i8>
%sub = sub <8 x i8> %tmp1, %tmp2 %sub = sub <8 x i8> %tmp1, %tmp2
%res = bitcast <8 x i8> %sub to i64 %res = bitcast <8 x i8> %sub to i64
ret i64 %res ret i64 %res
} }
define i64 @subv4i16(i64 %a, i64 %b) nounwind { define i64 @subv4i16(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: subv4i16: ; RV64IP-LABEL: subv4i16:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32 ; RV64IP-NEXT: sub16 a0, a0, a1
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lh a0, 22(sp)
; RV64IP-NEXT: lh a1, 14(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sh a0, 30(sp)
; RV64IP-NEXT: lh a0, 20(sp)
; RV64IP-NEXT: lh a1, 12(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sh a0, 28(sp)
; RV64IP-NEXT: lh a0, 18(sp)
; RV64IP-NEXT: lh a1, 10(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sh a0, 26(sp)
; RV64IP-NEXT: lh a0, 16(sp)
; RV64IP-NEXT: lh a1, 8(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sh a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: subv4i16: ; RV64IPN-LABEL: subv4i16:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32 ; RV64IPN-NEXT: sub16 a0, a0, a1
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lh a0, 22(sp)
; RV64IPN-NEXT: lh a1, 14(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sh a0, 30(sp)
; RV64IPN-NEXT: lh a0, 20(sp)
; RV64IPN-NEXT: lh a1, 12(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sh a0, 28(sp)
; RV64IPN-NEXT: lh a0, 18(sp)
; RV64IPN-NEXT: lh a1, 10(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sh a0, 26(sp)
; RV64IPN-NEXT: lh a0, 16(sp)
; RV64IPN-NEXT: lh a1, 8(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sh a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <4 x i16> %tmp1 = bitcast i64 %a to <4 x i16>
%tmp2 = bitcast i64 %b to <4 x i16> %tmp2 = bitcast i64 %b to <4 x i16>
%sub = sub <4 x i16> %tmp1, %tmp2 %sub = sub <4 x i16> %tmp1, %tmp2
%res = bitcast <4 x i16> %sub to i64 %res = bitcast <4 x i16> %sub to i64
ret i64 %res ret i64 %res
} }
define i64 @subv2i32(i64 %a, i64 %b) nounwind { define i64 @subv2i32(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: subv2i32: ; RV64IP-LABEL: subv2i32:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32 ; RV64IP-NEXT: sub32 a0, a0, a1
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lw a0, 20(sp)
; RV64IP-NEXT: lw a1, 12(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sw a0, 28(sp)
; RV64IP-NEXT: lw a0, 16(sp)
; RV64IP-NEXT: lw a1, 8(sp)
; RV64IP-NEXT: sub a0, a1, a0
; RV64IP-NEXT: sw a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: subv2i32: ; RV64IPN-LABEL: subv2i32:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32 ; RV64IPN-NEXT: sub32 a0, a0, a1
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lw a0, 20(sp)
; RV64IPN-NEXT: lw a1, 12(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sw a0, 28(sp)
; RV64IPN-NEXT: lw a0, 16(sp)
; RV64IPN-NEXT: lw a1, 8(sp)
; RV64IPN-NEXT: sub a0, a1, a0
; RV64IPN-NEXT: sw a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <2 x i32> %tmp1 = bitcast i64 %a to <2 x i32>
%tmp2 = bitcast i64 %b to <2 x i32> %tmp2 = bitcast i64 %b to <2 x i32>
%add = sub <2 x i32> %tmp1, %tmp2 %add = sub <2 x i32> %tmp1, %tmp2
%res = bitcast <2 x i32> %add to i64 %res = bitcast <2 x i32> %add to i64
ret i64 %res ret i64 %res
} }
define signext i32 @andv4i8(i32 signext %a) nounwind { define signext i32 @andv4i8(i32 signext %a) nounwind {
; RV64IP-LABEL: andv4i8: ; RV64IP-LABEL: andv4i8:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: lui a1, %hi(.LCPI10_0)
; RV64IP-NEXT: sw a0, 12(sp) ; RV64IP-NEXT: ld a1, %lo(.LCPI10_0)(a1)
; RV64IP-NEXT: lbu a0, 15(sp) ; RV64IP-NEXT: and a0, a0, a1
; RV64IP-NEXT: lbu a1, 12(sp) ; RV64IP-NEXT: lui a1, 16432
; RV64IP-NEXT: lbu a2, 14(sp) ; RV64IP-NEXT: addiw a1, a1, 513
; RV64IP-NEXT: lbu a3, 13(sp) ; RV64IP-NEXT: and a0, a0, a1
; RV64IP-NEXT: andi a0, a0, 4
; RV64IP-NEXT: sb a0, 11(sp)
; RV64IP-NEXT: andi a0, a2, 3
; RV64IP-NEXT: sb a0, 10(sp)
; RV64IP-NEXT: andi a0, a3, 2
; RV64IP-NEXT: sb a0, 9(sp)
; RV64IP-NEXT: andi a0, a1, 1
; RV64IP-NEXT: sb a0, 8(sp)
; RV64IP-NEXT: lwu a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: andv4i8: ; RV64IPN-LABEL: andv4i8:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: lui a1, %hi(.LCPI10_0)
; RV64IPN-NEXT: sw a0, 12(sp) ; RV64IPN-NEXT: ld a1, %lo(.LCPI10_0)(a1)
; RV64IPN-NEXT: lbu a0, 15(sp) ; RV64IPN-NEXT: and a0, a0, a1
; RV64IPN-NEXT: lbu a1, 12(sp) ; RV64IPN-NEXT: lui a1, 16432
; RV64IPN-NEXT: lbu a2, 14(sp) ; RV64IPN-NEXT: addiw a1, a1, 513
; RV64IPN-NEXT: lbu a3, 13(sp) ; RV64IPN-NEXT: and a0, a0, a1
; RV64IPN-NEXT: andi a0, a0, 4
; RV64IPN-NEXT: sb a0, 11(sp)
; RV64IPN-NEXT: andi a0, a2, 3
; RV64IPN-NEXT: sb a0, 10(sp)
; RV64IPN-NEXT: andi a0, a3, 2
; RV64IPN-NEXT: sb a0, 9(sp)
; RV64IPN-NEXT: andi a0, a1, 1
; RV64IPN-NEXT: sb a0, 8(sp)
; RV64IPN-NEXT: lwu a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp = bitcast i32 %a to <4 x i8> %tmp = bitcast i32 %a to <4 x i8>
%and = and <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4> %and = and <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4>
%res = bitcast <4 x i8> %and to i32 %res = bitcast <4 x i8> %and to i32
ret i32 %res ret i32 %res
} }
define signext i32 @andv2i16(i32 signext %a) nounwind { define signext i32 @andv2i16(i32 signext %a) nounwind {
; RV64IP-LABEL: andv2i16: ; RV64IP-LABEL: andv2i16:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: lui a1, %hi(.LCPI11_0)
; RV64IP-NEXT: sw a0, 12(sp) ; RV64IP-NEXT: ld a1, %lo(.LCPI11_0)(a1)
; RV64IP-NEXT: lhu a0, 14(sp) ; RV64IP-NEXT: and a0, a0, a1
; RV64IP-NEXT: lhu a1, 12(sp) ; RV64IP-NEXT: lui a1, 32
; RV64IP-NEXT: andi a0, a0, 2 ; RV64IP-NEXT: addiw a1, a1, 1
; RV64IP-NEXT: sh a0, 10(sp) ; RV64IP-NEXT: and a0, a0, a1
; RV64IP-NEXT: andi a0, a1, 1
; RV64IP-NEXT: sh a0, 8(sp)
; RV64IP-NEXT: lwu a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: andv2i16: ; RV64IPN-LABEL: andv2i16:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: lui a1, %hi(.LCPI11_0)
; RV64IPN-NEXT: sw a0, 12(sp) ; RV64IPN-NEXT: ld a1, %lo(.LCPI11_0)(a1)
; RV64IPN-NEXT: lhu a0, 14(sp) ; RV64IPN-NEXT: and a0, a0, a1
; RV64IPN-NEXT: lhu a1, 12(sp) ; RV64IPN-NEXT: lui a1, 32
; RV64IPN-NEXT: andi a0, a0, 2 ; RV64IPN-NEXT: addiw a1, a1, 1
; RV64IPN-NEXT: sh a0, 10(sp) ; RV64IPN-NEXT: and a0, a0, a1
; RV64IPN-NEXT: andi a0, a1, 1
; RV64IPN-NEXT: sh a0, 8(sp)
; RV64IPN-NEXT: lwu a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp = bitcast i32 %a to <2 x i16> %tmp = bitcast i32 %a to <2 x i16>
%and = and <2 x i16> %tmp, <i16 1, i16 2> %and = and <2 x i16> %tmp, <i16 1, i16 2>
%res = bitcast <2 x i16> %and to i32 %res = bitcast <2 x i16> %and to i32
ret i32 %res ret i32 %res
} }
define i64 @andv8i8(i64 %a) nounwind { define i64 @andv8i8(i64 %a) nounwind {
; RV64IP-LABEL: andv8i8: ; RV64IP-LABEL: andv8i8:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: lui a1, %hi(.LCPI12_0)
; RV64IP-NEXT: sd a0, 0(sp) ; RV64IP-NEXT: ld a1, %lo(.LCPI12_0)(a1)
; RV64IP-NEXT: lbu a0, 7(sp) ; RV64IP-NEXT: and a0, a0, a1
; RV64IP-NEXT: andi a0, a0, 8
; RV64IP-NEXT: sb a0, 15(sp)
; RV64IP-NEXT: lbu a0, 6(sp)
; RV64IP-NEXT: andi a0, a0, 7
; RV64IP-NEXT: sb a0, 14(sp)
; RV64IP-NEXT: lbu a0, 5(sp)
; RV64IP-NEXT: andi a0, a0, 6
; RV64IP-NEXT: sb a0, 13(sp)
; RV64IP-NEXT: lbu a0, 4(sp)
; RV64IP-NEXT: andi a0, a0, 5
; RV64IP-NEXT: sb a0, 12(sp)
; RV64IP-NEXT: lbu a0, 3(sp)
; RV64IP-NEXT: andi a0, a0, 4
; RV64IP-NEXT: sb a0, 11(sp)
; RV64IP-NEXT: lbu a0, 2(sp)
; RV64IP-NEXT: andi a0, a0, 3
; RV64IP-NEXT: sb a0, 10(sp)
; RV64IP-NEXT: lbu a0, 1(sp)
; RV64IP-NEXT: andi a0, a0, 2
; RV64IP-NEXT: sb a0, 9(sp)
; RV64IP-NEXT: lbu a0, 0(sp)
; RV64IP-NEXT: andi a0, a0, 1
; RV64IP-NEXT: sb a0, 8(sp)
; RV64IP-NEXT: ld a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: andv8i8: ; RV64IPN-LABEL: andv8i8:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: lui a1, %hi(.LCPI12_0)
; RV64IPN-NEXT: sd a0, 0(sp) ; RV64IPN-NEXT: ld a1, %lo(.LCPI12_0)(a1)
; RV64IPN-NEXT: lbu a0, 7(sp) ; RV64IPN-NEXT: and a0, a0, a1
; RV64IPN-NEXT: andi a0, a0, 8
; RV64IPN-NEXT: sb a0, 15(sp)
; RV64IPN-NEXT: lbu a0, 6(sp)
; RV64IPN-NEXT: andi a0, a0, 7
; RV64IPN-NEXT: sb a0, 14(sp)
; RV64IPN-NEXT: lbu a0, 5(sp)
; RV64IPN-NEXT: andi a0, a0, 6
; RV64IPN-NEXT: sb a0, 13(sp)
; RV64IPN-NEXT: lbu a0, 4(sp)
; RV64IPN-NEXT: andi a0, a0, 5
; RV64IPN-NEXT: sb a0, 12(sp)
; RV64IPN-NEXT: lbu a0, 3(sp)
; RV64IPN-NEXT: andi a0, a0, 4
; RV64IPN-NEXT: sb a0, 11(sp)
; RV64IPN-NEXT: lbu a0, 2(sp)
; RV64IPN-NEXT: andi a0, a0, 3
; RV64IPN-NEXT: sb a0, 10(sp)
; RV64IPN-NEXT: lbu a0, 1(sp)
; RV64IPN-NEXT: andi a0, a0, 2
; RV64IPN-NEXT: sb a0, 9(sp)
; RV64IPN-NEXT: lbu a0, 0(sp)
; RV64IPN-NEXT: andi a0, a0, 1
; RV64IPN-NEXT: sb a0, 8(sp)
; RV64IPN-NEXT: ld a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp = bitcast i64 %a to <8 x i8> %tmp = bitcast i64 %a to <8 x i8>
%and = and <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8> %and = and <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
%res = bitcast <8 x i8> %and to i64 %res = bitcast <8 x i8> %and to i64
ret i64 %res ret i64 %res
} }
define i64 @andv4i16(i64 %a) nounwind { define i64 @andv4i16(i64 %a) nounwind {
; RV64IP-LABEL: andv4i16: ; RV64IP-LABEL: andv4i16:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: lui a1, %hi(.LCPI13_0)
; RV64IP-NEXT: sd a0, 0(sp) ; RV64IP-NEXT: ld a1, %lo(.LCPI13_0)(a1)
; RV64IP-NEXT: lhu a0, 6(sp) ; RV64IP-NEXT: and a0, a0, a1
; RV64IP-NEXT: andi a0, a0, 4
; RV64IP-NEXT: sh a0, 14(sp)
; RV64IP-NEXT: lhu a0, 4(sp)
; RV64IP-NEXT: andi a0, a0, 3
; RV64IP-NEXT: sh a0, 12(sp)
; RV64IP-NEXT: lhu a0, 2(sp)
; RV64IP-NEXT: andi a0, a0, 2
; RV64IP-NEXT: sh a0, 10(sp)
; RV64IP-NEXT: lhu a0, 0(sp)
; RV64IP-NEXT: andi a0, a0, 1
; RV64IP-NEXT: sh a0, 8(sp)
; RV64IP-NEXT: ld a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: andv4i16: ; RV64IPN-LABEL: andv4i16:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: lui a1, %hi(.LCPI13_0)
; RV64IPN-NEXT: sd a0, 0(sp) ; RV64IPN-NEXT: ld a1, %lo(.LCPI13_0)(a1)
; RV64IPN-NEXT: lhu a0, 6(sp) ; RV64IPN-NEXT: and a0, a0, a1
; RV64IPN-NEXT: andi a0, a0, 4
; RV64IPN-NEXT: sh a0, 14(sp)
; RV64IPN-NEXT: lhu a0, 4(sp)
; RV64IPN-NEXT: andi a0, a0, 3
; RV64IPN-NEXT: sh a0, 12(sp)
; RV64IPN-NEXT: lhu a0, 2(sp)
; RV64IPN-NEXT: andi a0, a0, 2
; RV64IPN-NEXT: sh a0, 10(sp)
; RV64IPN-NEXT: lhu a0, 0(sp)
; RV64IPN-NEXT: andi a0, a0, 1
; RV64IPN-NEXT: sh a0, 8(sp)
; RV64IPN-NEXT: ld a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp = bitcast i64 %a to <4 x i16> %tmp = bitcast i64 %a to <4 x i16>
%and = and <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4> %and = and <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4>
%res = bitcast <4 x i16> %and to i64 %res = bitcast <4 x i16> %and to i64
ret i64 %res ret i64 %res
} }
define i64 @andv2i32(i64 %a) nounwind { define i64 @andv2i32(i64 %a) nounwind {
; RV64IP-LABEL: andv2i32: ; RV64IP-LABEL: andv2i32:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: lui a1, %hi(.LCPI14_0)
; RV64IP-NEXT: sd a0, 0(sp) ; RV64IP-NEXT: ld a1, %lo(.LCPI14_0)(a1)
; RV64IP-NEXT: lwu a0, 4(sp) ; RV64IP-NEXT: and a0, a0, a1
; RV64IP-NEXT: andi a0, a0, 2
; RV64IP-NEXT: sw a0, 12(sp)
; RV64IP-NEXT: lwu a0, 0(sp)
; RV64IP-NEXT: andi a0, a0, 1
; RV64IP-NEXT: sw a0, 8(sp)
; RV64IP-NEXT: ld a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: andv2i32: ; RV64IPN-LABEL: andv2i32:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: lui a1, %hi(.LCPI14_0)
; RV64IPN-NEXT: sd a0, 0(sp) ; RV64IPN-NEXT: ld a1, %lo(.LCPI14_0)(a1)
; RV64IPN-NEXT: lwu a0, 4(sp) ; RV64IPN-NEXT: and a0, a0, a1
; RV64IPN-NEXT: andi a0, a0, 2
; RV64IPN-NEXT: sw a0, 12(sp)
; RV64IPN-NEXT: lwu a0, 0(sp)
; RV64IPN-NEXT: andi a0, a0, 1
; RV64IPN-NEXT: sw a0, 8(sp)
; RV64IPN-NEXT: ld a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp = bitcast i64 %a to <2 x i32> %tmp = bitcast i64 %a to <2 x i32>
%and = and <2 x i32> %tmp, <i32 1, i32 2> %and = and <2 x i32> %tmp, <i32 1, i32 2>
%res = bitcast <2 x i32> %and to i64 %res = bitcast <2 x i32> %and to i64
ret i64 %res ret i64 %res
} }
define signext i32 @orv4i8(i32 signext %a) nounwind { define signext i32 @orv4i8(i32 signext %a) nounwind {
; RV64IP-LABEL: orv4i8: ; RV64IP-LABEL: orv4i8:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: lui a1, %hi(.LCPI15_0)
; RV64IP-NEXT: sw a0, 12(sp) ; RV64IP-NEXT: ld a1, %lo(.LCPI15_0)(a1)
; RV64IP-NEXT: lb a0, 15(sp) ; RV64IP-NEXT: or a0, a0, a1
; RV64IP-NEXT: lb a1, 12(sp) ; RV64IP-NEXT: sext.w a0, a0
; RV64IP-NEXT: lb a2, 14(sp)
; RV64IP-NEXT: lb a3, 13(sp)
; RV64IP-NEXT: ori a0, a0, 4
; RV64IP-NEXT: sb a0, 11(sp)
; RV64IP-NEXT: ori a0, a2, 3
; RV64IP-NEXT: sb a0, 10(sp)
; RV64IP-NEXT: ori a0, a3, 2
; RV64IP-NEXT: sb a0, 9(sp)
; RV64IP-NEXT: ori a0, a1, 1
; RV64IP-NEXT: sb a0, 8(sp)
; RV64IP-NEXT: lw a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: orv4i8: ; RV64IPN-LABEL: orv4i8:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: lui a1, %hi(.LCPI15_0)
; RV64IPN-NEXT: sw a0, 12(sp) ; RV64IPN-NEXT: ld a1, %lo(.LCPI15_0)(a1)
; RV64IPN-NEXT: lb a0, 15(sp) ; RV64IPN-NEXT: or a0, a0, a1
; RV64IPN-NEXT: lb a1, 12(sp) ; RV64IPN-NEXT: sext.w a0, a0
; RV64IPN-NEXT: lb a2, 14(sp)
; RV64IPN-NEXT: lb a3, 13(sp)
; RV64IPN-NEXT: ori a0, a0, 4
; RV64IPN-NEXT: sb a0, 11(sp)
; RV64IPN-NEXT: ori a0, a2, 3
; RV64IPN-NEXT: sb a0, 10(sp)
; RV64IPN-NEXT: ori a0, a3, 2
; RV64IPN-NEXT: sb a0, 9(sp)
; RV64IPN-NEXT: ori a0, a1, 1
; RV64IPN-NEXT: sb a0, 8(sp)
; RV64IPN-NEXT: lw a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp = bitcast i32 %a to <4 x i8> %tmp = bitcast i32 %a to <4 x i8>
%or = or <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4> %or = or <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4>
%res = bitcast <4 x i8> %or to i32 %res = bitcast <4 x i8> %or to i32
ret i32 %res ret i32 %res
} }
define signext i32 @orv2i16(i32 signext %a) nounwind { define signext i32 @orv2i16(i32 signext %a) nounwind {
; RV64IP-LABEL: orv2i16: ; RV64IP-LABEL: orv2i16:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: lui a1, %hi(.LCPI16_0)
; RV64IP-NEXT: sw a0, 12(sp) ; RV64IP-NEXT: ld a1, %lo(.LCPI16_0)(a1)
; RV64IP-NEXT: lh a0, 14(sp) ; RV64IP-NEXT: or a0, a0, a1
; RV64IP-NEXT: lh a1, 12(sp) ; RV64IP-NEXT: sext.w a0, a0
; RV64IP-NEXT: ori a0, a0, 2
; RV64IP-NEXT: sh a0, 10(sp)
; RV64IP-NEXT: ori a0, a1, 1
; RV64IP-NEXT: sh a0, 8(sp)
; RV64IP-NEXT: lw a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: orv2i16: ; RV64IPN-LABEL: orv2i16:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: lui a1, %hi(.LCPI16_0)
; RV64IPN-NEXT: sw a0, 12(sp) ; RV64IPN-NEXT: ld a1, %lo(.LCPI16_0)(a1)
; RV64IPN-NEXT: lh a0, 14(sp) ; RV64IPN-NEXT: or a0, a0, a1
; RV64IPN-NEXT: lh a1, 12(sp) ; RV64IPN-NEXT: sext.w a0, a0
; RV64IPN-NEXT: ori a0, a0, 2
; RV64IPN-NEXT: sh a0, 10(sp)
; RV64IPN-NEXT: ori a0, a1, 1
; RV64IPN-NEXT: sh a0, 8(sp)
; RV64IPN-NEXT: lw a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp = bitcast i32 %a to <2 x i16> %tmp = bitcast i32 %a to <2 x i16>
%or = or <2 x i16> %tmp, <i16 1, i16 2> %or = or <2 x i16> %tmp, <i16 1, i16 2>
%res = bitcast <2 x i16> %or to i32 %res = bitcast <2 x i16> %or to i32
ret i32 %res ret i32 %res
} }
define i64 @orv8i8(i64 %a) nounwind { define i64 @orv8i8(i64 %a) nounwind {
; RV64IP-LABEL: orv8i8: ; RV64IP-LABEL: orv8i8:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: lui a1, %hi(.LCPI17_0)
; RV64IP-NEXT: sd a0, 0(sp) ; RV64IP-NEXT: ld a1, %lo(.LCPI17_0)(a1)
; RV64IP-NEXT: lb a0, 7(sp) ; RV64IP-NEXT: or a0, a0, a1
; RV64IP-NEXT: ori a0, a0, 8
; RV64IP-NEXT: sb a0, 15(sp)
; RV64IP-NEXT: lb a0, 6(sp)
; RV64IP-NEXT: ori a0, a0, 7
; RV64IP-NEXT: sb a0, 14(sp)
; RV64IP-NEXT: lb a0, 5(sp)
; RV64IP-NEXT: ori a0, a0, 6
; RV64IP-NEXT: sb a0, 13(sp)
; RV64IP-NEXT: lb a0, 4(sp)
; RV64IP-NEXT: ori a0, a0, 5
; RV64IP-NEXT: sb a0, 12(sp)
; RV64IP-NEXT: lb a0, 3(sp)
; RV64IP-NEXT: ori a0, a0, 4
; RV64IP-NEXT: sb a0, 11(sp)
; RV64IP-NEXT: lb a0, 2(sp)
; RV64IP-NEXT: ori a0, a0, 3
; RV64IP-NEXT: sb a0, 10(sp)
; RV64IP-NEXT: lb a0, 1(sp)
; RV64IP-NEXT: ori a0, a0, 2
; RV64IP-NEXT: sb a0, 9(sp)
; RV64IP-NEXT: lb a0, 0(sp)
; RV64IP-NEXT: ori a0, a0, 1
; RV64IP-NEXT: sb a0, 8(sp)
; RV64IP-NEXT: ld a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: orv8i8: ; RV64IPN-LABEL: orv8i8:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: lui a1, %hi(.LCPI17_0)
; RV64IPN-NEXT: sd a0, 0(sp) ; RV64IPN-NEXT: ld a1, %lo(.LCPI17_0)(a1)
; RV64IPN-NEXT: lb a0, 7(sp) ; RV64IPN-NEXT: or a0, a0, a1
; RV64IPN-NEXT: ori a0, a0, 8
; RV64IPN-NEXT: sb a0, 15(sp)
; RV64IPN-NEXT: lb a0, 6(sp)
; RV64IPN-NEXT: ori a0, a0, 7
; RV64IPN-NEXT: sb a0, 14(sp)
; RV64IPN-NEXT: lb a0, 5(sp)
; RV64IPN-NEXT: ori a0, a0, 6
; RV64IPN-NEXT: sb a0, 13(sp)
; RV64IPN-NEXT: lb a0, 4(sp)
; RV64IPN-NEXT: ori a0, a0, 5
; RV64IPN-NEXT: sb a0, 12(sp)
; RV64IPN-NEXT: lb a0, 3(sp)
; RV64IPN-NEXT: ori a0, a0, 4
; RV64IPN-NEXT: sb a0, 11(sp)
; RV64IPN-NEXT: lb a0, 2(sp)
; RV64IPN-NEXT: ori a0, a0, 3
; RV64IPN-NEXT: sb a0, 10(sp)
; RV64IPN-NEXT: lb a0, 1(sp)
; RV64IPN-NEXT: ori a0, a0, 2
; RV64IPN-NEXT: sb a0, 9(sp)
; RV64IPN-NEXT: lb a0, 0(sp)
; RV64IPN-NEXT: ori a0, a0, 1
; RV64IPN-NEXT: sb a0, 8(sp)
; RV64IPN-NEXT: ld a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp = bitcast i64 %a to <8 x i8> %tmp = bitcast i64 %a to <8 x i8>
%or = or <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8> %or = or <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
%res = bitcast <8 x i8> %or to i64 %res = bitcast <8 x i8> %or to i64
ret i64 %res ret i64 %res
} }
define i64 @orv4i16(i64 %a) nounwind { define i64 @orv4i16(i64 %a) nounwind {
; RV64IP-LABEL: orv4i16: ; RV64IP-LABEL: orv4i16:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: lui a1, %hi(.LCPI18_0)
; RV64IP-NEXT: sd a0, 0(sp) ; RV64IP-NEXT: ld a1, %lo(.LCPI18_0)(a1)
; RV64IP-NEXT: lh a0, 6(sp) ; RV64IP-NEXT: or a0, a0, a1
; RV64IP-NEXT: ori a0, a0, 4
; RV64IP-NEXT: sh a0, 14(sp)
; RV64IP-NEXT: lh a0, 4(sp)
; RV64IP-NEXT: ori a0, a0, 3
; RV64IP-NEXT: sh a0, 12(sp)
; RV64IP-NEXT: lh a0, 2(sp)
; RV64IP-NEXT: ori a0, a0, 2
; RV64IP-NEXT: sh a0, 10(sp)
; RV64IP-NEXT: lh a0, 0(sp)
; RV64IP-NEXT: ori a0, a0, 1
; RV64IP-NEXT: sh a0, 8(sp)
; RV64IP-NEXT: ld a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: orv4i16: ; RV64IPN-LABEL: orv4i16:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: lui a1, %hi(.LCPI18_0)
; RV64IPN-NEXT: sd a0, 0(sp) ; RV64IPN-NEXT: ld a1, %lo(.LCPI18_0)(a1)
; RV64IPN-NEXT: lh a0, 6(sp) ; RV64IPN-NEXT: or a0, a0, a1
; RV64IPN-NEXT: ori a0, a0, 4
; RV64IPN-NEXT: sh a0, 14(sp)
; RV64IPN-NEXT: lh a0, 4(sp)
; RV64IPN-NEXT: ori a0, a0, 3
; RV64IPN-NEXT: sh a0, 12(sp)
; RV64IPN-NEXT: lh a0, 2(sp)
; RV64IPN-NEXT: ori a0, a0, 2
; RV64IPN-NEXT: sh a0, 10(sp)
; RV64IPN-NEXT: lh a0, 0(sp)
; RV64IPN-NEXT: ori a0, a0, 1
; RV64IPN-NEXT: sh a0, 8(sp)
; RV64IPN-NEXT: ld a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp = bitcast i64 %a to <4 x i16> %tmp = bitcast i64 %a to <4 x i16>
%or = or <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4> %or = or <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4>
%res = bitcast <4 x i16> %or to i64 %res = bitcast <4 x i16> %or to i64
ret i64 %res ret i64 %res
} }
define i64 @orv2i32(i64 %a) nounwind { define i64 @orv2i32(i64 %a) nounwind {
; RV64IP-LABEL: orv2i32: ; RV64IP-LABEL: orv2i32:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: lui a1, %hi(.LCPI19_0)
; RV64IP-NEXT: sd a0, 0(sp) ; RV64IP-NEXT: ld a1, %lo(.LCPI19_0)(a1)
; RV64IP-NEXT: lw a0, 4(sp) ; RV64IP-NEXT: or a0, a0, a1
; RV64IP-NEXT: ori a0, a0, 2
; RV64IP-NEXT: sw a0, 12(sp)
; RV64IP-NEXT: lw a0, 0(sp)
; RV64IP-NEXT: ori a0, a0, 1
; RV64IP-NEXT: sw a0, 8(sp)
; RV64IP-NEXT: ld a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: orv2i32: ; RV64IPN-LABEL: orv2i32:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: lui a1, %hi(.LCPI19_0)
; RV64IPN-NEXT: sd a0, 0(sp) ; RV64IPN-NEXT: ld a1, %lo(.LCPI19_0)(a1)
; RV64IPN-NEXT: lw a0, 4(sp) ; RV64IPN-NEXT: or a0, a0, a1
; RV64IPN-NEXT: ori a0, a0, 2
; RV64IPN-NEXT: sw a0, 12(sp)
; RV64IPN-NEXT: lw a0, 0(sp)
; RV64IPN-NEXT: ori a0, a0, 1
; RV64IPN-NEXT: sw a0, 8(sp)
; RV64IPN-NEXT: ld a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp = bitcast i64 %a to <2 x i32> %tmp = bitcast i64 %a to <2 x i32>
%or = or <2 x i32> %tmp, <i32 1, i32 2> %or = or <2 x i32> %tmp, <i32 1, i32 2>
%res = bitcast <2 x i32> %or to i64 %res = bitcast <2 x i32> %or to i64
ret i64 %res ret i64 %res
} }
define signext i32 @xorv4i8(i32 signext %a) nounwind { define signext i32 @xorv4i8(i32 signext %a) nounwind {
; RV64IP-LABEL: xorv4i8: ; RV64IP-LABEL: xorv4i8:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: lui a1, %hi(.LCPI20_0)
; RV64IP-NEXT: sw a0, 12(sp) ; RV64IP-NEXT: ld a1, %lo(.LCPI20_0)(a1)
; RV64IP-NEXT: lb a0, 15(sp) ; RV64IP-NEXT: xor a0, a0, a1
; RV64IP-NEXT: lb a1, 12(sp) ; RV64IP-NEXT: sext.w a0, a0
; RV64IP-NEXT: lb a2, 14(sp)
; RV64IP-NEXT: lb a3, 13(sp)
; RV64IP-NEXT: xori a0, a0, 4
; RV64IP-NEXT: sb a0, 11(sp)
; RV64IP-NEXT: xori a0, a2, 3
; RV64IP-NEXT: sb a0, 10(sp)
; RV64IP-NEXT: xori a0, a3, 2
; RV64IP-NEXT: sb a0, 9(sp)
; RV64IP-NEXT: xori a0, a1, 1
; RV64IP-NEXT: sb a0, 8(sp)
; RV64IP-NEXT: lw a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: xorv4i8: ; RV64IPN-LABEL: xorv4i8:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: lui a1, %hi(.LCPI20_0)
; RV64IPN-NEXT: sw a0, 12(sp) ; RV64IPN-NEXT: ld a1, %lo(.LCPI20_0)(a1)
; RV64IPN-NEXT: lb a0, 15(sp) ; RV64IPN-NEXT: xor a0, a0, a1
; RV64IPN-NEXT: lb a1, 12(sp) ; RV64IPN-NEXT: sext.w a0, a0
; RV64IPN-NEXT: lb a2, 14(sp)
; RV64IPN-NEXT: lb a3, 13(sp)
; RV64IPN-NEXT: xori a0, a0, 4
; RV64IPN-NEXT: sb a0, 11(sp)
; RV64IPN-NEXT: xori a0, a2, 3
; RV64IPN-NEXT: sb a0, 10(sp)
; RV64IPN-NEXT: xori a0, a3, 2
; RV64IPN-NEXT: sb a0, 9(sp)
; RV64IPN-NEXT: xori a0, a1, 1
; RV64IPN-NEXT: sb a0, 8(sp)
; RV64IPN-NEXT: lw a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp = bitcast i32 %a to <4 x i8> %tmp = bitcast i32 %a to <4 x i8>
%xor = xor <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4> %xor = xor <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4>
%res = bitcast <4 x i8> %xor to i32 %res = bitcast <4 x i8> %xor to i32
ret i32 %res ret i32 %res
} }
define signext i32 @xorv2i16(i32 signext %a) nounwind { define signext i32 @xorv2i16(i32 signext %a) nounwind {
; RV64IP-LABEL: xorv2i16: ; RV64IP-LABEL: xorv2i16:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: lui a1, %hi(.LCPI21_0)
; RV64IP-NEXT: sw a0, 12(sp) ; RV64IP-NEXT: ld a1, %lo(.LCPI21_0)(a1)
; RV64IP-NEXT: lh a0, 14(sp) ; RV64IP-NEXT: xor a0, a0, a1
; RV64IP-NEXT: lh a1, 12(sp) ; RV64IP-NEXT: sext.w a0, a0
; RV64IP-NEXT: xori a0, a0, 2
; RV64IP-NEXT: sh a0, 10(sp)
; RV64IP-NEXT: xori a0, a1, 1
; RV64IP-NEXT: sh a0, 8(sp)
; RV64IP-NEXT: lw a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: xorv2i16: ; RV64IPN-LABEL: xorv2i16:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: lui a1, %hi(.LCPI21_0)
; RV64IPN-NEXT: sw a0, 12(sp) ; RV64IPN-NEXT: ld a1, %lo(.LCPI21_0)(a1)
; RV64IPN-NEXT: lh a0, 14(sp) ; RV64IPN-NEXT: xor a0, a0, a1
; RV64IPN-NEXT: lh a1, 12(sp) ; RV64IPN-NEXT: sext.w a0, a0
; RV64IPN-NEXT: xori a0, a0, 2
; RV64IPN-NEXT: sh a0, 10(sp)
; RV64IPN-NEXT: xori a0, a1, 1
; RV64IPN-NEXT: sh a0, 8(sp)
; RV64IPN-NEXT: lw a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp = bitcast i32 %a to <2 x i16> %tmp = bitcast i32 %a to <2 x i16>
%xor = xor <2 x i16> %tmp, <i16 1, i16 2> %xor = xor <2 x i16> %tmp, <i16 1, i16 2>
%res = bitcast <2 x i16> %xor to i32 %res = bitcast <2 x i16> %xor to i32
ret i32 %res ret i32 %res
} }
define i64 @xorv8i8(i64 %a) nounwind { define i64 @xorv8i8(i64 %a) nounwind {
; RV64IP-LABEL: xorv8i8: ; RV64IP-LABEL: xorv8i8:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: lui a1, %hi(.LCPI22_0)
; RV64IP-NEXT: sd a0, 0(sp) ; RV64IP-NEXT: ld a1, %lo(.LCPI22_0)(a1)
; RV64IP-NEXT: lb a0, 7(sp) ; RV64IP-NEXT: xor a0, a0, a1
; RV64IP-NEXT: xori a0, a0, 8
; RV64IP-NEXT: sb a0, 15(sp)
; RV64IP-NEXT: lb a0, 6(sp)
; RV64IP-NEXT: xori a0, a0, 7
; RV64IP-NEXT: sb a0, 14(sp)
; RV64IP-NEXT: lb a0, 5(sp)
; RV64IP-NEXT: xori a0, a0, 6
; RV64IP-NEXT: sb a0, 13(sp)
; RV64IP-NEXT: lb a0, 4(sp)
; RV64IP-NEXT: xori a0, a0, 5
; RV64IP-NEXT: sb a0, 12(sp)
; RV64IP-NEXT: lb a0, 3(sp)
; RV64IP-NEXT: xori a0, a0, 4
; RV64IP-NEXT: sb a0, 11(sp)
; RV64IP-NEXT: lb a0, 2(sp)
; RV64IP-NEXT: xori a0, a0, 3
; RV64IP-NEXT: sb a0, 10(sp)
; RV64IP-NEXT: lb a0, 1(sp)
; RV64IP-NEXT: xori a0, a0, 2
; RV64IP-NEXT: sb a0, 9(sp)
; RV64IP-NEXT: lb a0, 0(sp)
; RV64IP-NEXT: xori a0, a0, 1
; RV64IP-NEXT: sb a0, 8(sp)
; RV64IP-NEXT: ld a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: xorv8i8: ; RV64IPN-LABEL: xorv8i8:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: lui a1, %hi(.LCPI22_0)
; RV64IPN-NEXT: sd a0, 0(sp) ; RV64IPN-NEXT: ld a1, %lo(.LCPI22_0)(a1)
; RV64IPN-NEXT: lb a0, 7(sp) ; RV64IPN-NEXT: xor a0, a0, a1
; RV64IPN-NEXT: xori a0, a0, 8
; RV64IPN-NEXT: sb a0, 15(sp)
; RV64IPN-NEXT: lb a0, 6(sp)
; RV64IPN-NEXT: xori a0, a0, 7
; RV64IPN-NEXT: sb a0, 14(sp)
; RV64IPN-NEXT: lb a0, 5(sp)
; RV64IPN-NEXT: xori a0, a0, 6
; RV64IPN-NEXT: sb a0, 13(sp)
; RV64IPN-NEXT: lb a0, 4(sp)
; RV64IPN-NEXT: xori a0, a0, 5
; RV64IPN-NEXT: sb a0, 12(sp)
; RV64IPN-NEXT: lb a0, 3(sp)
; RV64IPN-NEXT: xori a0, a0, 4
; RV64IPN-NEXT: sb a0, 11(sp)
; RV64IPN-NEXT: lb a0, 2(sp)
; RV64IPN-NEXT: xori a0, a0, 3
; RV64IPN-NEXT: sb a0, 10(sp)
; RV64IPN-NEXT: lb a0, 1(sp)
; RV64IPN-NEXT: xori a0, a0, 2
; RV64IPN-NEXT: sb a0, 9(sp)
; RV64IPN-NEXT: lb a0, 0(sp)
; RV64IPN-NEXT: xori a0, a0, 1
; RV64IPN-NEXT: sb a0, 8(sp)
; RV64IPN-NEXT: ld a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp = bitcast i64 %a to <8 x i8> %tmp = bitcast i64 %a to <8 x i8>
%xor = xor <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8> %xor = xor <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
%res = bitcast <8 x i8> %xor to i64 %res = bitcast <8 x i8> %xor to i64
ret i64 %res ret i64 %res
} }
define i64 @xorv4i16(i64 %a) nounwind { define i64 @xorv4i16(i64 %a) nounwind {
; RV64IP-LABEL: xorv4i16: ; RV64IP-LABEL: xorv4i16:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: lui a1, %hi(.LCPI23_0)
; RV64IP-NEXT: sd a0, 0(sp) ; RV64IP-NEXT: ld a1, %lo(.LCPI23_0)(a1)
; RV64IP-NEXT: lh a0, 6(sp) ; RV64IP-NEXT: xor a0, a0, a1
; RV64IP-NEXT: xori a0, a0, 4
; RV64IP-NEXT: sh a0, 14(sp)
; RV64IP-NEXT: lh a0, 4(sp)
; RV64IP-NEXT: xori a0, a0, 3
; RV64IP-NEXT: sh a0, 12(sp)
; RV64IP-NEXT: lh a0, 2(sp)
; RV64IP-NEXT: xori a0, a0, 2
; RV64IP-NEXT: sh a0, 10(sp)
; RV64IP-NEXT: lh a0, 0(sp)
; RV64IP-NEXT: xori a0, a0, 1
; RV64IP-NEXT: sh a0, 8(sp)
; RV64IP-NEXT: ld a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: xorv4i16: ; RV64IPN-LABEL: xorv4i16:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: lui a1, %hi(.LCPI23_0)
; RV64IPN-NEXT: sd a0, 0(sp) ; RV64IPN-NEXT: ld a1, %lo(.LCPI23_0)(a1)
; RV64IPN-NEXT: lh a0, 6(sp) ; RV64IPN-NEXT: xor a0, a0, a1
; RV64IPN-NEXT: xori a0, a0, 4
; RV64IPN-NEXT: sh a0, 14(sp)
; RV64IPN-NEXT: lh a0, 4(sp)
; RV64IPN-NEXT: xori a0, a0, 3
; RV64IPN-NEXT: sh a0, 12(sp)
; RV64IPN-NEXT: lh a0, 2(sp)
; RV64IPN-NEXT: xori a0, a0, 2
; RV64IPN-NEXT: sh a0, 10(sp)
; RV64IPN-NEXT: lh a0, 0(sp)
; RV64IPN-NEXT: xori a0, a0, 1
; RV64IPN-NEXT: sh a0, 8(sp)
; RV64IPN-NEXT: ld a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp = bitcast i64 %a to <4 x i16> %tmp = bitcast i64 %a to <4 x i16>
%xor = xor <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4> %xor = xor <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4>
%res = bitcast <4 x i16> %xor to i64 %res = bitcast <4 x i16> %xor to i64
ret i64 %res ret i64 %res
} }
define i64 @xorv2i32(i64 %a) nounwind { define i64 @xorv2i32(i64 %a) nounwind {
; RV64IP-LABEL: xorv2i32: ; RV64IP-LABEL: xorv2i32:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: lui a1, %hi(.LCPI24_0)
; RV64IP-NEXT: sd a0, 0(sp) ; RV64IP-NEXT: ld a1, %lo(.LCPI24_0)(a1)
; RV64IP-NEXT: lw a0, 4(sp) ; RV64IP-NEXT: xor a0, a0, a1
; RV64IP-NEXT: xori a0, a0, 2
; RV64IP-NEXT: sw a0, 12(sp)
; RV64IP-NEXT: lw a0, 0(sp)
; RV64IP-NEXT: xori a0, a0, 1
; RV64IP-NEXT: sw a0, 8(sp)
; RV64IP-NEXT: ld a0, 8(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: xorv2i32: ; RV64IPN-LABEL: xorv2i32:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: lui a1, %hi(.LCPI24_0)
; RV64IPN-NEXT: sd a0, 0(sp) ; RV64IPN-NEXT: ld a1, %lo(.LCPI24_0)(a1)
; RV64IPN-NEXT: lw a0, 4(sp) ; RV64IPN-NEXT: xor a0, a0, a1
; RV64IPN-NEXT: xori a0, a0, 2
; RV64IPN-NEXT: sw a0, 12(sp)
; RV64IPN-NEXT: lw a0, 0(sp)
; RV64IPN-NEXT: xori a0, a0, 1
; RV64IPN-NEXT: sw a0, 8(sp)
; RV64IPN-NEXT: ld a0, 8(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp = bitcast i64 %a to <2 x i32> %tmp = bitcast i64 %a to <2 x i32>
%xor = xor <2 x i32> %tmp, <i32 1, i32 2> %xor = xor <2 x i32> %tmp, <i32 1, i32 2>
%res = bitcast <2 x i32> %xor to i64 %res = bitcast <2 x i32> %xor to i64
ret i64 %res ret i64 %res
} }
; Logic operation with immediate. ; Logic operation with immediate.
; It has the input from the result of a vector operation to avoid ; It has the input from the result of a vector operation to avoid
; it bitcasted to a scalar operation. ; it bitcasted to a scalar operation.
define signext i32 @andiv4i8(i32 signext %a, i32 signext %b) nounwind { define signext i32 @andiv4i8(i32 signext %a, i32 signext %b) nounwind {
; RV64IP-LABEL: andiv4i8: ; RV64IP-LABEL: andiv4i8:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: add8 a0, a0, a1
; RV64IP-NEXT: sw a1, 4(sp) ; RV64IP-NEXT: andi a0, a0, 1
; RV64IP-NEXT: sw a0, 8(sp)
; RV64IP-NEXT: lb a0, 7(sp)
; RV64IP-NEXT: lb a1, 11(sp)
; RV64IP-NEXT: lb a2, 6(sp)
; RV64IP-NEXT: lb a3, 10(sp)
; RV64IP-NEXT: lb t0, 5(sp)
; RV64IP-NEXT: lb a5, 9(sp)
; RV64IP-NEXT: lb a6, 4(sp)
; RV64IP-NEXT: lb a7, 8(sp)
; RV64IP-NEXT: addi a4, zero, 1
; RV64IP-NEXT: sw a4, 12(sp)
; RV64IP-NEXT: lb a4, 15(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: and a0, a0, a4
; RV64IP-NEXT: sb a0, 3(sp)
; RV64IP-NEXT: lb a0, 14(sp)
; RV64IP-NEXT: add a1, a3, a2
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sb a0, 2(sp)
; RV64IP-NEXT: lb a0, 13(sp)
; RV64IP-NEXT: add a1, a5, t0
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sb a0, 1(sp)
; RV64IP-NEXT: lb a0, 12(sp)
; RV64IP-NEXT: add a1, a7, a6
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sb a0, 0(sp)
; RV64IP-NEXT: lwu a0, 0(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: andiv4i8: ; RV64IPN-LABEL: andiv4i8:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: add8 a0, a0, a1
; RV64IPN-NEXT: sw a1, 4(sp) ; RV64IPN-NEXT: andi a0, a0, 1
; RV64IPN-NEXT: sw a0, 8(sp)
; RV64IPN-NEXT: lb a0, 7(sp)
; RV64IPN-NEXT: lb a1, 11(sp)
; RV64IPN-NEXT: lb a2, 6(sp)
; RV64IPN-NEXT: lb a3, 10(sp)
; RV64IPN-NEXT: lb t0, 5(sp)
; RV64IPN-NEXT: lb a5, 9(sp)
; RV64IPN-NEXT: lb a6, 4(sp)
; RV64IPN-NEXT: lb a7, 8(sp)
; RV64IPN-NEXT: addi a4, zero, 1
; RV64IPN-NEXT: sw a4, 12(sp)
; RV64IPN-NEXT: lb a4, 15(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: and a0, a0, a4
; RV64IPN-NEXT: sb a0, 3(sp)
; RV64IPN-NEXT: lb a0, 14(sp)
; RV64IPN-NEXT: add a1, a3, a2
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sb a0, 2(sp)
; RV64IPN-NEXT: lb a0, 13(sp)
; RV64IPN-NEXT: add a1, a5, t0
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sb a0, 1(sp)
; RV64IPN-NEXT: lb a0, 12(sp)
; RV64IPN-NEXT: add a1, a7, a6
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sb a0, 0(sp)
; RV64IPN-NEXT: lwu a0, 0(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <4 x i8> %tmp1 = bitcast i32 %a to <4 x i8>
%tmp2 = bitcast i32 %b to <4 x i8> %tmp2 = bitcast i32 %b to <4 x i8>
%imm = bitcast i32 1 to <4 x i8> %imm = bitcast i32 1 to <4 x i8>
%add = add <4 x i8> %tmp1, %tmp2 %add = add <4 x i8> %tmp1, %tmp2
%and = and <4 x i8> %add, %imm %and = and <4 x i8> %add, %imm
%res = bitcast <4 x i8> %and to i32 %res = bitcast <4 x i8> %and to i32
ret i32 %res ret i32 %res
} }
define signext i32 @andiv2i16(i32 signext %a, i32 signext %b) nounwind { define signext i32 @andiv2i16(i32 signext %a, i32 signext %b) nounwind {
; RV64IP-LABEL: andiv2i16: ; RV64IP-LABEL: andiv2i16:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: add16 a0, a0, a1
; RV64IP-NEXT: sw a1, 4(sp) ; RV64IP-NEXT: andi a0, a0, -2
; RV64IP-NEXT: sw a0, 8(sp) ; RV64IP-NEXT: sext.w a0, a0
; RV64IP-NEXT: lh a0, 6(sp)
; RV64IP-NEXT: lh a1, 10(sp)
; RV64IP-NEXT: lh a2, 4(sp)
; RV64IP-NEXT: lh a3, 8(sp)
; RV64IP-NEXT: addi a4, zero, 1
; RV64IP-NEXT: slli a4, a4, 32
; RV64IP-NEXT: addi a4, a4, -2
; RV64IP-NEXT: sw a4, 12(sp)
; RV64IP-NEXT: lh a4, 14(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: and a0, a0, a4
; RV64IP-NEXT: sh a0, 2(sp)
; RV64IP-NEXT: lh a0, 12(sp)
; RV64IP-NEXT: add a1, a3, a2
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sh a0, 0(sp)
; RV64IP-NEXT: lw a0, 0(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: andiv2i16: ; RV64IPN-LABEL: andiv2i16:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: add16 a0, a0, a1
; RV64IPN-NEXT: sw a1, 4(sp) ; RV64IPN-NEXT: andi a0, a0, -2
; RV64IPN-NEXT: sw a0, 8(sp) ; RV64IPN-NEXT: sext.w a0, a0
; RV64IPN-NEXT: lh a0, 6(sp)
; RV64IPN-NEXT: lh a1, 10(sp)
; RV64IPN-NEXT: lh a2, 4(sp)
; RV64IPN-NEXT: lh a3, 8(sp)
; RV64IPN-NEXT: addi a4, zero, 1
; RV64IPN-NEXT: slli a4, a4, 32
; RV64IPN-NEXT: addi a4, a4, -2
; RV64IPN-NEXT: sw a4, 12(sp)
; RV64IPN-NEXT: lh a4, 14(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: and a0, a0, a4
; RV64IPN-NEXT: sh a0, 2(sp)
; RV64IPN-NEXT: lh a0, 12(sp)
; RV64IPN-NEXT: add a1, a3, a2
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sh a0, 0(sp)
; RV64IPN-NEXT: lw a0, 0(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <2 x i16> %tmp1 = bitcast i32 %a to <2 x i16>
%tmp2 = bitcast i32 %b to <2 x i16> %tmp2 = bitcast i32 %b to <2 x i16>
%imm = bitcast i32 -2 to <2 x i16> %imm = bitcast i32 -2 to <2 x i16>
%add = add <2 x i16> %tmp1, %tmp2 %add = add <2 x i16> %tmp1, %tmp2
%and = and <2 x i16> %add, %imm %and = and <2 x i16> %add, %imm
%res = bitcast <2 x i16> %and to i32 %res = bitcast <2 x i16> %and to i32
ret i32 %res ret i32 %res
} }
define i64 @andiv8i8(i64 %a, i64 %b) nounwind { define i64 @andiv8i8(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: andiv8i8: ; RV64IP-LABEL: andiv8i8:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -48 ; RV64IP-NEXT: add8 a0, a0, a1
; RV64IP-NEXT: sd s0, 40(sp) # 8-byte Folded Spill ; RV64IP-NEXT: andi a0, a0, -3
; RV64IP-NEXT: sd s1, 32(sp) # 8-byte Folded Spill
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lb a6, 16(sp)
; RV64IP-NEXT: lb a7, 8(sp)
; RV64IP-NEXT: lb t0, 17(sp)
; RV64IP-NEXT: lb t1, 9(sp)
; RV64IP-NEXT: lb t2, 18(sp)
; RV64IP-NEXT: lb t3, 10(sp)
; RV64IP-NEXT: lb t4, 19(sp)
; RV64IP-NEXT: lb t5, 11(sp)
; RV64IP-NEXT: lb t6, 20(sp)
; RV64IP-NEXT: lb a3, 12(sp)
; RV64IP-NEXT: lb a4, 21(sp)
; RV64IP-NEXT: lb a5, 13(sp)
; RV64IP-NEXT: lb a0, 22(sp)
; RV64IP-NEXT: lb a1, 14(sp)
; RV64IP-NEXT: lb a2, 23(sp)
; RV64IP-NEXT: lb s0, 15(sp)
; RV64IP-NEXT: addi s1, zero, -3
; RV64IP-NEXT: sd s1, 0(sp)
; RV64IP-NEXT: lb s1, 7(sp)
; RV64IP-NEXT: add a2, s0, a2
; RV64IP-NEXT: and a2, a2, s1
; RV64IP-NEXT: sb a2, 31(sp)
; RV64IP-NEXT: lb a2, 6(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: and a0, a0, a2
; RV64IP-NEXT: sb a0, 30(sp)
; RV64IP-NEXT: lb a0, 5(sp)
; RV64IP-NEXT: add a1, a5, a4
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sb a0, 29(sp)
; RV64IP-NEXT: lb a0, 4(sp)
; RV64IP-NEXT: add a1, a3, t6
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sb a0, 28(sp)
; RV64IP-NEXT: lb a0, 3(sp)
; RV64IP-NEXT: add a1, t5, t4
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sb a0, 27(sp)
; RV64IP-NEXT: lb a0, 2(sp)
; RV64IP-NEXT: add a1, t3, t2
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sb a0, 26(sp)
; RV64IP-NEXT: lb a0, 1(sp)
; RV64IP-NEXT: add a1, t1, t0
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sb a0, 25(sp)
; RV64IP-NEXT: lb a0, 0(sp)
; RV64IP-NEXT: add a1, a7, a6
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sb a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: ld s1, 32(sp) # 8-byte Folded Reload
; RV64IP-NEXT: ld s0, 40(sp) # 8-byte Folded Reload
; RV64IP-NEXT: addi sp, sp, 48
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: andiv8i8: ; RV64IPN-LABEL: andiv8i8:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -48 ; RV64IPN-NEXT: add8 a0, a0, a1
; RV64IPN-NEXT: sd s0, 40(sp) # 8-byte Folded Spill ; RV64IPN-NEXT: andi a0, a0, -3
; RV64IPN-NEXT: sd s1, 32(sp) # 8-byte Folded Spill
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lb a6, 16(sp)
; RV64IPN-NEXT: lb a7, 8(sp)
; RV64IPN-NEXT: lb t0, 17(sp)
; RV64IPN-NEXT: lb t1, 9(sp)
; RV64IPN-NEXT: lb t2, 18(sp)
; RV64IPN-NEXT: lb t3, 10(sp)
; RV64IPN-NEXT: lb t4, 19(sp)
; RV64IPN-NEXT: lb t5, 11(sp)
; RV64IPN-NEXT: lb t6, 20(sp)
; RV64IPN-NEXT: lb a3, 12(sp)
; RV64IPN-NEXT: lb a4, 21(sp)
; RV64IPN-NEXT: lb a5, 13(sp)
; RV64IPN-NEXT: lb a0, 22(sp)
; RV64IPN-NEXT: lb a1, 14(sp)
; RV64IPN-NEXT: lb a2, 23(sp)
; RV64IPN-NEXT: lb s0, 15(sp)
; RV64IPN-NEXT: addi s1, zero, -3
; RV64IPN-NEXT: sd s1, 0(sp)
; RV64IPN-NEXT: lb s1, 7(sp)
; RV64IPN-NEXT: add a2, s0, a2
; RV64IPN-NEXT: and a2, a2, s1
; RV64IPN-NEXT: sb a2, 31(sp)
; RV64IPN-NEXT: lb a2, 6(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: and a0, a0, a2
; RV64IPN-NEXT: sb a0, 30(sp)
; RV64IPN-NEXT: lb a0, 5(sp)
; RV64IPN-NEXT: add a1, a5, a4
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sb a0, 29(sp)
; RV64IPN-NEXT: lb a0, 4(sp)
; RV64IPN-NEXT: add a1, a3, t6
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sb a0, 28(sp)
; RV64IPN-NEXT: lb a0, 3(sp)
; RV64IPN-NEXT: add a1, t5, t4
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sb a0, 27(sp)
; RV64IPN-NEXT: lb a0, 2(sp)
; RV64IPN-NEXT: add a1, t3, t2
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sb a0, 26(sp)
; RV64IPN-NEXT: lb a0, 1(sp)
; RV64IPN-NEXT: add a1, t1, t0
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sb a0, 25(sp)
; RV64IPN-NEXT: lb a0, 0(sp)
; RV64IPN-NEXT: add a1, a7, a6
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sb a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: ld s1, 32(sp) # 8-byte Folded Reload
; RV64IPN-NEXT: ld s0, 40(sp) # 8-byte Folded Reload
; RV64IPN-NEXT: addi sp, sp, 48
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <8 x i8> %tmp1 = bitcast i64 %a to <8 x i8>
%tmp2 = bitcast i64 %b to <8 x i8> %tmp2 = bitcast i64 %b to <8 x i8>
%imm = bitcast i64 -3 to <8 x i8> %imm = bitcast i64 -3 to <8 x i8>
%add = add <8 x i8> %tmp1, %tmp2 %add = add <8 x i8> %tmp1, %tmp2
%and = and <8 x i8> %add, %imm %and = and <8 x i8> %add, %imm
%res = bitcast <8 x i8> %and to i64 %res = bitcast <8 x i8> %and to i64
ret i64 %res ret i64 %res
} }
define i64 @andvi4i16(i64 %a, i64 %b) nounwind { define i64 @andvi4i16(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: andvi4i16: ; RV64IP-LABEL: andvi4i16:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32 ; RV64IP-NEXT: add16 a0, a0, a1
; RV64IP-NEXT: sd a1, 16(sp) ; RV64IP-NEXT: andi a0, a0, -4
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lh a6, 16(sp)
; RV64IP-NEXT: lh a7, 8(sp)
; RV64IP-NEXT: lh t0, 18(sp)
; RV64IP-NEXT: lh a3, 10(sp)
; RV64IP-NEXT: lh a4, 20(sp)
; RV64IP-NEXT: lh a5, 12(sp)
; RV64IP-NEXT: lh a0, 22(sp)
; RV64IP-NEXT: lh a1, 14(sp)
; RV64IP-NEXT: addi a2, zero, -4
; RV64IP-NEXT: sd a2, 0(sp)
; RV64IP-NEXT: lh a2, 6(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: and a0, a0, a2
; RV64IP-NEXT: sh a0, 30(sp)
; RV64IP-NEXT: lh a0, 4(sp)
; RV64IP-NEXT: add a1, a5, a4
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sh a0, 28(sp)
; RV64IP-NEXT: lh a0, 2(sp)
; RV64IP-NEXT: add a1, a3, t0
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sh a0, 26(sp)
; RV64IP-NEXT: lh a0, 0(sp)
; RV64IP-NEXT: add a1, a7, a6
; RV64IP-NEXT: and a0, a1, a0
; RV64IP-NEXT: sh a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: andvi4i16: ; RV64IPN-LABEL: andvi4i16:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32 ; RV64IPN-NEXT: add16 a0, a0, a1
; RV64IPN-NEXT: sd a1, 16(sp) ; RV64IPN-NEXT: andi a0, a0, -4
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lh a6, 16(sp)
; RV64IPN-NEXT: lh a7, 8(sp)
; RV64IPN-NEXT: lh t0, 18(sp)
; RV64IPN-NEXT: lh a3, 10(sp)
; RV64IPN-NEXT: lh a4, 20(sp)
; RV64IPN-NEXT: lh a5, 12(sp)
; RV64IPN-NEXT: lh a0, 22(sp)
; RV64IPN-NEXT: lh a1, 14(sp)
; RV64IPN-NEXT: addi a2, zero, -4
; RV64IPN-NEXT: sd a2, 0(sp)
; RV64IPN-NEXT: lh a2, 6(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: and a0, a0, a2
; RV64IPN-NEXT: sh a0, 30(sp)
; RV64IPN-NEXT: lh a0, 4(sp)
; RV64IPN-NEXT: add a1, a5, a4
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sh a0, 28(sp)
; RV64IPN-NEXT: lh a0, 2(sp)
; RV64IPN-NEXT: add a1, a3, t0
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sh a0, 26(sp)
; RV64IPN-NEXT: lh a0, 0(sp)
; RV64IPN-NEXT: add a1, a7, a6
; RV64IPN-NEXT: and a0, a1, a0
; RV64IPN-NEXT: sh a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <4 x i16> %tmp1 = bitcast i64 %a to <4 x i16>
%tmp2 = bitcast i64 %b to <4 x i16> %tmp2 = bitcast i64 %b to <4 x i16>
%imm = bitcast i64 -4 to <4 x i16> %imm = bitcast i64 -4 to <4 x i16>
%add = add <4 x i16> %tmp1, %tmp2 %add = add <4 x i16> %tmp1, %tmp2
%and = and <4 x i16> %add, %imm %and = and <4 x i16> %add, %imm
%res = bitcast <4 x i16> %and to i64 %res = bitcast <4 x i16> %and to i64
ret i64 %res ret i64 %res
} }
define i64 @andiv2i32(i64 %a, i64 %b) nounwind { define i64 @andiv2i32(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: andiv2i32: ; RV64IP-LABEL: andiv2i32:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32 ; RV64IP-NEXT: add32 a0, a0, a1
; RV64IP-NEXT: sd a1, 16(sp) ; RV64IP-NEXT: andi a0, a0, -5
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lw a0, 16(sp)
; RV64IP-NEXT: lw a1, 8(sp)
; RV64IP-NEXT: lw a2, 20(sp)
; RV64IP-NEXT: lw a3, 12(sp)
; RV64IP-NEXT: addi a4, zero, -5
; RV64IP-NEXT: sd a4, 0(sp)
; RV64IP-NEXT: lw a4, 4(sp)
; RV64IP-NEXT: add a2, a3, a2
; RV64IP-NEXT: and a2, a2, a4
; RV64IP-NEXT: sw a2, 28(sp)
; RV64IP-NEXT: lw a2, 0(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: and a0, a0, a2
; RV64IP-NEXT: sw a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: andiv2i32: ; RV64IPN-LABEL: andiv2i32:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32 ; RV64IPN-NEXT: add32 a0, a0, a1
; RV64IPN-NEXT: sd a1, 16(sp) ; RV64IPN-NEXT: andi a0, a0, -5
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lw a0, 16(sp)
; RV64IPN-NEXT: lw a1, 8(sp)
; RV64IPN-NEXT: lw a2, 20(sp)
; RV64IPN-NEXT: lw a3, 12(sp)
; RV64IPN-NEXT: addi a4, zero, -5
; RV64IPN-NEXT: sd a4, 0(sp)
; RV64IPN-NEXT: lw a4, 4(sp)
; RV64IPN-NEXT: add a2, a3, a2
; RV64IPN-NEXT: and a2, a2, a4
; RV64IPN-NEXT: sw a2, 28(sp)
; RV64IPN-NEXT: lw a2, 0(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: and a0, a0, a2
; RV64IPN-NEXT: sw a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <2 x i32> %tmp1 = bitcast i64 %a to <2 x i32>
%tmp2 = bitcast i64 %b to <2 x i32> %tmp2 = bitcast i64 %b to <2 x i32>
%imm = bitcast i64 -5 to <2 x i32> %imm = bitcast i64 -5 to <2 x i32>
%add = add <2 x i32> %tmp1, %tmp2 %add = add <2 x i32> %tmp1, %tmp2
%and = and <2 x i32> %add, %imm %and = and <2 x i32> %add, %imm
%res = bitcast <2 x i32> %and to i64 %res = bitcast <2 x i32> %and to i64
ret i64 %res ret i64 %res
} }
define signext i32 @oriv4i8(i32 signext %a, i32 signext %b) nounwind { define signext i32 @oriv4i8(i32 signext %a, i32 signext %b) nounwind {
; RV64IP-LABEL: oriv4i8: ; RV64IP-LABEL: oriv4i8:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: add8 a0, a0, a1
; RV64IP-NEXT: sw a1, 4(sp) ; RV64IP-NEXT: ori a0, a0, 1
; RV64IP-NEXT: sw a0, 8(sp) ; RV64IP-NEXT: sext.w a0, a0
; RV64IP-NEXT: lb a0, 7(sp)
; RV64IP-NEXT: lb a1, 11(sp)
; RV64IP-NEXT: lb a2, 6(sp)
; RV64IP-NEXT: lb a3, 10(sp)
; RV64IP-NEXT: lb t0, 5(sp)
; RV64IP-NEXT: lb a5, 9(sp)
; RV64IP-NEXT: lb a6, 4(sp)
; RV64IP-NEXT: lb a7, 8(sp)
; RV64IP-NEXT: addi a4, zero, 1
; RV64IP-NEXT: sw a4, 12(sp)
; RV64IP-NEXT: lb a4, 15(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: or a0, a0, a4
; RV64IP-NEXT: sb a0, 3(sp)
; RV64IP-NEXT: lb a0, 14(sp)
; RV64IP-NEXT: add a1, a3, a2
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sb a0, 2(sp)
; RV64IP-NEXT: lb a0, 13(sp)
; RV64IP-NEXT: add a1, a5, t0
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sb a0, 1(sp)
; RV64IP-NEXT: lb a0, 12(sp)
; RV64IP-NEXT: add a1, a7, a6
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sb a0, 0(sp)
; RV64IP-NEXT: lw a0, 0(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: oriv4i8: ; RV64IPN-LABEL: oriv4i8:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: add8 a0, a0, a1
; RV64IPN-NEXT: sw a1, 4(sp) ; RV64IPN-NEXT: ori a0, a0, 1
; RV64IPN-NEXT: sw a0, 8(sp) ; RV64IPN-NEXT: sext.w a0, a0
; RV64IPN-NEXT: lb a0, 7(sp)
; RV64IPN-NEXT: lb a1, 11(sp)
; RV64IPN-NEXT: lb a2, 6(sp)
; RV64IPN-NEXT: lb a3, 10(sp)
; RV64IPN-NEXT: lb t0, 5(sp)
; RV64IPN-NEXT: lb a5, 9(sp)
; RV64IPN-NEXT: lb a6, 4(sp)
; RV64IPN-NEXT: lb a7, 8(sp)
; RV64IPN-NEXT: addi a4, zero, 1
; RV64IPN-NEXT: sw a4, 12(sp)
; RV64IPN-NEXT: lb a4, 15(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: or a0, a0, a4
; RV64IPN-NEXT: sb a0, 3(sp)
; RV64IPN-NEXT: lb a0, 14(sp)
; RV64IPN-NEXT: add a1, a3, a2
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sb a0, 2(sp)
; RV64IPN-NEXT: lb a0, 13(sp)
; RV64IPN-NEXT: add a1, a5, t0
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sb a0, 1(sp)
; RV64IPN-NEXT: lb a0, 12(sp)
; RV64IPN-NEXT: add a1, a7, a6
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sb a0, 0(sp)
; RV64IPN-NEXT: lw a0, 0(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <4 x i8> %tmp1 = bitcast i32 %a to <4 x i8>
%tmp2 = bitcast i32 %b to <4 x i8> %tmp2 = bitcast i32 %b to <4 x i8>
%imm = bitcast i32 1 to <4 x i8> %imm = bitcast i32 1 to <4 x i8>
%add = add <4 x i8> %tmp1, %tmp2 %add = add <4 x i8> %tmp1, %tmp2
%or = or <4 x i8> %add, %imm %or = or <4 x i8> %add, %imm
%res = bitcast <4 x i8> %or to i32 %res = bitcast <4 x i8> %or to i32
ret i32 %res ret i32 %res
} }
define signext i32 @oriv2i16(i32 signext %a, i32 signext %b) nounwind { define signext i32 @oriv2i16(i32 signext %a, i32 signext %b) nounwind {
; RV64IP-LABEL: oriv2i16: ; RV64IP-LABEL: oriv2i16:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: add16 a0, a0, a1
; RV64IP-NEXT: sw a1, 4(sp) ; RV64IP-NEXT: ori a0, a0, -2
; RV64IP-NEXT: sw a0, 8(sp)
; RV64IP-NEXT: lh a0, 6(sp)
; RV64IP-NEXT: lh a1, 10(sp)
; RV64IP-NEXT: lh a2, 4(sp)
; RV64IP-NEXT: lh a3, 8(sp)
; RV64IP-NEXT: addi a4, zero, 1
; RV64IP-NEXT: slli a4, a4, 32
; RV64IP-NEXT: addi a4, a4, -2
; RV64IP-NEXT: sw a4, 12(sp)
; RV64IP-NEXT: lh a4, 14(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: or a0, a0, a4
; RV64IP-NEXT: sh a0, 2(sp)
; RV64IP-NEXT: lh a0, 12(sp)
; RV64IP-NEXT: add a1, a3, a2
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sh a0, 0(sp)
; RV64IP-NEXT: lw a0, 0(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: oriv2i16: ; RV64IPN-LABEL: oriv2i16:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: add16 a0, a0, a1
; RV64IPN-NEXT: sw a1, 4(sp) ; RV64IPN-NEXT: ori a0, a0, -2
; RV64IPN-NEXT: sw a0, 8(sp)
; RV64IPN-NEXT: lh a0, 6(sp)
; RV64IPN-NEXT: lh a1, 10(sp)
; RV64IPN-NEXT: lh a2, 4(sp)
; RV64IPN-NEXT: lh a3, 8(sp)
; RV64IPN-NEXT: addi a4, zero, 1
; RV64IPN-NEXT: slli a4, a4, 32
; RV64IPN-NEXT: addi a4, a4, -2
; RV64IPN-NEXT: sw a4, 12(sp)
; RV64IPN-NEXT: lh a4, 14(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: or a0, a0, a4
; RV64IPN-NEXT: sh a0, 2(sp)
; RV64IPN-NEXT: lh a0, 12(sp)
; RV64IPN-NEXT: add a1, a3, a2
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sh a0, 0(sp)
; RV64IPN-NEXT: lw a0, 0(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <2 x i16> %tmp1 = bitcast i32 %a to <2 x i16>
%tmp2 = bitcast i32 %b to <2 x i16> %tmp2 = bitcast i32 %b to <2 x i16>
%imm = bitcast i32 -2 to <2 x i16> %imm = bitcast i32 -2 to <2 x i16>
%add = add <2 x i16> %tmp1, %tmp2 %add = add <2 x i16> %tmp1, %tmp2
%or = or <2 x i16> %add, %imm %or = or <2 x i16> %add, %imm
%res = bitcast <2 x i16> %or to i32 %res = bitcast <2 x i16> %or to i32
ret i32 %res ret i32 %res
} }
define i64 @oriv8i8(i64 %a, i64 %b) nounwind { define i64 @oriv8i8(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: oriv8i8: ; RV64IP-LABEL: oriv8i8:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -48 ; RV64IP-NEXT: add8 a0, a0, a1
; RV64IP-NEXT: sd s0, 40(sp) # 8-byte Folded Spill ; RV64IP-NEXT: ori a0, a0, -3
; RV64IP-NEXT: sd s1, 32(sp) # 8-byte Folded Spill
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lb a6, 16(sp)
; RV64IP-NEXT: lb a7, 8(sp)
; RV64IP-NEXT: lb t0, 17(sp)
; RV64IP-NEXT: lb t1, 9(sp)
; RV64IP-NEXT: lb t2, 18(sp)
; RV64IP-NEXT: lb t3, 10(sp)
; RV64IP-NEXT: lb t4, 19(sp)
; RV64IP-NEXT: lb t5, 11(sp)
; RV64IP-NEXT: lb t6, 20(sp)
; RV64IP-NEXT: lb a3, 12(sp)
; RV64IP-NEXT: lb a4, 21(sp)
; RV64IP-NEXT: lb a5, 13(sp)
; RV64IP-NEXT: lb a0, 22(sp)
; RV64IP-NEXT: lb a1, 14(sp)
; RV64IP-NEXT: lb a2, 23(sp)
; RV64IP-NEXT: lb s0, 15(sp)
; RV64IP-NEXT: addi s1, zero, -3
; RV64IP-NEXT: sd s1, 0(sp)
; RV64IP-NEXT: lb s1, 7(sp)
; RV64IP-NEXT: add a2, s0, a2
; RV64IP-NEXT: or a2, a2, s1
; RV64IP-NEXT: sb a2, 31(sp)
; RV64IP-NEXT: lb a2, 6(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: or a0, a0, a2
; RV64IP-NEXT: sb a0, 30(sp)
; RV64IP-NEXT: lb a0, 5(sp)
; RV64IP-NEXT: add a1, a5, a4
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sb a0, 29(sp)
; RV64IP-NEXT: lb a0, 4(sp)
; RV64IP-NEXT: add a1, a3, t6
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sb a0, 28(sp)
; RV64IP-NEXT: lb a0, 3(sp)
; RV64IP-NEXT: add a1, t5, t4
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sb a0, 27(sp)
; RV64IP-NEXT: lb a0, 2(sp)
; RV64IP-NEXT: add a1, t3, t2
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sb a0, 26(sp)
; RV64IP-NEXT: lb a0, 1(sp)
; RV64IP-NEXT: add a1, t1, t0
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sb a0, 25(sp)
; RV64IP-NEXT: lb a0, 0(sp)
; RV64IP-NEXT: add a1, a7, a6
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sb a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: ld s1, 32(sp) # 8-byte Folded Reload
; RV64IP-NEXT: ld s0, 40(sp) # 8-byte Folded Reload
; RV64IP-NEXT: addi sp, sp, 48
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: oriv8i8: ; RV64IPN-LABEL: oriv8i8:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -48 ; RV64IPN-NEXT: add8 a0, a0, a1
; RV64IPN-NEXT: sd s0, 40(sp) # 8-byte Folded Spill ; RV64IPN-NEXT: ori a0, a0, -3
; RV64IPN-NEXT: sd s1, 32(sp) # 8-byte Folded Spill
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lb a6, 16(sp)
; RV64IPN-NEXT: lb a7, 8(sp)
; RV64IPN-NEXT: lb t0, 17(sp)
; RV64IPN-NEXT: lb t1, 9(sp)
; RV64IPN-NEXT: lb t2, 18(sp)
; RV64IPN-NEXT: lb t3, 10(sp)
; RV64IPN-NEXT: lb t4, 19(sp)
; RV64IPN-NEXT: lb t5, 11(sp)
; RV64IPN-NEXT: lb t6, 20(sp)
; RV64IPN-NEXT: lb a3, 12(sp)
; RV64IPN-NEXT: lb a4, 21(sp)
; RV64IPN-NEXT: lb a5, 13(sp)
; RV64IPN-NEXT: lb a0, 22(sp)
; RV64IPN-NEXT: lb a1, 14(sp)
; RV64IPN-NEXT: lb a2, 23(sp)
; RV64IPN-NEXT: lb s0, 15(sp)
; RV64IPN-NEXT: addi s1, zero, -3
; RV64IPN-NEXT: sd s1, 0(sp)
; RV64IPN-NEXT: lb s1, 7(sp)
; RV64IPN-NEXT: add a2, s0, a2
; RV64IPN-NEXT: or a2, a2, s1
; RV64IPN-NEXT: sb a2, 31(sp)
; RV64IPN-NEXT: lb a2, 6(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: or a0, a0, a2
; RV64IPN-NEXT: sb a0, 30(sp)
; RV64IPN-NEXT: lb a0, 5(sp)
; RV64IPN-NEXT: add a1, a5, a4
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sb a0, 29(sp)
; RV64IPN-NEXT: lb a0, 4(sp)
; RV64IPN-NEXT: add a1, a3, t6
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sb a0, 28(sp)
; RV64IPN-NEXT: lb a0, 3(sp)
; RV64IPN-NEXT: add a1, t5, t4
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sb a0, 27(sp)
; RV64IPN-NEXT: lb a0, 2(sp)
; RV64IPN-NEXT: add a1, t3, t2
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sb a0, 26(sp)
; RV64IPN-NEXT: lb a0, 1(sp)
; RV64IPN-NEXT: add a1, t1, t0
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sb a0, 25(sp)
; RV64IPN-NEXT: lb a0, 0(sp)
; RV64IPN-NEXT: add a1, a7, a6
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sb a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: ld s1, 32(sp) # 8-byte Folded Reload
; RV64IPN-NEXT: ld s0, 40(sp) # 8-byte Folded Reload
; RV64IPN-NEXT: addi sp, sp, 48
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <8 x i8> %tmp1 = bitcast i64 %a to <8 x i8>
%tmp2 = bitcast i64 %b to <8 x i8> %tmp2 = bitcast i64 %b to <8 x i8>
%imm = bitcast i64 -3 to <8 x i8> %imm = bitcast i64 -3 to <8 x i8>
%add = add <8 x i8> %tmp1, %tmp2 %add = add <8 x i8> %tmp1, %tmp2
%or = or <8 x i8> %add, %imm %or = or <8 x i8> %add, %imm
%res = bitcast <8 x i8> %or to i64 %res = bitcast <8 x i8> %or to i64
ret i64 %res ret i64 %res
} }
define i64 @orvi4i16(i64 %a, i64 %b) nounwind { define i64 @orvi4i16(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: orvi4i16: ; RV64IP-LABEL: orvi4i16:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32 ; RV64IP-NEXT: add16 a0, a0, a1
; RV64IP-NEXT: sd a1, 16(sp) ; RV64IP-NEXT: ori a0, a0, -4
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lh a6, 16(sp)
; RV64IP-NEXT: lh a7, 8(sp)
; RV64IP-NEXT: lh t0, 18(sp)
; RV64IP-NEXT: lh a3, 10(sp)
; RV64IP-NEXT: lh a4, 20(sp)
; RV64IP-NEXT: lh a5, 12(sp)
; RV64IP-NEXT: lh a0, 22(sp)
; RV64IP-NEXT: lh a1, 14(sp)
; RV64IP-NEXT: addi a2, zero, -4
; RV64IP-NEXT: sd a2, 0(sp)
; RV64IP-NEXT: lh a2, 6(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: or a0, a0, a2
; RV64IP-NEXT: sh a0, 30(sp)
; RV64IP-NEXT: lh a0, 4(sp)
; RV64IP-NEXT: add a1, a5, a4
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sh a0, 28(sp)
; RV64IP-NEXT: lh a0, 2(sp)
; RV64IP-NEXT: add a1, a3, t0
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sh a0, 26(sp)
; RV64IP-NEXT: lh a0, 0(sp)
; RV64IP-NEXT: add a1, a7, a6
; RV64IP-NEXT: or a0, a1, a0
; RV64IP-NEXT: sh a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: orvi4i16: ; RV64IPN-LABEL: orvi4i16:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32 ; RV64IPN-NEXT: add16 a0, a0, a1
; RV64IPN-NEXT: sd a1, 16(sp) ; RV64IPN-NEXT: ori a0, a0, -4
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lh a6, 16(sp)
; RV64IPN-NEXT: lh a7, 8(sp)
; RV64IPN-NEXT: lh t0, 18(sp)
; RV64IPN-NEXT: lh a3, 10(sp)
; RV64IPN-NEXT: lh a4, 20(sp)
; RV64IPN-NEXT: lh a5, 12(sp)
; RV64IPN-NEXT: lh a0, 22(sp)
; RV64IPN-NEXT: lh a1, 14(sp)
; RV64IPN-NEXT: addi a2, zero, -4
; RV64IPN-NEXT: sd a2, 0(sp)
; RV64IPN-NEXT: lh a2, 6(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: or a0, a0, a2
; RV64IPN-NEXT: sh a0, 30(sp)
; RV64IPN-NEXT: lh a0, 4(sp)
; RV64IPN-NEXT: add a1, a5, a4
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sh a0, 28(sp)
; RV64IPN-NEXT: lh a0, 2(sp)
; RV64IPN-NEXT: add a1, a3, t0
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sh a0, 26(sp)
; RV64IPN-NEXT: lh a0, 0(sp)
; RV64IPN-NEXT: add a1, a7, a6
; RV64IPN-NEXT: or a0, a1, a0
; RV64IPN-NEXT: sh a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <4 x i16> %tmp1 = bitcast i64 %a to <4 x i16>
%tmp2 = bitcast i64 %b to <4 x i16> %tmp2 = bitcast i64 %b to <4 x i16>
%imm = bitcast i64 -4 to <4 x i16> %imm = bitcast i64 -4 to <4 x i16>
%add = add <4 x i16> %tmp1, %tmp2 %add = add <4 x i16> %tmp1, %tmp2
%or = or <4 x i16> %add, %imm %or = or <4 x i16> %add, %imm
%res = bitcast <4 x i16> %or to i64 %res = bitcast <4 x i16> %or to i64
ret i64 %res ret i64 %res
} }
define i64 @oriv2i32(i64 %a, i64 %b) nounwind { define i64 @oriv2i32(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: oriv2i32: ; RV64IP-LABEL: oriv2i32:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32 ; RV64IP-NEXT: add32 a0, a0, a1
; RV64IP-NEXT: sd a1, 16(sp) ; RV64IP-NEXT: ori a0, a0, -5
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lw a0, 16(sp)
; RV64IP-NEXT: lw a1, 8(sp)
; RV64IP-NEXT: lw a2, 20(sp)
; RV64IP-NEXT: lw a3, 12(sp)
; RV64IP-NEXT: addi a4, zero, -5
; RV64IP-NEXT: sd a4, 0(sp)
; RV64IP-NEXT: lw a4, 4(sp)
; RV64IP-NEXT: add a2, a3, a2
; RV64IP-NEXT: or a2, a2, a4
; RV64IP-NEXT: sw a2, 28(sp)
; RV64IP-NEXT: lw a2, 0(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: or a0, a0, a2
; RV64IP-NEXT: sw a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: oriv2i32: ; RV64IPN-LABEL: oriv2i32:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32 ; RV64IPN-NEXT: add32 a0, a0, a1
; RV64IPN-NEXT: sd a1, 16(sp) ; RV64IPN-NEXT: ori a0, a0, -5
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lw a0, 16(sp)
; RV64IPN-NEXT: lw a1, 8(sp)
; RV64IPN-NEXT: lw a2, 20(sp)
; RV64IPN-NEXT: lw a3, 12(sp)
; RV64IPN-NEXT: addi a4, zero, -5
; RV64IPN-NEXT: sd a4, 0(sp)
; RV64IPN-NEXT: lw a4, 4(sp)
; RV64IPN-NEXT: add a2, a3, a2
; RV64IPN-NEXT: or a2, a2, a4
; RV64IPN-NEXT: sw a2, 28(sp)
; RV64IPN-NEXT: lw a2, 0(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: or a0, a0, a2
; RV64IPN-NEXT: sw a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <2 x i32> %tmp1 = bitcast i64 %a to <2 x i32>
%tmp2 = bitcast i64 %b to <2 x i32> %tmp2 = bitcast i64 %b to <2 x i32>
%imm = bitcast i64 -5 to <2 x i32> %imm = bitcast i64 -5 to <2 x i32>
%add = add <2 x i32> %tmp1, %tmp2 %add = add <2 x i32> %tmp1, %tmp2
%or = or <2 x i32> %add, %imm %or = or <2 x i32> %add, %imm
%res = bitcast <2 x i32> %or to i64 %res = bitcast <2 x i32> %or to i64
ret i64 %res ret i64 %res
} }
define signext i32 @xoriv4i8(i32 signext %a, i32 signext %b) nounwind { define signext i32 @xoriv4i8(i32 signext %a, i32 signext %b) nounwind {
; RV64IP-LABEL: xoriv4i8: ; RV64IP-LABEL: xoriv4i8:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: add8 a0, a0, a1
; RV64IP-NEXT: sw a1, 4(sp) ; RV64IP-NEXT: not a0, a0
; RV64IP-NEXT: sw a0, 8(sp) ; RV64IP-NEXT: sext.w a0, a0
; RV64IP-NEXT: lb a0, 7(sp)
; RV64IP-NEXT: lb a1, 11(sp)
; RV64IP-NEXT: lb a2, 6(sp)
; RV64IP-NEXT: lb a3, 10(sp)
; RV64IP-NEXT: lb t0, 5(sp)
; RV64IP-NEXT: lb a5, 9(sp)
; RV64IP-NEXT: lb a6, 4(sp)
; RV64IP-NEXT: lb a7, 8(sp)
; RV64IP-NEXT: addi a4, zero, -1
; RV64IP-NEXT: srli a4, a4, 32
; RV64IP-NEXT: sw a4, 12(sp)
; RV64IP-NEXT: lb a4, 15(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: xor a0, a0, a4
; RV64IP-NEXT: sb a0, 3(sp)
; RV64IP-NEXT: lb a0, 14(sp)
; RV64IP-NEXT: add a1, a3, a2
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sb a0, 2(sp)
; RV64IP-NEXT: lb a0, 13(sp)
; RV64IP-NEXT: add a1, a5, t0
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sb a0, 1(sp)
; RV64IP-NEXT: lb a0, 12(sp)
; RV64IP-NEXT: add a1, a7, a6
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sb a0, 0(sp)
; RV64IP-NEXT: lw a0, 0(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: xoriv4i8: ; RV64IPN-LABEL: xoriv4i8:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: add8 a0, a0, a1
; RV64IPN-NEXT: sw a1, 4(sp) ; RV64IPN-NEXT: not a0, a0
; RV64IPN-NEXT: sw a0, 8(sp) ; RV64IPN-NEXT: sext.w a0, a0
; RV64IPN-NEXT: lb a0, 7(sp)
; RV64IPN-NEXT: lb a1, 11(sp)
; RV64IPN-NEXT: lb a2, 6(sp)
; RV64IPN-NEXT: lb a3, 10(sp)
; RV64IPN-NEXT: lb t0, 5(sp)
; RV64IPN-NEXT: lb a5, 9(sp)
; RV64IPN-NEXT: lb a6, 4(sp)
; RV64IPN-NEXT: lb a7, 8(sp)
; RV64IPN-NEXT: addi a4, zero, -1
; RV64IPN-NEXT: srli a4, a4, 32
; RV64IPN-NEXT: sw a4, 12(sp)
; RV64IPN-NEXT: lb a4, 15(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: xor a0, a0, a4
; RV64IPN-NEXT: sb a0, 3(sp)
; RV64IPN-NEXT: lb a0, 14(sp)
; RV64IPN-NEXT: add a1, a3, a2
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sb a0, 2(sp)
; RV64IPN-NEXT: lb a0, 13(sp)
; RV64IPN-NEXT: add a1, a5, t0
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sb a0, 1(sp)
; RV64IPN-NEXT: lb a0, 12(sp)
; RV64IPN-NEXT: add a1, a7, a6
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sb a0, 0(sp)
; RV64IPN-NEXT: lw a0, 0(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <4 x i8> %tmp1 = bitcast i32 %a to <4 x i8>
%tmp2 = bitcast i32 %b to <4 x i8> %tmp2 = bitcast i32 %b to <4 x i8>
%imm = bitcast i32 -1 to <4 x i8> %imm = bitcast i32 -1 to <4 x i8>
%add = add <4 x i8> %tmp1, %tmp2 %add = add <4 x i8> %tmp1, %tmp2
%xor = xor <4 x i8> %add, %imm %xor = xor <4 x i8> %add, %imm
%res = bitcast <4 x i8> %xor to i32 %res = bitcast <4 x i8> %xor to i32
ret i32 %res ret i32 %res
} }
define signext i32 @xoriv2i16(i32 signext %a, i32 signext %b) nounwind { define signext i32 @xoriv2i16(i32 signext %a, i32 signext %b) nounwind {
; RV64IP-LABEL: xoriv2i16: ; RV64IP-LABEL: xoriv2i16:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -16 ; RV64IP-NEXT: add16 a0, a0, a1
; RV64IP-NEXT: sw a1, 4(sp) ; RV64IP-NEXT: xori a0, a0, -2
; RV64IP-NEXT: sw a0, 8(sp) ; RV64IP-NEXT: sext.w a0, a0
; RV64IP-NEXT: lh a0, 6(sp)
; RV64IP-NEXT: lh a1, 10(sp)
; RV64IP-NEXT: lh a2, 4(sp)
; RV64IP-NEXT: lh a3, 8(sp)
; RV64IP-NEXT: addi a4, zero, 1
; RV64IP-NEXT: slli a4, a4, 32
; RV64IP-NEXT: addi a4, a4, -2
; RV64IP-NEXT: sw a4, 12(sp)
; RV64IP-NEXT: lh a4, 14(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: xor a0, a0, a4
; RV64IP-NEXT: sh a0, 2(sp)
; RV64IP-NEXT: lh a0, 12(sp)
; RV64IP-NEXT: add a1, a3, a2
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sh a0, 0(sp)
; RV64IP-NEXT: lw a0, 0(sp)
; RV64IP-NEXT: addi sp, sp, 16
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: xoriv2i16: ; RV64IPN-LABEL: xoriv2i16:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -16 ; RV64IPN-NEXT: add16 a0, a0, a1
; RV64IPN-NEXT: sw a1, 4(sp) ; RV64IPN-NEXT: xori a0, a0, -2
; RV64IPN-NEXT: sw a0, 8(sp) ; RV64IPN-NEXT: sext.w a0, a0
; RV64IPN-NEXT: lh a0, 6(sp)
; RV64IPN-NEXT: lh a1, 10(sp)
; RV64IPN-NEXT: lh a2, 4(sp)
; RV64IPN-NEXT: lh a3, 8(sp)
; RV64IPN-NEXT: addi a4, zero, 1
; RV64IPN-NEXT: slli a4, a4, 32
; RV64IPN-NEXT: addi a4, a4, -2
; RV64IPN-NEXT: sw a4, 12(sp)
; RV64IPN-NEXT: lh a4, 14(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: xor a0, a0, a4
; RV64IPN-NEXT: sh a0, 2(sp)
; RV64IPN-NEXT: lh a0, 12(sp)
; RV64IPN-NEXT: add a1, a3, a2
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sh a0, 0(sp)
; RV64IPN-NEXT: lw a0, 0(sp)
; RV64IPN-NEXT: addi sp, sp, 16
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i32 %a to <2 x i16> %tmp1 = bitcast i32 %a to <2 x i16>
%tmp2 = bitcast i32 %b to <2 x i16> %tmp2 = bitcast i32 %b to <2 x i16>
%imm = bitcast i32 -2 to <2 x i16> %imm = bitcast i32 -2 to <2 x i16>
%add = add <2 x i16> %tmp1, %tmp2 %add = add <2 x i16> %tmp1, %tmp2
%xor = xor <2 x i16> %add, %imm %xor = xor <2 x i16> %add, %imm
%res = bitcast <2 x i16> %xor to i32 %res = bitcast <2 x i16> %xor to i32
ret i32 %res ret i32 %res
} }
define i64 @xoriv8i8(i64 %a, i64 %b) nounwind { define i64 @xoriv8i8(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: xoriv8i8: ; RV64IP-LABEL: xoriv8i8:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -48 ; RV64IP-NEXT: add8 a0, a0, a1
; RV64IP-NEXT: sd s0, 40(sp) # 8-byte Folded Spill ; RV64IP-NEXT: xori a0, a0, -3
; RV64IP-NEXT: sd s1, 32(sp) # 8-byte Folded Spill
; RV64IP-NEXT: sd a1, 16(sp)
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lb a6, 16(sp)
; RV64IP-NEXT: lb a7, 8(sp)
; RV64IP-NEXT: lb t0, 17(sp)
; RV64IP-NEXT: lb t1, 9(sp)
; RV64IP-NEXT: lb t2, 18(sp)
; RV64IP-NEXT: lb t3, 10(sp)
; RV64IP-NEXT: lb t4, 19(sp)
; RV64IP-NEXT: lb t5, 11(sp)
; RV64IP-NEXT: lb t6, 20(sp)
; RV64IP-NEXT: lb a3, 12(sp)
; RV64IP-NEXT: lb a4, 21(sp)
; RV64IP-NEXT: lb a5, 13(sp)
; RV64IP-NEXT: lb a0, 22(sp)
; RV64IP-NEXT: lb a1, 14(sp)
; RV64IP-NEXT: lb a2, 23(sp)
; RV64IP-NEXT: lb s0, 15(sp)
; RV64IP-NEXT: addi s1, zero, -3
; RV64IP-NEXT: sd s1, 0(sp)
; RV64IP-NEXT: lb s1, 7(sp)
; RV64IP-NEXT: add a2, s0, a2
; RV64IP-NEXT: xor a2, a2, s1
; RV64IP-NEXT: sb a2, 31(sp)
; RV64IP-NEXT: lb a2, 6(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: xor a0, a0, a2
; RV64IP-NEXT: sb a0, 30(sp)
; RV64IP-NEXT: lb a0, 5(sp)
; RV64IP-NEXT: add a1, a5, a4
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sb a0, 29(sp)
; RV64IP-NEXT: lb a0, 4(sp)
; RV64IP-NEXT: add a1, a3, t6
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sb a0, 28(sp)
; RV64IP-NEXT: lb a0, 3(sp)
; RV64IP-NEXT: add a1, t5, t4
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sb a0, 27(sp)
; RV64IP-NEXT: lb a0, 2(sp)
; RV64IP-NEXT: add a1, t3, t2
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sb a0, 26(sp)
; RV64IP-NEXT: lb a0, 1(sp)
; RV64IP-NEXT: add a1, t1, t0
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sb a0, 25(sp)
; RV64IP-NEXT: lb a0, 0(sp)
; RV64IP-NEXT: add a1, a7, a6
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sb a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: ld s1, 32(sp) # 8-byte Folded Reload
; RV64IP-NEXT: ld s0, 40(sp) # 8-byte Folded Reload
; RV64IP-NEXT: addi sp, sp, 48
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: xoriv8i8: ; RV64IPN-LABEL: xoriv8i8:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -48 ; RV64IPN-NEXT: add8 a0, a0, a1
; RV64IPN-NEXT: sd s0, 40(sp) # 8-byte Folded Spill ; RV64IPN-NEXT: xori a0, a0, -3
; RV64IPN-NEXT: sd s1, 32(sp) # 8-byte Folded Spill
; RV64IPN-NEXT: sd a1, 16(sp)
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lb a6, 16(sp)
; RV64IPN-NEXT: lb a7, 8(sp)
; RV64IPN-NEXT: lb t0, 17(sp)
; RV64IPN-NEXT: lb t1, 9(sp)
; RV64IPN-NEXT: lb t2, 18(sp)
; RV64IPN-NEXT: lb t3, 10(sp)
; RV64IPN-NEXT: lb t4, 19(sp)
; RV64IPN-NEXT: lb t5, 11(sp)
; RV64IPN-NEXT: lb t6, 20(sp)
; RV64IPN-NEXT: lb a3, 12(sp)
; RV64IPN-NEXT: lb a4, 21(sp)
; RV64IPN-NEXT: lb a5, 13(sp)
; RV64IPN-NEXT: lb a0, 22(sp)
; RV64IPN-NEXT: lb a1, 14(sp)
; RV64IPN-NEXT: lb a2, 23(sp)
; RV64IPN-NEXT: lb s0, 15(sp)
; RV64IPN-NEXT: addi s1, zero, -3
; RV64IPN-NEXT: sd s1, 0(sp)
; RV64IPN-NEXT: lb s1, 7(sp)
; RV64IPN-NEXT: add a2, s0, a2
; RV64IPN-NEXT: xor a2, a2, s1
; RV64IPN-NEXT: sb a2, 31(sp)
; RV64IPN-NEXT: lb a2, 6(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: xor a0, a0, a2
; RV64IPN-NEXT: sb a0, 30(sp)
; RV64IPN-NEXT: lb a0, 5(sp)
; RV64IPN-NEXT: add a1, a5, a4
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sb a0, 29(sp)
; RV64IPN-NEXT: lb a0, 4(sp)
; RV64IPN-NEXT: add a1, a3, t6
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sb a0, 28(sp)
; RV64IPN-NEXT: lb a0, 3(sp)
; RV64IPN-NEXT: add a1, t5, t4
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sb a0, 27(sp)
; RV64IPN-NEXT: lb a0, 2(sp)
; RV64IPN-NEXT: add a1, t3, t2
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sb a0, 26(sp)
; RV64IPN-NEXT: lb a0, 1(sp)
; RV64IPN-NEXT: add a1, t1, t0
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sb a0, 25(sp)
; RV64IPN-NEXT: lb a0, 0(sp)
; RV64IPN-NEXT: add a1, a7, a6
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sb a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: ld s1, 32(sp) # 8-byte Folded Reload
; RV64IPN-NEXT: ld s0, 40(sp) # 8-byte Folded Reload
; RV64IPN-NEXT: addi sp, sp, 48
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <8 x i8> %tmp1 = bitcast i64 %a to <8 x i8>
%tmp2 = bitcast i64 %b to <8 x i8> %tmp2 = bitcast i64 %b to <8 x i8>
%imm = bitcast i64 -3 to <8 x i8> %imm = bitcast i64 -3 to <8 x i8>
%add = add <8 x i8> %tmp1, %tmp2 %add = add <8 x i8> %tmp1, %tmp2
%xor = xor <8 x i8> %add, %imm %xor = xor <8 x i8> %add, %imm
%res = bitcast <8 x i8> %xor to i64 %res = bitcast <8 x i8> %xor to i64
ret i64 %res ret i64 %res
} }
define i64 @xorvi4i16(i64 %a, i64 %b) nounwind { define i64 @xorvi4i16(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: xorvi4i16: ; RV64IP-LABEL: xorvi4i16:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32 ; RV64IP-NEXT: add16 a0, a0, a1
; RV64IP-NEXT: sd a1, 16(sp) ; RV64IP-NEXT: xori a0, a0, -4
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lh a6, 16(sp)
; RV64IP-NEXT: lh a7, 8(sp)
; RV64IP-NEXT: lh t0, 18(sp)
; RV64IP-NEXT: lh a3, 10(sp)
; RV64IP-NEXT: lh a4, 20(sp)
; RV64IP-NEXT: lh a5, 12(sp)
; RV64IP-NEXT: lh a0, 22(sp)
; RV64IP-NEXT: lh a1, 14(sp)
; RV64IP-NEXT: addi a2, zero, -4
; RV64IP-NEXT: sd a2, 0(sp)
; RV64IP-NEXT: lh a2, 6(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: xor a0, a0, a2
; RV64IP-NEXT: sh a0, 30(sp)
; RV64IP-NEXT: lh a0, 4(sp)
; RV64IP-NEXT: add a1, a5, a4
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sh a0, 28(sp)
; RV64IP-NEXT: lh a0, 2(sp)
; RV64IP-NEXT: add a1, a3, t0
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sh a0, 26(sp)
; RV64IP-NEXT: lh a0, 0(sp)
; RV64IP-NEXT: add a1, a7, a6
; RV64IP-NEXT: xor a0, a1, a0
; RV64IP-NEXT: sh a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: xorvi4i16: ; RV64IPN-LABEL: xorvi4i16:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32 ; RV64IPN-NEXT: add16 a0, a0, a1
; RV64IPN-NEXT: sd a1, 16(sp) ; RV64IPN-NEXT: xori a0, a0, -4
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lh a6, 16(sp)
; RV64IPN-NEXT: lh a7, 8(sp)
; RV64IPN-NEXT: lh t0, 18(sp)
; RV64IPN-NEXT: lh a3, 10(sp)
; RV64IPN-NEXT: lh a4, 20(sp)
; RV64IPN-NEXT: lh a5, 12(sp)
; RV64IPN-NEXT: lh a0, 22(sp)
; RV64IPN-NEXT: lh a1, 14(sp)
; RV64IPN-NEXT: addi a2, zero, -4
; RV64IPN-NEXT: sd a2, 0(sp)
; RV64IPN-NEXT: lh a2, 6(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: xor a0, a0, a2
; RV64IPN-NEXT: sh a0, 30(sp)
; RV64IPN-NEXT: lh a0, 4(sp)
; RV64IPN-NEXT: add a1, a5, a4
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sh a0, 28(sp)
; RV64IPN-NEXT: lh a0, 2(sp)
; RV64IPN-NEXT: add a1, a3, t0
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sh a0, 26(sp)
; RV64IPN-NEXT: lh a0, 0(sp)
; RV64IPN-NEXT: add a1, a7, a6
; RV64IPN-NEXT: xor a0, a1, a0
; RV64IPN-NEXT: sh a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <4 x i16> %tmp1 = bitcast i64 %a to <4 x i16>
%tmp2 = bitcast i64 %b to <4 x i16> %tmp2 = bitcast i64 %b to <4 x i16>
%imm = bitcast i64 -4 to <4 x i16> %imm = bitcast i64 -4 to <4 x i16>
%add = add <4 x i16> %tmp1, %tmp2 %add = add <4 x i16> %tmp1, %tmp2
%xor = xor <4 x i16> %add, %imm %xor = xor <4 x i16> %add, %imm
%res = bitcast <4 x i16> %xor to i64 %res = bitcast <4 x i16> %xor to i64
ret i64 %res ret i64 %res
} }
define i64 @xoriv2i32(i64 %a, i64 %b) nounwind { define i64 @xoriv2i32(i64 %a, i64 %b) nounwind {
; RV64IP-LABEL: xoriv2i32: ; RV64IP-LABEL: xoriv2i32:
; RV64IP: # %bb.0: ; RV64IP: # %bb.0:
; RV64IP-NEXT: addi sp, sp, -32 ; RV64IP-NEXT: add32 a0, a0, a1
; RV64IP-NEXT: sd a1, 16(sp) ; RV64IP-NEXT: xori a0, a0, -5
; RV64IP-NEXT: sd a0, 8(sp)
; RV64IP-NEXT: lw a0, 16(sp)
; RV64IP-NEXT: lw a1, 8(sp)
; RV64IP-NEXT: lw a2, 20(sp)
; RV64IP-NEXT: lw a3, 12(sp)
; RV64IP-NEXT: addi a4, zero, -5
; RV64IP-NEXT: sd a4, 0(sp)
; RV64IP-NEXT: lw a4, 4(sp)
; RV64IP-NEXT: add a2, a3, a2
; RV64IP-NEXT: xor a2, a2, a4
; RV64IP-NEXT: sw a2, 28(sp)
; RV64IP-NEXT: lw a2, 0(sp)
; RV64IP-NEXT: add a0, a1, a0
; RV64IP-NEXT: xor a0, a0, a2
; RV64IP-NEXT: sw a0, 24(sp)
; RV64IP-NEXT: ld a0, 24(sp)
; RV64IP-NEXT: addi sp, sp, 32
; RV64IP-NEXT: ret ; RV64IP-NEXT: ret
; ;
; RV64IPN-LABEL: xoriv2i32: ; RV64IPN-LABEL: xoriv2i32:
; RV64IPN: # %bb.0: ; RV64IPN: # %bb.0:
; RV64IPN-NEXT: addi sp, sp, -32 ; RV64IPN-NEXT: add32 a0, a0, a1
; RV64IPN-NEXT: sd a1, 16(sp) ; RV64IPN-NEXT: xori a0, a0, -5
; RV64IPN-NEXT: sd a0, 8(sp)
; RV64IPN-NEXT: lw a0, 16(sp)
; RV64IPN-NEXT: lw a1, 8(sp)
; RV64IPN-NEXT: lw a2, 20(sp)
; RV64IPN-NEXT: lw a3, 12(sp)
; RV64IPN-NEXT: addi a4, zero, -5
; RV64IPN-NEXT: sd a4, 0(sp)
; RV64IPN-NEXT: lw a4, 4(sp)
; RV64IPN-NEXT: add a2, a3, a2
; RV64IPN-NEXT: xor a2, a2, a4
; RV64IPN-NEXT: sw a2, 28(sp)
; RV64IPN-NEXT: lw a2, 0(sp)
; RV64IPN-NEXT: add a0, a1, a0
; RV64IPN-NEXT: xor a0, a0, a2
; RV64IPN-NEXT: sw a0, 24(sp)
; RV64IPN-NEXT: ld a0, 24(sp)
; RV64IPN-NEXT: addi sp, sp, 32
; RV64IPN-NEXT: ret ; RV64IPN-NEXT: ret
%tmp1 = bitcast i64 %a to <2 x i32> %tmp1 = bitcast i64 %a to <2 x i32>
%tmp2 = bitcast i64 %b to <2 x i32> %tmp2 = bitcast i64 %b to <2 x i32>
%imm = bitcast i64 -5 to <2 x i32> %imm = bitcast i64 -5 to <2 x i32>
%add = add <2 x i32> %tmp1, %tmp2 %add = add <2 x i32> %tmp1, %tmp2
%xor = xor <2 x i32> %add, %imm %xor = xor <2 x i32> %add, %imm
%res = bitcast <2 x i32> %xor to i64 %res = bitcast <2 x i32> %xor to i64
ret i64 %res ret i64 %res
} }