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[RISCV] Implement codegen patterns for RVP ALU operations
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Authored by Jim on May 13 2021, 10:14 PM.

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Summary

Add codegen patterns for vector add, sub, and, or and xor operations.

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Event Timeline

Jim created this revision.May 13 2021, 10:14 PM
Jim requested review of this revision.May 13 2021, 10:14 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 13 2021, 10:14 PM
Jim updated this revision to Diff 349825.Fri, Jun 4, 5:03 AM

Add support for vector and, or and xor operations and
implement getPreferredVectorAction hook to widen v4i8 and v2i16 to v8i8 and v4i16 for RV64P.

Jim retitled this revision from [RISCV] Implement codegen patterns for add8, add16, sub8 and sub16 to [RISCV] Implement codegen patterns for RVP ALU operations.Fri, Jun 4, 5:07 AM
Jim edited the summary of this revision. (Show Details)
Jim updated this revision to Diff 350222.Mon, Jun 7, 3:07 AM

Add codegen patterns for logic operation with immediate.

Jim updated this revision to Diff 352116.Tue, Jun 15, 6:25 AM

Move tests out of rvp directory.