[RISCV] Add support for BITREVERSE for RVP

[Jim]

Summary

Customized lower BITREVERSE to bitrevi.

[jrtc27]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2025

This will cause you to not assert for BSWAP when only RVP is enabled

2031–2034

Is BITREVI or bitmanip's REV better? Why do two extensions need to define the same instruction differently; can there not be a common sub-extension implemented by both (e.g. just the REV form of GREV), like how scalar crypto is using parts of bitmanip?

[jrtc27]

I do not think RVP needs its own subdirectory for CodeGen tests. RVV has one because the extension is massive, but RVP is comparatively small. It should be like all the others. Especially since I think we should be testing interesting combinations of extensions for various tests (e.g. bitmanip + P for things like this).

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2031–2034

It looks BITREVI reverses a range of bits while GREVI reverses nibbles, bytes, words, dwords, etc.?

I think you can also handle i32 bitreverse on RV64 by limiting the BITREVI range to the lower 32 bits? I would like to see that handled in this patch since we handle i32 with GREVIW.

We should probably do i8/i16 for this too, but we don't do it for GREVI so I'm less concerned about matching it.

[Jim]

In D103691#2798807, @jrtc27 wrote:

I do not think RVP needs its own subdirectory for CodeGen tests. RVV has one because the extension is massive, but RVP is comparatively small. It should be like all the others. Especially since I think we should be testing interesting combinations of extensions for various tests (e.g. bitmanip + P for things like this).

I am ongoing to move RVP tests out of its own subdirectory and add tests for the combination of bitmanip + P.

[Jim]

Merge this patch into D103689.

llvm/lib/Target/RISCV/RISCVISelLowering.h

enum NodeType : unsigned {
   // Bit Compress/Decompress implement the generic bit extract and bit deposit
   // functions. This operation is also referred to as bit gather/scatter, bit
   // pack/unpack, parallel extract/deposit, compress/expand, or right
   // compress/right expand.
   BCOMPRESS,
   BCOMPRESSW,
   BDECOMPRESS,
   BDECOMPRESSW,
+  // Packed SIMD Extension
+  BITREV,
   // Vector Extension
   // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
   // for the VL value to be used for the operation.
   VMV_V_X_VL,
   // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
   // for the VL value to be used for the operation.
   VFMV_V_F_VL,
   // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Subtarget.is64Bit()) {
       addTypeForP(MVT::v4i16, MVT::i64);
       addTypeForP(MVT::v2i32, MVT::i64);
     } else {
       addTypeForP(MVT::v4i8, MVT::i32);
       addTypeForP(MVT::v2i16, MVT::i32);
     }
 
     setOperationAction(ISD::BSWAP, XLenVT, Legal);
+    setOperationAction(ISD::BITREVERSE, XLenVT, Custom);
 
     // Expand all truncating stores and extending loads.
     for (MVT VT0 : MVT::vector_valuetypes()) {
       for (MVT VT1 : MVT::vector_valuetypes()) {
         setTruncStoreAction(VT0, VT1, Expand);
         setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand);
         setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand);
         setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand);
SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   }
   case ISD::INTRINSIC_WO_CHAIN:
     return LowerINTRINSIC_WO_CHAIN(Op, DAG);
   case ISD::INTRINSIC_W_CHAIN:
     return LowerINTRINSIC_W_CHAIN(Op, DAG);
   case ISD::BSWAP:
   case ISD::BITREVERSE: {
     // Convert BSWAP/BITREVERSE to GREVI to enable GREVI combinining.
-    assert(Subtarget.hasStdExtZbp() && "Unexpected custom legalisation");
+    assert((Subtarget.hasStdExtZbp() || Subtarget.hasStdExtP()) &&
+           "Unexpected custom legalisation");
     MVT VT = Op.getSimpleValueType();
     SDLoc DL(Op);
     // Start with the maximum immediate value which is the bitwidth - 1.
     unsigned Imm = VT.getSizeInBits() - 1;
+    // If RVP is enabled, lower BITREVERSE to customized BITREV node.
+    if (Subtarget.hasStdExtP() && Op.getOpcode() == ISD::BITREVERSE)
+      return DAG.getNode(RISCVISD::BITREV, DL, VT, Op.getOperand(0),
+                         DAG.getConstant(Imm, DL, VT));
     // If this is BSWAP rather than BITREVERSE, clear the lower 3 bits.
     if (Op.getOpcode() == ISD::BSWAP)
       Imm &= ~0x7U;
     return DAG.getNode(RISCVISD::GREV, DL, VT, Op.getOperand(0),
                        DAG.getConstant(Imm, DL, VT));
   }
   case ISD::FSHL:
   case ISD::FSHR: {
#define NODE_NAME_CASE(NODE)                                                   \
   NODE_NAME_CASE(SHFL)
   NODE_NAME_CASE(SHFLW)
   NODE_NAME_CASE(UNSHFL)
   NODE_NAME_CASE(UNSHFLW)
   NODE_NAME_CASE(BCOMPRESS)
   NODE_NAME_CASE(BCOMPRESSW)
   NODE_NAME_CASE(BDECOMPRESS)
   NODE_NAME_CASE(BDECOMPRESSW)
+  NODE_NAME_CASE(BITREV)
   NODE_NAME_CASE(VMV_V_X_VL)
   NODE_NAME_CASE(VFMV_V_F_VL)
   NODE_NAME_CASE(VMV_X_S)
   NODE_NAME_CASE(VMV_S_X_VL)
   NODE_NAME_CASE(VFMV_S_F_VL)
   NODE_NAME_CASE(SPLAT_VECTOR_I64)
   NODE_NAME_CASE(SPLAT_VECTOR_SPLIT_I64_VL)
   NODE_NAME_CASE(READ_VLENB)

llvm/lib/Target/RISCV/RISCVInstrInfoP.td

 /// ratified yet.
 ///
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // Operand and SDNode transformation definitions.
 //===----------------------------------------------------------------------===//
 
+def riscv_bitrev : SDNode<"RISCVISD::BITREV", SDT_RISCVIntBinOp>;
+
 def uimm3 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<3>(Imm);}]> {
   let ParserMatchClass = UImmAsmOperand<3>;
   let DecoderMethod = "decodeUImmOperand<3>";
   let OperandType = "OPERAND_UIMM3";
   let OperandNamespace = "RISCVOp";
 }
 
 def uimm4 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<4>(Imm);}]> {

 } // [HasStdExtZpn, IsRV64]
 
 // bswap
 let Predicates = [HasStdExtZpn] in
 def : Pat<(bswap i32:$rs1), (SWAP16 (SWAP8 GPR:$rs1))>;
 let Predicates = [HasStdExtZpn, IsRV64] in
 def : Pat<(bswap i64:$rs1), (PKBT32 (SWAP16 (SWAP8 GPR:$rs1)),
                                     (SWAP16 (SWAP8 GPR:$rs1)))>;
+
+// bitreverse
+let Predicates = [HasStdExtZpn] in
+def : Pat<(riscv_bitrev GPR:$rs1, uimmlog2xlen:$imm),
+          (BITREVI GPR:$rs1, uimmlog2xlen:$imm)>;

llvm/test/CodeGen/RISCV/rvp/bitreverse.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-p -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s --check-prefixes=RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s --check-prefixes=RV64
 
 declare i8 @llvm.bitreverse.i8(i8)
 declare i16 @llvm.bitreverse.i16(i16)
 declare i32 @llvm.bitreverse.i32(i32)
 declare i64 @llvm.bitreverse.i64(i64)
 
 define i8 @bitreverse8(i8 %a) nounwind {
 ; RV32-LABEL: bitreverse8:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    andi a1, a0, 15
-; RV32-NEXT:    slli a1, a1, 4
-; RV32-NEXT:    andi a0, a0, 240
-; RV32-NEXT:    srli a0, a0, 4
-; RV32-NEXT:    or a0, a0, a1
-; RV32-NEXT:    andi a1, a0, 51
-; RV32-NEXT:    slli a1, a1, 2
-; RV32-NEXT:    andi a0, a0, 204
-; RV32-NEXT:    srli a0, a0, 2
-; RV32-NEXT:    or a0, a0, a1
-; RV32-NEXT:    andi a1, a0, 85
-; RV32-NEXT:    slli a1, a1, 1
-; RV32-NEXT:    andi a0, a0, 170
-; RV32-NEXT:    srli a0, a0, 1
-; RV32-NEXT:    or a0, a0, a1
+; RV32-NEXT:    bitrevi a0, a0, 31
+; RV32-NEXT:    srli a0, a0, 24
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bitreverse8:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    andi a1, a0, 15
-; RV64-NEXT:    slli a1, a1, 4
-; RV64-NEXT:    andi a0, a0, 240
-; RV64-NEXT:    srli a0, a0, 4
-; RV64-NEXT:    or a0, a0, a1
-; RV64-NEXT:    andi a1, a0, 51
-; RV64-NEXT:    slli a1, a1, 2
-; RV64-NEXT:    andi a0, a0, 204
-; RV64-NEXT:    srli a0, a0, 2
-; RV64-NEXT:    or a0, a0, a1
-; RV64-NEXT:    andi a1, a0, 85
-; RV64-NEXT:    slli a1, a1, 1
-; RV64-NEXT:    andi a0, a0, 170
-; RV64-NEXT:    srli a0, a0, 1
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    bitrevi a0, a0, 63
+; RV64-NEXT:    srli a0, a0, 56
 ; RV64-NEXT:    ret
   %ret = call i8 @llvm.bitreverse.i8(i8 %a)
   ret i8 %ret
 }
 
 define i16 @bitreverse16(i16 %a) nounwind {
 ; RV32-LABEL: bitreverse16:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    swap8 a0, a0
-; RV32-NEXT:    swap16 a0, a0
-; RV32-NEXT:    srli a1, a0, 12
-; RV32-NEXT:    lui a2, 15
-; RV32-NEXT:    addi a2, a2, 240
-; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:    srli a0, a0, 20
-; RV32-NEXT:    andi a0, a0, -241
-; RV32-NEXT:    or a0, a0, a1
-; RV32-NEXT:    lui a1, 3
-; RV32-NEXT:    addi a1, a1, 819
-; RV32-NEXT:    and a1, a0, a1
-; RV32-NEXT:    slli a1, a1, 2
-; RV32-NEXT:    lui a2, 13
-; RV32-NEXT:    addi a2, a2, -820
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    srli a0, a0, 2
-; RV32-NEXT:    or a0, a0, a1
-; RV32-NEXT:    lui a1, 5
-; RV32-NEXT:    addi a1, a1, 1365
-; RV32-NEXT:    and a1, a0, a1
-; RV32-NEXT:    slli a1, a1, 1
-; RV32-NEXT:    lui a2, 11
-; RV32-NEXT:    addi a2, a2, -1366
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    srli a0, a0, 1
-; RV32-NEXT:    or a0, a0, a1
+; RV32-NEXT:    bitrevi a0, a0, 31
+; RV32-NEXT:    srli a0, a0, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bitreverse16:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    swap8 a0, a0
-; RV64-NEXT:    swap16 a0, a0
-; RV64-NEXT:    pkbt32 a0, a0, a0
-; RV64-NEXT:    srli a1, a0, 44
-; RV64-NEXT:    lui a2, 15
-; RV64-NEXT:    addiw a2, a2, 240
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    srli a0, a0, 52
-; RV64-NEXT:    andi a0, a0, -241
-; RV64-NEXT:    or a0, a0, a1
-; RV64-NEXT:    lui a1, 3
-; RV64-NEXT:    addiw a1, a1, 819
-; RV64-NEXT:    and a1, a0, a1
-; RV64-NEXT:    slli a1, a1, 2
-; RV64-NEXT:    lui a2, 13
-; RV64-NEXT:    addiw a2, a2, -820
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    srli a0, a0, 2
-; RV64-NEXT:    or a0, a0, a1
-; RV64-NEXT:    lui a1, 5
-; RV64-NEXT:    addiw a1, a1, 1365
-; RV64-NEXT:    and a1, a0, a1
-; RV64-NEXT:    slli a1, a1, 1
-; RV64-NEXT:    lui a2, 11
-; RV64-NEXT:    addiw a2, a2, -1366
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    srli a0, a0, 1
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    bitrevi a0, a0, 63
+; RV64-NEXT:    srli a0, a0, 48
 ; RV64-NEXT:    ret
   %ret = call i16 @llvm.bitreverse.i16(i16 %a)
   ret i16 %ret
 }
 
 define i32 @bitreverse32(i32 %a) nounwind {
 ; RV32-LABEL: bitreverse32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    swap8 a0, a0
-; RV32-NEXT:    swap16 a0, a0
-; RV32-NEXT:    lui a1, 61681
-; RV32-NEXT:    addi a1, a1, -241
-; RV32-NEXT:    and a1, a0, a1
-; RV32-NEXT:    slli a1, a1, 4
-; RV32-NEXT:    lui a2, 986895
-; RV32-NEXT:    addi a2, a2, 240
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    srli a0, a0, 4
-; RV32-NEXT:    or a0, a0, a1
-; RV32-NEXT:    lui a1, 209715
-; RV32-NEXT:    addi a1, a1, 819
-; RV32-NEXT:    and a1, a0, a1
-; RV32-NEXT:    slli a1, a1, 2
-; RV32-NEXT:    lui a2, 838861
-; RV32-NEXT:    addi a2, a2, -820
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    srli a0, a0, 2
-; RV32-NEXT:    or a0, a0, a1
-; RV32-NEXT:    lui a1, 349525
-; RV32-NEXT:    addi a1, a1, 1365
-; RV32-NEXT:    and a1, a0, a1
-; RV32-NEXT:    slli a1, a1, 1
-; RV32-NEXT:    lui a2, 699051
-; RV32-NEXT:    addi a2, a2, -1366
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    srli a0, a0, 1
-; RV32-NEXT:    or a0, a0, a1
+; RV32-NEXT:    bitrevi a0, a0, 31
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bitreverse32:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    swap8 a0, a0
-; RV64-NEXT:    swap16 a0, a0
-; RV64-NEXT:    pkbt32 a0, a0, a0
-; RV64-NEXT:    srli a1, a0, 28
-; RV64-NEXT:    lui a2, 241
-; RV64-NEXT:    addiw a2, a2, -241
-; RV64-NEXT:    slli a2, a2, 12
-; RV64-NEXT:    addi a2, a2, 240
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    srli a0, a0, 36
-; RV64-NEXT:    lui a2, 61681
-; RV64-NEXT:    addiw a2, a2, -241
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    or a0, a0, a1
-; RV64-NEXT:    lui a1, 209715
-; RV64-NEXT:    addiw a1, a1, 819
-; RV64-NEXT:    and a1, a0, a1
-; RV64-NEXT:    slli a1, a1, 2
-; RV64-NEXT:    lui a2, 838861
-; RV64-NEXT:    addiw a2, a2, -820
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    srli a0, a0, 2
-; RV64-NEXT:    or a0, a0, a1
-; RV64-NEXT:    lui a1, 349525
-; RV64-NEXT:    addiw a1, a1, 1365
-; RV64-NEXT:    and a1, a0, a1
-; RV64-NEXT:    slli a1, a1, 1
-; RV64-NEXT:    lui a2, 699051
-; RV64-NEXT:    addiw a2, a2, -1366
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    srli a0, a0, 1
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    bitrevi a0, a0, 63
+; RV64-NEXT:    srli a0, a0, 32
 ; RV64-NEXT:    ret
   %ret = call i32 @llvm.bitreverse.i32(i32 %a)
   ret i32 %ret
 }
 
 define i64 @bitreverse64(i64 %a) nounwind {
 ; RV32-LABEL: bitreverse64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    swap8 a1, a1
-; RV32-NEXT:    swap16 a1, a1
-; RV32-NEXT:    lui a2, 61681
-; RV32-NEXT:    addi a6, a2, -241
-; RV32-NEXT:    and a2, a1, a6
-; RV32-NEXT:    slli a2, a2, 4
-; RV32-NEXT:    lui a4, 986895
-; RV32-NEXT:    addi t0, a4, 240
-; RV32-NEXT:    and a1, a1, t0
-; RV32-NEXT:    srli a1, a1, 4
-; RV32-NEXT:    or a1, a1, a2
-; RV32-NEXT:    lui a2, 209715
-; RV32-NEXT:    addi t1, a2, 819
-; RV32-NEXT:    and a2, a1, t1
-; RV32-NEXT:    slli a2, a2, 2
-; RV32-NEXT:    lui a3, 838861
-; RV32-NEXT:    addi a3, a3, -820
-; RV32-NEXT:    and a1, a1, a3
-; RV32-NEXT:    srli a1, a1, 2
-; RV32-NEXT:    or a1, a1, a2
-; RV32-NEXT:    lui a2, 349525
-; RV32-NEXT:    addi a2, a2, 1365
-; RV32-NEXT:    and a4, a1, a2
-; RV32-NEXT:    slli a4, a4, 1
-; RV32-NEXT:    lui a5, 699051
-; RV32-NEXT:    addi a5, a5, -1366
-; RV32-NEXT:    and a1, a1, a5
-; RV32-NEXT:    srli a1, a1, 1
-; RV32-NEXT:    or a7, a1, a4
-; RV32-NEXT:    swap8 a0, a0
-; RV32-NEXT:    swap16 a0, a0
-; RV32-NEXT:    and a1, a0, a6
-; RV32-NEXT:    slli a1, a1, 4
-; RV32-NEXT:    and a0, a0, t0
-; RV32-NEXT:    srli a0, a0, 4
-; RV32-NEXT:    or a0, a0, a1
-; RV32-NEXT:    and a1, a0, t1
-; RV32-NEXT:    slli a1, a1, 2
-; RV32-NEXT:    and a0, a0, a3
-; RV32-NEXT:    srli a0, a0, 2
-; RV32-NEXT:    or a0, a0, a1
-; RV32-NEXT:    and a1, a0, a2
-; RV32-NEXT:    slli a1, a1, 1
-; RV32-NEXT:    and a0, a0, a5
-; RV32-NEXT:    srli a0, a0, 1
-; RV32-NEXT:    or a1, a0, a1
-; RV32-NEXT:    mv a0, a7
+; RV32-NEXT:    bitrevi a2, a1, 31
+; RV32-NEXT:    bitrevi a1, a0, 31
+; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bitreverse64:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    swap8 a0, a0
-; RV64-NEXT:    swap16 a0, a0
-; RV64-NEXT:    pkbt32 a0, a0, a0
-; RV64-NEXT:    lui a1, 3855
-; RV64-NEXT:    addiw a1, a1, 241
-; RV64-NEXT:    slli a1, a1, 12
-; RV64-NEXT:    addi a1, a1, -241
-; RV64-NEXT:    slli a1, a1, 12
-; RV64-NEXT:    addi a1, a1, 241
-; RV64-NEXT:    slli a1, a1, 12
-; RV64-NEXT:    addi a1, a1, -241
-; RV64-NEXT:    and a1, a0, a1
-; RV64-NEXT:    slli a1, a1, 4
-; RV64-NEXT:    lui a2, 1044721
-; RV64-NEXT:    addiw a2, a2, -241
-; RV64-NEXT:    slli a2, a2, 12
-; RV64-NEXT:    addi a2, a2, 241
-; RV64-NEXT:    slli a2, a2, 12
-; RV64-NEXT:    addi a2, a2, -241
-; RV64-NEXT:    slli a2, a2, 12
-; RV64-NEXT:    addi a2, a2, 240
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    srli a0, a0, 4
-; RV64-NEXT:    or a0, a0, a1
-; RV64-NEXT:    lui a1, 13107
-; RV64-NEXT:    addiw a1, a1, 819
-; RV64-NEXT:    slli a1, a1, 12
-; RV64-NEXT:    addi a1, a1, 819
-; RV64-NEXT:    slli a1, a1, 12
-; RV64-NEXT:    addi a1, a1, 819
-; RV64-NEXT:    slli a1, a1, 12
-; RV64-NEXT:    addi a1, a1, 819
-; RV64-NEXT:    and a1, a0, a1
-; RV64-NEXT:    slli a1, a1, 2
-; RV64-NEXT:    lui a2, 1035469
-; RV64-NEXT:    addiw a2, a2, -819
-; RV64-NEXT:    slli a2, a2, 12
-; RV64-NEXT:    addi a2, a2, -819
-; RV64-NEXT:    slli a2, a2, 12
-; RV64-NEXT:    addi a2, a2, -819
-; RV64-NEXT:    slli a2, a2, 12
-; RV64-NEXT:    addi a2, a2, -820
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    srli a0, a0, 2
-; RV64-NEXT:    or a0, a0, a1
-; RV64-NEXT:    lui a1, 21845
-; RV64-NEXT:    addiw a1, a1, 1365
-; RV64-NEXT:    slli a1, a1, 12
-; RV64-NEXT:    addi a1, a1, 1365
-; RV64-NEXT:    slli a1, a1, 12
-; RV64-NEXT:    addi a1, a1, 1365
-; RV64-NEXT:    slli a1, a1, 12
-; RV64-NEXT:    addi a1, a1, 1365
-; RV64-NEXT:    and a1, a0, a1
-; RV64-NEXT:    slli a1, a1, 1
-; RV64-NEXT:    lui a2, 1026731
-; RV64-NEXT:    addiw a2, a2, -1365
-; RV64-NEXT:    slli a2, a2, 12
-; RV64-NEXT:    addi a2, a2, -1365
-; RV64-NEXT:    slli a2, a2, 12
-; RV64-NEXT:    addi a2, a2, -1365
-; RV64-NEXT:    slli a2, a2, 12
-; RV64-NEXT:    addi a2, a2, -1366
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    srli a0, a0, 1
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    bitrevi a0, a0, 63
 ; RV64-NEXT:    ret
   %ret = call i64 @llvm.bitreverse.i64(i64 %a)
   ret i64 %ret
 }