[RISCV] Add support for BSWAP and BITREVERSE for RVP

[Jim]

Summary

Use swap8, swap16 and pkbt32 to swap bytes for XLenVT and
customized lower BITREVERSE to bitrevi.

[jrtc27]

llvm/test/CodeGen/RISCV/rvp/bswap.ll

21–24 ↗

(On Diff #349828)

This is not a code size win. This has also introduced more instruction dependencies; previously 1 and 2 were independent, as were 1 and 3, but now every instruction is dependent on the previous, forming a slow chain that will hurt out-of-order cores, or simple in-order cores that can't execute back-to-back P instructions with forwarding.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoP.td

1292

What if Zbb is enabled. Who gets priority?

llvm/test/CodeGen/RISCV/rvp/bswap.ll

21–24 ↗

(On Diff #349828)

You probably want to catch i8/i16 on RV32/RV64 and i32 on RV64 in ReplaceNodeResults and map them to the minimum swap instruction you need before they get promoted.

[Jim]

Merge https://reviews.llvm.org/D103691 into this patch.
Add the codegen of RVB for testcases.

[Jim]

clang-foramt

[Jim]

format td file.

[Jim]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

5033

catch i8/i16 on RV32/RV64 and i32 on RV64

6330

I have the concern about correctness here.

llvm/lib/Target/RISCV/RISCVInstrInfoP.td

1292

Zbb would be first. Zbb only emit one grev instructions. That is better I think.

llvm/lib/Target/RISCV/RISCVISelLowering.h

enum NodeType : unsigned {
   // Bit Compress/Decompress implement the generic bit extract and bit deposit
   // functions. This operation is also referred to as bit gather/scatter, bit
   // pack/unpack, parallel extract/deposit, compress/expand, or right
   // compress/right expand.
   BCOMPRESS,
   BCOMPRESSW,
   BDECOMPRESS,
   BDECOMPRESSW,
+  // Packed SIMD Extension
+  BSWAPH,
+  BSWAPW,
+  BSWAP,
+  BITREVI,
   // Vector Extension
   // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
   // for the VL value to be used for the operation.
   VMV_V_X_VL,
   // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
   // for the VL value to be used for the operation.
   VFMV_V_F_VL,
   // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

const auto addTypeForP = [&](MVT VT, MVT PromotedBitwiseVT) {
 
       // Promote load and store operations.
       setOperationAction(ISD::LOAD, VT, Promote);
       AddPromotedToType(ISD::LOAD, VT, PromotedBitwiseVT);
       setOperationAction(ISD::STORE, VT, Promote);
       AddPromotedToType(ISD::STORE, VT, PromotedBitwiseVT);
     };
 
+    setOperationAction(ISD::BITREVERSE, XLenVT, Custom);
+    setOperationAction(ISD::BSWAP, XLenVT, Custom);
+    setOperationAction(ISD::BITREVERSE, MVT::i8, Custom);
+    // BSWAP i8 doesn't exist.
+    setOperationAction(ISD::BITREVERSE, MVT::i16, Custom);
+    setOperationAction(ISD::BSWAP, MVT::i16, Custom);
+
     if (Subtarget.is64Bit()) {
       addTypeForP(MVT::v8i8, MVT::i64);
       addTypeForP(MVT::v4i16, MVT::i64);
       addTypeForP(MVT::v2i32, MVT::i64);
+
+      setOperationAction(ISD::BITREVERSE, MVT::i32, Custom);
+      setOperationAction(ISD::BSWAP, MVT::i32, Custom);
     } else {
       addTypeForP(MVT::v4i8, MVT::i32);
       addTypeForP(MVT::v2i16, MVT::i32);
     }
 
     // Expand all truncating stores and extending loads.
     for (MVT VT0 : MVT::vector_valuetypes()) {
       for (MVT VT1 : MVT::vector_valuetypes()) {
SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   }
   case ISD::INTRINSIC_WO_CHAIN:
     return LowerINTRINSIC_WO_CHAIN(Op, DAG);
   case ISD::INTRINSIC_W_CHAIN:
     return LowerINTRINSIC_W_CHAIN(Op, DAG);
   case ISD::BSWAP:
   case ISD::BITREVERSE: {
     // Convert BSWAP/BITREVERSE to GREVI to enable GREVI combinining.
-    assert(Subtarget.hasStdExtZbp() && "Unexpected custom legalisation");
+    assert((Subtarget.hasStdExtZbp() || Subtarget.hasStdExtZpn()) &&
+           "Unexpected custom legalisation");
     MVT VT = Op.getSimpleValueType();
     SDLoc DL(Op);
+    // Only RVP is enabled, lower BSWAP to customized BSWAP.
+    if (!Subtarget.hasStdExtZbp() && Op.getOpcode() == ISD::BSWAP)
+      return DAG.getNode(RISCVISD::BSWAP, DL, VT, Op.getOperand(0));
     // Start with the maximum immediate value which is the bitwidth - 1.
     unsigned Imm = VT.getSizeInBits() - 1;
     // If this is BSWAP rather than BITREVERSE, clear the lower 3 bits.
     if (Op.getOpcode() == ISD::BSWAP)
       Imm &= ~0x7U;
-    return DAG.getNode(RISCVISD::GREV, DL, VT, Op.getOperand(0),
+    unsigned Opc =
+        Subtarget.hasStdExtZbp() ? RISCVISD::GREV : RISCVISD::BITREVI;
+    return DAG.getNode(Opc, DL, VT, Op.getOperand(0),
                        DAG.getConstant(Imm, DL, VT));
   }
   case ISD::FSHL:
   case ISD::FSHR: {
     MVT VT = Op.getSimpleValueType();
     assert(VT == Subtarget.getXLenVT() && "Unexpected custom legalization");
     SDLoc DL(Op);
     if (Op.getOperand(2).getOpcode() == ISD::Constant)
case RISCVISD::SHFL: {
     break;
   }
   case ISD::BSWAP:
   case ISD::BITREVERSE: {
     MVT VT = N->getSimpleValueType(0);
     MVT XLenVT = Subtarget.getXLenVT();
     assert((VT == MVT::i8 || VT == MVT::i16 ||
             (VT == MVT::i32 && Subtarget.is64Bit())) &&
-           Subtarget.hasStdExtZbp() && "Unexpected custom legalisation");
+           (Subtarget.hasStdExtZbp() || Subtarget.hasStdExtZpn()) &&
+           "Unexpected custom legalisation");
     SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, N->getOperand(0));
+    SDValue NewOp;
+    // Only RVP is enabled, lower BSWAP to customized BSWAP.
+    if (!Subtarget.hasStdExtZbp() && N->getOpcode() == ISD::BSWAP)
+      NewOp = DAG.getNode(VT == MVT::i16 ? RISCVISD::BSWAPH : RISCVISD::BSWAPW,
+                          DL, XLenVT, NewOp0);
+    else {
       unsigned Imm = VT.getSizeInBits() - 1;
       // If this is BSWAP rather than BITREVERSE, clear the lower 3 bits.
       if (N->getOpcode() == ISD::BSWAP)
         Imm &= ~0x7U;
-    unsigned Opc = Subtarget.is64Bit() ? RISCVISD::GREVW : RISCVISD::GREV;
-    SDValue GREVI =
-        DAG.getNode(Opc, DL, XLenVT, NewOp0, DAG.getConstant(Imm, DL, XLenVT));
+      unsigned Opc =
+          Subtarget.hasStdExtZbp()
+              ? Subtarget.is64Bit() ? RISCVISD::GREVW : RISCVISD::GREV
+              : RISCVISD::BITREVI;
+      NewOp = DAG.getNode(Opc, DL, XLenVT, NewOp0,
+                          DAG.getConstant(Imm, DL, XLenVT));
+    }
     // ReplaceNodeResults requires we maintain the same type for the return
     // value.
-    Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, GREVI));
+    Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, NewOp));
     break;
   }
   case ISD::FSHL:
   case ISD::FSHR: {
     assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
            Subtarget.hasStdExtZbt() && "Unexpected custom legalisation");
     SDValue NewOp0 =
         DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0));
if (auto *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
       unsigned ShAmt = C->getZExtValue();
       computeGREV(Known.Zero, ShAmt);
       computeGREV(Known.One, ShAmt);
       if (Opc == RISCVISD::GREVW)
         Known = Known.sext(BitWidth);
     }
     break;
   }
+  case RISCVISD::BSWAPH:
+    Known.Zero.setBitsFrom(16);
+    break;
+  case RISCVISD::BITREVI: {
+    unsigned Imm = Op.getConstantOperandVal(1);
+    Known.Zero.setBitsFrom(Imm);
+    break;
+  }
   case RISCVISD::READ_VLENB:
     // We assume VLENB is at least 16 bytes.
     Known.Zero.setLowBits(4);
     break;
   case ISD::INTRINSIC_W_CHAIN: {
     unsigned IntNo = Op.getConstantOperandVal(1);
     switch (IntNo) {
     default:
#define NODE_NAME_CASE(NODE)                                                   \
   NODE_NAME_CASE(SHFL)
   NODE_NAME_CASE(SHFLW)
   NODE_NAME_CASE(UNSHFL)
   NODE_NAME_CASE(UNSHFLW)
   NODE_NAME_CASE(BCOMPRESS)
   NODE_NAME_CASE(BCOMPRESSW)
   NODE_NAME_CASE(BDECOMPRESS)
   NODE_NAME_CASE(BDECOMPRESSW)
+  NODE_NAME_CASE(BSWAPH)
+  NODE_NAME_CASE(BSWAPW)
+  NODE_NAME_CASE(BSWAP)
+  NODE_NAME_CASE(BITREVI)
   NODE_NAME_CASE(VMV_V_X_VL)
   NODE_NAME_CASE(VFMV_V_F_VL)
   NODE_NAME_CASE(VMV_X_S)
   NODE_NAME_CASE(VMV_S_X_VL)
   NODE_NAME_CASE(VFMV_S_F_VL)
   NODE_NAME_CASE(SPLAT_VECTOR_I64)
   NODE_NAME_CASE(SPLAT_VECTOR_SPLIT_I64_VL)
   NODE_NAME_CASE(READ_VLENB)

llvm/lib/Target/RISCV/RISCVInstrInfo.td

def SDT_RISCVBrCC : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>,
                                          SDTCisVT<2, OtherVT>,
                                          SDTCisVT<3, OtherVT>]>;
 def SDT_RISCVReadCSR  : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>]>;
 def SDT_RISCVWriteCSR : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisInt<1>]>;
 def SDT_RISCVSwapCSR  : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
                                              SDTCisInt<2>]>;
 def SDT_RISCVReadCycleWide : SDTypeProfile<2, 0, [SDTCisVT<0, i32>,
                                                   SDTCisVT<1, i32>]>;
+def SDT_RISCVIntUnaryOp : SDTypeProfile<1, 1, [
+  SDTCisSameAs<0, 1>, SDTCisVT<0, XLenVT>
+]>;
 def SDT_RISCVIntUnaryOpW : SDTypeProfile<1, 1, [
   SDTCisSameAs<0, 1>, SDTCisVT<0, i64>
 ]>;
 def SDT_RISCVIntBinOp : SDTypeProfile<1, 2, [
   SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<0, XLenVT>
 ]>;
 def SDT_RISCVIntBinOpW : SDTypeProfile<1, 2, [
   SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<0, i64>

llvm/lib/Target/RISCV/RISCVInstrInfoP.td

 /// ratified yet.
 ///
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // Operand and SDNode transformation definitions.
 //===----------------------------------------------------------------------===//
 
+def riscv_bswaph  : SDNode<"RISCVISD::BSWAPH", SDT_RISCVIntUnaryOp>;
+def riscv_bswapw  : SDNode<"RISCVISD::BSWAPW", SDT_RISCVIntUnaryOpW>;
+def riscv_bswap   : SDNode<"RISCVISD::BSWAP", SDT_RISCVIntUnaryOp>;
+def riscv_bitrevi : SDNode<"RISCVISD::BITREVI", SDT_RISCVIntBinOp>;
+
 def uimm3 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<3>(Imm);}]> {
   let ParserMatchClass = UImmAsmOperand<3>;
   let DecoderMethod = "decodeUImmOperand<3>";
   let OperandType = "OPERAND_UIMM3";
   let OperandNamespace = "RISCVOp";
 }
 
 def uimm4 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<4>(Imm);}]> {

 def : PatALU32<and, AND>;
 def : PatALU32<or, OR>;
 def : PatALU32<xor, XOR>;
 
 def : PatALU32I<and, ANDI>;
 def : PatALU32I<or, ORI>;
 def : PatALU32I<xor, XORI>;
 } // [HasStdExtZpn, IsRV64]
+
+// bswap
+let Predicates = [HasStdExtZpn] in
+def : Pat<(riscv_bswaph GPR:$rs1), (SWAP8 GPR:$rs1)>;
+
+let Predicates = [HasStdExtZpn, IsRV32] in
+def : Pat<(riscv_bswap i32:$rs1), (PKBT16 (SWAP8 GPR:$rs1), (SWAP8 GPR:$rs1))>;
+
+let Predicates = [HasStdExtZpn, IsRV64] in {
+def : Pat<(riscv_bswapw GPR:$rs1),
+          (PKBT16 (SWAP8 GPR:$rs1), (SWAP8 GPR:$rs1))>;
+def : Pat<(riscv_bswap i64:$rs1),
+          (PKBT32 (PKBT16 (SWAP8 GPR:$rs1), (SWAP8 GPR:$rs1)),
+                  (PKBT16 (SWAP8 GPR:$rs1), (SWAP8 GPR:$rs1)))>;
+}
+
+// bitreverse
+let Predicates = [HasStdExtZpn] in
+def : Pat<(riscv_bitrevi GPR:$rs1, uimmlog2xlen:$imm),
+          (BITREVI GPR:$rs1, uimmlog2xlen:$imm)>;

llvm/test/CodeGen/RISCV/rv32zpn-bitreverse.ll

 define zeroext i8 @bitreverse_i8(i8 zeroext %a) nounwind {
 ; RV32IB-LABEL: bitreverse_i8:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    rev.b a0, a0
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IP-LABEL: bitreverse_i8:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    srli a1, a0, 4
-; RV32IP-NEXT:    andi a0, a0, 15
-; RV32IP-NEXT:    slli a0, a0, 4
-; RV32IP-NEXT:    or a0, a1, a0
-; RV32IP-NEXT:    andi a1, a0, 51
-; RV32IP-NEXT:    slli a1, a1, 2
-; RV32IP-NEXT:    andi a0, a0, 204
-; RV32IP-NEXT:    srli a0, a0, 2
-; RV32IP-NEXT:    or a0, a0, a1
-; RV32IP-NEXT:    andi a1, a0, 85
-; RV32IP-NEXT:    slli a1, a1, 1
-; RV32IP-NEXT:    andi a0, a0, 170
-; RV32IP-NEXT:    srli a0, a0, 1
-; RV32IP-NEXT:    or a0, a0, a1
+; RV32IP-NEXT:    bitrevi a0, a0, 7
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: bitreverse_i8:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    srli a1, a0, 4
-; RV32IPN-NEXT:    andi a0, a0, 15
-; RV32IPN-NEXT:    slli a0, a0, 4
-; RV32IPN-NEXT:    or a0, a1, a0
-; RV32IPN-NEXT:    andi a1, a0, 51
-; RV32IPN-NEXT:    slli a1, a1, 2
-; RV32IPN-NEXT:    andi a0, a0, 204
-; RV32IPN-NEXT:    srli a0, a0, 2
-; RV32IPN-NEXT:    or a0, a0, a1
-; RV32IPN-NEXT:    andi a1, a0, 85
-; RV32IPN-NEXT:    slli a1, a1, 1
-; RV32IPN-NEXT:    andi a0, a0, 170
-; RV32IPN-NEXT:    srli a0, a0, 1
-; RV32IPN-NEXT:    or a0, a0, a1
+; RV32IPN-NEXT:    bitrevi a0, a0, 7
 ; RV32IPN-NEXT:    ret
 ;
 ; RV32IBP-LABEL: bitreverse_i8:
 ; RV32IBP:       # %bb.0:
 ; RV32IBP-NEXT:    rev.b a0, a0
 ; RV32IBP-NEXT:    ret
   %ret = tail call i8 @llvm.bitreverse.i8(i8 %a)
   ret i8 %ret
 }
 
 define zeroext i16 @bitreverse_i16(i16 zeroext %a) nounwind {
 ; RV32IB-LABEL: bitreverse_i16:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    rev.h a0, a0
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IP-LABEL: bitreverse_i16:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    srli a1, a0, 8
-; RV32IP-NEXT:    slli a0, a0, 8
-; RV32IP-NEXT:    or a0, a0, a1
-; RV32IP-NEXT:    lui a1, 1
-; RV32IP-NEXT:    addi a1, a1, -241
-; RV32IP-NEXT:    and a1, a0, a1
-; RV32IP-NEXT:    slli a1, a1, 4
-; RV32IP-NEXT:    lui a2, 15
-; RV32IP-NEXT:    addi a2, a2, 240
-; RV32IP-NEXT:    and a0, a0, a2
-; RV32IP-NEXT:    srli a0, a0, 4
-; RV32IP-NEXT:    or a0, a0, a1
-; RV32IP-NEXT:    lui a1, 3
-; RV32IP-NEXT:    addi a1, a1, 819
-; RV32IP-NEXT:    and a1, a0, a1
-; RV32IP-NEXT:    slli a1, a1, 2
-; RV32IP-NEXT:    lui a2, 13
-; RV32IP-NEXT:    addi a2, a2, -820
-; RV32IP-NEXT:    and a0, a0, a2
-; RV32IP-NEXT:    srli a0, a0, 2
-; RV32IP-NEXT:    or a0, a0, a1
-; RV32IP-NEXT:    lui a1, 5
-; RV32IP-NEXT:    addi a1, a1, 1365
-; RV32IP-NEXT:    and a1, a0, a1
-; RV32IP-NEXT:    slli a1, a1, 1
-; RV32IP-NEXT:    lui a2, 11
-; RV32IP-NEXT:    addi a2, a2, -1366
-; RV32IP-NEXT:    and a0, a0, a2
-; RV32IP-NEXT:    srli a0, a0, 1
-; RV32IP-NEXT:    or a0, a0, a1
+; RV32IP-NEXT:    bitrevi a0, a0, 15
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: bitreverse_i16:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    srli a1, a0, 8
-; RV32IPN-NEXT:    slli a0, a0, 8
-; RV32IPN-NEXT:    or a0, a0, a1
-; RV32IPN-NEXT:    lui a1, 1
-; RV32IPN-NEXT:    addi a1, a1, -241
-; RV32IPN-NEXT:    and a1, a0, a1
-; RV32IPN-NEXT:    slli a1, a1, 4
-; RV32IPN-NEXT:    lui a2, 15
-; RV32IPN-NEXT:    addi a2, a2, 240
-; RV32IPN-NEXT:    and a0, a0, a2
-; RV32IPN-NEXT:    srli a0, a0, 4
-; RV32IPN-NEXT:    or a0, a0, a1
-; RV32IPN-NEXT:    lui a1, 3
-; RV32IPN-NEXT:    addi a1, a1, 819
-; RV32IPN-NEXT:    and a1, a0, a1
-; RV32IPN-NEXT:    slli a1, a1, 2
-; RV32IPN-NEXT:    lui a2, 13
-; RV32IPN-NEXT:    addi a2, a2, -820
-; RV32IPN-NEXT:    and a0, a0, a2
-; RV32IPN-NEXT:    srli a0, a0, 2
-; RV32IPN-NEXT:    or a0, a0, a1
-; RV32IPN-NEXT:    lui a1, 5
-; RV32IPN-NEXT:    addi a1, a1, 1365
-; RV32IPN-NEXT:    and a1, a0, a1
-; RV32IPN-NEXT:    slli a1, a1, 1
-; RV32IPN-NEXT:    lui a2, 11
-; RV32IPN-NEXT:    addi a2, a2, -1366
-; RV32IPN-NEXT:    and a0, a0, a2
-; RV32IPN-NEXT:    srli a0, a0, 1
-; RV32IPN-NEXT:    or a0, a0, a1
+; RV32IPN-NEXT:    bitrevi a0, a0, 15
 ; RV32IPN-NEXT:    ret
 ;
 ; RV32IBP-LABEL: bitreverse_i16:
 ; RV32IBP:       # %bb.0:
 ; RV32IBP-NEXT:    rev.h a0, a0
 ; RV32IBP-NEXT:    ret
   %ret = tail call i16 @llvm.bitreverse.i16(i16 %a)
   ret i16 %ret
 }
 
 define i32 @bitreverse_i32(i32 %a) nounwind {
 ; RV32IB-LABEL: bitreverse_i32:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    rev a0, a0
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IP-LABEL: bitreverse_i32:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    srli a1, a0, 8
-; RV32IP-NEXT:    lui a2, 16
-; RV32IP-NEXT:    addi a2, a2, -256
-; RV32IP-NEXT:    and a1, a1, a2
-; RV32IP-NEXT:    srli a2, a0, 24
-; RV32IP-NEXT:    or a1, a1, a2
-; RV32IP-NEXT:    slli a2, a0, 8
-; RV32IP-NEXT:    lui a3, 4080
-; RV32IP-NEXT:    and a2, a2, a3
-; RV32IP-NEXT:    slli a0, a0, 24
-; RV32IP-NEXT:    or a0, a0, a2
-; RV32IP-NEXT:    or a0, a0, a1
-; RV32IP-NEXT:    lui a1, 61681
-; RV32IP-NEXT:    addi a1, a1, -241
-; RV32IP-NEXT:    and a1, a0, a1
-; RV32IP-NEXT:    slli a1, a1, 4
-; RV32IP-NEXT:    lui a2, 986895
-; RV32IP-NEXT:    addi a2, a2, 240
-; RV32IP-NEXT:    and a0, a0, a2
-; RV32IP-NEXT:    srli a0, a0, 4
-; RV32IP-NEXT:    or a0, a0, a1
-; RV32IP-NEXT:    lui a1, 209715
-; RV32IP-NEXT:    addi a1, a1, 819
-; RV32IP-NEXT:    and a1, a0, a1
-; RV32IP-NEXT:    slli a1, a1, 2
-; RV32IP-NEXT:    lui a2, 838861
-; RV32IP-NEXT:    addi a2, a2, -820
-; RV32IP-NEXT:    and a0, a0, a2
-; RV32IP-NEXT:    srli a0, a0, 2
-; RV32IP-NEXT:    or a0, a0, a1
-; RV32IP-NEXT:    lui a1, 349525
-; RV32IP-NEXT:    addi a1, a1, 1365
-; RV32IP-NEXT:    and a1, a0, a1
-; RV32IP-NEXT:    slli a1, a1, 1
-; RV32IP-NEXT:    lui a2, 699051
-; RV32IP-NEXT:    addi a2, a2, -1366
-; RV32IP-NEXT:    and a0, a0, a2
-; RV32IP-NEXT:    srli a0, a0, 1
-; RV32IP-NEXT:    or a0, a0, a1
+; RV32IP-NEXT:    bitrevi a0, a0, 31
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: bitreverse_i32:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    srli a1, a0, 8
-; RV32IPN-NEXT:    lui a2, 16
-; RV32IPN-NEXT:    addi a2, a2, -256
-; RV32IPN-NEXT:    and a1, a1, a2
-; RV32IPN-NEXT:    srli a2, a0, 24
-; RV32IPN-NEXT:    or a1, a1, a2
-; RV32IPN-NEXT:    slli a2, a0, 8
-; RV32IPN-NEXT:    lui a3, 4080
-; RV32IPN-NEXT:    and a2, a2, a3
-; RV32IPN-NEXT:    slli a0, a0, 24
-; RV32IPN-NEXT:    or a0, a0, a2
-; RV32IPN-NEXT:    or a0, a0, a1
-; RV32IPN-NEXT:    lui a1, 61681
-; RV32IPN-NEXT:    addi a1, a1, -241
-; RV32IPN-NEXT:    and a1, a0, a1
-; RV32IPN-NEXT:    slli a1, a1, 4
-; RV32IPN-NEXT:    lui a2, 986895
-; RV32IPN-NEXT:    addi a2, a2, 240
-; RV32IPN-NEXT:    and a0, a0, a2
-; RV32IPN-NEXT:    srli a0, a0, 4
-; RV32IPN-NEXT:    or a0, a0, a1
-; RV32IPN-NEXT:    lui a1, 209715
-; RV32IPN-NEXT:    addi a1, a1, 819
-; RV32IPN-NEXT:    and a1, a0, a1
-; RV32IPN-NEXT:    slli a1, a1, 2
-; RV32IPN-NEXT:    lui a2, 838861
-; RV32IPN-NEXT:    addi a2, a2, -820
-; RV32IPN-NEXT:    and a0, a0, a2
-; RV32IPN-NEXT:    srli a0, a0, 2
-; RV32IPN-NEXT:    or a0, a0, a1
-; RV32IPN-NEXT:    lui a1, 349525
-; RV32IPN-NEXT:    addi a1, a1, 1365
-; RV32IPN-NEXT:    and a1, a0, a1
-; RV32IPN-NEXT:    slli a1, a1, 1
-; RV32IPN-NEXT:    lui a2, 699051
-; RV32IPN-NEXT:    addi a2, a2, -1366
-; RV32IPN-NEXT:    and a0, a0, a2
-; RV32IPN-NEXT:    srli a0, a0, 1
-; RV32IPN-NEXT:    or a0, a0, a1
+; RV32IPN-NEXT:    bitrevi a0, a0, 31
 ; RV32IPN-NEXT:    ret
 ;
 ; RV32IBP-LABEL: bitreverse_i32:
 ; RV32IBP:       # %bb.0:
 ; RV32IBP-NEXT:    rev a0, a0
 ; RV32IBP-NEXT:    ret
   %ret = tail call i32 @llvm.bitreverse.i32(i32 %a)
   ret i32 %ret
 }
 
 define i64 @bitreverse_i64(i64 %a) nounwind {
 ; RV32IB-LABEL: bitreverse_i64:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    rev a2, a1
 ; RV32IB-NEXT:    rev a1, a0
 ; RV32IB-NEXT:    mv a0, a2
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IP-LABEL: bitreverse_i64:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    srli a2, a1, 8
-; RV32IP-NEXT:    lui a3, 16
-; RV32IP-NEXT:    addi t0, a3, -256
-; RV32IP-NEXT:    and a2, a2, t0
-; RV32IP-NEXT:    srli a4, a1, 24
-; RV32IP-NEXT:    or a2, a2, a4
-; RV32IP-NEXT:    slli a4, a1, 8
-; RV32IP-NEXT:    lui a6, 4080
-; RV32IP-NEXT:    and a4, a4, a6
-; RV32IP-NEXT:    slli a1, a1, 24
-; RV32IP-NEXT:    or a1, a1, a4
-; RV32IP-NEXT:    or a1, a1, a2
-; RV32IP-NEXT:    lui a2, 61681
-; RV32IP-NEXT:    addi t1, a2, -241
-; RV32IP-NEXT:    and a2, a1, t1
-; RV32IP-NEXT:    slli a2, a2, 4
-; RV32IP-NEXT:    lui a5, 986895
-; RV32IP-NEXT:    addi t2, a5, 240
-; RV32IP-NEXT:    and a1, a1, t2
-; RV32IP-NEXT:    srli a1, a1, 4
-; RV32IP-NEXT:    or a1, a1, a2
-; RV32IP-NEXT:    lui a2, 209715
-; RV32IP-NEXT:    addi t3, a2, 819
-; RV32IP-NEXT:    and a3, a1, t3
-; RV32IP-NEXT:    slli a3, a3, 2
-; RV32IP-NEXT:    lui a4, 838861
-; RV32IP-NEXT:    addi a4, a4, -820
-; RV32IP-NEXT:    and a1, a1, a4
-; RV32IP-NEXT:    srli a1, a1, 2
-; RV32IP-NEXT:    or a1, a1, a3
-; RV32IP-NEXT:    lui a3, 349525
-; RV32IP-NEXT:    addi a3, a3, 1365
-; RV32IP-NEXT:    and a5, a1, a3
-; RV32IP-NEXT:    slli a5, a5, 1
-; RV32IP-NEXT:    lui a2, 699051
-; RV32IP-NEXT:    addi a2, a2, -1366
-; RV32IP-NEXT:    and a1, a1, a2
-; RV32IP-NEXT:    srli a1, a1, 1
-; RV32IP-NEXT:    or a7, a1, a5
-; RV32IP-NEXT:    srli a1, a0, 8
-; RV32IP-NEXT:    and a1, a1, t0
-; RV32IP-NEXT:    srli a5, a0, 24
-; RV32IP-NEXT:    or a1, a1, a5
-; RV32IP-NEXT:    slli a5, a0, 8
-; RV32IP-NEXT:    and a5, a5, a6
-; RV32IP-NEXT:    slli a0, a0, 24
-; RV32IP-NEXT:    or a0, a0, a5
-; RV32IP-NEXT:    or a0, a0, a1
-; RV32IP-NEXT:    and a1, a0, t1
-; RV32IP-NEXT:    slli a1, a1, 4
-; RV32IP-NEXT:    and a0, a0, t2
-; RV32IP-NEXT:    srli a0, a0, 4
-; RV32IP-NEXT:    or a0, a0, a1
-; RV32IP-NEXT:    and a1, a0, t3
-; RV32IP-NEXT:    slli a1, a1, 2
-; RV32IP-NEXT:    and a0, a0, a4
-; RV32IP-NEXT:    srli a0, a0, 2
-; RV32IP-NEXT:    or a0, a0, a1
-; RV32IP-NEXT:    and a1, a0, a3
-; RV32IP-NEXT:    slli a1, a1, 1
-; RV32IP-NEXT:    and a0, a0, a2
-; RV32IP-NEXT:    srli a0, a0, 1
-; RV32IP-NEXT:    or a1, a0, a1
-; RV32IP-NEXT:    mv a0, a7
+; RV32IP-NEXT:    bitrevi a2, a1, 31
+; RV32IP-NEXT:    bitrevi a1, a0, 31
+; RV32IP-NEXT:    mv a0, a2
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: bitreverse_i64:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    srli a2, a1, 8
-; RV32IPN-NEXT:    lui a3, 16
-; RV32IPN-NEXT:    addi t0, a3, -256
-; RV32IPN-NEXT:    and a2, a2, t0
-; RV32IPN-NEXT:    srli a4, a1, 24
-; RV32IPN-NEXT:    or a2, a2, a4
-; RV32IPN-NEXT:    slli a4, a1, 8
-; RV32IPN-NEXT:    lui a6, 4080
-; RV32IPN-NEXT:    and a4, a4, a6
-; RV32IPN-NEXT:    slli a1, a1, 24
-; RV32IPN-NEXT:    or a1, a1, a4
-; RV32IPN-NEXT:    or a1, a1, a2
-; RV32IPN-NEXT:    lui a2, 61681
-; RV32IPN-NEXT:    addi t1, a2, -241
-; RV32IPN-NEXT:    and a2, a1, t1
-; RV32IPN-NEXT:    slli a2, a2, 4
-; RV32IPN-NEXT:    lui a5, 986895
-; RV32IPN-NEXT:    addi t2, a5, 240
-; RV32IPN-NEXT:    and a1, a1, t2
-; RV32IPN-NEXT:    srli a1, a1, 4
-; RV32IPN-NEXT:    or a1, a1, a2
-; RV32IPN-NEXT:    lui a2, 209715
-; RV32IPN-NEXT:    addi t3, a2, 819
-; RV32IPN-NEXT:    and a3, a1, t3
-; RV32IPN-NEXT:    slli a3, a3, 2
-; RV32IPN-NEXT:    lui a4, 838861
-; RV32IPN-NEXT:    addi a4, a4, -820
-; RV32IPN-NEXT:    and a1, a1, a4
-; RV32IPN-NEXT:    srli a1, a1, 2
-; RV32IPN-NEXT:    or a1, a1, a3
-; RV32IPN-NEXT:    lui a3, 349525
-; RV32IPN-NEXT:    addi a3, a3, 1365
-; RV32IPN-NEXT:    and a5, a1, a3
-; RV32IPN-NEXT:    slli a5, a5, 1
-; RV32IPN-NEXT:    lui a2, 699051
-; RV32IPN-NEXT:    addi a2, a2, -1366
-; RV32IPN-NEXT:    and a1, a1, a2
-; RV32IPN-NEXT:    srli a1, a1, 1
-; RV32IPN-NEXT:    or a7, a1, a5
-; RV32IPN-NEXT:    srli a1, a0, 8
-; RV32IPN-NEXT:    and a1, a1, t0
-; RV32IPN-NEXT:    srli a5, a0, 24
-; RV32IPN-NEXT:    or a1, a1, a5
-; RV32IPN-NEXT:    slli a5, a0, 8
-; RV32IPN-NEXT:    and a5, a5, a6
-; RV32IPN-NEXT:    slli a0, a0, 24
-; RV32IPN-NEXT:    or a0, a0, a5
-; RV32IPN-NEXT:    or a0, a0, a1
-; RV32IPN-NEXT:    and a1, a0, t1
-; RV32IPN-NEXT:    slli a1, a1, 4
-; RV32IPN-NEXT:    and a0, a0, t2
-; RV32IPN-NEXT:    srli a0, a0, 4
-; RV32IPN-NEXT:    or a0, a0, a1
-; RV32IPN-NEXT:    and a1, a0, t3
-; RV32IPN-NEXT:    slli a1, a1, 2
-; RV32IPN-NEXT:    and a0, a0, a4
-; RV32IPN-NEXT:    srli a0, a0, 2
-; RV32IPN-NEXT:    or a0, a0, a1
-; RV32IPN-NEXT:    and a1, a0, a3
-; RV32IPN-NEXT:    slli a1, a1, 1
-; RV32IPN-NEXT:    and a0, a0, a2
-; RV32IPN-NEXT:    srli a0, a0, 1
-; RV32IPN-NEXT:    or a1, a0, a1
-; RV32IPN-NEXT:    mv a0, a7
+; RV32IPN-NEXT:    bitrevi a2, a1, 31
+; RV32IPN-NEXT:    bitrevi a1, a0, 31
+; RV32IPN-NEXT:    mv a0, a2
 ; RV32IPN-NEXT:    ret
 ;
 ; RV32IBP-LABEL: bitreverse_i64:
 ; RV32IBP:       # %bb.0:
 ; RV32IBP-NEXT:    rev a2, a1
 ; RV32IBP-NEXT:    rev a1, a0
 ; RV32IBP-NEXT:    mv a0, a2
 ; RV32IBP-NEXT:    ret
   %ret = tail call i64 @llvm.bitreverse.i64(i64 %a)
   ret i64 %ret
 }

llvm/test/CodeGen/RISCV/rv32zpn-bswap.ll

 define zeroext i16 @bswap_i16(i16 zeroext %a) nounwind {
 ; RV32IB-LABEL: bswap_i16:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    rev8.h a0, a0
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IP-LABEL: bswap_i16:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    srli a1, a0, 8
-; RV32IP-NEXT:    slli a0, a0, 8
-; RV32IP-NEXT:    or a0, a0, a1
-; RV32IP-NEXT:    lui a1, 16
-; RV32IP-NEXT:    addi a1, a1, -1
-; RV32IP-NEXT:    and a0, a0, a1
+; RV32IP-NEXT:    swap8 a0, a0
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: bswap_i16:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    srli a1, a0, 8
-; RV32IPN-NEXT:    slli a0, a0, 8
-; RV32IPN-NEXT:    or a0, a0, a1
-; RV32IPN-NEXT:    lui a1, 16
-; RV32IPN-NEXT:    addi a1, a1, -1
-; RV32IPN-NEXT:    and a0, a0, a1
+; RV32IPN-NEXT:    swap8 a0, a0
 ; RV32IPN-NEXT:    ret
 ;
 ; RV32IBP-LABEL: bswap_i16:
 ; RV32IBP:       # %bb.0:
 ; RV32IBP-NEXT:    rev8.h a0, a0
 ; RV32IBP-NEXT:    ret
   %ret = tail call i16 @llvm.bswap.i16(i16 %a)
   ret i16 %ret
 }
 
 define i32 @bswap_i32(i32 %a) nounwind {
 ; RV32IB-LABEL: bswap_i32:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    rev8 a0, a0
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IP-LABEL: bswap_i32:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    srli a1, a0, 8
-; RV32IP-NEXT:    lui a2, 16
-; RV32IP-NEXT:    addi a2, a2, -256
-; RV32IP-NEXT:    and a1, a1, a2
-; RV32IP-NEXT:    srli a2, a0, 24
-; RV32IP-NEXT:    or a1, a1, a2
-; RV32IP-NEXT:    slli a2, a0, 8
-; RV32IP-NEXT:    lui a3, 4080
-; RV32IP-NEXT:    and a2, a2, a3
-; RV32IP-NEXT:    slli a0, a0, 24
-; RV32IP-NEXT:    or a0, a0, a2
-; RV32IP-NEXT:    or a0, a0, a1
+; RV32IP-NEXT:    swap8 a0, a0
+; RV32IP-NEXT:    swap16 a0, a0
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: bswap_i32:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    srli a1, a0, 8
-; RV32IPN-NEXT:    lui a2, 16
-; RV32IPN-NEXT:    addi a2, a2, -256
-; RV32IPN-NEXT:    and a1, a1, a2
-; RV32IPN-NEXT:    srli a2, a0, 24
-; RV32IPN-NEXT:    or a1, a1, a2
-; RV32IPN-NEXT:    slli a2, a0, 8
-; RV32IPN-NEXT:    lui a3, 4080
-; RV32IPN-NEXT:    and a2, a2, a3
-; RV32IPN-NEXT:    slli a0, a0, 24
-; RV32IPN-NEXT:    or a0, a0, a2
-; RV32IPN-NEXT:    or a0, a0, a1
+; RV32IPN-NEXT:    swap8 a0, a0
+; RV32IPN-NEXT:    swap16 a0, a0
 ; RV32IPN-NEXT:    ret
 ;
 ; RV32IBP-LABEL: bswap_i32:
 ; RV32IBP:       # %bb.0:
 ; RV32IBP-NEXT:    rev8 a0, a0
 ; RV32IBP-NEXT:    ret
   %ret = tail call i32 @llvm.bswap.i32(i32 %a)
   ret i32 %ret
 }
 
 define i64 @bswap_i64(i64 %a) nounwind {
 ; RV32IB-LABEL: bswap_i64:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    rev8 a2, a1
 ; RV32IB-NEXT:    rev8 a1, a0
 ; RV32IB-NEXT:    mv a0, a2
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IP-LABEL: bswap_i64:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    srli a2, a1, 8
-; RV32IP-NEXT:    lui a3, 16
-; RV32IP-NEXT:    addi a3, a3, -256
-; RV32IP-NEXT:    and a2, a2, a3
-; RV32IP-NEXT:    srli a4, a1, 24
-; RV32IP-NEXT:    or a2, a2, a4
-; RV32IP-NEXT:    slli a4, a1, 8
-; RV32IP-NEXT:    lui a5, 4080
-; RV32IP-NEXT:    and a4, a4, a5
-; RV32IP-NEXT:    slli a1, a1, 24
-; RV32IP-NEXT:    or a1, a1, a4
-; RV32IP-NEXT:    or a2, a1, a2
-; RV32IP-NEXT:    srli a1, a0, 8
-; RV32IP-NEXT:    and a1, a1, a3
-; RV32IP-NEXT:    srli a3, a0, 24
-; RV32IP-NEXT:    or a1, a1, a3
-; RV32IP-NEXT:    slli a3, a0, 8
-; RV32IP-NEXT:    and a3, a3, a5
-; RV32IP-NEXT:    slli a0, a0, 24
-; RV32IP-NEXT:    or a0, a0, a3
-; RV32IP-NEXT:    or a1, a0, a1
+; RV32IP-NEXT:    swap8 a1, a1
+; RV32IP-NEXT:    swap16 a2, a1
+; RV32IP-NEXT:    swap8 a0, a0
+; RV32IP-NEXT:    swap16 a1, a0
 ; RV32IP-NEXT:    mv a0, a2
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: bswap_i64:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    srli a2, a1, 8
-; RV32IPN-NEXT:    lui a3, 16
-; RV32IPN-NEXT:    addi a3, a3, -256
-; RV32IPN-NEXT:    and a2, a2, a3
-; RV32IPN-NEXT:    srli a4, a1, 24
-; RV32IPN-NEXT:    or a2, a2, a4
-; RV32IPN-NEXT:    slli a4, a1, 8
-; RV32IPN-NEXT:    lui a5, 4080
-; RV32IPN-NEXT:    and a4, a4, a5
-; RV32IPN-NEXT:    slli a1, a1, 24
-; RV32IPN-NEXT:    or a1, a1, a4
-; RV32IPN-NEXT:    or a2, a1, a2
-; RV32IPN-NEXT:    srli a1, a0, 8
-; RV32IPN-NEXT:    and a1, a1, a3
-; RV32IPN-NEXT:    srli a3, a0, 24
-; RV32IPN-NEXT:    or a1, a1, a3
-; RV32IPN-NEXT:    slli a3, a0, 8
-; RV32IPN-NEXT:    and a3, a3, a5
-; RV32IPN-NEXT:    slli a0, a0, 24
-; RV32IPN-NEXT:    or a0, a0, a3
-; RV32IPN-NEXT:    or a1, a0, a1
+; RV32IPN-NEXT:    swap8 a1, a1
+; RV32IPN-NEXT:    swap16 a2, a1
+; RV32IPN-NEXT:    swap8 a0, a0
+; RV32IPN-NEXT:    swap16 a1, a0
 ; RV32IPN-NEXT:    mv a0, a2
 ; RV32IPN-NEXT:    ret
 ;
 ; RV32IBP-LABEL: bswap_i64:
 ; RV32IBP:       # %bb.0:
 ; RV32IBP-NEXT:    rev8 a2, a1
 ; RV32IBP-NEXT:    rev8 a1, a0
 ; RV32IBP-NEXT:    mv a0, a2
 ; RV32IBP-NEXT:    ret
   %ret = tail call i64 @llvm.bswap.i64(i64 %a)
   ret i64 %ret
 }

llvm/test/CodeGen/RISCV/rv64zpn-bitreverse.ll

 define zeroext i8 @bitreverse_i8(i8 zeroext %a) nounwind {
 ; RV64IB-LABEL: bitreverse_i8:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    greviw a0, a0, 7
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IP-LABEL: bitreverse_i8:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    srli a1, a0, 4
-; RV64IP-NEXT:    andi a0, a0, 15
-; RV64IP-NEXT:    slli a0, a0, 4
-; RV64IP-NEXT:    or a0, a1, a0
-; RV64IP-NEXT:    andi a1, a0, 51
-; RV64IP-NEXT:    slli a1, a1, 2
-; RV64IP-NEXT:    andi a0, a0, 204
-; RV64IP-NEXT:    srli a0, a0, 2
-; RV64IP-NEXT:    or a0, a0, a1
-; RV64IP-NEXT:    andi a1, a0, 85
-; RV64IP-NEXT:    slli a1, a1, 1
-; RV64IP-NEXT:    andi a0, a0, 170
-; RV64IP-NEXT:    srli a0, a0, 1
-; RV64IP-NEXT:    or a0, a0, a1
+; RV64IP-NEXT:    bitrevi a0, a0, 7
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: bitreverse_i8:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    srli a1, a0, 4
-; RV64IPN-NEXT:    andi a0, a0, 15
-; RV64IPN-NEXT:    slli a0, a0, 4
-; RV64IPN-NEXT:    or a0, a1, a0
-; RV64IPN-NEXT:    andi a1, a0, 51
-; RV64IPN-NEXT:    slli a1, a1, 2
-; RV64IPN-NEXT:    andi a0, a0, 204
-; RV64IPN-NEXT:    srli a0, a0, 2
-; RV64IPN-NEXT:    or a0, a0, a1
-; RV64IPN-NEXT:    andi a1, a0, 85
-; RV64IPN-NEXT:    slli a1, a1, 1
-; RV64IPN-NEXT:    andi a0, a0, 170
-; RV64IPN-NEXT:    srli a0, a0, 1
-; RV64IPN-NEXT:    or a0, a0, a1
+; RV64IPN-NEXT:    bitrevi a0, a0, 7
 ; RV64IPN-NEXT:    ret
 ;
 ; RV64IBP-LABEL: bitreverse_i8:
 ; RV64IBP:       # %bb.0:
 ; RV64IBP-NEXT:    greviw a0, a0, 7
 ; RV64IBP-NEXT:    ret
   %ret = tail call i8 @llvm.bitreverse.i8(i8 %a)
   ret i8 %ret
 }
 
 define zeroext i16 @bitreverse_i16(i16 zeroext %a) nounwind {
 ; RV64IB-LABEL: bitreverse_i16:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    greviw a0, a0, 15
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IP-LABEL: bitreverse_i16:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    srli a1, a0, 8
-; RV64IP-NEXT:    slli a0, a0, 8
-; RV64IP-NEXT:    or a0, a0, a1
-; RV64IP-NEXT:    lui a1, 1
-; RV64IP-NEXT:    addiw a1, a1, -241
-; RV64IP-NEXT:    and a1, a0, a1
-; RV64IP-NEXT:    slli a1, a1, 4
-; RV64IP-NEXT:    lui a2, 15
-; RV64IP-NEXT:    addiw a2, a2, 240
-; RV64IP-NEXT:    and a0, a0, a2
-; RV64IP-NEXT:    srli a0, a0, 4
-; RV64IP-NEXT:    or a0, a0, a1
-; RV64IP-NEXT:    lui a1, 3
-; RV64IP-NEXT:    addiw a1, a1, 819
-; RV64IP-NEXT:    and a1, a0, a1
-; RV64IP-NEXT:    slli a1, a1, 2
-; RV64IP-NEXT:    lui a2, 13
-; RV64IP-NEXT:    addiw a2, a2, -820
-; RV64IP-NEXT:    and a0, a0, a2
-; RV64IP-NEXT:    srli a0, a0, 2
-; RV64IP-NEXT:    or a0, a0, a1
-; RV64IP-NEXT:    lui a1, 5
-; RV64IP-NEXT:    addiw a1, a1, 1365
-; RV64IP-NEXT:    and a1, a0, a1
-; RV64IP-NEXT:    slli a1, a1, 1
-; RV64IP-NEXT:    lui a2, 11
-; RV64IP-NEXT:    addiw a2, a2, -1366
-; RV64IP-NEXT:    and a0, a0, a2
-; RV64IP-NEXT:    srli a0, a0, 1
-; RV64IP-NEXT:    or a0, a0, a1
+; RV64IP-NEXT:    bitrevi a0, a0, 15
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: bitreverse_i16:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    srli a1, a0, 8
-; RV64IPN-NEXT:    slli a0, a0, 8
-; RV64IPN-NEXT:    or a0, a0, a1
-; RV64IPN-NEXT:    lui a1, 1
-; RV64IPN-NEXT:    addiw a1, a1, -241
-; RV64IPN-NEXT:    and a1, a0, a1
-; RV64IPN-NEXT:    slli a1, a1, 4
-; RV64IPN-NEXT:    lui a2, 15
-; RV64IPN-NEXT:    addiw a2, a2, 240
-; RV64IPN-NEXT:    and a0, a0, a2
-; RV64IPN-NEXT:    srli a0, a0, 4
-; RV64IPN-NEXT:    or a0, a0, a1
-; RV64IPN-NEXT:    lui a1, 3
-; RV64IPN-NEXT:    addiw a1, a1, 819
-; RV64IPN-NEXT:    and a1, a0, a1
-; RV64IPN-NEXT:    slli a1, a1, 2
-; RV64IPN-NEXT:    lui a2, 13
-; RV64IPN-NEXT:    addiw a2, a2, -820
-; RV64IPN-NEXT:    and a0, a0, a2
-; RV64IPN-NEXT:    srli a0, a0, 2
-; RV64IPN-NEXT:    or a0, a0, a1
-; RV64IPN-NEXT:    lui a1, 5
-; RV64IPN-NEXT:    addiw a1, a1, 1365
-; RV64IPN-NEXT:    and a1, a0, a1
-; RV64IPN-NEXT:    slli a1, a1, 1
-; RV64IPN-NEXT:    lui a2, 11
-; RV64IPN-NEXT:    addiw a2, a2, -1366
-; RV64IPN-NEXT:    and a0, a0, a2
-; RV64IPN-NEXT:    srli a0, a0, 1
-; RV64IPN-NEXT:    or a0, a0, a1
+; RV64IPN-NEXT:    bitrevi a0, a0, 15
 ; RV64IPN-NEXT:    ret
 ;
 ; RV64IBP-LABEL: bitreverse_i16:
 ; RV64IBP:       # %bb.0:
 ; RV64IBP-NEXT:    greviw a0, a0, 15
 ; RV64IBP-NEXT:    ret
   %ret = tail call i16 @llvm.bitreverse.i16(i16 %a)
   ret i16 %ret
 }
 
 define signext i32 @bitreverse_i32(i32 signext %a) nounwind {
 ; RV64IB-LABEL: bitreverse_i32:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    greviw a0, a0, 31
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IP-LABEL: bitreverse_i32:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    srliw a1, a0, 8
-; RV64IP-NEXT:    lui a2, 16
-; RV64IP-NEXT:    addiw a2, a2, -256
-; RV64IP-NEXT:    and a1, a1, a2
-; RV64IP-NEXT:    srliw a2, a0, 24
-; RV64IP-NEXT:    or a1, a1, a2
-; RV64IP-NEXT:    slli a2, a0, 8
-; RV64IP-NEXT:    lui a3, 4080
-; RV64IP-NEXT:    and a2, a2, a3
-; RV64IP-NEXT:    slli a0, a0, 24
-; RV64IP-NEXT:    or a0, a0, a2
-; RV64IP-NEXT:    or a0, a0, a1
-; RV64IP-NEXT:    lui a1, 61681
-; RV64IP-NEXT:    addiw a1, a1, -241
-; RV64IP-NEXT:    and a1, a0, a1
-; RV64IP-NEXT:    slli a1, a1, 4
-; RV64IP-NEXT:    lui a2, 241
-; RV64IP-NEXT:    addiw a2, a2, -241
-; RV64IP-NEXT:    slli a2, a2, 12
-; RV64IP-NEXT:    addi a2, a2, 240
-; RV64IP-NEXT:    and a0, a0, a2
-; RV64IP-NEXT:    srli a0, a0, 4
-; RV64IP-NEXT:    or a0, a0, a1
-; RV64IP-NEXT:    lui a1, 209715
-; RV64IP-NEXT:    addiw a1, a1, 819
-; RV64IP-NEXT:    and a1, a0, a1
-; RV64IP-NEXT:    slli a1, a1, 2
-; RV64IP-NEXT:    lui a2, 838861
-; RV64IP-NEXT:    addiw a2, a2, -820
-; RV64IP-NEXT:    and a0, a0, a2
-; RV64IP-NEXT:    srli a0, a0, 2
-; RV64IP-NEXT:    or a0, a0, a1
-; RV64IP-NEXT:    lui a1, 349525
-; RV64IP-NEXT:    addiw a1, a1, 1365
-; RV64IP-NEXT:    and a1, a0, a1
-; RV64IP-NEXT:    slli a1, a1, 1
-; RV64IP-NEXT:    lui a2, 699051
-; RV64IP-NEXT:    addiw a2, a2, -1366
-; RV64IP-NEXT:    and a0, a0, a2
-; RV64IP-NEXT:    srli a0, a0, 1
-; RV64IP-NEXT:    or a0, a0, a1
-; RV64IP-NEXT:    sext.w a0, a0
+; RV64IP-NEXT:    bitrevi a0, a0, 31
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: bitreverse_i32:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    srliw a1, a0, 8
-; RV64IPN-NEXT:    lui a2, 16
-; RV64IPN-NEXT:    addiw a2, a2, -256
-; RV64IPN-NEXT:    and a1, a1, a2
-; RV64IPN-NEXT:    srliw a2, a0, 24
-; RV64IPN-NEXT:    or a1, a1, a2
-; RV64IPN-NEXT:    slli a2, a0, 8
-; RV64IPN-NEXT:    lui a3, 4080
-; RV64IPN-NEXT:    and a2, a2, a3
-; RV64IPN-NEXT:    slli a0, a0, 24
-; RV64IPN-NEXT:    or a0, a0, a2
-; RV64IPN-NEXT:    or a0, a0, a1
-; RV64IPN-NEXT:    lui a1, 61681
-; RV64IPN-NEXT:    addiw a1, a1, -241
-; RV64IPN-NEXT:    and a1, a0, a1
-; RV64IPN-NEXT:    slli a1, a1, 4
-; RV64IPN-NEXT:    lui a2, 241
-; RV64IPN-NEXT:    addiw a2, a2, -241
-; RV64IPN-NEXT:    slli a2, a2, 12
-; RV64IPN-NEXT:    addi a2, a2, 240
-; RV64IPN-NEXT:    and a0, a0, a2
-; RV64IPN-NEXT:    srli a0, a0, 4
-; RV64IPN-NEXT:    or a0, a0, a1
-; RV64IPN-NEXT:    lui a1, 209715
-; RV64IPN-NEXT:    addiw a1, a1, 819
-; RV64IPN-NEXT:    and a1, a0, a1
-; RV64IPN-NEXT:    slli a1, a1, 2
-; RV64IPN-NEXT:    lui a2, 838861
-; RV64IPN-NEXT:    addiw a2, a2, -820
-; RV64IPN-NEXT:    and a0, a0, a2
-; RV64IPN-NEXT:    srli a0, a0, 2
-; RV64IPN-NEXT:    or a0, a0, a1
-; RV64IPN-NEXT:    lui a1, 349525
-; RV64IPN-NEXT:    addiw a1, a1, 1365
-; RV64IPN-NEXT:    and a1, a0, a1
-; RV64IPN-NEXT:    slli a1, a1, 1
-; RV64IPN-NEXT:    lui a2, 699051
-; RV64IPN-NEXT:    addiw a2, a2, -1366
-; RV64IPN-NEXT:    and a0, a0, a2
-; RV64IPN-NEXT:    srli a0, a0, 1
-; RV64IPN-NEXT:    or a0, a0, a1
-; RV64IPN-NEXT:    sext.w a0, a0
+; RV64IPN-NEXT:    bitrevi a0, a0, 31
 ; RV64IPN-NEXT:    ret
 ;
 ; RV64IBP-LABEL: bitreverse_i32:
 ; RV64IBP:       # %bb.0:
 ; RV64IBP-NEXT:    greviw a0, a0, 31
 ; RV64IBP-NEXT:    ret
   %ret = tail call i32 @llvm.bitreverse.i32(i32 %a)
   ret i32 %ret
 }
 
 ; Similar to bitreverse32 but the result is not sign extended.
 define void @bitreverse_i32_nosext(i32 signext %a, i32* %x) nounwind {
 ; RV64IB-LABEL: bitreverse_i32_nosext:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    greviw a0, a0, 31
 ; RV64IB-NEXT:    sw a0, 0(a1)
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IP-LABEL: bitreverse_i32_nosext:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    srliw a2, a0, 8
-; RV64IP-NEXT:    lui a3, 16
-; RV64IP-NEXT:    addiw a3, a3, -256
-; RV64IP-NEXT:    and a2, a2, a3
-; RV64IP-NEXT:    srliw a3, a0, 24
-; RV64IP-NEXT:    or a2, a2, a3
-; RV64IP-NEXT:    slli a3, a0, 8
-; RV64IP-NEXT:    lui a4, 4080
-; RV64IP-NEXT:    and a3, a3, a4
-; RV64IP-NEXT:    slli a0, a0, 24
-; RV64IP-NEXT:    or a0, a0, a3
-; RV64IP-NEXT:    or a0, a0, a2
-; RV64IP-NEXT:    lui a2, 61681
-; RV64IP-NEXT:    addiw a2, a2, -241
-; RV64IP-NEXT:    and a2, a0, a2
-; RV64IP-NEXT:    slli a2, a2, 4
-; RV64IP-NEXT:    lui a3, 241
-; RV64IP-NEXT:    addiw a3, a3, -241
-; RV64IP-NEXT:    slli a3, a3, 12
-; RV64IP-NEXT:    addi a3, a3, 240
-; RV64IP-NEXT:    and a0, a0, a3
-; RV64IP-NEXT:    srli a0, a0, 4
-; RV64IP-NEXT:    or a0, a0, a2
-; RV64IP-NEXT:    lui a2, 209715
-; RV64IP-NEXT:    addiw a2, a2, 819
-; RV64IP-NEXT:    and a2, a0, a2
-; RV64IP-NEXT:    slli a2, a2, 2
-; RV64IP-NEXT:    lui a3, 838861
-; RV64IP-NEXT:    addiw a3, a3, -820
-; RV64IP-NEXT:    and a0, a0, a3
-; RV64IP-NEXT:    srli a0, a0, 2
-; RV64IP-NEXT:    or a0, a0, a2
-; RV64IP-NEXT:    lui a2, 349525
-; RV64IP-NEXT:    addiw a2, a2, 1365
-; RV64IP-NEXT:    and a2, a0, a2
-; RV64IP-NEXT:    slli a2, a2, 1
-; RV64IP-NEXT:    lui a3, 699051
-; RV64IP-NEXT:    addiw a3, a3, -1366
-; RV64IP-NEXT:    and a0, a0, a3
-; RV64IP-NEXT:    srli a0, a0, 1
-; RV64IP-NEXT:    or a0, a0, a2
+; RV64IP-NEXT:    bitrevi a0, a0, 31
 ; RV64IP-NEXT:    sw a0, 0(a1)
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: bitreverse_i32_nosext:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    srliw a2, a0, 8
-; RV64IPN-NEXT:    lui a3, 16
-; RV64IPN-NEXT:    addiw a3, a3, -256
-; RV64IPN-NEXT:    and a2, a2, a3
-; RV64IPN-NEXT:    srliw a3, a0, 24
-; RV64IPN-NEXT:    or a2, a2, a3
-; RV64IPN-NEXT:    slli a3, a0, 8
-; RV64IPN-NEXT:    lui a4, 4080
-; RV64IPN-NEXT:    and a3, a3, a4
-; RV64IPN-NEXT:    slli a0, a0, 24
-; RV64IPN-NEXT:    or a0, a0, a3
-; RV64IPN-NEXT:    or a0, a0, a2
-; RV64IPN-NEXT:    lui a2, 61681
-; RV64IPN-NEXT:    addiw a2, a2, -241
-; RV64IPN-NEXT:    and a2, a0, a2
-; RV64IPN-NEXT:    slli a2, a2, 4
-; RV64IPN-NEXT:    lui a3, 241
-; RV64IPN-NEXT:    addiw a3, a3, -241
-; RV64IPN-NEXT:    slli a3, a3, 12
-; RV64IPN-NEXT:    addi a3, a3, 240
-; RV64IPN-NEXT:    and a0, a0, a3
-; RV64IPN-NEXT:    srli a0, a0, 4
-; RV64IPN-NEXT:    or a0, a0, a2
-; RV64IPN-NEXT:    lui a2, 209715
-; RV64IPN-NEXT:    addiw a2, a2, 819
-; RV64IPN-NEXT:    and a2, a0, a2
-; RV64IPN-NEXT:    slli a2, a2, 2
-; RV64IPN-NEXT:    lui a3, 838861
-; RV64IPN-NEXT:    addiw a3, a3, -820
-; RV64IPN-NEXT:    and a0, a0, a3
-; RV64IPN-NEXT:    srli a0, a0, 2
-; RV64IPN-NEXT:    or a0, a0, a2
-; RV64IPN-NEXT:    lui a2, 349525
-; RV64IPN-NEXT:    addiw a2, a2, 1365
-; RV64IPN-NEXT:    and a2, a0, a2
-; RV64IPN-NEXT:    slli a2, a2, 1
-; RV64IPN-NEXT:    lui a3, 699051
-; RV64IPN-NEXT:    addiw a3, a3, -1366
-; RV64IPN-NEXT:    and a0, a0, a3
-; RV64IPN-NEXT:    srli a0, a0, 1
-; RV64IPN-NEXT:    or a0, a0, a2
+; RV64IPN-NEXT:    bitrevi a0, a0, 31
 ; RV64IPN-NEXT:    sw a0, 0(a1)
 ; RV64IPN-NEXT:    ret
 ;
 ; RV64IBP-LABEL: bitreverse_i32_nosext:
 ; RV64IBP:       # %bb.0:
 ; RV64IBP-NEXT:    greviw a0, a0, 31
 ; RV64IBP-NEXT:    sw a0, 0(a1)
 ; RV64IBP-NEXT:    ret
   %ret = tail call i32 @llvm.bitreverse.i32(i32 %a)
   store i32 %ret, i32* %x
   ret void
 }
 
 define i64 @bitreverse_i64(i64 %a) nounwind {
 ; RV64IB-LABEL: bitreverse_i64:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    rev a0, a0
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IP-LABEL: bitreverse_i64:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    srli a1, a0, 24
-; RV64IP-NEXT:    lui a2, 4080
-; RV64IP-NEXT:    and a1, a1, a2
-; RV64IP-NEXT:    srli a2, a0, 8
-; RV64IP-NEXT:    addi a3, zero, 255
-; RV64IP-NEXT:    slli a4, a3, 24
-; RV64IP-NEXT:    and a2, a2, a4
-; RV64IP-NEXT:    or a1, a2, a1
-; RV64IP-NEXT:    srli a2, a0, 40
-; RV64IP-NEXT:    lui a4, 16
-; RV64IP-NEXT:    addiw a4, a4, -256
-; RV64IP-NEXT:    and a2, a2, a4
-; RV64IP-NEXT:    srli a4, a0, 56
-; RV64IP-NEXT:    or a2, a2, a4
-; RV64IP-NEXT:    or a1, a1, a2
-; RV64IP-NEXT:    slli a2, a0, 8
-; RV64IP-NEXT:    slli a4, a3, 32
-; RV64IP-NEXT:    and a2, a2, a4
-; RV64IP-NEXT:    slli a4, a0, 24
-; RV64IP-NEXT:    slli a5, a3, 40
-; RV64IP-NEXT:    and a4, a4, a5
-; RV64IP-NEXT:    or a2, a4, a2
-; RV64IP-NEXT:    slli a4, a0, 40
-; RV64IP-NEXT:    slli a3, a3, 48
-; RV64IP-NEXT:    and a3, a4, a3
-; RV64IP-NEXT:    slli a0, a0, 56
-; RV64IP-NEXT:    or a0, a0, a3
-; RV64IP-NEXT:    or a0, a0, a2
-; RV64IP-NEXT:    or a0, a0, a1
-; RV64IP-NEXT:    lui a1, 3855
-; RV64IP-NEXT:    addiw a1, a1, 241
-; RV64IP-NEXT:    slli a1, a1, 12
-; RV64IP-NEXT:    addi a1, a1, -241
-; RV64IP-NEXT:    slli a1, a1, 12
-; RV64IP-NEXT:    addi a1, a1, 241
-; RV64IP-NEXT:    slli a1, a1, 12
-; RV64IP-NEXT:    addi a1, a1, -241
-; RV64IP-NEXT:    and a1, a0, a1
-; RV64IP-NEXT:    slli a1, a1, 4
-; RV64IP-NEXT:    lui a2, 1044721
-; RV64IP-NEXT:    addiw a2, a2, -241
-; RV64IP-NEXT:    slli a2, a2, 12
-; RV64IP-NEXT:    addi a2, a2, 241
-; RV64IP-NEXT:    slli a2, a2, 12
-; RV64IP-NEXT:    addi a2, a2, -241
-; RV64IP-NEXT:    slli a2, a2, 12
-; RV64IP-NEXT:    addi a2, a2, 240
-; RV64IP-NEXT:    and a0, a0, a2
-; RV64IP-NEXT:    srli a0, a0, 4
-; RV64IP-NEXT:    or a0, a0, a1
-; RV64IP-NEXT:    lui a1, 13107
-; RV64IP-NEXT:    addiw a1, a1, 819
-; RV64IP-NEXT:    slli a1, a1, 12
-; RV64IP-NEXT:    addi a1, a1, 819
-; RV64IP-NEXT:    slli a1, a1, 12
-; RV64IP-NEXT:    addi a1, a1, 819
-; RV64IP-NEXT:    slli a1, a1, 12
-; RV64IP-NEXT:    addi a1, a1, 819
-; RV64IP-NEXT:    and a1, a0, a1
-; RV64IP-NEXT:    slli a1, a1, 2
-; RV64IP-NEXT:    lui a2, 1035469
-; RV64IP-NEXT:    addiw a2, a2, -819
-; RV64IP-NEXT:    slli a2, a2, 12
-; RV64IP-NEXT:    addi a2, a2, -819
-; RV64IP-NEXT:    slli a2, a2, 12
-; RV64IP-NEXT:    addi a2, a2, -819
-; RV64IP-NEXT:    slli a2, a2, 12
-; RV64IP-NEXT:    addi a2, a2, -820
-; RV64IP-NEXT:    and a0, a0, a2
-; RV64IP-NEXT:    srli a0, a0, 2
-; RV64IP-NEXT:    or a0, a0, a1
-; RV64IP-NEXT:    lui a1, 21845
-; RV64IP-NEXT:    addiw a1, a1, 1365
-; RV64IP-NEXT:    slli a1, a1, 12
-; RV64IP-NEXT:    addi a1, a1, 1365
-; RV64IP-NEXT:    slli a1, a1, 12
-; RV64IP-NEXT:    addi a1, a1, 1365
-; RV64IP-NEXT:    slli a1, a1, 12
-; RV64IP-NEXT:    addi a1, a1, 1365
-; RV64IP-NEXT:    and a1, a0, a1
-; RV64IP-NEXT:    slli a1, a1, 1
-; RV64IP-NEXT:    lui a2, 1026731
-; RV64IP-NEXT:    addiw a2, a2, -1365
-; RV64IP-NEXT:    slli a2, a2, 12
-; RV64IP-NEXT:    addi a2, a2, -1365
-; RV64IP-NEXT:    slli a2, a2, 12
-; RV64IP-NEXT:    addi a2, a2, -1365
-; RV64IP-NEXT:    slli a2, a2, 12
-; RV64IP-NEXT:    addi a2, a2, -1366
-; RV64IP-NEXT:    and a0, a0, a2
-; RV64IP-NEXT:    srli a0, a0, 1
-; RV64IP-NEXT:    or a0, a0, a1
+; RV64IP-NEXT:    bitrevi a0, a0, 63
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: bitreverse_i64:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    srli a1, a0, 24
-; RV64IPN-NEXT:    lui a2, 4080
-; RV64IPN-NEXT:    and a1, a1, a2
-; RV64IPN-NEXT:    srli a2, a0, 8
-; RV64IPN-NEXT:    addi a3, zero, 255
-; RV64IPN-NEXT:    slli a4, a3, 24
-; RV64IPN-NEXT:    and a2, a2, a4
-; RV64IPN-NEXT:    or a1, a2, a1
-; RV64IPN-NEXT:    srli a2, a0, 40
-; RV64IPN-NEXT:    lui a4, 16
-; RV64IPN-NEXT:    addiw a4, a4, -256
-; RV64IPN-NEXT:    and a2, a2, a4
-; RV64IPN-NEXT:    srli a4, a0, 56
-; RV64IPN-NEXT:    or a2, a2, a4
-; RV64IPN-NEXT:    or a1, a1, a2
-; RV64IPN-NEXT:    slli a2, a0, 8
-; RV64IPN-NEXT:    slli a4, a3, 32
-; RV64IPN-NEXT:    and a2, a2, a4
-; RV64IPN-NEXT:    slli a4, a0, 24
-; RV64IPN-NEXT:    slli a5, a3, 40
-; RV64IPN-NEXT:    and a4, a4, a5
-; RV64IPN-NEXT:    or a2, a4, a2
-; RV64IPN-NEXT:    slli a4, a0, 40
-; RV64IPN-NEXT:    slli a3, a3, 48
-; RV64IPN-NEXT:    and a3, a4, a3
-; RV64IPN-NEXT:    slli a0, a0, 56
-; RV64IPN-NEXT:    or a0, a0, a3
-; RV64IPN-NEXT:    or a0, a0, a2
-; RV64IPN-NEXT:    or a0, a0, a1
-; RV64IPN-NEXT:    lui a1, 3855
-; RV64IPN-NEXT:    addiw a1, a1, 241
-; RV64IPN-NEXT:    slli a1, a1, 12
-; RV64IPN-NEXT:    addi a1, a1, -241
-; RV64IPN-NEXT:    slli a1, a1, 12
-; RV64IPN-NEXT:    addi a1, a1, 241
-; RV64IPN-NEXT:    slli a1, a1, 12
-; RV64IPN-NEXT:    addi a1, a1, -241
-; RV64IPN-NEXT:    and a1, a0, a1
-; RV64IPN-NEXT:    slli a1, a1, 4
-; RV64IPN-NEXT:    lui a2, 1044721
-; RV64IPN-NEXT:    addiw a2, a2, -241
-; RV64IPN-NEXT:    slli a2, a2, 12
-; RV64IPN-NEXT:    addi a2, a2, 241
-; RV64IPN-NEXT:    slli a2, a2, 12
-; RV64IPN-NEXT:    addi a2, a2, -241
-; RV64IPN-NEXT:    slli a2, a2, 12
-; RV64IPN-NEXT:    addi a2, a2, 240
-; RV64IPN-NEXT:    and a0, a0, a2
-; RV64IPN-NEXT:    srli a0, a0, 4
-; RV64IPN-NEXT:    or a0, a0, a1
-; RV64IPN-NEXT:    lui a1, 13107
-; RV64IPN-NEXT:    addiw a1, a1, 819
-; RV64IPN-NEXT:    slli a1, a1, 12
-; RV64IPN-NEXT:    addi a1, a1, 819
-; RV64IPN-NEXT:    slli a1, a1, 12
-; RV64IPN-NEXT:    addi a1, a1, 819
-; RV64IPN-NEXT:    slli a1, a1, 12
-; RV64IPN-NEXT:    addi a1, a1, 819
-; RV64IPN-NEXT:    and a1, a0, a1
-; RV64IPN-NEXT:    slli a1, a1, 2
-; RV64IPN-NEXT:    lui a2, 1035469
-; RV64IPN-NEXT:    addiw a2, a2, -819
-; RV64IPN-NEXT:    slli a2, a2, 12
-; RV64IPN-NEXT:    addi a2, a2, -819
-; RV64IPN-NEXT:    slli a2, a2, 12
-; RV64IPN-NEXT:    addi a2, a2, -819
-; RV64IPN-NEXT:    slli a2, a2, 12
-; RV64IPN-NEXT:    addi a2, a2, -820
-; RV64IPN-NEXT:    and a0, a0, a2
-; RV64IPN-NEXT:    srli a0, a0, 2
-; RV64IPN-NEXT:    or a0, a0, a1
-; RV64IPN-NEXT:    lui a1, 21845
-; RV64IPN-NEXT:    addiw a1, a1, 1365
-; RV64IPN-NEXT:    slli a1, a1, 12
-; RV64IPN-NEXT:    addi a1, a1, 1365
-; RV64IPN-NEXT:    slli a1, a1, 12
-; RV64IPN-NEXT:    addi a1, a1, 1365
-; RV64IPN-NEXT:    slli a1, a1, 12
-; RV64IPN-NEXT:    addi a1, a1, 1365
-; RV64IPN-NEXT:    and a1, a0, a1
-; RV64IPN-NEXT:    slli a1, a1, 1
-; RV64IPN-NEXT:    lui a2, 1026731
-; RV64IPN-NEXT:    addiw a2, a2, -1365
-; RV64IPN-NEXT:    slli a2, a2, 12
-; RV64IPN-NEXT:    addi a2, a2, -1365
-; RV64IPN-NEXT:    slli a2, a2, 12
-; RV64IPN-NEXT:    addi a2, a2, -1365
-; RV64IPN-NEXT:    slli a2, a2, 12
-; RV64IPN-NEXT:    addi a2, a2, -1366
-; RV64IPN-NEXT:    and a0, a0, a2
-; RV64IPN-NEXT:    srli a0, a0, 1
-; RV64IPN-NEXT:    or a0, a0, a1
+; RV64IPN-NEXT:    bitrevi a0, a0, 63
 ; RV64IPN-NEXT:    ret
 ;
 ; RV64IBP-LABEL: bitreverse_i64:
 ; RV64IBP:       # %bb.0:
 ; RV64IBP-NEXT:    rev a0, a0
 ; RV64IBP-NEXT:    ret
   %ret = tail call i64 @llvm.bitreverse.i64(i64 %a)
   ret i64 %ret
 }

llvm/test/CodeGen/RISCV/rv64zpn-bswap.ll

 define zeroext i16 @bswap_i16(i16 zeroext %a) nounwind {
 ; RV64IB-LABEL: bswap_i16:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    greviw a0, a0, 8
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IP-LABEL: bswap_i16:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    srli a1, a0, 8
-; RV64IP-NEXT:    slli a0, a0, 8
-; RV64IP-NEXT:    or a0, a0, a1
-; RV64IP-NEXT:    lui a1, 16
-; RV64IP-NEXT:    addiw a1, a1, -1
-; RV64IP-NEXT:    and a0, a0, a1
+; RV64IP-NEXT:    swap8 a0, a0
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: bswap_i16:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    srli a1, a0, 8
-; RV64IPN-NEXT:    slli a0, a0, 8
-; RV64IPN-NEXT:    or a0, a0, a1
-; RV64IPN-NEXT:    lui a1, 16
-; RV64IPN-NEXT:    addiw a1, a1, -1
-; RV64IPN-NEXT:    and a0, a0, a1
+; RV64IPN-NEXT:    swap8 a0, a0
 ; RV64IPN-NEXT:    ret
 ;
 ; RV64IBP-LABEL: bswap_i16:
 ; RV64IBP:       # %bb.0:
 ; RV64IBP-NEXT:    greviw a0, a0, 8
 ; RV64IBP-NEXT:    ret
   %ret = tail call i16 @llvm.bswap.i16(i16 %a)
   ret i16 %ret
 }
 
 define signext i32 @bswap_i32(i32 signext %a) nounwind {
 ; RV64IB-LABEL: bswap_i32:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    greviw a0, a0, 24
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IP-LABEL: bswap_i32:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    srliw a1, a0, 8
-; RV64IP-NEXT:    lui a2, 16
-; RV64IP-NEXT:    addiw a2, a2, -256
-; RV64IP-NEXT:    and a1, a1, a2
-; RV64IP-NEXT:    srliw a2, a0, 24
-; RV64IP-NEXT:    or a1, a1, a2
-; RV64IP-NEXT:    slli a2, a0, 8
-; RV64IP-NEXT:    lui a3, 4080
-; RV64IP-NEXT:    and a2, a2, a3
-; RV64IP-NEXT:    slli a0, a0, 24
-; RV64IP-NEXT:    or a0, a0, a2
-; RV64IP-NEXT:    or a0, a0, a1
+; RV64IP-NEXT:    swap8 a0, a0
+; RV64IP-NEXT:    swap16 a0, a0
 ; RV64IP-NEXT:    sext.w a0, a0
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: bswap_i32:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    srliw a1, a0, 8
-; RV64IPN-NEXT:    lui a2, 16
-; RV64IPN-NEXT:    addiw a2, a2, -256
-; RV64IPN-NEXT:    and a1, a1, a2
-; RV64IPN-NEXT:    srliw a2, a0, 24
-; RV64IPN-NEXT:    or a1, a1, a2
-; RV64IPN-NEXT:    slli a2, a0, 8
-; RV64IPN-NEXT:    lui a3, 4080
-; RV64IPN-NEXT:    and a2, a2, a3
-; RV64IPN-NEXT:    slli a0, a0, 24
-; RV64IPN-NEXT:    or a0, a0, a2
-; RV64IPN-NEXT:    or a0, a0, a1
+; RV64IPN-NEXT:    swap8 a0, a0
+; RV64IPN-NEXT:    swap16 a0, a0
 ; RV64IPN-NEXT:    sext.w a0, a0
 ; RV64IPN-NEXT:    ret
 ;
 ; RV64IBP-LABEL: bswap_i32:
 ; RV64IBP:       # %bb.0:
 ; RV64IBP-NEXT:    greviw a0, a0, 24
 ; RV64IBP-NEXT:    ret
   %ret = tail call i32 @llvm.bswap.i32(i32 %a)
   ret i32 %ret
 }
 
 ; Similar to bswap_i32 but the result is not sign extended.
 define void @bswap_i32_nosext(i32 signext %a, i32* %x) nounwind {
 ; RV64IB-LABEL: bswap_i32_nosext:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    greviw a0, a0, 24
 ; RV64IB-NEXT:    sw a0, 0(a1)
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IP-LABEL: bswap_i32_nosext:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    srliw a2, a0, 8
-; RV64IP-NEXT:    lui a3, 16
-; RV64IP-NEXT:    addiw a3, a3, -256
-; RV64IP-NEXT:    and a2, a2, a3
-; RV64IP-NEXT:    srliw a3, a0, 24
-; RV64IP-NEXT:    or a2, a2, a3
-; RV64IP-NEXT:    slli a3, a0, 8
-; RV64IP-NEXT:    lui a4, 4080
-; RV64IP-NEXT:    and a3, a3, a4
-; RV64IP-NEXT:    slli a0, a0, 24
-; RV64IP-NEXT:    or a0, a0, a3
-; RV64IP-NEXT:    or a0, a0, a2
+; RV64IP-NEXT:    swap8 a0, a0
+; RV64IP-NEXT:    swap16 a0, a0
 ; RV64IP-NEXT:    sw a0, 0(a1)
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: bswap_i32_nosext:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    srliw a2, a0, 8
-; RV64IPN-NEXT:    lui a3, 16
-; RV64IPN-NEXT:    addiw a3, a3, -256
-; RV64IPN-NEXT:    and a2, a2, a3
-; RV64IPN-NEXT:    srliw a3, a0, 24
-; RV64IPN-NEXT:    or a2, a2, a3
-; RV64IPN-NEXT:    slli a3, a0, 8
-; RV64IPN-NEXT:    lui a4, 4080
-; RV64IPN-NEXT:    and a3, a3, a4
-; RV64IPN-NEXT:    slli a0, a0, 24
-; RV64IPN-NEXT:    or a0, a0, a3
-; RV64IPN-NEXT:    or a0, a0, a2
+; RV64IPN-NEXT:    swap8 a0, a0
+; RV64IPN-NEXT:    swap16 a0, a0
 ; RV64IPN-NEXT:    sw a0, 0(a1)
 ; RV64IPN-NEXT:    ret
 ;
 ; RV64IBP-LABEL: bswap_i32_nosext:
 ; RV64IBP:       # %bb.0:
 ; RV64IBP-NEXT:    greviw a0, a0, 24
 ; RV64IBP-NEXT:    sw a0, 0(a1)
 ; RV64IBP-NEXT:    ret
   %ret = tail call i32 @llvm.bswap.i32(i32 %a)
   store i32 %ret, i32* %x
   ret void
 }
 
 define i64 @bswap_i64(i64 %a) nounwind {
 ; RV64IB-LABEL: bswap_i64:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    rev8 a0, a0
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IP-LABEL: bswap_i64:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    srli a1, a0, 24
-; RV64IP-NEXT:    lui a2, 4080
-; RV64IP-NEXT:    and a1, a1, a2
-; RV64IP-NEXT:    srli a2, a0, 8
-; RV64IP-NEXT:    addi a3, zero, 255
-; RV64IP-NEXT:    slli a4, a3, 24
-; RV64IP-NEXT:    and a2, a2, a4
-; RV64IP-NEXT:    or a1, a2, a1
-; RV64IP-NEXT:    srli a2, a0, 40
-; RV64IP-NEXT:    lui a4, 16
-; RV64IP-NEXT:    addiw a4, a4, -256
-; RV64IP-NEXT:    and a2, a2, a4
-; RV64IP-NEXT:    srli a4, a0, 56
-; RV64IP-NEXT:    or a2, a2, a4
-; RV64IP-NEXT:    or a1, a1, a2
-; RV64IP-NEXT:    slli a2, a0, 8
-; RV64IP-NEXT:    slli a4, a3, 32
-; RV64IP-NEXT:    and a2, a2, a4
-; RV64IP-NEXT:    slli a4, a0, 24
-; RV64IP-NEXT:    slli a5, a3, 40
-; RV64IP-NEXT:    and a4, a4, a5
-; RV64IP-NEXT:    or a2, a4, a2
-; RV64IP-NEXT:    slli a4, a0, 40
-; RV64IP-NEXT:    slli a3, a3, 48
-; RV64IP-NEXT:    and a3, a4, a3
-; RV64IP-NEXT:    slli a0, a0, 56
-; RV64IP-NEXT:    or a0, a0, a3
-; RV64IP-NEXT:    or a0, a0, a2
-; RV64IP-NEXT:    or a0, a0, a1
+; RV64IP-NEXT:    swap8 a0, a0
+; RV64IP-NEXT:    swap16 a0, a0
+; RV64IP-NEXT:    pkbt32 a0, a0, a0
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: bswap_i64:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    srli a1, a0, 24
-; RV64IPN-NEXT:    lui a2, 4080
-; RV64IPN-NEXT:    and a1, a1, a2
-; RV64IPN-NEXT:    srli a2, a0, 8
-; RV64IPN-NEXT:    addi a3, zero, 255
-; RV64IPN-NEXT:    slli a4, a3, 24
-; RV64IPN-NEXT:    and a2, a2, a4
-; RV64IPN-NEXT:    or a1, a2, a1
-; RV64IPN-NEXT:    srli a2, a0, 40
-; RV64IPN-NEXT:    lui a4, 16
-; RV64IPN-NEXT:    addiw a4, a4, -256
-; RV64IPN-NEXT:    and a2, a2, a4
-; RV64IPN-NEXT:    srli a4, a0, 56
-; RV64IPN-NEXT:    or a2, a2, a4
-; RV64IPN-NEXT:    or a1, a1, a2
-; RV64IPN-NEXT:    slli a2, a0, 8
-; RV64IPN-NEXT:    slli a4, a3, 32
-; RV64IPN-NEXT:    and a2, a2, a4
-; RV64IPN-NEXT:    slli a4, a0, 24
-; RV64IPN-NEXT:    slli a5, a3, 40
-; RV64IPN-NEXT:    and a4, a4, a5
-; RV64IPN-NEXT:    or a2, a4, a2
-; RV64IPN-NEXT:    slli a4, a0, 40
-; RV64IPN-NEXT:    slli a3, a3, 48
-; RV64IPN-NEXT:    and a3, a4, a3
-; RV64IPN-NEXT:    slli a0, a0, 56
-; RV64IPN-NEXT:    or a0, a0, a3
-; RV64IPN-NEXT:    or a0, a0, a2
-; RV64IPN-NEXT:    or a0, a0, a1
+; RV64IPN-NEXT:    swap8 a0, a0
+; RV64IPN-NEXT:    swap16 a0, a0
+; RV64IPN-NEXT:    pkbt32 a0, a0, a0
 ; RV64IPN-NEXT:    ret
 ;
 ; RV64IBP-LABEL: bswap_i64:
 ; RV64IBP:       # %bb.0:
 ; RV64IBP-NEXT:    rev8 a0, a0
 ; RV64IBP-NEXT:    ret
   %ret = tail call i64 @llvm.bswap.i64(i64 %a)
   ret i64 %ret
 }