[RISCV] Support RVP vectors in the calling convention

[Jim]

Summary

Vectors in RVP are passed via GPRs. It can reuse the same
allocation rules as XLen to pass via registers or via the stack.

[jrtc27]

Is this the right place to do it, or should it be done in Clang with bitcasts to/from integers?

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

6800

Unnecessary parens

[frasercrmck]

In D102466#2759440, @jrtc27 wrote:

Is this the right place to do it, or should it be done in Clang with bitcasts to/from integers?

Personally, I think it's okay to do this here as it's likely we'll have the vector types in IR when coming from ABIs like SPIR or SPIR-V. At least, that was the justification for the V vectors. I know what you mean, though. I don't know if the authors anticipate a similar use-case for the P extension.

[frasercrmck]

As mentioned, I think this patch is missing test cases for vector types smaller or larger than XLEN.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

6803

Can this else ever fall through with P? What if you passed <4 x i64>? Should P ensure that vectors are correctly broken down into XLen-sized part vectors?

[Jim]

I did the experiments that vector type arguments have been passed as XLenVT. And it is bitcasted back to vector type before using.

typedef signed char int8x4_t __attribute((vector_size(4))); 

int8x4_t foo1(int8x4_t a, int8x4_t b) { 
  return a + b;
}

And its dag looks like:

t4: i32,ch = CopyFromReg t0, Register:i32 %1
t6: v4i8 = bitcast t4
t2: i32,ch = CopyFromReg t0, Register:i32 %0 
t5: v4i8 = bitcast t2
t7: v4i8 = add t6, t5

It is my mistake. This patch is unneeded. How do you think? @frasercrmck

[frasercrmck]

In D102466#2770479, @Jim wrote:

I did the experiments that vector type arguments have been passed as XLenVT. And it is bitcasted back to vector type before using.

typedef signed char int8x4_t __attribute((vector_size(4))); 

int8x4_t foo1(int8x4_t a, int8x4_t b) { 
  return a + b;
}

And its dag looks like:

t4: i32,ch = CopyFromReg t0, Register:i32 %1
t6: v4i8 = bitcast t4
t2: i32,ch = CopyFromReg t0, Register:i32 %0 
t5: v4i8 = bitcast t2
t7: v4i8 = add t6, t5

It is my mistake. This patch is unneeded. How do you think? @frasercrmck

Sure, if this XLenVT use-case works better for you then I don't see a point in adding unused code. We can revisit if there's another reason to support vectors directly in IR.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (UseGPRForF16_F32 && (ValVT == MVT::f16 || ValVT == MVT::f32)) {
     LocInfo = CCValAssign::BCvt;
   } else if (UseGPRForF64 && XLen == 64 && ValVT == MVT::f64) {
     LocVT = MVT::i64;
     LocInfo = CCValAssign::BCvt;
   }
 
   // If this is a variadic argument, the RISC-V calling convention requires
   // that it is assigned an 'even' or 'aligned' register if it has 8-byte
   // alignment (RV32) or 16-byte alignment (RV64). An aligned register should
   // be used regardless of whether the original argument was split during
   // legalisation or not. The argument will not be passed by registers if the
   // original type is larger than 2*XLEN, so the register alignment rule does
   // not apply.
   unsigned TwoXLenInBytes = (2 * XLen) / 8;
   if (!IsFixed && ArgFlags.getNonZeroOrigAlign() == TwoXLenInBytes &&
       DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) {
     unsigned RegIdx = State.getFirstUnallocated(ArgGPRs);
if (!Reg) {
       return false;
     }
     if (!State.AllocateReg(ArgGPRs))
       State.AllocateStack(4, Align(4));
     State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
     return false;
   }
 
+  if (ValVT.isFixedLengthVector()) {
+    // Pass vectors with the same size as XLen by GPRs for RVP.
+    if (TLI.getSubtarget().hasStdExtP() && (XLen == ValVT.getSizeInBits())) {
+      LocVT = XLenVT;
+      LocInfo = CCValAssign::BCvt;
+    } else {
       // Fixed-length vectors are located in the corresponding scalable-vector
       // container types.
-  if (ValVT.isFixedLengthVector())
       LocVT = TLI.getContainerForFixedLengthVector(LocVT);
+    }
+  }
 
   // Split arguments might be passed indirectly, so keep track of the pending
   // values. Split vectors are passed via a mix of registers and indirectly, so
   // treat them as we would any other argument.
   if (!LocVT.isVector() && (ArgFlags.isSplit() || !PendingLocs.empty())) {
     LocVT = XLenVT;
     LocInfo = CCValAssign::Indirect;
     PendingLocs.push_back(
static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
   // Allocate to a register if possible, or else a stack slot.
   Register Reg;
   if (ValVT == MVT::f16 && !UseGPRForF16_F32)
     Reg = State.AllocateReg(ArgFPR16s);
   else if (ValVT == MVT::f32 && !UseGPRForF16_F32)
     Reg = State.AllocateReg(ArgFPR32s);
   else if (ValVT == MVT::f64 && !UseGPRForF64)
     Reg = State.AllocateReg(ArgFPR64s);
-  else if (ValVT.isVector()) {
+  else if (ValVT.isVector() && LocVT.isVector()) {
     const TargetRegisterClass *RC = TLI.getRegClassFor(ValVT);
     if (RC == &RISCV::VRRegClass) {
       // Assign the first mask argument to V0.
       // This is an interim calling convention and it may be changed in the
       // future.
       if (FirstMaskArgument.hasValue() &&
           ValNo == FirstMaskArgument.getValue()) {
         Reg = State.AllocateReg(RISCV::V0);

llvm/test/CodeGen/RISCV/rvp/calling-conv-rv32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-p -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-p,+f -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-p,+d -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+define <4 x i8> @ret_v4i8(<4 x i8>* %p) nounwind {
+; CHECK-LABEL: ret_v4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lw a0, 0(a0)
+; CHECK-NEXT:    ret
+  %v = load <4 x i8>, <4 x i8>* %p
+  ret <4 x i8> %v
+}
+
+define <4 x i8> @param_v4i8(<4 x i8> %a, <4 x i8> %b) nounwind {
+; CHECK-LABEL: param_v4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    and a0, a0, a1
+; CHECK-NEXT:    ret
+  %r = and <4 x i8> %a, %b
+  ret <4 x i8> %r
+}
+
+define <2 x i16> @ret_v2i16(<2 x i16>* %p) nounwind {
+; CHECK-LABEL: ret_v2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lw a0, 0(a0)
+; CHECK-NEXT:    ret
+  %v = load <2 x i16>, <2 x i16>* %p
+  ret <2 x i16> %v
+}
+
+define <2 x i16> @param_v2i16(<2 x i16> %a, <2 x i16> %b) nounwind {
+; CHECK-LABEL: param_v2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    and a0, a0, a1
+; CHECK-NEXT:    ret
+  %r = and <2 x i16> %a, %b
+  ret <2 x i16> %r
+}
+
+declare <4 x i8> @callee_v4i8(<4 x i8>, <4 x i8>)
+
+define <4 x i8> @call_v4i8(<4 x i8> %a, <4 x i8> %b) nounwind {
+; CHECK-LABEL: call_v4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    mv a2, a0
+; CHECK-NEXT:    mv a0, a1
+; CHECK-NEXT:    mv a1, a2
+; CHECK-NEXT:    call callee_v4i8@plt
+; CHECK-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  %r = call <4 x i8> @callee_v4i8(<4 x i8> %b, <4 x i8> %a)
+  ret <4 x i8> %r
+}
+
+declare <2 x i16> @callee_v2i16(<2 x i16>, <2 x i16>)
+
+define <2 x i16> @call_v2i16(<2 x i16> %a, <2 x i16> %b) nounwind {
+; CHECK-LABEL: call_v2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    mv a2, a0
+; CHECK-NEXT:    mv a0, a1
+; CHECK-NEXT:    mv a1, a2
+; CHECK-NEXT:    call callee_v2i16@plt
+; CHECK-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  %r = call <2 x i16> @callee_v2i16(<2 x i16> %b, <2 x i16> %a)
+  ret <2 x i16> %r
+}

llvm/test/CodeGen/RISCV/rvp/calling-conv-rv64.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-p,+f -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-p,+d -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+define <8 x i8> @ret_v8i8(<8 x i8>* %p) nounwind {
+; CHECK-LABEL: ret_v8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ld a0, 0(a0)
+; CHECK-NEXT:    ret
+  %v = load <8 x i8>, <8 x i8>* %p
+  ret <8 x i8> %v
+}
+
+define <8 x i8> @param_v8i8(<8 x i8> %a, <8 x i8> %b) nounwind {
+; CHECK-LABEL: param_v8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    and a0, a0, a1
+; CHECK-NEXT:    ret
+  %r = and <8 x i8> %a, %b
+  ret <8 x i8> %r
+}
+
+define <4 x i16> @ret_v4i16(<4 x i16>* %p) nounwind {
+; CHECK-LABEL: ret_v4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ld a0, 0(a0)
+; CHECK-NEXT:    ret
+  %v = load <4 x i16>, <4 x i16>* %p
+  ret <4 x i16> %v
+}
+
+define <4 x i16> @param_v4i16(<4 x i16> %a, <4 x i16> %b) nounwind {
+; CHECK-LABEL: param_v4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    and a0, a0, a1
+; CHECK-NEXT:    ret
+  %r = and <4 x i16> %a, %b
+  ret <4 x i16> %r
+}
+
+define <2 x i32> @ret_v2i32(<2 x i32>* %p) nounwind {
+; CHECK-LABEL: ret_v2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ld a0, 0(a0)
+; CHECK-NEXT:    ret
+  %v = load <2 x i32>, <2 x i32>* %p
+  ret <2 x i32> %v
+}
+
+define <2 x i32> @param_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
+; CHECK-LABEL: param_v2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    and a0, a0, a1
+; CHECK-NEXT:    ret
+  %r = and <2 x i32> %a, %b
+  ret <2 x i32> %r
+}
+
+declare <8 x i8> @callee_v8i8(<8 x i8>, <8 x i8>)
+
+define <8 x i8> @call_v8i8(<8 x i8> %a, <8 x i8> %b) nounwind {
+; CHECK-LABEL: call_v8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    mv a2, a0
+; CHECK-NEXT:    mv a0, a1
+; CHECK-NEXT:    mv a1, a2
+; CHECK-NEXT:    call callee_v8i8@plt
+; CHECK-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  %r = call <8 x i8> @callee_v8i8(<8 x i8> %b, <8 x i8> %a)
+  ret <8 x i8> %r
+}
+
+declare <4 x i16> @callee_v4i16(<4 x i16>, <4 x i16>)
+
+define <4 x i16> @call_v4i16(<4 x i16> %a, <4 x i16> %b) nounwind {
+; CHECK-LABEL: call_v4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    mv a2, a0
+; CHECK-NEXT:    mv a0, a1
+; CHECK-NEXT:    mv a1, a2
+; CHECK-NEXT:    call callee_v4i16@plt
+; CHECK-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  %r = call <4 x i16> @callee_v4i16(<4 x i16> %b, <4 x i16> %a)
+  ret <4 x i16> %r
+}
+
+declare <2 x i32> @callee_v2i32(<2 x i32>, <2 x i32>)
+
+define <2 x i32> @call_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
+; CHECK-LABEL: call_v2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    mv a2, a0
+; CHECK-NEXT:    mv a0, a1
+; CHECK-NEXT:    mv a1, a2
+; CHECK-NEXT:    call callee_v2i32@plt
+; CHECK-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  %r = call <2 x i32> @callee_v2i32(<2 x i32> %b, <2 x i32> %a)
+  ret <2 x i32> %r
+}