[RISCV] Prevent __builtin_riscv_orc_b_64 from being compiled RV32 target.

[craig.topper]

Summary

The backend can't handle this and will throw a fatal error from
type legalization. It's easy enough to fix that for this intrinsic
by just splitting the IR intrinsic since it works on individual bytes.

There will be other intrinsics in the future that would be harder
to support through splitting, for example grev, gorc, and shfl. Those
would require a compare and a select be inserted to check the MSB of
their control input.

This patch adds support for preventing this in the frontend with
a nice diagnostic.

[frasercrmck]

clang/lib/Basic/Targets/RISCV.cpp

259

What's the difference between this new feature and riscv64 above?

[craig.topper]

clang/lib/Basic/Targets/RISCV.cpp

259

The name I added to initFeatureMap has to match the feature name in RISCV.td because it will end up in the target-features attribute in IR.

SemaChecking just calls hasFeature, but CodeGenFunction also checks builtin features using the feature map. We check features in SemaChecking because the CodeGenFunction diagnostic isn’t phrased well for RISCV.

[frasercrmck]

clang/lib/Basic/Targets/RISCV.cpp

259

Ah I see, so since it has to match our "64bit" SubtargetFeature we can't reuse "riscv64"? Thanks.

[craig.topper]

clang/lib/Basic/Targets/RISCV.cpp

259

Correct.

clang/include/clang/Basic/BuiltinsRISCV.def

 #if defined(BUILTIN) && !defined(TARGET_BUILTIN)
 #   define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
 #endif
 
 #include "clang/Basic/riscv_vector_builtins.inc"
 
 // Zbb extension
 TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "experimental-zbb")
-TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "experimental-zbb")
+TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "experimental-zbb,64bit")
 
 // Zbc extension
 TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "experimental-zbc")
 TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "experimental-zbc")
 TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "experimental-zbc")
 
 // Zbr extension
 TARGET_BUILTIN(__builtin_riscv_crc32_b, "LiLi", "nc", "experimental-zbr")

clang/lib/Basic/Targets/RISCV.h

 //===--- RISCV.h - Declare RISCV target feature support ---------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
public:
 
   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
 
   bool validateAsmConstraint(const char *&Name,
                              TargetInfo::ConstraintInfo &Info) const override;
 
   std::string convertConstraint(const char *&Constraint) const override;
 
+  bool
+  initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
+                 StringRef CPU,
+                 const std::vector<std::string> &FeaturesVec) const override;
+
   bool hasFeature(StringRef Feature) const override;
 
   bool handleTargetFeatures(std::vector<std::string> &Features,
                             DiagnosticsEngine &Diags) override;
 
   bool hasExtIntType() const override { return true; }
 };
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {

clang/lib/Basic/Targets/RISCV.cpp

 //===--- RISCV.cpp - Implement RISCV target feature support ---------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 #include "clang/Basic/BuiltinsRISCV.def"
 };
 
 ArrayRef<Builtin::Info> RISCVTargetInfo::getTargetBuiltins() const {
   return llvm::makeArrayRef(BuiltinInfo, clang::RISCV::LastTSBuiltin -
                                              Builtin::FirstTSBuiltin);
 }
 
+bool RISCVTargetInfo::initFeatureMap(
+    llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
+    const std::vector<std::string> &FeaturesVec) const {
+
+  if (getTriple().getArch() == llvm::Triple::riscv64)
+    Features["64bit"] = true;
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+}
+
 /// Return true if has this feature, need to sync with handleTargetFeatures.
 bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
   bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
   return llvm::StringSwitch<bool>(Feature)
       .Case("riscv", true)
       .Case("riscv32", !Is64Bit)
       .Case("riscv64", Is64Bit)
+      .Case("64bit", Is64Bit)
       .Case("m", HasM)
       .Case("a", HasA)
       .Case("f", HasF)
       .Case("d", HasD)
       .Case("c", HasC)
       .Case("experimental-b", HasB)
       .Case("experimental-v", HasV)
       .Case("experimental-zba", HasZba)

clang/lib/Sema/SemaChecking.cpp

 //===- SemaChecking.cpp - Extra Semantic Checking -------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
   // CodeGenFunction can also detect this, but this gives a better error
   // message.
   bool FeatureMissing = false;
   SmallVector<StringRef> ReqFeatures;
   StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
   Features.split(ReqFeatures, ',');
 
   // Check if each required feature is included
-  for (auto &I : ReqFeatures) {
-    if (TI.hasFeature(I))
+  for (StringRef F : ReqFeatures) {
+    if (TI.hasFeature(F))
       continue;
+
+    // If the feature is 64bit, alter the string so it will print better in
+    // the diagnostic.
+    if (F == "64bit")
+      F = "RV64";
+
     // Convert features like "zbr" and "experimental-zbr" to "Zbr".
-    I.consume_front("experimental-");
-    std::string FeatureStr = I.str();
+    F.consume_front("experimental-");
+    std::string FeatureStr = F.str();
     FeatureStr[0] = std::toupper(FeatureStr[0]);
 
     // Error message
     FeatureMissing = true;
     Diag(TheCall->getBeginLoc(), diag::err_riscv_builtin_requires_extension)
         << TheCall->getSourceRange() << StringRef(FeatureStr);
   }
 

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbb -verify %s -o -
+
+int orc_b_64(int a) {
+  return __builtin_riscv_orc_b_64(a); // expected-error {{builtin requires 'RV64' extension support to be enabled}}
+}