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Differential D96934

[RISCV] Add support for fixed vector MULHU/MULHS.
ClosedPublic

Authored by craig.topper on Feb 17 2021, 9:33 PM.

Details

Reviewers
frasercrmck
evandro
HsiangKai
rogfer01
khchen
arcbbb
Commits
rG156fc07e19ae: [RISCV] Add support for fixed vector MULHU/MULHS.
Summary

This uses to division by constant optimization to use MULHU/MULHS.

Diff Detail

Unit TestsFailed

TimeTest
440 msx64 debian > LLVM.CodeGen/RISCV/rvv::fixed-vectors-int.ll
250 msx64 windows > LLVM.CodeGen/RISCV/rvv::fixed-vectors-int.ll

Event Timeline

craig.topper created this revision.Feb 17 2021, 9:33 PM
Herald added subscribers: StephenFan, vkmr, luismarques and 23 others. · View Herald TranscriptFeb 17 2021, 9:33 PM
craig.topper requested review of this revision.Feb 17 2021, 9:33 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 17 2021, 9:33 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B89672: Diff 324520.Feb 17 2021, 11:08 PM
arcbbb accepted this revision.Feb 18 2021, 1:09 AM

LGTM

This revision is now accepted and ready to land.Feb 18 2021, 1:09 AM
frasercrmck added a comment.Feb 18 2021, 1:14 AM

The test report suggests that something's failing? Does one of these tests depend on D96921?

LLVM ERROR: Cannot select: t51: nxv1i64 = bitcast t69
  t69: nxv2i32,ch = RISCVISD::VLE_VL<(load 16 from constant-pool)> t0, t75, Constant:i32<4>
craig.topper added a comment.Feb 18 2021, 1:33 AM
In D96934#2570919, @frasercrmck wrote:

The test report suggests that something's failing? Does one of these tests depend on D96921?

LLVM ERROR: Cannot select: t51: nxv1i64 = bitcast t69
  t69: nxv2i32,ch = RISCVISD::VLE_VL<(load 16 from constant-pool)> t0, t75, Constant:i32<4>

Yes I forgot to set the parent revision

craig.topper added a parent revision: D96921: [RISCV] Support isel of scalable vector bitcasts.Feb 18 2021, 1:33 AM
frasercrmck accepted this revision.Feb 18 2021, 1:38 AM
In D96934#2570949, @craig.topper wrote:

Yes I forgot to set the parent revision

No worries. LGTM.

This revision was landed with ongoing or failed builds.Feb 18 2021, 9:15 AM
Closed by commit rG156fc07e19ae: [RISCV] Add support for fixed vector MULHU/MULHS. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG156fc07e19ae: [RISCV] Add support for fixed vector MULHU/MULHS..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
2 lines
9 lines
4 lines
test/
CodeGen/
RISCV/
rvv/
1010 lines

Diff 324520

llvm/lib/Target/RISCV/RISCVISelLowering.h

//===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===// //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
Lint: Lint
Inline Actions

clang-format not found in user's PATH; not linting file.

Lint: Lint: clang-format not found in user's PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 156 Lines • ▼ Show 20 Linesenum NodeType : unsigned {
FNEG_VL, FNEG_VL,
FABS_VL, FABS_VL,
FSQRT_VL, FSQRT_VL,
FMA_VL, FMA_VL,
SMIN_VL, SMIN_VL,
SMAX_VL, SMAX_VL,
UMIN_VL, UMIN_VL,
UMAX_VL, UMAX_VL,
MULHS_VL,
MULHU_VL,
// Vector compare producing a mask. Fourth operand is input mask. Fifth // Vector compare producing a mask. Fourth operand is input mask. Fifth
// operand is VL. // operand is VL.
SETCC_VL, SETCC_VL,
// Vector select with an additional VL operand. This operation is unmasked. // Vector select with an additional VL operand. This operation is unmasked.
VSELECT_VL, VSELECT_VL,
▲ Show 20 Lines • Show All 275 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

//===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===// //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===//
Lint: Lint
Inline Actions

clang-format not found in user's PATH; not linting file.

Lint: Lint: clang-format not found in user's PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 545 Lines • ▼ Show 20 Lines if (Subtarget.useRVVForFixedLengthVectors()) {
setOperationAction(ISD::SRA, VT, Custom); setOperationAction(ISD::SRA, VT, Custom);
setOperationAction(ISD::SRL, VT, Custom); setOperationAction(ISD::SRL, VT, Custom);
setOperationAction(ISD::SMIN, VT, Custom); setOperationAction(ISD::SMIN, VT, Custom);
setOperationAction(ISD::SMAX, VT, Custom); setOperationAction(ISD::SMAX, VT, Custom);
setOperationAction(ISD::UMIN, VT, Custom); setOperationAction(ISD::UMIN, VT, Custom);
setOperationAction(ISD::UMAX, VT, Custom); setOperationAction(ISD::UMAX, VT, Custom);
setOperationAction(ISD::MULHS, VT, Custom);
setOperationAction(ISD::MULHU, VT, Custom);
setOperationAction(ISD::VSELECT, VT, Custom); setOperationAction(ISD::VSELECT, VT, Custom);
} }
for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) { for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) {
if (!useRVVForFixedLengthVectorVT(VT)) if (!useRVVForFixedLengthVectorVT(VT))
continue; continue;
// By default everything must be expanded. // By default everything must be expanded.
▲ Show 20 Lines • Show All 640 Lines • ▼ Show 20 LinesSDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::SETCC: case ISD::SETCC:
return lowerFixedLengthVectorSetccToRVV(Op, DAG); return lowerFixedLengthVectorSetccToRVV(Op, DAG);
case ISD::ADD: case ISD::ADD:
return lowerToScalableOp(Op, DAG, RISCVISD::ADD_VL); return lowerToScalableOp(Op, DAG, RISCVISD::ADD_VL);
case ISD::SUB: case ISD::SUB:
return lowerToScalableOp(Op, DAG, RISCVISD::SUB_VL); return lowerToScalableOp(Op, DAG, RISCVISD::SUB_VL);
case ISD::MUL: case ISD::MUL:
return lowerToScalableOp(Op, DAG, RISCVISD::MUL_VL); return lowerToScalableOp(Op, DAG, RISCVISD::MUL_VL);
case ISD::MULHS:
return lowerToScalableOp(Op, DAG, RISCVISD::MULHS_VL);
case ISD::MULHU:
return lowerToScalableOp(Op, DAG, RISCVISD::MULHU_VL);
case ISD::AND: case ISD::AND:
return lowerFixedLengthVectorLogicOpToRVV(Op, DAG, RISCVISD::VMAND_VL, return lowerFixedLengthVectorLogicOpToRVV(Op, DAG, RISCVISD::VMAND_VL,
RISCVISD::AND_VL); RISCVISD::AND_VL);
case ISD::OR: case ISD::OR:
return lowerFixedLengthVectorLogicOpToRVV(Op, DAG, RISCVISD::VMOR_VL, return lowerFixedLengthVectorLogicOpToRVV(Op, DAG, RISCVISD::VMOR_VL,
RISCVISD::OR_VL); RISCVISD::OR_VL);
case ISD::XOR: case ISD::XOR:
return lowerFixedLengthVectorLogicOpToRVV(Op, DAG, RISCVISD::VMXOR_VL, return lowerFixedLengthVectorLogicOpToRVV(Op, DAG, RISCVISD::VMXOR_VL,
▲ Show 20 Lines • Show All 3,712 Lines • ▼ Show 20 Lines#define NODE_NAME_CASE(NODE) \
NODE_NAME_CASE(FNEG_VL) NODE_NAME_CASE(FNEG_VL)
NODE_NAME_CASE(FABS_VL) NODE_NAME_CASE(FABS_VL)
NODE_NAME_CASE(FSQRT_VL) NODE_NAME_CASE(FSQRT_VL)
NODE_NAME_CASE(FMA_VL) NODE_NAME_CASE(FMA_VL)
NODE_NAME_CASE(SMIN_VL) NODE_NAME_CASE(SMIN_VL)
NODE_NAME_CASE(SMAX_VL) NODE_NAME_CASE(SMAX_VL)
NODE_NAME_CASE(UMIN_VL) NODE_NAME_CASE(UMIN_VL)
NODE_NAME_CASE(UMAX_VL) NODE_NAME_CASE(UMAX_VL)
NODE_NAME_CASE(MULHS_VL)
NODE_NAME_CASE(MULHU_VL)
NODE_NAME_CASE(SETCC_VL) NODE_NAME_CASE(SETCC_VL)
NODE_NAME_CASE(VSELECT_VL) NODE_NAME_CASE(VSELECT_VL)
NODE_NAME_CASE(VMAND_VL) NODE_NAME_CASE(VMAND_VL)
NODE_NAME_CASE(VMOR_VL) NODE_NAME_CASE(VMOR_VL)
NODE_NAME_CASE(VMXOR_VL) NODE_NAME_CASE(VMXOR_VL)
NODE_NAME_CASE(VMCLR_VL) NODE_NAME_CASE(VMCLR_VL)
NODE_NAME_CASE(VMSET_VL) NODE_NAME_CASE(VMSET_VL)
NODE_NAME_CASE(VRGATHER_VX_VL) NODE_NAME_CASE(VRGATHER_VX_VL)
▲ Show 20 Lines • Show All 532 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

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def riscv_vle_vl : SDNode<"RISCVISD::VLE_VL", SDT_RISCVVLE_VL, def riscv_vle_vl : SDNode<"RISCVISD::VLE_VL", SDT_RISCVVLE_VL,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def riscv_vse_vl : SDNode<"RISCVISD::VSE_VL", SDT_RISCVVSE_VL, def riscv_vse_vl : SDNode<"RISCVISD::VSE_VL", SDT_RISCVVSE_VL,
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
def riscv_add_vl : SDNode<"RISCVISD::ADD_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; def riscv_add_vl : SDNode<"RISCVISD::ADD_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;
def riscv_sub_vl : SDNode<"RISCVISD::SUB_VL", SDT_RISCVIntBinOp_VL>; def riscv_sub_vl : SDNode<"RISCVISD::SUB_VL", SDT_RISCVIntBinOp_VL>;
def riscv_mul_vl : SDNode<"RISCVISD::MUL_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; def riscv_mul_vl : SDNode<"RISCVISD::MUL_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;
def riscv_mulhs_vl : SDNode<"RISCVISD::MULHS_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;
def riscv_mulhu_vl : SDNode<"RISCVISD::MULHU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;
def riscv_and_vl : SDNode<"RISCVISD::AND_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; def riscv_and_vl : SDNode<"RISCVISD::AND_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;
def riscv_or_vl : SDNode<"RISCVISD::OR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; def riscv_or_vl : SDNode<"RISCVISD::OR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;
def riscv_xor_vl : SDNode<"RISCVISD::XOR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; def riscv_xor_vl : SDNode<"RISCVISD::XOR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;
def riscv_sdiv_vl : SDNode<"RISCVISD::SDIV_VL", SDT_RISCVIntBinOp_VL>; def riscv_sdiv_vl : SDNode<"RISCVISD::SDIV_VL", SDT_RISCVIntBinOp_VL>;
def riscv_srem_vl : SDNode<"RISCVISD::SREM_VL", SDT_RISCVIntBinOp_VL>; def riscv_srem_vl : SDNode<"RISCVISD::SREM_VL", SDT_RISCVIntBinOp_VL>;
def riscv_udiv_vl : SDNode<"RISCVISD::UDIV_VL", SDT_RISCVIntBinOp_VL>; def riscv_udiv_vl : SDNode<"RISCVISD::UDIV_VL", SDT_RISCVIntBinOp_VL>;
def riscv_urem_vl : SDNode<"RISCVISD::UREM_VL", SDT_RISCVIntBinOp_VL>; def riscv_urem_vl : SDNode<"RISCVISD::UREM_VL", SDT_RISCVIntBinOp_VL>;
def riscv_shl_vl : SDNode<"RISCVISD::SHL_VL", SDT_RISCVIntBinOp_VL>; def riscv_shl_vl : SDNode<"RISCVISD::SHL_VL", SDT_RISCVIntBinOp_VL>;
▲ Show 20 Lines • Show All 364 Lines • ▼ Show 20 Lines
// 12.9. Vector Integer Min/Max Instructions // 12.9. Vector Integer Min/Max Instructions
defm "" : VPatBinaryVL_VV_VX<riscv_umin_vl, "PseudoVMINU">; defm "" : VPatBinaryVL_VV_VX<riscv_umin_vl, "PseudoVMINU">;
defm "" : VPatBinaryVL_VV_VX<riscv_smin_vl, "PseudoVMIN">; defm "" : VPatBinaryVL_VV_VX<riscv_smin_vl, "PseudoVMIN">;
defm "" : VPatBinaryVL_VV_VX<riscv_umax_vl, "PseudoVMAXU">; defm "" : VPatBinaryVL_VV_VX<riscv_umax_vl, "PseudoVMAXU">;
defm "" : VPatBinaryVL_VV_VX<riscv_smax_vl, "PseudoVMAX">; defm "" : VPatBinaryVL_VV_VX<riscv_smax_vl, "PseudoVMAX">;
// 12.10. Vector Single-Width Integer Multiply Instructions // 12.10. Vector Single-Width Integer Multiply Instructions
defm "" : VPatBinaryVL_VV_VX<riscv_mul_vl, "PseudoVMUL">; defm "" : VPatBinaryVL_VV_VX<riscv_mul_vl, "PseudoVMUL">;
defm "" : VPatBinaryVL_VV_VX<riscv_mulhs_vl, "PseudoVMULH">;
defm "" : VPatBinaryVL_VV_VX<riscv_mulhu_vl, "PseudoVMULHU">;
// 12.11. Vector Integer Divide Instructions // 12.11. Vector Integer Divide Instructions
defm "" : VPatBinaryVL_VV_VX<riscv_udiv_vl, "PseudoVDIVU">; defm "" : VPatBinaryVL_VV_VX<riscv_udiv_vl, "PseudoVDIVU">;
defm "" : VPatBinaryVL_VV_VX<riscv_sdiv_vl, "PseudoVDIV">; defm "" : VPatBinaryVL_VV_VX<riscv_sdiv_vl, "PseudoVDIV">;
defm "" : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU">; defm "" : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU">;
defm "" : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM">; defm "" : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM">;
// 12.16. Vector Integer Merge Instructions // 12.16. Vector Integer Merge Instructions
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x %a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y %b = load <2 x i64>, <2 x i64>* %y
%c = urem <2 x i64> %a, %b %c = urem <2 x i64> %a, %b
store <2 x i64> %c, <2 x i64>* %x store <2 x i64> %c, <2 x i64>* %x
ret void ret void
} }
define void @mulhu_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: mulhu_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 16
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vle8.v v25, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI52_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI52_0)
; CHECK-NEXT: vle8.v v26, (a1)
; CHECK-NEXT: lui a1, %hi(.LCPI52_1)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI52_1)
; CHECK-NEXT: vle8.v v27, (a1)
; CHECK-NEXT: vsrl.vv v26, v25, v26
; CHECK-NEXT: vmulhu.vv v26, v26, v27
; CHECK-NEXT: lui a1, %hi(.LCPI52_2)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI52_2)
; CHECK-NEXT: vle8.v v27, (a1)
; CHECK-NEXT: lui a1, %hi(.LCPI52_3)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI52_3)
; CHECK-NEXT: vle8.v v28, (a1)
; CHECK-NEXT: vsub.vv v25, v25, v26
; CHECK-NEXT: vmulhu.vv v25, v25, v27
; CHECK-NEXT: vadd.vv v25, v25, v26
; CHECK-NEXT: vsrl.vv v25, v25, v28
; CHECK-NEXT: vse8.v v25, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = udiv <16 x i8> %a, <i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25>
store <16 x i8> %b, <16 x i8>* %x
ret void
}
define void @mulhu_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: mulhu_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 8
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI53_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI53_0)
; CHECK-NEXT: vle16.v v26, (a1)
; CHECK-NEXT: lui a1, %hi(.LCPI53_1)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI53_1)
; CHECK-NEXT: vle16.v v27, (a1)
; CHECK-NEXT: vsrl.vv v26, v25, v26
; CHECK-NEXT: vmulhu.vv v26, v26, v27
; CHECK-NEXT: lui a1, %hi(.LCPI53_2)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI53_2)
; CHECK-NEXT: vle16.v v27, (a1)
; CHECK-NEXT: lui a1, %hi(.LCPI53_3)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI53_3)
; CHECK-NEXT: vle16.v v28, (a1)
; CHECK-NEXT: vsub.vv v25, v25, v26
; CHECK-NEXT: vmulhu.vv v25, v25, v27
; CHECK-NEXT: vadd.vv v25, v25, v26
; CHECK-NEXT: vsrl.vv v25, v25, v28
; CHECK-NEXT: vse16.v v25, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = udiv <8 x i16> %a, <i16 7, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
store <8 x i16> %b, <8 x i16>* %x
ret void
}
define void @mulhu_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: mulhu_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 4
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vle32.v v25, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI54_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI54_0)
; CHECK-NEXT: vle32.v v26, (a1)
; CHECK-NEXT: vmulhu.vv v26, v25, v26
; CHECK-NEXT: lui a1, %hi(.LCPI54_1)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI54_1)
; CHECK-NEXT: vle32.v v27, (a1)
; CHECK-NEXT: lui a1, %hi(.LCPI54_2)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI54_2)
; CHECK-NEXT: vle32.v v28, (a1)
; CHECK-NEXT: vsub.vv v25, v25, v26
; CHECK-NEXT: vmulhu.vv v25, v25, v27
; CHECK-NEXT: vadd.vv v25, v25, v26
; CHECK-NEXT: vsrl.vv v25, v25, v28
; CHECK-NEXT: vse32.v v25, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = udiv <4 x i32> %a, <i32 5, i32 6, i32 7, i32 9>
store <4 x i32> %b, <4 x i32>* %x
ret void
}
define void @mulhu_v2i64(<2 x i64>* %x) {
; LMULMAX1-RV32-LABEL: mulhu_v2i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi a1, zero, 2
; LMULMAX1-RV32-NEXT: vsetvli a2, a1, e64,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI55_0)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI55_0)
; LMULMAX1-RV32-NEXT: addi a3, zero, 4
; LMULMAX1-RV32-NEXT: vsetvli a4, a3, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
; LMULMAX1-RV32-NEXT: vsetvli a2, a1, e64,m1,ta,mu
; LMULMAX1-RV32-NEXT: vmulhu.vv v25, v25, v26
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI55_1)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI55_1)
; LMULMAX1-RV32-NEXT: vsetvli a3, a3, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
; LMULMAX1-RV32-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; LMULMAX1-RV32-NEXT: vsrl.vv v25, v25, v26
; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhu_v2i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: addi a1, zero, 2
; LMULMAX1-RV64-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
; LMULMAX1-RV64-NEXT: lui a1, %hi(.LCPI55_0)
; LMULMAX1-RV64-NEXT: addi a1, a1, %lo(.LCPI55_0)
; LMULMAX1-RV64-NEXT: vle64.v v26, (a1)
; LMULMAX1-RV64-NEXT: lui a1, %hi(.LCPI55_1)
; LMULMAX1-RV64-NEXT: addi a1, a1, %lo(.LCPI55_1)
; LMULMAX1-RV64-NEXT: vle64.v v27, (a1)
; LMULMAX1-RV64-NEXT: vmulhu.vv v25, v25, v26
; LMULMAX1-RV64-NEXT: vsrl.vv v25, v25, v27
; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = udiv <2 x i64> %a, <i64 3, i64 5>
store <2 x i64> %b, <2 x i64>* %x
ret void
}
define void @mulhs_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: mulhs_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 16
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vle8.v v25, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI56_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI56_0)
; CHECK-NEXT: vle8.v v26, (a1)
; CHECK-NEXT: lui a1, %hi(.LCPI56_1)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI56_1)
; CHECK-NEXT: vle8.v v27, (a1)
; CHECK-NEXT: vmulhu.vv v25, v25, v26
; CHECK-NEXT: vsrl.vv v25, v25, v27
; CHECK-NEXT: vse8.v v25, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = udiv <16 x i8> %a, <i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9>
store <16 x i8> %b, <16 x i8>* %x
ret void
}
define void @mulhs_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: mulhs_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 8
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI57_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI57_0)
; CHECK-NEXT: vle16.v v26, (a1)
; CHECK-NEXT: vmulh.vv v25, v25, v26
; CHECK-NEXT: vsra.vi v25, v25, 1
; CHECK-NEXT: vsrl.vi v26, v25, 15
; CHECK-NEXT: vadd.vv v25, v25, v26
; CHECK-NEXT: vse16.v v25, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = sdiv <8 x i16> %a, <i16 -7, i16 7, i16 7, i16 -7, i16 7, i16 -7, i16 -7, i16 7>
store <8 x i16> %b, <8 x i16>* %x
ret void
}
define void @mulhs_v4i32(<4 x i32>* %x) {
; LMULMAX1-RV32-LABEL: mulhs_v4i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi a1, zero, 4
; LMULMAX1-RV32-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
; LMULMAX1-RV32-NEXT: lui a1, %hi(.LCPI58_0)
; LMULMAX1-RV32-NEXT: addi a1, a1, %lo(.LCPI58_0)
; LMULMAX1-RV32-NEXT: vle32.v v26, (a1)
; LMULMAX1-RV32-NEXT: vmulh.vv v25, v25, v26
; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 31
; LMULMAX1-RV32-NEXT: vsra.vi v25, v25, 1
; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v26
; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhs_v4i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: addi a1, zero, 4
; LMULMAX1-RV64-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
; LMULMAX1-RV64-NEXT: lui a1, %hi(.LCPI58_0)
; LMULMAX1-RV64-NEXT: addi a1, a1, %lo(.LCPI58_0)
; LMULMAX1-RV64-NEXT: vle32.v v26, (a1)
; LMULMAX1-RV64-NEXT: vmulh.vv v25, v25, v26
; LMULMAX1-RV64-NEXT: vsra.vi v25, v25, 1
; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 31
; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v26
; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = sdiv <4 x i32> %a, <i32 -5, i32 5, i32 -5, i32 5>
store <4 x i32> %b, <4 x i32>* %x
ret void
}
define void @mulhs_v2i64(<2 x i64>* %x) {
; LMULMAX1-RV32-LABEL: mulhs_v2i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi a1, zero, 2
; LMULMAX1-RV32-NEXT: vsetvli a2, a1, e64,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI59_0)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI59_0)
; LMULMAX1-RV32-NEXT: addi a3, zero, 4
; LMULMAX1-RV32-NEXT: vsetvli a4, a3, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
; LMULMAX1-RV32-NEXT: vsetvli a2, a1, e64,m1,ta,mu
; LMULMAX1-RV32-NEXT: vmul.vv v26, v25, v26
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI59_1)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI59_1)
; LMULMAX1-RV32-NEXT: vsetvli a4, a3, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle32.v v27, (a2)
; LMULMAX1-RV32-NEXT: vsetvli a2, a1, e64,m1,ta,mu
; LMULMAX1-RV32-NEXT: vmulh.vv v25, v25, v27
; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v26
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI59_2)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI59_2)
; LMULMAX1-RV32-NEXT: vsetvli a4, a3, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
; LMULMAX1-RV32-NEXT: vsetvli a2, a1, e64,m1,ta,mu
; LMULMAX1-RV32-NEXT: vsrl.vv v26, v25, v26
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI59_3)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI59_3)
; LMULMAX1-RV32-NEXT: vsetvli a3, a3, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle32.v v27, (a2)
; LMULMAX1-RV32-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; LMULMAX1-RV32-NEXT: vsra.vv v25, v25, v27
; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v26
; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhs_v2i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: addi a1, zero, 2
; LMULMAX1-RV64-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
; LMULMAX1-RV64-NEXT: lui a1, %hi(.LCPI59_0)
; LMULMAX1-RV64-NEXT: addi a1, a1, %lo(.LCPI59_0)
; LMULMAX1-RV64-NEXT: vle64.v v26, (a1)
; LMULMAX1-RV64-NEXT: lui a1, %hi(.LCPI59_1)
; LMULMAX1-RV64-NEXT: addi a1, a1, %lo(.LCPI59_1)
; LMULMAX1-RV64-NEXT: vle64.v v27, (a1)
; LMULMAX1-RV64-NEXT: vmul.vv v26, v25, v26
; LMULMAX1-RV64-NEXT: vmulh.vv v25, v25, v27
; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v26
; LMULMAX1-RV64-NEXT: addi a1, zero, 63
; LMULMAX1-RV64-NEXT: vsrl.vx v26, v25, a1
; LMULMAX1-RV64-NEXT: vid.v v27
; LMULMAX1-RV64-NEXT: vsra.vv v25, v25, v27
; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v26
; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = sdiv <2 x i64> %a, <i64 3, i64 -3>
store <2 x i64> %b, <2 x i64>* %x
ret void
}
define void @smin_v16i8(<16 x i8>* %x, <16 x i8>* %y) { define void @smin_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: smin_v16i8: ; CHECK-LABEL: smin_v16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 16 ; CHECK-NEXT: addi a2, zero, 16
; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu
; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vle8.v v25, (a0)
; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vle8.v v26, (a1)
; CHECK-NEXT: vmin.vv v25, v25, v26 ; CHECK-NEXT: vmin.vv v25, v25, v26
▲ Show 20 Lines • Show All 2,874 Lines • ▼ Show 20 Lines; LMULMAX1-RV64-NEXT: ret
%b = load <4 x i64>, <4 x i64>* %y %b = load <4 x i64>, <4 x i64>* %y
br label %"compute" br label %"compute"
"compute": "compute":
%c = add <4 x i64> %a, %b %c = add <4 x i64> %a, %b
store <4 x i64> %c, <4 x i64>* %x store <4 x i64> %c, <4 x i64>* %x
ret void ret void
} }
define void @mulhu_v32i8(<32 x i8>* %x) {
; LMULMAX2-LABEL: mulhu_v32i8:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 32
; LMULMAX2-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; LMULMAX2-NEXT: vle8.v v26, (a0)
; LMULMAX2-NEXT: lui a1, %hi(.LCPI129_0)
; LMULMAX2-NEXT: addi a1, a1, %lo(.LCPI129_0)
; LMULMAX2-NEXT: vle8.v v28, (a1)
; LMULMAX2-NEXT: lui a1, %hi(.LCPI129_1)
; LMULMAX2-NEXT: addi a1, a1, %lo(.LCPI129_1)
; LMULMAX2-NEXT: vle8.v v30, (a1)
; LMULMAX2-NEXT: vsrl.vv v28, v26, v28
; LMULMAX2-NEXT: vmulhu.vv v28, v28, v30
; LMULMAX2-NEXT: lui a1, %hi(.LCPI129_2)
; LMULMAX2-NEXT: addi a1, a1, %lo(.LCPI129_2)
; LMULMAX2-NEXT: vle8.v v30, (a1)
; LMULMAX2-NEXT: lui a1, %hi(.LCPI129_3)
; LMULMAX2-NEXT: addi a1, a1, %lo(.LCPI129_3)
; LMULMAX2-NEXT: vle8.v v8, (a1)
; LMULMAX2-NEXT: vsub.vv v26, v26, v28
; LMULMAX2-NEXT: vmulhu.vv v26, v26, v30
; LMULMAX2-NEXT: vadd.vv v26, v26, v28
; LMULMAX2-NEXT: vsrl.vv v26, v26, v8
; LMULMAX2-NEXT: vse8.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: mulhu_v32i8:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi a1, zero, 16
; LMULMAX1-RV32-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle8.v v25, (a1)
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI129_0)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI129_0)
; LMULMAX1-RV32-NEXT: vle8.v v26, (a2)
; LMULMAX1-RV32-NEXT: vle8.v v27, (a0)
; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v26
; LMULMAX1-RV32-NEXT: vdivu.vv v26, v27, v26
; LMULMAX1-RV32-NEXT: vse8.v v26, (a0)
; LMULMAX1-RV32-NEXT: vse8.v v25, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhu_v32i8:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: addi a1, zero, 16
; LMULMAX1-RV64-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle8.v v25, (a1)
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI129_0)
; LMULMAX1-RV64-NEXT: addi a2, a2, %lo(.LCPI129_0)
; LMULMAX1-RV64-NEXT: vle8.v v26, (a2)
; LMULMAX1-RV64-NEXT: vle8.v v27, (a0)
; LMULMAX1-RV64-NEXT: vdivu.vv v25, v25, v26
; LMULMAX1-RV64-NEXT: vdivu.vv v26, v27, v26
; LMULMAX1-RV64-NEXT: vse8.v v26, (a0)
; LMULMAX1-RV64-NEXT: vse8.v v25, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = udiv <32 x i8> %a, <i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25>
store <32 x i8> %b, <32 x i8>* %x
ret void
}
define void @mulhu_v16i16(<16 x i16>* %x) {
; LMULMAX2-LABEL: mulhu_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 16
; LMULMAX2-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; LMULMAX2-NEXT: vle16.v v26, (a0)
; LMULMAX2-NEXT: lui a1, %hi(.LCPI130_0)
; LMULMAX2-NEXT: addi a1, a1, %lo(.LCPI130_0)
; LMULMAX2-NEXT: vle16.v v28, (a1)
; LMULMAX2-NEXT: lui a1, %hi(.LCPI130_1)
; LMULMAX2-NEXT: addi a1, a1, %lo(.LCPI130_1)
; LMULMAX2-NEXT: vle16.v v30, (a1)
; LMULMAX2-NEXT: vsrl.vv v28, v26, v28
; LMULMAX2-NEXT: vmulhu.vv v28, v28, v30
; LMULMAX2-NEXT: lui a1, %hi(.LCPI130_2)
; LMULMAX2-NEXT: addi a1, a1, %lo(.LCPI130_2)
; LMULMAX2-NEXT: vle16.v v30, (a1)
; LMULMAX2-NEXT: lui a1, %hi(.LCPI130_3)
; LMULMAX2-NEXT: addi a1, a1, %lo(.LCPI130_3)
; LMULMAX2-NEXT: vle16.v v8, (a1)
; LMULMAX2-NEXT: vsub.vv v26, v26, v28
; LMULMAX2-NEXT: vmulhu.vv v26, v26, v30
; LMULMAX2-NEXT: vadd.vv v26, v26, v28
; LMULMAX2-NEXT: vsrl.vv v26, v26, v8
; LMULMAX2-NEXT: vse16.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: mulhu_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi a1, zero, 8
; LMULMAX1-RV32-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle16.v v25, (a1)
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI130_0)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI130_0)
; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
; LMULMAX1-RV32-NEXT: vle16.v v27, (a0)
; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v26
; LMULMAX1-RV32-NEXT: vdivu.vv v26, v27, v26
; LMULMAX1-RV32-NEXT: vse16.v v26, (a0)
; LMULMAX1-RV32-NEXT: vse16.v v25, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhu_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: addi a1, zero, 8
; LMULMAX1-RV64-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle16.v v25, (a1)
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI130_0)
; LMULMAX1-RV64-NEXT: addi a2, a2, %lo(.LCPI130_0)
; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
; LMULMAX1-RV64-NEXT: vle16.v v27, (a0)
; LMULMAX1-RV64-NEXT: vdivu.vv v25, v25, v26
; LMULMAX1-RV64-NEXT: vdivu.vv v26, v27, v26
; LMULMAX1-RV64-NEXT: vse16.v v26, (a0)
; LMULMAX1-RV64-NEXT: vse16.v v25, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = udiv <16 x i16> %a, <i16 7, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 7, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
store <16 x i16> %b, <16 x i16>* %x
ret void
}
define void @mulhu_v8i32(<8 x i32>* %x) {
; LMULMAX2-LABEL: mulhu_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 8
; LMULMAX2-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; LMULMAX2-NEXT: vle32.v v26, (a0)
; LMULMAX2-NEXT: lui a1, %hi(.LCPI131_0)
; LMULMAX2-NEXT: addi a1, a1, %lo(.LCPI131_0)
; LMULMAX2-NEXT: vle32.v v28, (a1)
; LMULMAX2-NEXT: vmulhu.vv v28, v26, v28
; LMULMAX2-NEXT: lui a1, %hi(.LCPI131_1)
; LMULMAX2-NEXT: addi a1, a1, %lo(.LCPI131_1)
; LMULMAX2-NEXT: vle32.v v30, (a1)
; LMULMAX2-NEXT: lui a1, %hi(.LCPI131_2)
; LMULMAX2-NEXT: addi a1, a1, %lo(.LCPI131_2)
; LMULMAX2-NEXT: vle32.v v8, (a1)
; LMULMAX2-NEXT: vsub.vv v26, v26, v28
; LMULMAX2-NEXT: vmulhu.vv v26, v26, v30
; LMULMAX2-NEXT: vadd.vv v26, v26, v28
; LMULMAX2-NEXT: vsrl.vv v26, v26, v8
; LMULMAX2-NEXT: vse32.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: mulhu_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi a1, zero, 4
; LMULMAX1-RV32-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle32.v v25, (a1)
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI131_0)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI131_0)
; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
; LMULMAX1-RV32-NEXT: vle32.v v27, (a0)
; LMULMAX1-RV32-NEXT: vmulhu.vv v28, v25, v26
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI131_1)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI131_1)
; LMULMAX1-RV32-NEXT: vle32.v v29, (a2)
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI131_2)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI131_2)
; LMULMAX1-RV32-NEXT: vle32.v v30, (a2)
; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v28
; LMULMAX1-RV32-NEXT: vmulhu.vv v25, v25, v29
; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v28
; LMULMAX1-RV32-NEXT: vsrl.vv v25, v25, v30
; LMULMAX1-RV32-NEXT: vmulhu.vv v26, v27, v26
; LMULMAX1-RV32-NEXT: vsub.vv v27, v27, v26
; LMULMAX1-RV32-NEXT: vmulhu.vv v27, v27, v29
; LMULMAX1-RV32-NEXT: vadd.vv v26, v27, v26
; LMULMAX1-RV32-NEXT: vsrl.vv v26, v26, v30
; LMULMAX1-RV32-NEXT: vse32.v v26, (a0)
; LMULMAX1-RV32-NEXT: vse32.v v25, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhu_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: addi a1, zero, 4
; LMULMAX1-RV64-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle32.v v25, (a1)
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI131_0)
; LMULMAX1-RV64-NEXT: addi a2, a2, %lo(.LCPI131_0)
; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
; LMULMAX1-RV64-NEXT: vle32.v v27, (a0)
; LMULMAX1-RV64-NEXT: vdivu.vv v25, v25, v26
; LMULMAX1-RV64-NEXT: vdivu.vv v26, v27, v26
; LMULMAX1-RV64-NEXT: vse32.v v26, (a0)
; LMULMAX1-RV64-NEXT: vse32.v v25, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = udiv <8 x i32> %a, <i32 5, i32 6, i32 7, i32 9, i32 5, i32 6, i32 7, i32 9>
store <8 x i32> %b, <8 x i32>* %x
ret void
}
define void @mulhu_v4i64(<4 x i64>* %x) {
; LMULMAX1-RV32-LABEL: mulhu_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi a1, zero, 2
; LMULMAX1-RV32-NEXT: vsetvli a2, a1, e64,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
; LMULMAX1-RV32-NEXT: lui a3, %hi(.LCPI132_0)
; LMULMAX1-RV32-NEXT: addi a3, a3, %lo(.LCPI132_0)
; LMULMAX1-RV32-NEXT: addi a4, zero, 4
; LMULMAX1-RV32-NEXT: vsetvli a5, a4, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
; LMULMAX1-RV32-NEXT: vsetvli a3, a1, e64,m1,ta,mu
; LMULMAX1-RV32-NEXT: vdivu.vv v26, v26, v27
; LMULMAX1-RV32-NEXT: lui a3, %hi(.LCPI132_1)
; LMULMAX1-RV32-NEXT: addi a3, a3, %lo(.LCPI132_1)
; LMULMAX1-RV32-NEXT: vsetvli a4, a4, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
; LMULMAX1-RV32-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v27
; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhu_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: addi a1, zero, 2
; LMULMAX1-RV64-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle64.v v25, (a1)
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI132_0)
; LMULMAX1-RV64-NEXT: addi a2, a2, %lo(.LCPI132_0)
; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI132_1)
; LMULMAX1-RV64-NEXT: addi a2, a2, %lo(.LCPI132_1)
; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
; LMULMAX1-RV64-NEXT: vle64.v v28, (a0)
; LMULMAX1-RV64-NEXT: vmulhu.vv v26, v25, v26
; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v26
; LMULMAX1-RV64-NEXT: vmulhu.vv v25, v25, v27
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI132_2)
; LMULMAX1-RV64-NEXT: addi a2, a2, %lo(.LCPI132_2)
; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI132_3)
; LMULMAX1-RV64-NEXT: addi a2, a2, %lo(.LCPI132_3)
; LMULMAX1-RV64-NEXT: vle64.v v29, (a2)
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI132_4)
; LMULMAX1-RV64-NEXT: addi a2, a2, %lo(.LCPI132_4)
; LMULMAX1-RV64-NEXT: vle64.v v30, (a2)
; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v26
; LMULMAX1-RV64-NEXT: vsrl.vv v25, v25, v27
; LMULMAX1-RV64-NEXT: vmulhu.vv v26, v28, v29
; LMULMAX1-RV64-NEXT: vsrl.vv v26, v26, v30
; LMULMAX1-RV64-NEXT: vse64.v v26, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v25, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = udiv <4 x i64> %a, <i64 3, i64 5, i64 7, i64 9>
store <4 x i64> %b, <4 x i64>* %x
ret void
}
define void @mulhs_v32i8(<32 x i8>* %x) {
; LMULMAX2-LABEL: mulhs_v32i8:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 32
; LMULMAX2-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; LMULMAX2-NEXT: vle8.v v26, (a0)
; LMULMAX2-NEXT: lui a1, %hi(.LCPI133_0)
; LMULMAX2-NEXT: addi a1, a1, %lo(.LCPI133_0)
; LMULMAX2-NEXT: vle8.v v28, (a1)
; LMULMAX2-NEXT: lui a1, %hi(.LCPI133_1)
; LMULMAX2-NEXT: addi a1, a1, %lo(.LCPI133_1)
; LMULMAX2-NEXT: vle8.v v30, (a1)
; LMULMAX2-NEXT: vmulhu.vv v26, v26, v28
; LMULMAX2-NEXT: vsrl.vv v26, v26, v30
; LMULMAX2-NEXT: vse8.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: mulhs_v32i8:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi a1, zero, 16
; LMULMAX1-RV32-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle8.v v25, (a1)
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI133_0)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI133_0)
; LMULMAX1-RV32-NEXT: vle8.v v26, (a2)
; LMULMAX1-RV32-NEXT: vle8.v v27, (a0)
; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v26
; LMULMAX1-RV32-NEXT: vdivu.vv v26, v27, v26
; LMULMAX1-RV32-NEXT: vse8.v v26, (a0)
; LMULMAX1-RV32-NEXT: vse8.v v25, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhs_v32i8:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: addi a1, zero, 16
; LMULMAX1-RV64-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle8.v v25, (a1)
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI133_0)
; LMULMAX1-RV64-NEXT: addi a2, a2, %lo(.LCPI133_0)
; LMULMAX1-RV64-NEXT: vle8.v v26, (a2)
; LMULMAX1-RV64-NEXT: vle8.v v27, (a0)
; LMULMAX1-RV64-NEXT: vdivu.vv v25, v25, v26
; LMULMAX1-RV64-NEXT: vdivu.vv v26, v27, v26
; LMULMAX1-RV64-NEXT: vse8.v v26, (a0)
; LMULMAX1-RV64-NEXT: vse8.v v25, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = udiv <32 x i8> %a, <i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9, i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9>
store <32 x i8> %b, <32 x i8>* %x
ret void
}
define void @mulhs_v16i16(<16 x i16>* %x) {
; LMULMAX2-LABEL: mulhs_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 16
; LMULMAX2-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; LMULMAX2-NEXT: vle16.v v26, (a0)
; LMULMAX2-NEXT: lui a1, %hi(.LCPI134_0)
; LMULMAX2-NEXT: addi a1, a1, %lo(.LCPI134_0)
; LMULMAX2-NEXT: vle16.v v28, (a1)
; LMULMAX2-NEXT: vmulh.vv v26, v26, v28
; LMULMAX2-NEXT: vsra.vi v26, v26, 1
; LMULMAX2-NEXT: vsrl.vi v28, v26, 15
; LMULMAX2-NEXT: vadd.vv v26, v26, v28
; LMULMAX2-NEXT: vse16.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: mulhs_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi a1, zero, 8
; LMULMAX1-RV32-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle16.v v25, (a1)
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI134_0)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI134_0)
; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
; LMULMAX1-RV32-NEXT: vle16.v v27, (a0)
; LMULMAX1-RV32-NEXT: vdiv.vv v25, v25, v26
; LMULMAX1-RV32-NEXT: vdiv.vv v26, v27, v26
; LMULMAX1-RV32-NEXT: vse16.v v26, (a0)
; LMULMAX1-RV32-NEXT: vse16.v v25, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhs_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: addi a1, zero, 8
; LMULMAX1-RV64-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle16.v v25, (a1)
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI134_0)
; LMULMAX1-RV64-NEXT: addi a2, a2, %lo(.LCPI134_0)
; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
; LMULMAX1-RV64-NEXT: vle16.v v27, (a0)
; LMULMAX1-RV64-NEXT: vdiv.vv v25, v25, v26
; LMULMAX1-RV64-NEXT: vdiv.vv v26, v27, v26
; LMULMAX1-RV64-NEXT: vse16.v v26, (a0)
; LMULMAX1-RV64-NEXT: vse16.v v25, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = sdiv <16 x i16> %a, <i16 -7, i16 7, i16 7, i16 -7, i16 7, i16 -7, i16 -7, i16 7, i16 -7, i16 7, i16 7, i16 -7, i16 7, i16 -7, i16 -7, i16 7>
store <16 x i16> %b, <16 x i16>* %x
ret void
}
define void @mulhs_v8i32(<8 x i32>* %x) {
; LMULMAX1-RV32-LABEL: mulhs_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi a1, zero, 4
; LMULMAX1-RV32-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle32.v v25, (a1)
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI135_0)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI135_0)
; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
; LMULMAX1-RV32-NEXT: vle32.v v27, (a0)
; LMULMAX1-RV32-NEXT: vmulh.vv v25, v25, v26
; LMULMAX1-RV32-NEXT: vsrl.vi v28, v25, 31
; LMULMAX1-RV32-NEXT: vsra.vi v25, v25, 1
; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v28
; LMULMAX1-RV32-NEXT: vmulh.vv v26, v27, v26
; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 31
; LMULMAX1-RV32-NEXT: vsra.vi v26, v26, 1
; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v27
; LMULMAX1-RV32-NEXT: vse32.v v26, (a0)
; LMULMAX1-RV32-NEXT: vse32.v v25, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhs_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: addi a1, zero, 4
; LMULMAX1-RV64-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle32.v v25, (a1)
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI135_0)
; LMULMAX1-RV64-NEXT: addi a2, a2, %lo(.LCPI135_0)
; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
; LMULMAX1-RV64-NEXT: vle32.v v27, (a0)
; LMULMAX1-RV64-NEXT: vdiv.vv v25, v25, v26
; LMULMAX1-RV64-NEXT: vdiv.vv v26, v27, v26
; LMULMAX1-RV64-NEXT: vse32.v v26, (a0)
; LMULMAX1-RV64-NEXT: vse32.v v25, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = sdiv <8 x i32> %a, <i32 -5, i32 5, i32 -5, i32 5, i32 -5, i32 5, i32 -5, i32 5>
store <8 x i32> %b, <8 x i32>* %x
ret void
}
define void @mulhs_v4i64(<4 x i64>* %x) {
; LMULMAX1-RV32-LABEL: mulhs_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi a1, zero, 2
; LMULMAX1-RV32-NEXT: vsetvli a2, a1, e64,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
; LMULMAX1-RV32-NEXT: lui a3, %hi(.LCPI136_0)
; LMULMAX1-RV32-NEXT: addi a3, a3, %lo(.LCPI136_0)
; LMULMAX1-RV32-NEXT: addi a4, zero, 4
; LMULMAX1-RV32-NEXT: vsetvli a4, a4, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
; LMULMAX1-RV32-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; LMULMAX1-RV32-NEXT: vdiv.vv v26, v26, v27
; LMULMAX1-RV32-NEXT: vdiv.vv v25, v25, v27
; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhs_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: addi a1, zero, 2
; LMULMAX1-RV64-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle64.v v25, (a1)
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI136_0)
; LMULMAX1-RV64-NEXT: addi a2, a2, %lo(.LCPI136_0)
; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI136_1)
; LMULMAX1-RV64-NEXT: addi a2, a2, %lo(.LCPI136_1)
; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
; LMULMAX1-RV64-NEXT: vle64.v v28, (a0)
; LMULMAX1-RV64-NEXT: vmul.vv v29, v25, v26
; LMULMAX1-RV64-NEXT: vmulh.vv v25, v25, v27
; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v29
; LMULMAX1-RV64-NEXT: addi a2, zero, 63
; LMULMAX1-RV64-NEXT: vsrl.vx v29, v25, a2
; LMULMAX1-RV64-NEXT: vid.v v30
; LMULMAX1-RV64-NEXT: vsra.vv v25, v25, v30
; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v29
; LMULMAX1-RV64-NEXT: vmul.vv v26, v28, v26
; LMULMAX1-RV64-NEXT: vmulh.vv v27, v28, v27
; LMULMAX1-RV64-NEXT: vadd.vv v26, v27, v26
; LMULMAX1-RV64-NEXT: vsrl.vx v27, v26, a2
; LMULMAX1-RV64-NEXT: vsra.vv v26, v26, v30
; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v27
; LMULMAX1-RV64-NEXT: vse64.v v26, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v25, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = sdiv <4 x i64> %a, <i64 3, i64 -3, i64 3, i64 -3>
store <4 x i64> %b, <4 x i64>* %x
ret void
}
define void @smin_v32i8(<32 x i8>* %x, <32 x i8>* %y) { define void @smin_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-LABEL: smin_v32i8: ; LMULMAX2-LABEL: smin_v32i8:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli a2, a2, e8,m2,ta,mu ; LMULMAX2-NEXT: vsetvli a2, a2, e8,m2,ta,mu
; LMULMAX2-NEXT: vle8.v v26, (a0) ; LMULMAX2-NEXT: vle8.v v26, (a0)
; LMULMAX2-NEXT: vle8.v v28, (a1) ; LMULMAX2-NEXT: vle8.v v28, (a1)
; LMULMAX2-NEXT: vmin.vv v26, v26, v28 ; LMULMAX2-NEXT: vmin.vv v26, v26, v28
▲ Show 20 Lines • Show All 2,418 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x %a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i32 0 %b = insertelement <4 x i32> undef, i32 %y, i32 0
%c = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer %c = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer
%d = urem <4 x i32> %a, %c %d = urem <4 x i32> %a, %c
store <4 x i32> %d, <4 x i32>* %x store <4 x i32> %d, <4 x i32>* %x
ret void ret void
} }
define void @mulhu_vx_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: mulhu_vx_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 16
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vle8.v v25, (a0)
; CHECK-NEXT: addi a1, zero, 57
; CHECK-NEXT: vmulhu.vx v25, v25, a1
; CHECK-NEXT: vsrl.vi v25, v25, 1
; CHECK-NEXT: vse8.v v25, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = udiv <16 x i8> %a, <i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9>
store <16 x i8> %b, <16 x i8>* %x
ret void
}
define void @mulhu_vx_v8i16(<8 x i16>* %x) {
; LMULMAX1-RV32-LABEL: mulhu_vx_v8i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi a1, zero, 8
; LMULMAX1-RV32-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
; LMULMAX1-RV32-NEXT: lui a1, 2
; LMULMAX1-RV32-NEXT: addi a1, a1, 1171
; LMULMAX1-RV32-NEXT: vmulhu.vx v26, v25, a1
; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v26
; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 1
; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v26
; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 2
; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhu_vx_v8i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: addi a1, zero, 8
; LMULMAX1-RV64-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
; LMULMAX1-RV64-NEXT: lui a1, 2
; LMULMAX1-RV64-NEXT: addiw a1, a1, 1171
; LMULMAX1-RV64-NEXT: vmulhu.vx v26, v25, a1
; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v26
; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 1
; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v26
; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 2
; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = udiv <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
store <8 x i16> %b, <8 x i16>* %x
ret void
}
define void @mulhu_vx_v4i32(<4 x i32>* %x) {
; LMULMAX1-RV32-LABEL: mulhu_vx_v4i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi a1, zero, 4
; LMULMAX1-RV32-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
; LMULMAX1-RV32-NEXT: lui a1, 838861
; LMULMAX1-RV32-NEXT: addi a1, a1, -819
; LMULMAX1-RV32-NEXT: vmulhu.vx v25, v25, a1
; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 2
; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhu_vx_v4i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: addi a1, zero, 4
; LMULMAX1-RV64-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
; LMULMAX1-RV64-NEXT: lui a1, 838861
; LMULMAX1-RV64-NEXT: addiw a1, a1, -819
; LMULMAX1-RV64-NEXT: vmulhu.vx v25, v25, a1
; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 2
; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = udiv <4 x i32> %a, <i32 5, i32 5, i32 5, i32 5>
store <4 x i32> %b, <4 x i32>* %x
ret void
}
define void @mulhu_vx_v2i64(<2 x i64>* %x) {
; LMULMAX1-RV32-LABEL: mulhu_vx_v2i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi a1, zero, 2
; LMULMAX1-RV32-NEXT: vsetvli a2, a1, e64,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI252_0)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI252_0)
; LMULMAX1-RV32-NEXT: addi a3, zero, 4
; LMULMAX1-RV32-NEXT: vsetvli a4, a3, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
; LMULMAX1-RV32-NEXT: vsetvli a2, a1, e64,m1,ta,mu
; LMULMAX1-RV32-NEXT: vmulhu.vv v25, v25, v26
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI252_1)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI252_1)
; LMULMAX1-RV32-NEXT: vsetvli a3, a3, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
; LMULMAX1-RV32-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; LMULMAX1-RV32-NEXT: vsrl.vv v25, v25, v26
; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhu_vx_v2i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: addi a1, zero, 2
; LMULMAX1-RV64-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
; LMULMAX1-RV64-NEXT: lui a1, 1026731
; LMULMAX1-RV64-NEXT: addiw a1, a1, -1365
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
; LMULMAX1-RV64-NEXT: addi a1, a1, -1365
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
; LMULMAX1-RV64-NEXT: addi a1, a1, -1365
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
; LMULMAX1-RV64-NEXT: addi a1, a1, -1365
; LMULMAX1-RV64-NEXT: vmulhu.vx v25, v25, a1
; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 1
; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = udiv <2 x i64> %a, <i64 3, i64 3>
store <2 x i64> %b, <2 x i64>* %x
ret void
}
define void @mulhs_vx_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: mulhs_vx_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 16
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vle8.v v25, (a0)
; CHECK-NEXT: addi a1, zero, -123
; CHECK-NEXT: vmulhu.vx v25, v25, a1
; CHECK-NEXT: vsrl.vi v25, v25, 7
; CHECK-NEXT: vse8.v v25, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = udiv <16 x i8> %a, <i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9>
store <16 x i8> %b, <16 x i8>* %x
ret void
}
define void @mulhs_vx_v8i16(<8 x i16>* %x) {
; LMULMAX1-RV32-LABEL: mulhs_vx_v8i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi a1, zero, 8
; LMULMAX1-RV32-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
; LMULMAX1-RV32-NEXT: lui a1, 5
; LMULMAX1-RV32-NEXT: addi a1, a1, -1755
; LMULMAX1-RV32-NEXT: vmulh.vx v25, v25, a1
; LMULMAX1-RV32-NEXT: vsra.vi v25, v25, 1
; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 15
; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v26
; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhs_vx_v8i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: addi a1, zero, 8
; LMULMAX1-RV64-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
; LMULMAX1-RV64-NEXT: lui a1, 5
; LMULMAX1-RV64-NEXT: addiw a1, a1, -1755
; LMULMAX1-RV64-NEXT: vmulh.vx v25, v25, a1
; LMULMAX1-RV64-NEXT: vsra.vi v25, v25, 1
; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 15
; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v26
; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = sdiv <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
store <8 x i16> %b, <8 x i16>* %x
ret void
}
define void @mulhs_vx_v4i32(<4 x i32>* %x) {
; LMULMAX1-RV32-LABEL: mulhs_vx_v4i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi a1, zero, 4
; LMULMAX1-RV32-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
; LMULMAX1-RV32-NEXT: lui a1, 629146
; LMULMAX1-RV32-NEXT: addi a1, a1, -1639
; LMULMAX1-RV32-NEXT: vmulh.vx v25, v25, a1
; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 31
; LMULMAX1-RV32-NEXT: vsra.vi v25, v25, 1
; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v26
; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhs_vx_v4i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: addi a1, zero, 4
; LMULMAX1-RV64-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
; LMULMAX1-RV64-NEXT: lui a1, 629146
; LMULMAX1-RV64-NEXT: addiw a1, a1, -1639
; LMULMAX1-RV64-NEXT: vmulh.vx v25, v25, a1
; LMULMAX1-RV64-NEXT: vsra.vi v25, v25, 1
; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 31
; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v26
; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = sdiv <4 x i32> %a, <i32 -5, i32 -5, i32 -5, i32 -5>
store <4 x i32> %b, <4 x i32>* %x
ret void
}
define void @mulhs_vx_v2i64(<2 x i64>* %x) {
; LMULMAX1-RV32-LABEL: mulhs_vx_v2i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi a1, zero, 2
; LMULMAX1-RV32-NEXT: vsetvli a2, a1, e64,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI256_0)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI256_0)
; LMULMAX1-RV32-NEXT: addi a3, zero, 4
; LMULMAX1-RV32-NEXT: vsetvli a4, a3, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
; LMULMAX1-RV32-NEXT: vsetvli a2, a1, e64,m1,ta,mu
; LMULMAX1-RV32-NEXT: vmulh.vv v25, v25, v26
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI256_1)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI256_1)
; LMULMAX1-RV32-NEXT: vsetvli a3, a3, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
; LMULMAX1-RV32-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; LMULMAX1-RV32-NEXT: vsrl.vv v26, v25, v26
; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v26
; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhs_vx_v2i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: addi a1, zero, 2
; LMULMAX1-RV64-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
; LMULMAX1-RV64-NEXT: lui a1, 21845
; LMULMAX1-RV64-NEXT: addiw a1, a1, 1365
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
; LMULMAX1-RV64-NEXT: addi a1, a1, 1365
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
; LMULMAX1-RV64-NEXT: addi a1, a1, 1365
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
; LMULMAX1-RV64-NEXT: addi a1, a1, 1366
; LMULMAX1-RV64-NEXT: vmulh.vx v25, v25, a1
; LMULMAX1-RV64-NEXT: addi a1, zero, 63
; LMULMAX1-RV64-NEXT: vsrl.vx v26, v25, a1
; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v26
; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = sdiv <2 x i64> %a, <i64 3, i64 3>
store <2 x i64> %b, <2 x i64>* %x
ret void
}