[RISCV] Support isel of scalable vector bitcasts

[craig.topper]

Summary

These should be NOPs so we can just replace with the input. This
matches what SVE does with isel patterns for all permutations.
Custom isel saves us from having to list all permurations for
all LMULs.

[frasercrmck]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

752

I'm kind of surprised this works - doesn't ReplaceUses expect the "from" and "to" to have the same type?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

752

It doesn't check. Here is what tablegen generates for AArch64

/*278776*/    OPC_CompleteMatch, 1, 0,-                                                                                                                                                                                                                                                                                             
               // Src: (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv8bf16] }:$src) - Complexity = 3                                                                                                                                                                                                                                      
               // Dst: ZPR:{ *:[nxv2f64] }:$src

CompleteMatch calls ReplaceUses, there's an assert above the call to ReplaceUses in CompleteMatch that checks if the VT matches OR that the type has the same number of bits.

[frasercrmck]

LGTM.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

752

Thanks: that's the bit I was missing; the fact that at that stage it's no longer purely value-type-focused.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

case ISD::INTRINSIC_VOID: {
     case Intrinsic::riscv_vsuxseg7_mask:
     case Intrinsic::riscv_vsuxseg8_mask: {
       selectVSXSEG(Node, IntNo, /*IsMasked*/ true);
       return;
     }
     }
     break;
   }
+  case ISD::BITCAST:
+    // Just drop bitcasts between scalable vectors.
+    if (VT.isScalableVector() &&
+        Node->getOperand(0).getSimpleValueType().isScalableVector()) {
+      ReplaceUses(SDValue(Node, 0), Node->getOperand(0));
+      CurDAG->RemoveDeadNode(Node);
+      return;
+    }
+    break;
   case ISD::INSERT_SUBVECTOR: {
     SDValue V = Node->getOperand(0);
     SDValue SubV = Node->getOperand(1);
     SDLoc DL(SubV);
     auto Idx = Node->getConstantOperandVal(2);
     MVT SubVecVT = Node->getOperand(1).getSimpleValueType();
 
     // TODO: This method of selecting INSERT_SUBVECTOR should work

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat-rv32.ll

 ; LMULMAX1-NEXT:    vse32.v v25, (a1)
 ; LMULMAX1-NEXT:    vse32.v v25, (a0)
 ; LMULMAX1-NEXT:    ret
   %a = insertelement <4 x i64> undef, i64 -1, i32 0
   %b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer
   store <4 x i64> %b, <4 x i64>* %x
   ret void
 }
+
+; This requires a bitcast on RV32 due to type legalization rewriting the
+; build_vector to v8i32.
+; FIXME: We should prevent this and use the implicit sign extension of vmv.v.x
+; with SEW=64 on RV32.
+define void @splat_allones_with_use_v4i64(<4 x i64>* %x) {
+; LMULMAX2-LABEL: splat_allones_with_use_v4i64:
+; LMULMAX2:       # %bb.0:
+; LMULMAX2-NEXT:    addi a1, zero, 4
+; LMULMAX2-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; LMULMAX2-NEXT:    vle64.v v26, (a0)
+; LMULMAX2-NEXT:    addi a2, zero, 8
+; LMULMAX2-NEXT:    vsetvli a2, a2, e32,m2,ta,mu
+; LMULMAX2-NEXT:    vmv.v.i v28, -1
+; LMULMAX2-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; LMULMAX2-NEXT:    vadd.vv v26, v26, v28
+; LMULMAX2-NEXT:    vse64.v v26, (a0)
+; LMULMAX2-NEXT:    ret
+;
+; LMULMAX1-LABEL: splat_allones_with_use_v4i64:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    addi a1, zero, 2
+; LMULMAX1-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vle64.v v25, (a0)
+; LMULMAX1-NEXT:    addi a2, a0, 16
+; LMULMAX1-NEXT:    vle64.v v26, (a2)
+; LMULMAX1-NEXT:    addi a3, zero, 4
+; LMULMAX1-NEXT:    vsetvli a3, a3, e32,m1,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v27, -1
+; LMULMAX1-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vadd.vv v26, v26, v27
+; LMULMAX1-NEXT:    vadd.vv v25, v25, v27
+; LMULMAX1-NEXT:    vse64.v v25, (a0)
+; LMULMAX1-NEXT:    vse64.v v26, (a2)
+; LMULMAX1-NEXT:    ret
+  %a = load <4 x i64>, <4 x i64>* %x
+  %b = add <4 x i64> %a, <i64 -1, i64 -1, i64 -1, i64 -1>
+  store <4 x i64> %b, <4 x i64>* %x
+  ret void
+}