[RISCV] Add support loads, stores, and splats of vXi1 fixed vectors.

[craig.topper]

Summary

This refines how we determine which masks types are legal and adds
support for loads, stores, and all ones/zeros splats.

I left a fixme in store handling where I think we need to zero
extra bits if the type isn't a multiple of a byte. If I remember
right from X86 there was some case we could have a store of a
1, 2, or 4 bit mask and have a scalar zextload that then expected the
bits to be 0. Its tricky to zero the bits with RVV. We need to do
something like round VL up, zero a register, lower the VL back down,
then do a tail undisturbed move into the zero register. Another
option might be to generate a mask of 1/2/4 bits set with a VL of 8
and use that to mask off the bits.

[frasercrmck]

LGTM. I'm a little surprised by this possible requirement to zero the bytes though, unless I'm not understanding the exact conditions. Are you able to find a testcase?

[craig.topper]

In D96468#2557160, @frasercrmck wrote:

LGTM. I'm a little surprised by this possible requirement to zero the bytes though, unless I'm not understanding the exact conditions. Are you able to find a testcase?

define zeroext i2 @seteq_vv_v16i8(<2 x i8>* %x, <2 x i8>* %y) {
  %a = load <2 x i8>, <2 x i8>* %x
  %b = load <2 x i8>, <2 x i8>* %y                                                          
  %c = icmp eq <2 x i8> %a, %b
  %d = bitcast <2 x i1> %c to i2
  ret i2 %d
}

becomes this after type legalization. The bitcast is turned into a store to stack and a load.

SelectionDAG has 18 nodes:
  t0: ch = EntryToken
              t2: i64,ch = CopyFromReg t0, Register:i64 %0
            t7: v2i8,ch = load<(load 2 from %ir.x)> t0, t2, undef:i64
              t4: i64,ch = CopyFromReg t0, Register:i64 %1                                                            
            t8: v2i8,ch = load<(load 2 from %ir.y)> t0, t4, undef:i64                                                                                 
          t10: v2i1 = setcc t7, t8, seteq:ch
        t17: ch = store<(store 1 into %stack.0, align 2)> t0, t10, FrameIndex:i64<0>, undef:i64
      t22: i64,ch = load<(load 1 from %stack.0, align 2), anyext from i2> t17, FrameIndex:i64<0>, undef:i64
    t21: i64 = and t22, Constant:i64<3>
  t14: ch,glue = CopyToReg t0, Register:i64 $x10, t21
  t15: ch = RISCVISD::RET_FLAG t14, Register:i64 $x10, t14:1

After DAG combine the anyext load becomes a zextload and the t21 'and' is removed

SelectionDAG has 16 nodes:                                                                                                                                                                                                                                                           
  t0: ch = EntryToken                                                                                                                                                                                                                                                                
            t2: i64,ch = CopyFromReg t0, Register:i64 %0
          t7: v2i8,ch = load<(load 2 from %ir.x)> t0, t2, undef:i64
            t4: i64,ch = CopyFromReg t0, Register:i64 %1
          t8: v2i8,ch = load<(load 2 from %ir.y)> t0, t4, undef:i64
        t10: v2i1 = setcc t7, t8, seteq:ch
      t17: ch = store<(store 1 into %stack.0, align 2)> t0, t10, FrameIndex:i64<0>, undef:i64
    t23: i64,ch = load<(load 1 from %stack.0, align 2), zext from i2> t17, FrameIndex:i64<0>, undef:i64
  t14: ch,glue = CopyToReg t0, Register:i64 $x10, t23
  t15: ch = RISCVISD::RET_FLAG t14, Register:i64 $x10, t14:1

After op legalization the zext from i2 load becomes zext from i8, but no additional code was added to put zeros in the other 6 bits. It's just assumed they are zero.

SelectionDAG has 20 nodes:                                                                                                                                                                                                                                                           
  t0: ch = EntryToken
              t2: i64,ch = CopyFromReg t0, Register:i64 %0
            t40: nxv8i8,ch = RISCVISD::VLE_VL<(load 2 from %ir.x)> t0, t2, Constant:i64<2>
              t4: i64,ch = CopyFromReg t0, Register:i64 %1
            t37: nxv8i8,ch = RISCVISD::VLE_VL<(load 2 from %ir.y)> t0, t4, Constant:i64<2>                                                   
            t29: nxv8i1 = RISCVISD::VMSET_VL Constant:i64<2>
          t30: nxv8i1 = RISCVISD::SETCC_VL t40, t37, seteq:ch, t29, Constant:i64<2>
        t36: ch = RISCVISD::VSE_VL<(store 1 into %stack.0, align 2)> t0, t30, FrameIndex:i64<0>, Constant:i64<2>
      t32: i64,ch = load<(load 1 from %stack.0, align 2), zext from i8> t36, FrameIndex:i64<0>, undef:i64
    t34: i64 = AssertZext t32, ValueType:ch:i2                                                                                                                                     
  t14: ch,glue = CopyToReg t0, Register:i64 $x10, t34
  t15: ch = RISCVISD::RET_FLAG t14, Register:i64 $x10, t14:1

Legalization of an i2 truncstore does put zeros in those 6 bits which is why zextload has this expectation.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Subtarget.useRVVForFixedLengthVectors()) {
         // By default everything must be expanded.
         for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op)
           setOperationAction(Op, VT, Expand);
 
         // We use EXTRACT_SUBVECTOR as a "cast" from scalable to fixed.
         setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
 
         setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
-        setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
 
         setOperationAction(ISD::LOAD, VT, Custom);
         setOperationAction(ISD::STORE, VT, Custom);
+
+        // Operations below are not valid for masks.
+        if (VT.getVectorElementType() == MVT::i1)
+          continue;
+
+        setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
+
         setOperationAction(ISD::ADD, VT, Custom);
         setOperationAction(ISD::MUL, VT, Custom);
         setOperationAction(ISD::SUB, VT, Custom);
         setOperationAction(ISD::AND, VT, Custom);
         setOperationAction(ISD::OR, VT, Custom);
         setOperationAction(ISD::XOR, VT, Custom);
         setOperationAction(ISD::SDIV, VT, Custom);
         setOperationAction(ISD::SREM, VT, Custom);
static MVT getContainerForFixedLengthVector(SelectionDAG &DAG, MVT VT,
                                             const RISCVSubtarget &Subtarget) {
   assert(VT.isFixedLengthVector() &&
          DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
          "Expected legal fixed length vector!");
 
   unsigned LMul = Subtarget.getLMULForFixedLengthVector(VT);
   assert(LMul <= 8 && isPowerOf2_32(LMul) && "Unexpected LMUL!");
 
-  switch (VT.getVectorElementType().SimpleTy) {
+  MVT EltVT = VT.getVectorElementType();
+  switch (EltVT.SimpleTy) {
   default:
     llvm_unreachable("unexpected element type for RVV container");
+  case MVT::i1: {
+    // Masks are calculated assuming 8-bit elements since that's when we need
+    // the most elements.
+    unsigned EltsPerBlock = RISCV::RVVBitsPerBlock / 8;
+    return MVT::getScalableVectorVT(MVT::i1, LMul * EltsPerBlock);
+  }
   case MVT::i8:
-    return MVT::getScalableVectorVT(MVT::i8, LMul * 8);
   case MVT::i16:
-    return MVT::getScalableVectorVT(MVT::i16, LMul * 4);
   case MVT::i32:
-    return MVT::getScalableVectorVT(MVT::i32, LMul * 2);
   case MVT::i64:
-    return MVT::getScalableVectorVT(MVT::i64, LMul);
   case MVT::f16:
-    return MVT::getScalableVectorVT(MVT::f16, LMul * 4);
   case MVT::f32:
-    return MVT::getScalableVectorVT(MVT::f32, LMul * 2);
-  case MVT::f64:
-    return MVT::getScalableVectorVT(MVT::f64, LMul);
+  case MVT::f64: {
+    unsigned EltsPerBlock = RISCV::RVVBitsPerBlock / EltVT.getSizeInBits();
+    return MVT::getScalableVectorVT(EltVT, LMul * EltsPerBlock);
+  }
   }
 }
 
 // Grow V to consume an entire RVV register.
 static SDValue convertToScalableVector(EVT VT, SDValue V, SelectionDAG &DAG,
                                        const RISCVSubtarget &Subtarget) {
   assert(VT.isScalableVector() &&
          "Expected to convert into a scalable vector!");
static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
   assert(VT.isFixedLengthVector() && "Unexpected vector!");
 
   MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget);
 
   SDLoc DL(Op);
   SDValue VL =
       DAG.getConstant(VT.getVectorNumElements(), DL, Subtarget.getXLenVT());
 
+  if (VT.getVectorElementType() == MVT::i1) {
+    if (ISD::isBuildVectorAllZeros(Op.getNode())) {
+      SDValue VMClr = DAG.getNode(RISCVISD::VMCLR_VL, DL, ContainerVT, VL);
+      return convertFromScalableVector(VT, VMClr, DAG, Subtarget);
+    }
+
+    if (ISD::isBuildVectorAllOnes(Op.getNode())) {
+      SDValue VMSet = DAG.getNode(RISCVISD::VMSET_VL, DL, ContainerVT, VL);
+      return convertFromScalableVector(VT, VMSet, DAG, Subtarget);
+    }
+
+    return SDValue();
+  }
+
   if (SDValue Splat = cast<BuildVectorSDNode>(Op)->getSplatValue()) {
     unsigned Opc = VT.isFloatingPoint() ? RISCVISD::VFMV_V_F_VL
                                         : RISCVISD::VMV_V_X_VL;
     Splat = DAG.getNode(Opc, DL, ContainerVT, Splat, VL);
     return convertFromScalableVector(VT, Splat, DAG, Subtarget);
   }
 
   // Try and match an index sequence, which we can lower directly to the vid

 
 SDValue
 RISCVTargetLowering::lowerFixedLengthVectorStoreToRVV(SDValue Op,
                                                       SelectionDAG &DAG) const {
   auto *Store = cast<StoreSDNode>(Op);
 
   SDLoc DL(Op);
   MVT VT = Store->getValue().getSimpleValueType();
+
+  // FIXME: We probably need to zero any extra bits in a byte for mask stores.
+  // This is tricky to do.
+
   MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget);
 
   SDValue VL =
       DAG.getConstant(VT.getVectorNumElements(), DL, Subtarget.getXLenVT());
 
   SDValue NewValue =
       convertToScalableVector(ContainerVT, Store->getValue(), DAG, Subtarget);
   return DAG.getMemIntrinsicNode(

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

 defm PseudoVMNAND: VPseudoBinaryM_MM;
 defm PseudoVMANDNOT: VPseudoBinaryM_MM;
 defm PseudoVMXOR: VPseudoBinaryM_MM;
 defm PseudoVMOR: VPseudoBinaryM_MM;
 defm PseudoVMNOR: VPseudoBinaryM_MM;
 defm PseudoVMORNOT: VPseudoBinaryM_MM;
 defm PseudoVMXNOR: VPseudoBinaryM_MM;
 
-// Pseudo insturctions
+// Pseudo instructions
 defm PseudoVMCLR : VPseudoNullaryPseudoM<"VMXOR">;
 defm PseudoVMSET : VPseudoNullaryPseudoM<"VMXNOR">;
 
 //===----------------------------------------------------------------------===//
 // 16.2. Vector mask population count vpopc
 //===----------------------------------------------------------------------===//
 
 defm PseudoVPOPC: VPseudoUnaryS_M;

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

 // 7.4. Vector Unit-Stride Instructions
 foreach vti = AllVectors in {
   defvar load_instr = !cast<Instruction>("PseudoVLE"#vti.SEW#"_V_"#vti.LMul.MX);
   defvar store_instr = !cast<Instruction>("PseudoVSE"#vti.SEW#"_V_"#vti.LMul.MX);
   // Load
   def : Pat<(vti.Vector (riscv_vle_vl RVVBaseAddr:$rs1, (XLenVT (VLOp GPR:$vl)))),
             (load_instr RVVBaseAddr:$rs1, GPR:$vl, vti.SEW)>;
   // Store
-  def : Pat<(riscv_vse_vl (vti.Vector vti.RegClass:$rs2), RVVBaseAddr:$rs1, (XLenVT (VLOp GPR:$vl))),
+  def : Pat<(riscv_vse_vl (vti.Vector vti.RegClass:$rs2), RVVBaseAddr:$rs1,
+                          (XLenVT (VLOp GPR:$vl))),
             (store_instr vti.RegClass:$rs2, RVVBaseAddr:$rs1, GPR:$vl, vti.SEW)>;
 }
 
+foreach mti = AllMasks in {
+  defvar load_instr = !cast<Instruction>("PseudoVLE1_V_"#mti.BX);
+  defvar store_instr = !cast<Instruction>("PseudoVSE1_V_"#mti.BX);
+  def : Pat<(mti.Mask (riscv_vle_vl RVVBaseAddr:$rs1, (XLenVT (VLOp GPR:$vl)))),
+            (load_instr RVVBaseAddr:$rs1, GPR:$vl, mti.SEW)>;
+  def : Pat<(riscv_vse_vl (mti.Mask VR:$rs2), RVVBaseAddr:$rs1,
+                          (XLenVT (VLOp GPR:$vl))),
+            (store_instr VR:$rs2, RVVBaseAddr:$rs1, GPR:$vl, mti.SEW)>;
+}
+
 // 12.1. Vector Single-Width Integer Add and Subtract
 defm "" : VPatBinaryVL_VV_VX_VI<riscv_add_vl, "PseudoVADD">;
 defm "" : VPatBinaryVL_VV_VX<riscv_sub_vl, "PseudoVSUB">;
 
 // 12.5. Vector Bitwise Logical Instructions
 defm "" : VPatBinaryVL_VV_VX_VI<riscv_and_vl, "PseudoVAND">;
 defm "" : VPatBinaryVL_VV_VX_VI<riscv_or_vl,  "PseudoVOR">;
 defm "" : VPatBinaryVL_VV_VX_VI<riscv_xor_vl, "PseudoVXOR">;
foreach vti = AllFloatVectors in {
   def : Pat<(riscv_fneg_vl (vti.Vector vti.RegClass:$rs), (vti.Mask true_mask),
                            (XLenVT (VLOp GPR:$vl))),
             (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX)
                  vti.RegClass:$rs, vti.RegClass:$rs, GPR:$vl, vti.SEW)>;
 }
 
 } // Predicates = [HasStdExtV, HasStdExtF]
 
+// 16.1 Vector Mask-Register Logical Instructions
+let Predicates = [HasStdExtV] in {
+
+foreach mti = AllMasks in {
+  def : Pat<(mti.Mask (riscv_vmset_vl (XLenVT (VLOp GPR:$vl)))),
+            (!cast<Instruction>("PseudoVMSET_M_" # mti.BX) GPR:$vl, mti.SEW)>;
+  def : Pat<(mti.Mask (riscv_vmclr_vl (XLenVT (VLOp GPR:$vl)))),
+            (!cast<Instruction>("PseudoVMCLR_M_" # mti.BX) GPR:$vl, mti.SEW)>;
+}
+
+} // Predicates = [HasStdExtV]
+
 // 17.4. Vector Register GAther Instruction
 let Predicates = [HasStdExtV] in {
 
 foreach vti = AllIntegerVectors in {
   def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1,
                                               (vti.Mask true_mask),
                                               (XLenVT (VLOp GPR:$vl)))),
             (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX)

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

 }
 
 bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
   return hasStdExtV() && getMinRVVVectorSizeInBits() != 0;
 }
 
 unsigned RISCVSubtarget::getLMULForFixedLengthVector(MVT VT) const {
   unsigned MinVLen = getMinRVVVectorSizeInBits();
+
+  // Masks only occupy a single register. An LMUL==1 operation can only use
+  // at most 1/8 of the register. Only an LMUL==8 operaton on i8 types can
+  // use the whole register.
+  if (VT.getVectorElementType() == MVT::i1)
+    MinVLen /= 8;
+
   return divideCeil(VT.getSizeInBits(), MinVLen);
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64
+
+define void @load_store_v1i1(<1 x i1>* %x, <1 x i1>* %y) {
+; CHECK-LABEL: load_store_v1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a2, zero, 1
+; CHECK-NEXT:    vsetvli a2, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vle1.v v25, (a0)
+; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <1 x i1>, <1 x i1>* %x
+  store <1 x i1> %a, <1 x i1>* %y
+  ret void
+}
+
+define void @load_store_v2i1(<2 x i1>* %x, <2 x i1>* %y) {
+; CHECK-LABEL: load_store_v2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a2, zero, 2
+; CHECK-NEXT:    vsetvli a2, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vle1.v v25, (a0)
+; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <2 x i1>, <2 x i1>* %x
+  store <2 x i1> %a, <2 x i1>* %y
+  ret void
+}
+
+define void @load_store_v4i1(<4 x i1>* %x, <4 x i1>* %y) {
+; CHECK-LABEL: load_store_v4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a2, zero, 4
+; CHECK-NEXT:    vsetvli a2, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vle1.v v25, (a0)
+; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <4 x i1>, <4 x i1>* %x
+  store <4 x i1> %a, <4 x i1>* %y
+  ret void
+}
+
+define void @load_store_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
+; CHECK-LABEL: load_store_v8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a2, zero, 8
+; CHECK-NEXT:    vsetvli a2, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vle1.v v25, (a0)
+; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <8 x i1>, <8 x i1>* %x
+  store <8 x i1> %a, <8 x i1>* %y
+  ret void
+}
+
+define void @load_store_v16i1(<16 x i1>* %x, <16 x i1>* %y) {
+; CHECK-LABEL: load_store_v16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a2, zero, 16
+; CHECK-NEXT:    vsetvli a2, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vle1.v v25, (a0)
+; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <16 x i1>, <16 x i1>* %x
+  store <16 x i1> %a, <16 x i1>* %y
+  ret void
+}
+
+define void @load_store_v32i1(<32 x i1>* %x, <32 x i1>* %y) {
+; LMULMAX2-LABEL: load_store_v32i1:
+; LMULMAX2:       # %bb.0:
+; LMULMAX2-NEXT:    addi a2, zero, 32
+; LMULMAX2-NEXT:    vsetvli a2, a2, e8,m2,ta,mu
+; LMULMAX2-NEXT:    vle1.v v25, (a0)
+; LMULMAX2-NEXT:    vse1.v v25, (a1)
+; LMULMAX2-NEXT:    ret
+;
+; LMULMAX1-RV32-LABEL: load_store_v32i1:
+; LMULMAX1-RV32:       # %bb.0:
+; LMULMAX1-RV32-NEXT:    lw a0, 0(a0)
+; LMULMAX1-RV32-NEXT:    sw a0, 0(a1)
+; LMULMAX1-RV32-NEXT:    ret
+;
+; LMULMAX1-RV64-LABEL: load_store_v32i1:
+; LMULMAX1-RV64:       # %bb.0:
+; LMULMAX1-RV64-NEXT:    lw a0, 0(a0)
+; LMULMAX1-RV64-NEXT:    sw a0, 0(a1)
+; LMULMAX1-RV64-NEXT:    ret
+  %a = load <32 x i1>, <32 x i1>* %x
+  store <32 x i1> %a, <32 x i1>* %y
+  ret void
+}

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64
+
+define void @splat_ones_v1i1(<1 x i1>* %x) {
+; CHECK-LABEL: splat_ones_v1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a1, zero, 1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vmset.m v25
+; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    ret
+  store <1 x i1> <i1 1>, <1 x i1>* %x
+  ret void
+}
+
+define void @splat_zeros_v2i1(<2 x i1>* %x) {
+; CHECK-LABEL: splat_zeros_v2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a1, zero, 2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vmclr.m v25
+; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    ret
+  store <2 x i1> zeroinitializer, <2 x i1>* %x
+  ret void
+}
+
+define void @splat_ones_v4i1(<4 x i1>* %x) {
+; CHECK-LABEL: splat_ones_v4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a1, zero, 4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vmset.m v25
+; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    ret
+  store <4 x i1> <i1 1, i1 1, i1 1, i1 1>, <4 x i1>* %x
+  ret void
+}
+
+define void @splat_zeros_v8i1(<8 x i1>* %x) {
+; CHECK-LABEL: splat_zeros_v8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a1, zero, 8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vmclr.m v25
+; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    ret
+  store <8 x i1> zeroinitializer, <8 x i1>* %x
+  ret void
+}
+
+define void @splat_ones_v16i1(<16 x i1>* %x) {
+; CHECK-LABEL: splat_ones_v16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a1, zero, 16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vmset.m v25
+; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    ret
+  store <16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <16 x i1>* %x
+  ret void
+}
+
+define void @splat_zeros_v32i1(<32 x i1>* %x) {
+; LMULMAX2-LABEL: splat_zeros_v32i1:
+; LMULMAX2:       # %bb.0:
+; LMULMAX2-NEXT:    addi a1, zero, 32
+; LMULMAX2-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; LMULMAX2-NEXT:    vmclr.m v25
+; LMULMAX2-NEXT:    vse1.v v25, (a0)
+; LMULMAX2-NEXT:    ret
+;
+; LMULMAX1-RV32-LABEL: splat_zeros_v32i1:
+; LMULMAX1-RV32:       # %bb.0:
+; LMULMAX1-RV32-NEXT:    addi a1, a0, 2
+; LMULMAX1-RV32-NEXT:    addi a2, zero, 16
+; LMULMAX1-RV32-NEXT:    vsetvli a2, a2, e8,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vmclr.m v25
+; LMULMAX1-RV32-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-RV32-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-RV32-NEXT:    ret
+;
+; LMULMAX1-RV64-LABEL: splat_zeros_v32i1:
+; LMULMAX1-RV64:       # %bb.0:
+; LMULMAX1-RV64-NEXT:    addi a1, a0, 2
+; LMULMAX1-RV64-NEXT:    addi a2, zero, 16
+; LMULMAX1-RV64-NEXT:    vsetvli a2, a2, e8,m1,ta,mu
+; LMULMAX1-RV64-NEXT:    vmclr.m v25
+; LMULMAX1-RV64-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-RV64-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-RV64-NEXT:    ret
+  store <32 x i1> zeroinitializer, <32 x i1>* %x
+  ret void
+}
+
+define void @splat_ones_v64i1(<64 x i1>* %x) {
+; LMULMAX2-LABEL: splat_ones_v64i1:
+; LMULMAX2:       # %bb.0:
+; LMULMAX2-NEXT:    addi a1, a0, 4
+; LMULMAX2-NEXT:    addi a2, zero, 32
+; LMULMAX2-NEXT:    vsetvli a2, a2, e8,m2,ta,mu
+; LMULMAX2-NEXT:    vmset.m v25
+; LMULMAX2-NEXT:    vse1.v v25, (a1)
+; LMULMAX2-NEXT:    vse1.v v25, (a0)
+; LMULMAX2-NEXT:    ret
+;
+; LMULMAX1-RV32-LABEL: splat_ones_v64i1:
+; LMULMAX1-RV32:       # %bb.0:
+; LMULMAX1-RV32-NEXT:    addi a1, a0, 6
+; LMULMAX1-RV32-NEXT:    addi a2, zero, 16
+; LMULMAX1-RV32-NEXT:    vsetvli a2, a2, e8,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vmset.m v25
+; LMULMAX1-RV32-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-RV32-NEXT:    addi a1, a0, 4
+; LMULMAX1-RV32-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-RV32-NEXT:    addi a1, a0, 2
+; LMULMAX1-RV32-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-RV32-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-RV32-NEXT:    ret
+;
+; LMULMAX1-RV64-LABEL: splat_ones_v64i1:
+; LMULMAX1-RV64:       # %bb.0:
+; LMULMAX1-RV64-NEXT:    addi a1, a0, 6
+; LMULMAX1-RV64-NEXT:    addi a2, zero, 16
+; LMULMAX1-RV64-NEXT:    vsetvli a2, a2, e8,m1,ta,mu
+; LMULMAX1-RV64-NEXT:    vmset.m v25
+; LMULMAX1-RV64-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-RV64-NEXT:    addi a1, a0, 4
+; LMULMAX1-RV64-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-RV64-NEXT:    addi a1, a0, 2
+; LMULMAX1-RV64-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-RV64-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-RV64-NEXT:    ret
+  store <64 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <64 x i1>* %x
+  ret void
+}