[RISCV] Add support for integer fixed vector setcc

[craig.topper]

Summary

I believe I've covered all orderings of splat operands here. Better
canonicalization in lowering might help reduce this. I did not handle
the immediate adjustments needed for set(u)gt/set(u)lt.

Testing here is limited to byte types because the scalable vector
type used for masks for the store is calculated assuming 8 byte
elements. But for the setcc its based on the element count of the
container type for the setcc input. So they don't agree. We'll need
to enhanced D96352 to handle this I think.

[craig.topper]

Add mask load pattern even though its not tested. I think I'll try to split this patch up.

[craig.topper]

Remove masked load/store handling. That's been moved to another patch

[frasercrmck]

LGTM.

[craig.topper]

Use the splat ComplexPatterns that were updated for vmv_v_x_vl in the integer binary operation patch.

llvm/lib/Target/RISCV/RISCVISelLowering.h

enum NodeType : unsigned {
   VECREDUCE_UMIN,
   VECREDUCE_SMIN,
   VECREDUCE_AND,
   VECREDUCE_OR,
   VECREDUCE_XOR,
   VECREDUCE_FADD,
   VECREDUCE_SEQ_FADD,
 
-  // Vector binary and unary ops with VL as a third operand.
+  // Vector binary and unary ops with a mask as a third operand, and VL as a
+  // fourth operand.
   // FIXME: Can we replace these with ISD::VP_*?
   ADD_VL,
   AND_VL,
   MUL_VL,
   OR_VL,
   SDIV_VL,
   SHL_VL,
   SREM_VL,
enum NodeType : unsigned {
   FDIV_VL,
   FNEG_VL,
   FMA_VL,
   SMIN_VL,
   SMAX_VL,
   UMIN_VL,
   UMAX_VL,
 
+  // Vector compare producing a mask. Fourth operand is input mask. Fifth
+  // operand is VL.
+  SETCC_VL,
+
   // Set mask vector to all zeros or ones.
   VMCLR_VL,
   VMSET_VL,
 
   // Matches the semantics of vrgather.vx with an extra operand for VL.
   VRGATHER_VX_VL,
 
   // Memory opcodes start here.
private:
   SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG,
                             unsigned NewOpc) const;
 
   bool isEligibleForTailCallOptimization(
       CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
       const SmallVector<CCValAssign, 16> &ArgLocs) const;
 
   /// Generate error diagnostics if any register used by CC has been marked

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Subtarget.useRVVForFixedLengthVectors()) {
         // We use EXTRACT_SUBVECTOR as a "cast" from scalable to fixed.
         setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
 
         setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
 
         setOperationAction(ISD::LOAD, VT, Custom);
         setOperationAction(ISD::STORE, VT, Custom);
 
-        // Operations below are not valid for masks.
-        if (VT.getVectorElementType() == MVT::i1)
+        // Operations below are different for between masks and other vectors.
+        if (VT.getVectorElementType() == MVT::i1) {
+          setOperationAction(ISD::SETCC, VT, Custom);
           continue;
+        }
 
         setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
 
         setOperationAction(ISD::ADD, VT, Custom);
         setOperationAction(ISD::MUL, VT, Custom);
         setOperationAction(ISD::SUB, VT, Custom);
         setOperationAction(ISD::AND, VT, Custom);
         setOperationAction(ISD::OR, VT, Custom);
RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   }
 }
 
 EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL,
                                             LLVMContext &Context,
                                             EVT VT) const {
   if (!VT.isVector())
     return getPointerTy(DL);
-  if (Subtarget.hasStdExtV() && VT.isScalableVector())
+  if (Subtarget.hasStdExtV() &&
+      (VT.isScalableVector() || Subtarget.useRVVForFixedLengthVectors()))
     return EVT::getVectorVT(Context, MVT::i1, VT.getVectorElementCount());
   return VT.changeVectorElementTypeToInteger();
 }
 
 bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
                                              const CallInst &I,
                                              MachineFunction &MF,
                                              unsigned Intrinsic) const {
SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   case ISD::BUILD_VECTOR:
     return lowerBUILD_VECTOR(Op, DAG, Subtarget);
   case ISD::VECTOR_SHUFFLE:
     return lowerVECTOR_SHUFFLE(Op, DAG, Subtarget);
   case ISD::LOAD:
     return lowerFixedLengthVectorLoadToRVV(Op, DAG);
   case ISD::STORE:
     return lowerFixedLengthVectorStoreToRVV(Op, DAG);
+  case ISD::SETCC:
+    return lowerFixedLengthVectorSetccToRVV(Op, DAG);
   case ISD::ADD:
     return lowerToScalableOp(Op, DAG, RISCVISD::ADD_VL);
   case ISD::SUB:
     return lowerToScalableOp(Op, DAG, RISCVISD::SUB_VL);
   case ISD::MUL:
     return lowerToScalableOp(Op, DAG, RISCVISD::MUL_VL);
   case ISD::AND:
     return lowerToScalableOp(Op, DAG, RISCVISD::AND_VL);
RISCVTargetLowering::lowerFixedLengthVectorStoreToRVV(SDValue Op,
   SDValue NewValue =
       convertToScalableVector(ContainerVT, Store->getValue(), DAG, Subtarget);
   return DAG.getMemIntrinsicNode(
       RISCVISD::VSE_VL, DL, DAG.getVTList(MVT::Other),
       {Store->getChain(), NewValue, Store->getBasePtr(), VL},
       Store->getMemoryVT(), Store->getMemOperand());
 }
 
+SDValue
+RISCVTargetLowering::lowerFixedLengthVectorSetccToRVV(SDValue Op,
+                                                      SelectionDAG &DAG) const {
+  MVT InVT = Op.getOperand(0).getSimpleValueType();
+  MVT ContainerVT = getContainerForFixedLengthVector(DAG, InVT, Subtarget);
+
+  MVT VT = Op.getSimpleValueType();
+
+  SDValue Op1 =
+      convertToScalableVector(ContainerVT, Op.getOperand(0), DAG, Subtarget);
+  SDValue Op2 =
+      convertToScalableVector(ContainerVT, Op.getOperand(1), DAG, Subtarget);
+
+  SDLoc DL(Op);
+  SDValue VL =
+      DAG.getConstant(VT.getVectorNumElements(), DL, Subtarget.getXLenVT());
+
+  MVT MaskVT = MVT::getVectorVT(MVT::i1, ContainerVT.getVectorElementCount());
+  SDValue Mask = DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL);
+  SDValue Cmp = DAG.getNode(RISCVISD::SETCC_VL, DL, MaskVT, Op1, Op2,
+                            Op.getOperand(2), Mask, VL);
+
+  return convertFromScalableVector(VT, Cmp, DAG, Subtarget);
+}
+
 SDValue RISCVTargetLowering::lowerToScalableOp(SDValue Op, SelectionDAG &DAG,
                                                unsigned NewOpc) const {
   MVT VT = Op.getSimpleValueType();
   assert(useRVVForFixedLengthVectorVT(VT) &&
          "Only expected to lower fixed length vector operation!");
   MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget);
 
   // Create list of operands by converting existing ones to scalable types.
#define NODE_NAME_CASE(NODE)                                                   \
   NODE_NAME_CASE(FMUL_VL)
   NODE_NAME_CASE(FDIV_VL)
   NODE_NAME_CASE(FNEG_VL)
   NODE_NAME_CASE(FMA_VL)
   NODE_NAME_CASE(SMIN_VL)
   NODE_NAME_CASE(SMAX_VL)
   NODE_NAME_CASE(UMIN_VL)
   NODE_NAME_CASE(UMAX_VL)
+  NODE_NAME_CASE(SETCC_VL)
   NODE_NAME_CASE(VMCLR_VL)
   NODE_NAME_CASE(VMSET_VL)
   NODE_NAME_CASE(VRGATHER_VX_VL)
   NODE_NAME_CASE(VLE_VL)
   NODE_NAME_CASE(VSE_VL)
   }
   // clang-format on
   return nullptr;
bool RISCVTargetLowering::useRVVForFixedLengthVectorVT(MVT VT) const {
   if (!Subtarget.useRVVForFixedLengthVectors())
     return false;
 
   if (!VT.isFixedLengthVector())
     return false;
 
   // Don't use RVV for vectors we cannot scalarize if required.
   switch (VT.getVectorElementType().SimpleTy) {
+  // i1 is supported but has different rules.
   default:
     return false;
   case MVT::i1:
+    // Masks can only use a single register.
+    if (VT.getVectorNumElements() > Subtarget.getMinRVVVectorSizeInBits())
+      return false;
+    break;
   case MVT::i8:
   case MVT::i16:
   case MVT::i32:
   case MVT::i64:
     break;
   case MVT::f16:
     if (!Subtarget.hasStdExtZfh())
       return false;

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

def SDT_RISCVVecFMA_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>,
                                               SDTCisSameAs<0, 2>,
                                               SDTCisSameAs<0, 3>,
                                               SDTCisVec<0>, SDTCisFP<0>,
                                               SDTCVecEltisVT<4, i1>,
                                               SDTCisSameNumEltsAs<0, 4>,
                                               SDTCisVT<5, XLenVT>]>;
 def riscv_fma_vl : SDNode<"RISCVISD::FMA_VL", SDT_RISCVVecFMA_VL>;
 
+def riscv_setcc_vl : SDNode<"RISCVISD::SETCC_VL",
+                            SDTypeProfile<1, 5, [SDTCisVec<0>,
+                                                 SDTCVecEltisVT<0, i1>,
+                                                 SDTCisVec<1>,
+                                                 SDTCisSameNumEltsAs<0, 1>,
+                                                 SDTCisSameAs<1, 2>,
+                                                 SDTCisVT<3, OtherVT>,
+                                                 SDTCisSameAs<0, 4>,
+                                                 SDTCisVT<5, XLenVT>]>>;
+
 def riscv_vrgather_vx_vl : SDNode<"RISCVISD::VRGATHER_VX_VL",
                                   SDTypeProfile<1, 4, [SDTCisVec<0>,
                                                        SDTCisSameAs<0, 1>,
                                                        SDTCisVT<2, XLenVT>,
                                                        SDTCVecEltisVT<3, i1>,
                                                        SDTCisSameNumEltsAs<0, 3>,
                                                        SDTCisVT<4, XLenVT>]>>;
 
def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2),
                                 fvti.RegClass:$rs1,
                                 (fvti.Mask true_mask),
                                 (XLenVT (VLOp GPR:$vl)))),
               (!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX)
                            fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2,
                            GPR:$vl, fvti.SEW)>;
 }
 
+multiclass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name,
+                                 CondCode cc> {
+  def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
+                                      vti.RegClass:$rs2, cc,
+                                      (vti.Mask true_mask),
+                                      (XLenVT (VLOp GPR:$vl)))),
+            (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
+                         vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl,
+                         vti.SEW)>;
+}
+
+// Inherits from VPatIntegerSetCCVL_VV and adds a pattern with operands swapped.
+multiclass VPatIntegerSetCCVL_VV_Swappable<VTypeInfo vti, string instruction_name,
+                                           CondCode cc, CondCode invcc> :
+  VPatIntegerSetCCVL_VV<vti, instruction_name, cc> {
+  def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2),
+                                      vti.RegClass:$rs1, invcc,
+                                      (vti.Mask true_mask),
+                                      (XLenVT (VLOp GPR:$vl)))),
+            (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
+                         vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl,
+                         vti.SEW)>;
+}
+
+multiclass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_name,
+                                           CondCode cc, CondCode invcc> {
+  defvar instruction = !cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX);
+  def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
+                                      (SplatPat GPR:$rs2), cc,
+                                      (vti.Mask true_mask),
+                                      (XLenVT (VLOp GPR:$vl)))),
+            (instruction vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.SEW)>;
+  def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat GPR:$rs2),
+                                      (vti.Vector vti.RegClass:$rs1), invcc,
+                                      (vti.Mask true_mask),
+                                      (XLenVT (VLOp GPR:$vl)))),
+            (instruction vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.SEW)>;
+}
+
+multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name,
+                                           CondCode cc, CondCode invcc> {
+  defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX);
+  defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5");
+  def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
+                                      (SplatPat_simm5 simm5:$rs2), cc,
+                                      (vti.Mask true_mask),
+                                      (XLenVT (VLOp GPR:$vl)))),
+            (instruction vti.RegClass:$rs1, XLenVT:$rs2, GPR:$vl, vti.SEW)>;
+  def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2),
+                                      (vti.Vector vti.RegClass:$rs1), invcc,
+                                      (vti.Mask true_mask),
+                                      (XLenVT (VLOp GPR:$vl)))),
+            (instruction vti.RegClass:$rs1, simm5:$rs2, GPR:$vl, vti.SEW)>;
+}
+
 //===----------------------------------------------------------------------===//
 // Patterns.
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtV] in {
 
 // 7.4. Vector Unit-Stride Instructions
 foreach vti = AllVectors in {

 defm "" : VPatBinaryVL_VV_VX_VI<riscv_or_vl,  "PseudoVOR">;
 defm "" : VPatBinaryVL_VV_VX_VI<riscv_xor_vl, "PseudoVXOR">;
 
 // 12.6. Vector Single-Width Bit Shift Instructions
 defm "" : VPatBinaryVL_VV_VX_VI<riscv_shl_vl, "PseudoVSLL", uimm5>;
 defm "" : VPatBinaryVL_VV_VX_VI<riscv_srl_vl, "PseudoVSRL", uimm5>;
 defm "" : VPatBinaryVL_VV_VX_VI<riscv_sra_vl, "PseudoVSRA", uimm5>;
 
+// 12.8. Vector Integer Comparison Instructions
+foreach vti = AllIntegerVectors in {
+  defm "" : VPatIntegerSetCCVL_VV<vti, "PseudoVMSEQ", SETEQ>;
+  defm "" : VPatIntegerSetCCVL_VV<vti, "PseudoVMSNE", SETNE>;
+
+  defm "" : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLT",  SETLT,  SETGT>;
+  defm "" : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;
+  defm "" : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLE",  SETLE,  SETGE>;
+  defm "" : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
+
+  defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSEQ",  SETEQ,  SETEQ>;
+  defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSNE",  SETNE,  SETNE>;
+  defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLT",  SETLT,  SETGT>;
+  defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;
+  defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLE",  SETLE,  SETGE>;
+  defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
+  defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGT",  SETGT,  SETLT>;
+  defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
+  // There is no VMSGE(U)_VX instruction
+
+  // FIXME: Support immediate forms of these by choosing SGT and decrementing
+  // the immediate
+  defm "" : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSEQ",  SETEQ,  SETEQ>;
+  defm "" : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSNE",  SETNE,  SETNE>;
+  defm "" : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLE",  SETLE,  SETGE>;
+  defm "" : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
+} // foreach vti = AllIntegerVectors
+
 // 12.9. Vector Integer Min/Max Instructions
 defm "" : VPatBinaryVL_VV_VX<riscv_umin_vl, "PseudoVMINU">;
 defm "" : VPatBinaryVL_VV_VX<riscv_smin_vl, "PseudoVMIN">;
 defm "" : VPatBinaryVL_VV_VX<riscv_umax_vl, "PseudoVMAXU">;
 defm "" : VPatBinaryVL_VV_VX<riscv_smax_vl, "PseudoVMAX">;
 
 // 12.10. Vector Single-Width Integer Multiply Instructions
 defm "" : VPatBinaryVL_VV_VX<riscv_mul_vl, "PseudoVMUL">;

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+
+; FIXME: We use exclusively byte types here because the MVT we use for the
+; stores is calculated assuming byte elements. We need to deal with mismatched
+; subvector "casts" to make other elements work.
+
+define void @seteq_vv_v16i8(<16 x i8>* %x, <16 x i8>* %y, <16 x i1>* %z) {
+; CHECK-LABEL: seteq_vv_v16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 16
+; CHECK-NEXT:    vsetvli a3, a3, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vle8.v v26, (a1)
+; CHECK-NEXT:    vmseq.vv v27, v25, v26
+; CHECK-NEXT:    vse1.v v27, (a2)
+; CHECK-NEXT:    ret
+  %a = load <16 x i8>, <16 x i8>* %x
+  %b = load <16 x i8>, <16 x i8>* %y
+  %c = icmp eq <16 x i8> %a, %b
+  store <16 x i1> %c, <16 x i1>* %z
+  ret void
+}
+
+define void @setne_vv_v32i8(<32 x i8>* %x, <32 x i8>* %y, <32 x i1>* %z) {
+; CHECK-LABEL: setne_vv_v32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 32
+; CHECK-NEXT:    vsetvli a3, a3, e8,m2,ta,mu
+; CHECK-NEXT:    vle8.v v26, (a0)
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vmsne.vv v25, v26, v28
+; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    ret
+  %a = load <32 x i8>, <32 x i8>* %x
+  %b = load <32 x i8>, <32 x i8>* %y
+  %c = icmp ne <32 x i8> %a, %b
+  store <32 x i1> %c, <32 x i1>* %z
+  ret void
+}
+
+define void @setgt_vv_v64i8(<64 x i8>* %x, <64 x i8>* %y, <64 x i1>* %z) {
+; CHECK-LABEL: setgt_vv_v64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 64
+; CHECK-NEXT:    vsetvli a3, a3, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a0)
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmslt.vv v25, v8, v28
+; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    ret
+  %a = load <64 x i8>, <64 x i8>* %x
+  %b = load <64 x i8>, <64 x i8>* %y
+  %c = icmp sgt <64 x i8> %a, %b
+  store <64 x i1> %c, <64 x i1>* %z
+  ret void
+}
+
+define void @setlt_vv_v128i8(<128 x i8>* %x, <128 x i8>* %y, <128 x i1>* %z) {
+; CHECK-LABEL: setlt_vv_v128i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 128
+; CHECK-NEXT:    vsetvli a3, a3, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vle8.v v16, (a1)
+; CHECK-NEXT:    vmslt.vv v25, v8, v16
+; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    ret
+  %a = load <128 x i8>, <128 x i8>* %x
+  %b = load <128 x i8>, <128 x i8>* %y
+  %c = icmp slt <128 x i8> %a, %b
+  store <128 x i1> %c, <128 x i1>* %z
+  ret void
+}
+
+define void @setge_vv_v8i8(<8 x i8>* %x, <8 x i8>* %y, <8 x i1>* %z) {
+; CHECK-LABEL: setge_vv_v8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 8
+; CHECK-NEXT:    vsetvli a3, a3, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vle8.v v26, (a1)
+; CHECK-NEXT:    vmsle.vv v27, v26, v25
+; CHECK-NEXT:    vse1.v v27, (a2)
+; CHECK-NEXT:    ret
+  %a = load <8 x i8>, <8 x i8>* %x
+  %b = load <8 x i8>, <8 x i8>* %y
+  %c = icmp sge <8 x i8> %a, %b
+  store <8 x i1> %c, <8 x i1>* %z
+  ret void
+}
+
+define void @setle_vv_v16i8(<16 x i8>* %x, <16 x i8>* %y, <16 x i1>* %z) {
+; CHECK-LABEL: setle_vv_v16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 16
+; CHECK-NEXT:    vsetvli a3, a3, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vle8.v v26, (a1)
+; CHECK-NEXT:    vmsle.vv v27, v25, v26
+; CHECK-NEXT:    vse1.v v27, (a2)
+; CHECK-NEXT:    ret
+  %a = load <16 x i8>, <16 x i8>* %x
+  %b = load <16 x i8>, <16 x i8>* %y
+  %c = icmp sle <16 x i8> %a, %b
+  store <16 x i1> %c, <16 x i1>* %z
+  ret void
+}
+
+define void @setugt_vv_v32i8(<32 x i8>* %x, <32 x i8>* %y, <32 x i1>* %z) {
+; CHECK-LABEL: setugt_vv_v32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 32
+; CHECK-NEXT:    vsetvli a3, a3, e8,m2,ta,mu
+; CHECK-NEXT:    vle8.v v26, (a0)
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vmsltu.vv v25, v28, v26
+; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    ret
+  %a = load <32 x i8>, <32 x i8>* %x
+  %b = load <32 x i8>, <32 x i8>* %y
+  %c = icmp ugt <32 x i8> %a, %b
+  store <32 x i1> %c, <32 x i1>* %z
+  ret void
+}
+
+define void @setult_vv_v64i8(<64 x i8>* %x, <64 x i8>* %y, <64 x i1>* %z) {
+; CHECK-LABEL: setult_vv_v64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 64
+; CHECK-NEXT:    vsetvli a3, a3, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a0)
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmsltu.vv v25, v28, v8
+; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    ret
+  %a = load <64 x i8>, <64 x i8>* %x
+  %b = load <64 x i8>, <64 x i8>* %y
+  %c = icmp ult <64 x i8> %a, %b
+  store <64 x i1> %c, <64 x i1>* %z
+  ret void
+}
+
+define void @setuge_vv_v128i8(<128 x i8>* %x, <128 x i8>* %y, <128 x i1>* %z) {
+; CHECK-LABEL: setuge_vv_v128i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 128
+; CHECK-NEXT:    vsetvli a3, a3, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vle8.v v16, (a1)
+; CHECK-NEXT:    vmsleu.vv v25, v16, v8
+; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    ret
+  %a = load <128 x i8>, <128 x i8>* %x
+  %b = load <128 x i8>, <128 x i8>* %y
+  %c = icmp uge <128 x i8> %a, %b
+  store <128 x i1> %c, <128 x i1>* %z
+  ret void
+}
+
+define void @setule_vv_v8i8(<8 x i8>* %x, <8 x i8>* %y, <8 x i1>* %z) {
+; CHECK-LABEL: setule_vv_v8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 8
+; CHECK-NEXT:    vsetvli a3, a3, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vle8.v v26, (a1)
+; CHECK-NEXT:    vmsleu.vv v27, v25, v26
+; CHECK-NEXT:    vse1.v v27, (a2)
+; CHECK-NEXT:    ret
+  %a = load <8 x i8>, <8 x i8>* %x
+  %b = load <8 x i8>, <8 x i8>* %y
+  %c = icmp ule <8 x i8> %a, %b
+  store <8 x i1> %c, <8 x i1>* %z
+  ret void
+}
+
+define void @seteq_vx_v16i8(<16 x i8>* %x, i8 %y, <16 x i1>* %z) {
+; CHECK-LABEL: seteq_vx_v16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 16
+; CHECK-NEXT:    vsetvli a3, a3, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vmseq.vx v26, v25, a1
+; CHECK-NEXT:    vse1.v v26, (a2)
+; CHECK-NEXT:    ret
+  %a = load <16 x i8>, <16 x i8>* %x
+  %b = insertelement <16 x i8> undef, i8 %y, i32 0
+  %c = shufflevector <16 x i8> %b, <16 x i8> undef, <16 x i32> zeroinitializer
+  %d = icmp eq <16 x i8> %a, %c
+  store <16 x i1> %d, <16 x i1>* %z
+  ret void
+}
+
+define void @setne_vx_v32i8(<32 x i8>* %x, i8 %y, <32 x i1>* %z) {
+; CHECK-LABEL: setne_vx_v32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 32
+; CHECK-NEXT:    vsetvli a3, a3, e8,m2,ta,mu
+; CHECK-NEXT:    vle8.v v26, (a0)
+; CHECK-NEXT:    vmsne.vx v25, v26, a1
+; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    ret
+  %a = load <32 x i8>, <32 x i8>* %x
+  %b = insertelement <32 x i8> undef, i8 %y, i32 0
+  %c = shufflevector <32 x i8> %b, <32 x i8> undef, <32 x i32> zeroinitializer
+  %d = icmp ne <32 x i8> %a, %c
+  store <32 x i1> %d, <32 x i1>* %z
+  ret void
+}
+
+define void @setgt_vx_v64i8(<64 x i8>* %x, i8 %y, <64 x i1>* %z) {
+; CHECK-LABEL: setgt_vx_v64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 64
+; CHECK-NEXT:    vsetvli a3, a3, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a0)
+; CHECK-NEXT:    vmsgt.vx v25, v28, a1
+; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    ret
+  %a = load <64 x i8>, <64 x i8>* %x
+  %b = insertelement <64 x i8> undef, i8 %y, i32 0
+  %c = shufflevector <64 x i8> %b, <64 x i8> undef, <64 x i32> zeroinitializer
+  %d = icmp sgt <64 x i8> %a, %c
+  store <64 x i1> %d, <64 x i1>* %z
+  ret void
+}
+
+define void @setlt_vx_v128i8(<128 x i8>* %x, i8 %y, <128 x i1>* %z) {
+; CHECK-LABEL: setlt_vx_v128i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 128
+; CHECK-NEXT:    vsetvli a3, a3, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vmslt.vx v25, v8, a1
+; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    ret
+  %a = load <128 x i8>, <128 x i8>* %x
+  %b = insertelement <128 x i8> undef, i8 %y, i32 0
+  %c = shufflevector <128 x i8> %b, <128 x i8> undef, <128 x i32> zeroinitializer
+  %d = icmp slt <128 x i8> %a, %c
+  store <128 x i1> %d, <128 x i1>* %z
+  ret void
+}
+
+define void @setge_vx_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) {
+; CHECK-LABEL: setge_vx_v8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 8
+; CHECK-NEXT:    vsetvli a3, a3, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vmv.v.x v26, a1
+; CHECK-NEXT:    vmsle.vv v27, v26, v25
+; CHECK-NEXT:    vse1.v v27, (a2)
+; CHECK-NEXT:    ret
+  %a = load <8 x i8>, <8 x i8>* %x
+  %b = insertelement <8 x i8> undef, i8 %y, i32 0
+  %c = shufflevector <8 x i8> %b, <8 x i8> undef, <8 x i32> zeroinitializer
+  %d = icmp sge <8 x i8> %a, %c
+  store <8 x i1> %d, <8 x i1>* %z
+  ret void
+}
+
+define void @setle_vx_v16i8(<16 x i8>* %x, i8 %y, <16 x i1>* %z) {
+; CHECK-LABEL: setle_vx_v16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 16
+; CHECK-NEXT:    vsetvli a3, a3, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vmsle.vx v26, v25, a1
+; CHECK-NEXT:    vse1.v v26, (a2)
+; CHECK-NEXT:    ret
+  %a = load <16 x i8>, <16 x i8>* %x
+  %b = insertelement <16 x i8> undef, i8 %y, i32 0
+  %c = shufflevector <16 x i8> %b, <16 x i8> undef, <16 x i32> zeroinitializer
+  %d = icmp sle <16 x i8> %a, %c
+  store <16 x i1> %d, <16 x i1>* %z
+  ret void
+}
+
+define void @setugt_vx_v32i8(<32 x i8>* %x, i8 %y, <32 x i1>* %z) {
+; CHECK-LABEL: setugt_vx_v32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 32
+; CHECK-NEXT:    vsetvli a3, a3, e8,m2,ta,mu
+; CHECK-NEXT:    vle8.v v26, (a0)
+; CHECK-NEXT:    vmsgtu.vx v25, v26, a1
+; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    ret
+  %a = load <32 x i8>, <32 x i8>* %x
+  %b = insertelement <32 x i8> undef, i8 %y, i32 0
+  %c = shufflevector <32 x i8> %b, <32 x i8> undef, <32 x i32> zeroinitializer
+  %d = icmp ugt <32 x i8> %a, %c
+  store <32 x i1> %d, <32 x i1>* %z
+  ret void
+}
+
+define void @setult_vx_v64i8(<64 x i8>* %x, i8 %y, <64 x i1>* %z) {
+; CHECK-LABEL: setult_vx_v64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 64
+; CHECK-NEXT:    vsetvli a3, a3, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a0)
+; CHECK-NEXT:    vmsltu.vx v25, v28, a1
+; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    ret
+  %a = load <64 x i8>, <64 x i8>* %x
+  %b = insertelement <64 x i8> undef, i8 %y, i32 0
+  %c = shufflevector <64 x i8> %b, <64 x i8> undef, <64 x i32> zeroinitializer
+  %d = icmp ult <64 x i8> %a, %c
+  store <64 x i1> %d, <64 x i1>* %z
+  ret void
+}
+
+define void @setuge_vx_v128i8(<128 x i8>* %x, i8 %y, <128 x i1>* %z) {
+; CHECK-LABEL: setuge_vx_v128i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 128
+; CHECK-NEXT:    vsetvli a3, a3, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vmv.v.x v16, a1
+; CHECK-NEXT:    vmsleu.vv v25, v16, v8
+; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    ret
+  %a = load <128 x i8>, <128 x i8>* %x
+  %b = insertelement <128 x i8> undef, i8 %y, i32 0
+  %c = shufflevector <128 x i8> %b, <128 x i8> undef, <128 x i32> zeroinitializer
+  %d = icmp uge <128 x i8> %a, %c
+  store <128 x i1> %d, <128 x i1>* %z
+  ret void
+}
+
+define void @setule_vx_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) {
+; CHECK-LABEL: setule_vx_v8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 8
+; CHECK-NEXT:    vsetvli a3, a3, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vmsleu.vx v26, v25, a1
+; CHECK-NEXT:    vse1.v v26, (a2)
+; CHECK-NEXT:    ret
+  %a = load <8 x i8>, <8 x i8>* %x
+  %b = insertelement <8 x i8> undef, i8 %y, i32 0
+  %c = shufflevector <8 x i8> %b, <8 x i8> undef, <8 x i32> zeroinitializer
+  %d = icmp ule <8 x i8> %a, %c
+  store <8 x i1> %d, <8 x i1>* %z
+  ret void
+}
+
+define void @seteq_xv_v16i8(<16 x i8>* %x, i8 %y, <16 x i1>* %z) {
+; CHECK-LABEL: seteq_xv_v16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 16
+; CHECK-NEXT:    vsetvli a3, a3, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vmseq.vx v26, v25, a1
+; CHECK-NEXT:    vse1.v v26, (a2)
+; CHECK-NEXT:    ret
+  %a = load <16 x i8>, <16 x i8>* %x
+  %b = insertelement <16 x i8> undef, i8 %y, i32 0
+  %c = shufflevector <16 x i8> %b, <16 x i8> undef, <16 x i32> zeroinitializer
+  %d = icmp eq <16 x i8> %c, %a
+  store <16 x i1> %d, <16 x i1>* %z
+  ret void
+}
+
+define void @setne_xv_v32i8(<32 x i8>* %x, i8 %y, <32 x i1>* %z) {
+; CHECK-LABEL: setne_xv_v32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 32
+; CHECK-NEXT:    vsetvli a3, a3, e8,m2,ta,mu
+; CHECK-NEXT:    vle8.v v26, (a0)
+; CHECK-NEXT:    vmsne.vx v25, v26, a1
+; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    ret
+  %a = load <32 x i8>, <32 x i8>* %x
+  %b = insertelement <32 x i8> undef, i8 %y, i32 0
+  %c = shufflevector <32 x i8> %b, <32 x i8> undef, <32 x i32> zeroinitializer
+  %d = icmp ne <32 x i8> %c, %a
+  store <32 x i1> %d, <32 x i1>* %z
+  ret void
+}
+
+define void @setgt_xv_v64i8(<64 x i8>* %x, i8 %y, <64 x i1>* %z) {
+; CHECK-LABEL: setgt_xv_v64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 64
+; CHECK-NEXT:    vsetvli a3, a3, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a0)
+; CHECK-NEXT:    vmslt.vx v25, v28, a1
+; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    ret
+  %a = load <64 x i8>, <64 x i8>* %x
+  %b = insertelement <64 x i8> undef, i8 %y, i32 0
+  %c = shufflevector <64 x i8> %b, <64 x i8> undef, <64 x i32> zeroinitializer
+  %d = icmp sgt <64 x i8> %c, %a
+  store <64 x i1> %d, <64 x i1>* %z
+  ret void
+}
+
+define void @setlt_xv_v128i8(<128 x i8>* %x, i8 %y, <128 x i1>* %z) {
+; CHECK-LABEL: setlt_xv_v128i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 128
+; CHECK-NEXT:    vsetvli a3, a3, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vmsgt.vx v25, v8, a1
+; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    ret
+  %a = load <128 x i8>, <128 x i8>* %x
+  %b = insertelement <128 x i8> undef, i8 %y, i32 0
+  %c = shufflevector <128 x i8> %b, <128 x i8> undef, <128 x i32> zeroinitializer
+  %d = icmp slt <128 x i8> %c, %a
+  store <128 x i1> %d, <128 x i1>* %z
+  ret void
+}
+
+define void @setge_xv_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) {
+; CHECK-LABEL: setge_xv_v8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 8
+; CHECK-NEXT:    vsetvli a3, a3, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vmsle.vx v26, v25, a1
+; CHECK-NEXT:    vse1.v v26, (a2)
+; CHECK-NEXT:    ret
+  %a = load <8 x i8>, <8 x i8>* %x
+  %b = insertelement <8 x i8> undef, i8 %y, i32 0
+  %c = shufflevector <8 x i8> %b, <8 x i8> undef, <8 x i32> zeroinitializer
+  %d = icmp sge <8 x i8> %c, %a
+  store <8 x i1> %d, <8 x i1>* %z
+  ret void
+}
+
+define void @setle_xv_v16i8(<16 x i8>* %x, i8 %y, <16 x i1>* %z) {
+; CHECK-LABEL: setle_xv_v16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 16
+; CHECK-NEXT:    vsetvli a3, a3, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vmv.v.x v26, a1
+; CHECK-NEXT:    vmsle.vv v27, v26, v25
+; CHECK-NEXT:    vse1.v v27, (a2)
+; CHECK-NEXT:    ret
+  %a = load <16 x i8>, <16 x i8>* %x
+  %b = insertelement <16 x i8> undef, i8 %y, i32 0
+  %c = shufflevector <16 x i8> %b, <16 x i8> undef, <16 x i32> zeroinitializer
+  %d = icmp sle <16 x i8> %c, %a
+  store <16 x i1> %d, <16 x i1>* %z
+  ret void
+}
+
+define void @setugt_xv_v32i8(<32 x i8>* %x, i8 %y, <32 x i1>* %z) {
+; CHECK-LABEL: setugt_xv_v32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 32
+; CHECK-NEXT:    vsetvli a3, a3, e8,m2,ta,mu
+; CHECK-NEXT:    vle8.v v26, (a0)
+; CHECK-NEXT:    vmsltu.vx v25, v26, a1
+; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    ret
+  %a = load <32 x i8>, <32 x i8>* %x
+  %b = insertelement <32 x i8> undef, i8 %y, i32 0
+  %c = shufflevector <32 x i8> %b, <32 x i8> undef, <32 x i32> zeroinitializer
+  %d = icmp ugt <32 x i8> %c, %a
+  store <32 x i1> %d, <32 x i1>* %z
+  ret void
+}
+
+define void @setult_xv_v64i8(<64 x i8>* %x, i8 %y, <64 x i1>* %z) {
+; CHECK-LABEL: setult_xv_v64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 64
+; CHECK-NEXT:    vsetvli a3, a3, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a0)
+; CHECK-NEXT:    vmsgtu.vx v25, v28, a1
+; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    ret
+  %a = load <64 x i8>, <64 x i8>* %x
+  %b = insertelement <64 x i8> undef, i8 %y, i32 0
+  %c = shufflevector <64 x i8> %b, <64 x i8> undef, <64 x i32> zeroinitializer
+  %d = icmp ult <64 x i8> %c, %a
+  store <64 x i1> %d, <64 x i1>* %z
+  ret void
+}
+
+define void @setuge_xv_v128i8(<128 x i8>* %x, i8 %y, <128 x i1>* %z) {
+; CHECK-LABEL: setuge_xv_v128i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 128
+; CHECK-NEXT:    vsetvli a3, a3, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vmsleu.vx v25, v8, a1
+; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    ret
+  %a = load <128 x i8>, <128 x i8>* %x
+  %b = insertelement <128 x i8> undef, i8 %y, i32 0
+  %c = shufflevector <128 x i8> %b, <128 x i8> undef, <128 x i32> zeroinitializer
+  %d = icmp uge <128 x i8> %c, %a
+  store <128 x i1> %d, <128 x i1>* %z
+  ret void
+}
+
+define void @setule_xv_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) {
+; CHECK-LABEL: setule_xv_v8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a3, zero, 8
+; CHECK-NEXT:    vsetvli a3, a3, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vmv.v.x v26, a1
+; CHECK-NEXT:    vmsleu.vv v27, v26, v25
+; CHECK-NEXT:    vse1.v v27, (a2)
+; CHECK-NEXT:    ret
+  %a = load <8 x i8>, <8 x i8>* %x
+  %b = insertelement <8 x i8> undef, i8 %y, i32 0
+  %c = shufflevector <8 x i8> %b, <8 x i8> undef, <8 x i32> zeroinitializer
+  %d = icmp ule <8 x i8> %c, %a
+  store <8 x i1> %d, <8 x i1>* %z
+  ret void
+}
+
+define void @seteq_vi_v16i8(<16 x i8>* %x, <16 x i1>* %z) {
+; CHECK-LABEL: seteq_vi_v16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a2, zero, 16
+; CHECK-NEXT:    vsetvli a2, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vmseq.vi v26, v25, 0
+; CHECK-NEXT:    vse1.v v26, (a1)
+; CHECK-NEXT:    ret
+  %a = load <16 x i8>, <16 x i8>* %x
+  %b = insertelement <16 x i8> undef, i8 0, i32 0
+  %c = shufflevector <16 x i8> %b, <16 x i8> undef, <16 x i32> zeroinitializer
+  %d = icmp eq <16 x i8> %a, %c
+  store <16 x i1> %d, <16 x i1>* %z
+  ret void
+}
+
+define void @setne_vi_v32i8(<32 x i8>* %x, <32 x i1>* %z) {
+; CHECK-LABEL: setne_vi_v32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a2, zero, 32
+; CHECK-NEXT:    vsetvli a2, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vle8.v v26, (a0)
+; CHECK-NEXT:    vmsne.vi v25, v26, 0
+; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <32 x i8>, <32 x i8>* %x
+  %b = insertelement <32 x i8> undef, i8 0, i32 0
+  %c = shufflevector <32 x i8> %b, <32 x i8> undef, <32 x i32> zeroinitializer
+  %d = icmp ne <32 x i8> %a, %c
+  store <32 x i1> %d, <32 x i1>* %z
+  ret void
+}
+
+define void @setgt_vi_v64i8(<64 x i8>* %x, <64 x i1>* %z) {
+; CHECK-LABEL: setgt_vi_v64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a2, zero, 64
+; CHECK-NEXT:    vsetvli a2, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a0)
+; CHECK-NEXT:    vmsgt.vx v25, v28, zero
+; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <64 x i8>, <64 x i8>* %x
+  %b = insertelement <64 x i8> undef, i8 0, i32 0
+  %c = shufflevector <64 x i8> %b, <64 x i8> undef, <64 x i32> zeroinitializer
+  %d = icmp sgt <64 x i8> %a, %c
+  store <64 x i1> %d, <64 x i1>* %z
+  ret void
+}
+
+define void @setlt_vi_v128i8(<128 x i8>* %x, <128 x i1>* %z) {
+; CHECK-LABEL: setlt_vi_v128i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a2, zero, 128
+; CHECK-NEXT:    vsetvli a2, a2, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vmslt.vx v25, v8, zero
+; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <128 x i8>, <128 x i8>* %x
+  %b = insertelement <128 x i8> undef, i8 0, i32 0
+  %c = shufflevector <128 x i8> %b, <128 x i8> undef, <128 x i32> zeroinitializer
+  %d = icmp slt <128 x i8> %a, %c
+  store <128 x i1> %d, <128 x i1>* %z
+  ret void
+}
+
+define void @setge_vi_v8i8(<8 x i8>* %x, <8 x i1>* %z) {
+; CHECK-LABEL: setge_vi_v8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a2, zero, 8
+; CHECK-NEXT:    vsetvli a2, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmsle.vv v27, v26, v25
+; CHECK-NEXT:    vse1.v v27, (a1)
+; CHECK-NEXT:    ret
+  %a = load <8 x i8>, <8 x i8>* %x
+  %b = insertelement <8 x i8> undef, i8 0, i32 0
+  %c = shufflevector <8 x i8> %b, <8 x i8> undef, <8 x i32> zeroinitializer
+  %d = icmp sge <8 x i8> %a, %c
+  store <8 x i1> %d, <8 x i1>* %z
+  ret void
+}
+
+define void @setle_vi_v16i8(<16 x i8>* %x, <16 x i1>* %z) {
+; CHECK-LABEL: setle_vi_v16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a2, zero, 16
+; CHECK-NEXT:    vsetvli a2, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vmsle.vi v26, v25, 0
+; CHECK-NEXT:    vse1.v v26, (a1)
+; CHECK-NEXT:    ret
+  %a = load <16 x i8>, <16 x i8>* %x
+  %b = insertelement <16 x i8> undef, i8 0, i32 0
+  %c = shufflevector <16 x i8> %b, <16 x i8> undef, <16 x i32> zeroinitializer
+  %d = icmp sle <16 x i8> %a, %c
+  store <16 x i1> %d, <16 x i1>* %z
+  ret void
+}
+
+define void @setugt_vi_v32i8(<32 x i8>* %x, <32 x i1>* %z) {
+; CHECK-LABEL: setugt_vi_v32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a2, zero, 32
+; CHECK-NEXT:    vsetvli a2, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vle8.v v26, (a0)
+; CHECK-NEXT:    addi a0, zero, 5
+; CHECK-NEXT:    vmsgtu.vx v25, v26, a0
+; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <32 x i8>, <32 x i8>* %x
+  %b = insertelement <32 x i8> undef, i8 5, i32 0
+  %c = shufflevector <32 x i8> %b, <32 x i8> undef, <32 x i32> zeroinitializer
+  %d = icmp ugt <32 x i8> %a, %c
+  store <32 x i1> %d, <32 x i1>* %z
+  ret void
+}
+
+define void @setult_vi_v64i8(<64 x i8>* %x, <64 x i1>* %z) {
+; CHECK-LABEL: setult_vi_v64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a2, zero, 64
+; CHECK-NEXT:    vsetvli a2, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a0)
+; CHECK-NEXT:    addi a0, zero, 5
+; CHECK-NEXT:    vmsltu.vx v25, v28, a0
+; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <64 x i8>, <64 x i8>* %x
+  %b = insertelement <64 x i8> undef, i8 5, i32 0
+  %c = shufflevector <64 x i8> %b, <64 x i8> undef, <64 x i32> zeroinitializer
+  %d = icmp ult <64 x i8> %a, %c
+  store <64 x i1> %d, <64 x i1>* %z
+  ret void
+}
+
+define void @setuge_vi_v128i8(<128 x i8>* %x, <128 x i1>* %z) {
+; CHECK-LABEL: setuge_vi_v128i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a2, zero, 128
+; CHECK-NEXT:    vsetvli a2, a2, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vmv.v.i v16, 5
+; CHECK-NEXT:    vmsleu.vv v25, v16, v8
+; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <128 x i8>, <128 x i8>* %x
+  %b = insertelement <128 x i8> undef, i8 5, i32 0
+  %c = shufflevector <128 x i8> %b, <128 x i8> undef, <128 x i32> zeroinitializer
+  %d = icmp uge <128 x i8> %a, %c
+  store <128 x i1> %d, <128 x i1>* %z
+  ret void
+}
+
+define void @setule_vi_v8i8(<8 x i8>* %x, <8 x i1>* %z) {
+; CHECK-LABEL: setule_vi_v8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a2, zero, 8
+; CHECK-NEXT:    vsetvli a2, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vmsleu.vi v26, v25, 5
+; CHECK-NEXT:    vse1.v v26, (a1)
+; CHECK-NEXT:    ret
+  %a = load <8 x i8>, <8 x i8>* %x
+  %b = insertelement <8 x i8> undef, i8 5, i32 0
+  %c = shufflevector <8 x i8> %b, <8 x i8> undef, <8 x i32> zeroinitializer
+  %d = icmp ule <8 x i8> %a, %c
+  store <8 x i1> %d, <8 x i1>* %z
+  ret void
+}