[RISCV] Alternate attempt to optimize sign-extended EXTRACT_VECTOR_ELT nodes.

[craig.topper]

Summary

This is an alternate version of D95741 which defers the conversion
of extract_vector_elt to VMV_X_S until LegalDAG. This allows
it to be available to DAG combines for longer. To make this work
I've taught DAGCombiner to remove the SRA/SHL equivalent of
sext_inreg when the input to the pair is already sign extended.

If we decide to go this direction, I can split out the DAGCombiner
and Mips/atomic.ll change into a separate patch.

[jrtc27]

llvm/test/CodeGen/Mips/atomic.ll

4300

Strange that this one didn't change

[craig.topper]

llvm/test/CodeGen/Mips/atomic.ll

4300

AtomicCmpSwap8 uses ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS which is expanded by SelectionDAGLegalize::ExpandNode to a sequence that includes an AssertSExt.

AtomicSwap8 just uses ISD::ATOMIC_SWAP and does not go through any expanding. A custom inserter creates ATOMIC_SWAP_I8_POSTRA and then that is expanded by MipsExpandPseudo.cpp. Only after that do the earlier shifts appear.

[frasercrmck]

Cheers. I'm happy for you to split the DAGCombiner bits off into a separate patch. I can update mine as required.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

8371

Ah, excellent: so this is what I was missing. I'm surprised this wasn't already there.

[craig.topper]

The DAGCombiner change was commited separately and D95741 has been reworked on top of it.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 //===- DAGCombiner.cpp - Implement a DAG node combiner --------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
     if (VT.isVector())
       ExtVT = EVT::getVectorVT(*DAG.getContext(),
                                ExtVT, VT.getVectorNumElements());
     if (!LegalOperations ||
         TLI.getOperationAction(ISD::SIGN_EXTEND_INREG, ExtVT) ==
         TargetLowering::Legal)
       return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
                          N0.getOperand(0), DAG.getValueType(ExtVT));
+    // Even if we can't convert to sext_inreg, we might be able to remove
+    // this shift pair if the input is already sign extended.
+    if (DAG.ComputeNumSignBits(N0.getOperand(0)) > N1C->getZExtValue())
+      return N0.getOperand(0);
   }
 
   // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
   // clamp (add c1, c2) to max shift.
   if (N0.getOpcode() == ISD::SRA) {
     SDLoc DL(N);
     EVT ShiftVT = N1.getValueType();
     EVT ShiftSVT = ShiftVT.getScalarType();

llvm/lib/Target/RISCV/RISCVISelLowering.h

 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
enum NodeType : unsigned {
   // DAGs. Each node takes an input operand and a TargetConstant immediate
   // shift amount, and outputs a bit-manipulated version of input. All operands
   // are of type XLenVT.
   GREVI,
   GREVIW,
   GORCI,
   GORCIW,
   // Vector Extension
-  // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT
-  // sign extended from the vector element size. NOTE: The result size will
-  // never be less than the vector element size.
+  // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign
+  // extended from the vector element size.
   VMV_X_S,
   // Splats an i64 scalar to a vector type (with element type i64) where the
   // scalar is a sign-extended i32.
   SPLAT_VECTOR_I64,
   // Read VLENB CSR
   READ_VLENB,
   // Truncates a RVV integer vector by one power-of-two.
   TRUNCATE_VECTOR,

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
   auto SetCCVT =
       getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VecVT);
   SDValue Mask = DAG.getSetCC(DL, SetCCVT, VID, SplattedIdx, ISD::SETEQ);
 
   return DAG.getNode(ISD::VSELECT, DL, VecVT, Mask, SplattedVal, Vec);
 }
 
 // Custom-lower EXTRACT_VECTOR_ELT operations to slide the vector down, then
-// extract the first element: (extractelt (slidedown vec, idx), 0). This is
-// done to maintain partity with the legalization of RV32 vXi64 legalization.
+// extract the first element: (extractelt (slidedown vec, idx), 0). For integer
+// types this is done using VMV_X_S to allow us to glean information about the
+// sign bits of the result.
 SDValue RISCVTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
                                                      SelectionDAG &DAG) const {
   SDLoc DL(Op);
   SDValue Idx = Op.getOperand(1);
-  if (isNullConstant(Idx))
-    return Op;
-
   SDValue Vec = Op.getOperand(0);
   EVT EltVT = Op.getValueType();
   EVT VecVT = Vec.getValueType();
-  SDValue Slidedown = DAG.getNode(RISCVISD::VSLIDEDOWN, DL, VecVT,
-                                  DAG.getUNDEF(VecVT), Vec, Idx);
+  MVT XLenVT = Subtarget.getXLenVT();
 
-  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Slidedown,
-                     DAG.getConstant(0, DL, Subtarget.getXLenVT()));
+  // If the index is 0, the vector is already in the right position.
+  if (!isNullConstant(Idx)) {
+    Vec = DAG.getNode(RISCVISD::VSLIDEDOWN, DL, VecVT, DAG.getUNDEF(VecVT), Vec,
+                      Idx);
+  }
+
+  if (!EltVT.isInteger()) {
+    // Floating-point extracts are handled in TableGen.
+    return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vec,
+                       DAG.getConstant(0, DL, XLenVT));
+  }
+
+  SDValue Elt0 = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, Vec);
+  return DAG.getNode(ISD::TRUNCATE, DL, EltVT, Elt0);
 }
 
 SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
                                                      SelectionDAG &DAG) const {
   unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
   SDLoc DL(Op);
 
   if (Subtarget.hasStdExtV()) {

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

def : Pat<(fvti.Vector (splat_vector (fvti.Scalar fpimm0))),
               0, fvti.AVL, fvti.SEW)>;
 }
 } // Predicates = [HasStdExtV, HasStdExtF]
 
 //===----------------------------------------------------------------------===//
 // Vector Element Inserts/Extracts
 //===----------------------------------------------------------------------===//
 
-// The built-in TableGen 'extractelt' and 'insertelt' nodes must return the
-// same type as the vector element type. On RISC-V, XLenVT is the only legal
-// integer type, so for integer inserts/extracts we use a custom node which
-// returns XLenVT.
+// The built-in TableGen 'insertelt' node must return the same type as the
+// vector element type. On RISC-V, XLenVT is the only legal integer type, so
+// for integer inserts we use a custom node which inserts an XLenVT-typed
+// value.
 def riscv_insert_vector_elt
     : SDNode<"ISD::INSERT_VECTOR_ELT",
              SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, XLenVT>,
                                   SDTCisPtrTy<3>]>, []>;
-def riscv_extract_vector_elt
-    : SDNode<"ISD::EXTRACT_VECTOR_ELT",
-             SDTypeProfile<1, 2, [SDTCisVT<0, XLenVT>, SDTCisPtrTy<2>]>, []>;
-
-multiclass VPatInsertExtractElt_XI_Idx<bit IsFloat> {
-  defvar vtilist = !if(IsFloat, AllFloatVectors, AllIntegerVectors);
-  defvar insertelt_node = !if(IsFloat, insertelt, riscv_insert_vector_elt);
-  defvar extractelt_node = !if(IsFloat, extractelt, riscv_extract_vector_elt);
-  foreach vti = vtilist in {
-    defvar MX = vti.LMul.MX;
-    defvar vmv_xf_s_inst = !cast<Instruction>(!strconcat("PseudoV",
-                                                         !if(IsFloat, "F", ""),
-                                                         "MV_",
-                                                         vti.ScalarSuffix,
-                                                         "_S_", MX));
-    defvar vmv_s_xf_inst = !cast<Instruction>(!strconcat("PseudoV",
-                                                         !if(IsFloat, "F", ""),
-                                                         "MV_S_",
-                                                         vti.ScalarSuffix,
-                                                         "_", MX));
-    // Only pattern-match insert/extract-element operations where the index is
-    // 0. Any other index will have been custom-lowered to slide the vector
-    // correctly into place (and, in the case of insert, slide it back again
-    // afterwards).
-    def : Pat<(vti.Scalar (extractelt_node (vti.Vector vti.RegClass:$rs2), 0)),
-              (vmv_xf_s_inst vti.RegClass:$rs2, vti.SEW)>;
+
+let Predicates = [HasStdExtV] in
+foreach vti = AllIntegerVectors in {
+  def : Pat<(vti.Vector (riscv_insert_vector_elt (vti.Vector vti.RegClass:$merge),
+                                                 vti.ScalarRegClass:$rs1, 0)),
+            (!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX)
+                vti.RegClass:$merge,
+                (vti.Scalar vti.ScalarRegClass:$rs1),
+                vti.AVL, vti.SEW)>;
+}
+
+let Predicates = [HasStdExtV, HasStdExtF] in
+foreach vti = AllFloatVectors in {
+  defvar vmv_f_s_inst = !cast<Instruction>(!strconcat("PseudoVFMV_",
+  defvar vmv_s_f_inst = !cast<Instruction>(!strconcat("PseudoVFMV_S_",
+                                                       "_", vti.LMul.MX));
+  def : Pat<(vti.Scalar (extractelt (vti.Vector vti.RegClass:$rs2), 0)),
+            (vmv_f_s_inst vti.RegClass:$rs2, vti.SEW)>;
 
-    def : Pat<(vti.Vector (insertelt_node (vti.Vector vti.RegClass:$merge),
-                                          vti.ScalarRegClass:$rs1, 0)),
-              (vmv_s_xf_inst vti.RegClass:$merge,
-                      (vti.Scalar vti.ScalarRegClass:$rs1),
-                      vti.AVL, vti.SEW)>;
-  }
-}
-
-let Predicates = [HasStdExtV] in
-defm "" : VPatInsertExtractElt_XI_Idx</*IsFloat*/0>;
-let Predicates = [HasStdExtV, HasStdExtF] in
-defm "" : VPatInsertExtractElt_XI_Idx</*IsFloat*/1>;
+  def : Pat<(vti.Vector (insertelt (vti.Vector vti.RegClass:$merge),
+            (vmv_s_f_inst vti.RegClass:$merge,
 
 //===----------------------------------------------------------------------===//
 // Miscellaneous RISCVISD SDNodes
 //===----------------------------------------------------------------------===//
 
 def riscv_vid
     : SDNode<"RISCVISD::VID", SDTypeProfile<1, 0, [SDTCisVec<0>]>, []>;
 

llvm/test/CodeGen/Mips/atomic.ll

 ; MIPS32EB-NEXT:  # %bb.2: # %entry
 ; MIPS32EB-NEXT:    and $1, $7, $5
 ; MIPS32EB-NEXT:    srlv $1, $1, $3
 ; MIPS32EB-NEXT:    sll $1, $1, 24
 ; MIPS32EB-NEXT:    sra $1, $1, 24
 ; MIPS32EB-NEXT:  # %bb.3: # %entry
 ; MIPS32EB-NEXT:    sll $1, $1, 24
 ; MIPS32EB-NEXT:    jr $ra
 ; MIPS32EB-NEXT:    sra $2, $1, 24
 entry:
   %0 = atomicrmw xchg i8* @y, i8 %newval monotonic
   ret i8 %0
 }
 
 define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind {
 ; MIPS32-LABEL: AtomicCmpSwap8:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32-NEXT:    addu $1, $2, $25
 ; MIPS32-NEXT:    lw $1, %got(y)($1)
 ; MIPS32-NEXT:    addiu $2, $zero, -4
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    and $3, $1, $2
 ; MIPS32-NEXT:    andi $1, $1, 3
-; MIPS32-NEXT:    sll $3, $1, 3
-; MIPS32-NEXT:    ori $1, $zero, 255
-; MIPS32-NEXT:    sllv $6, $1, $3
+; MIPS32-NEXT:    sll $1, $1, 3
+; MIPS32-NEXT:    ori $2, $zero, 255
+; MIPS32-NEXT:    sllv $6, $2, $1
 ; MIPS32-NEXT:    nor $7, $zero, $6
-; MIPS32-NEXT:    andi $1, $4, 255
-; MIPS32-NEXT:    sllv $4, $1, $3
-; MIPS32-NEXT:    andi $1, $5, 255
-; MIPS32-NEXT:    sllv $5, $1, $3
+; MIPS32-NEXT:    andi $2, $4, 255
+; MIPS32-NEXT:    sllv $4, $2, $1
+; MIPS32-NEXT:    andi $2, $5, 255
+; MIPS32-NEXT:    sllv $5, $2, $1
 ; MIPS32-NEXT:  $BB12_1: # %entry
 ; MIPS32-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32-NEXT:    ll $8, 0($2)
+; MIPS32-NEXT:    ll $8, 0($3)
 ; MIPS32-NEXT:    and $9, $8, $6
 ; MIPS32-NEXT:    bne $9, $4, $BB12_3
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.2: # %entry
 ; MIPS32-NEXT:    # in Loop: Header=BB12_1 Depth=1
 ; MIPS32-NEXT:    and $8, $8, $7
 ; MIPS32-NEXT:    or $8, $8, $5
-; MIPS32-NEXT:    sc $8, 0($2)
+; MIPS32-NEXT:    sc $8, 0($3)
 ; MIPS32-NEXT:    beqz $8, $BB12_1
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB12_3: # %entry
-; MIPS32-NEXT:    srlv $1, $9, $3
-; MIPS32-NEXT:    sll $1, $1, 24
-; MIPS32-NEXT:    sra $1, $1, 24
+; MIPS32-NEXT:    srlv $2, $9, $1
+; MIPS32-NEXT:    sll $2, $2, 24
+; MIPS32-NEXT:    sra $2, $2, 24
 ; MIPS32-NEXT:  # %bb.4: # %entry
-; MIPS32-NEXT:    sll $1, $1, 24
 ; MIPS32-NEXT:    jr $ra
-; MIPS32-NEXT:    sra $2, $1, 24
+; MIPS32-NEXT:    nop
 ;
 ; MIPS32O0-LABEL: AtomicCmpSwap8:
 ; MIPS32O0:       # %bb.0: # %entry
 ; MIPS32O0-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32O0-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32O0-NEXT:    addiu $sp, $sp, -8
 ; MIPS32O0-NEXT:    addu $3, $2, $25
 ; MIPS32O0-NEXT:    move $1, $5

 ;
 ; MIPS4-LABEL: AtomicCmpSwap8:
 ; MIPS4:       # %bb.0: # %entry
 ; MIPS4-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicCmpSwap8)))
 ; MIPS4-NEXT:    daddu $1, $1, $25
 ; MIPS4-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicCmpSwap8)))
 ; MIPS4-NEXT:    ld $1, %got_disp(y)($1)
 ; MIPS4-NEXT:    daddiu $2, $zero, -4
-; MIPS4-NEXT:    and $2, $1, $2
+; MIPS4-NEXT:    and $3, $1, $2
 ; MIPS4-NEXT:    andi $1, $1, 3
-; MIPS4-NEXT:    sll $3, $1, 3
-; MIPS4-NEXT:    ori $1, $zero, 255
-; MIPS4-NEXT:    sllv $6, $1, $3
+; MIPS4-NEXT:    sll $1, $1, 3
+; MIPS4-NEXT:    ori $2, $zero, 255
+; MIPS4-NEXT:    sllv $6, $2, $1
 ; MIPS4-NEXT:    nor $7, $zero, $6
-; MIPS4-NEXT:    andi $1, $4, 255
-; MIPS4-NEXT:    sllv $4, $1, $3
-; MIPS4-NEXT:    andi $1, $5, 255
-; MIPS4-NEXT:    sllv $5, $1, $3
+; MIPS4-NEXT:    andi $2, $4, 255
+; MIPS4-NEXT:    sllv $4, $2, $1
+; MIPS4-NEXT:    andi $2, $5, 255
+; MIPS4-NEXT:    sllv $5, $2, $1
 ; MIPS4-NEXT:  .LBB12_1: # %entry
 ; MIPS4-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS4-NEXT:    ll $8, 0($2)
+; MIPS4-NEXT:    ll $8, 0($3)
 ; MIPS4-NEXT:    and $9, $8, $6
 ; MIPS4-NEXT:    bne $9, $4, .LBB12_3
 ; MIPS4-NEXT:    nop
 ; MIPS4-NEXT:  # %bb.2: # %entry
 ; MIPS4-NEXT:    # in Loop: Header=BB12_1 Depth=1
 ; MIPS4-NEXT:    and $8, $8, $7
 ; MIPS4-NEXT:    or $8, $8, $5
-; MIPS4-NEXT:    sc $8, 0($2)
+; MIPS4-NEXT:    sc $8, 0($3)
 ; MIPS4-NEXT:    beqz $8, .LBB12_1
 ; MIPS4-NEXT:    nop
 ; MIPS4-NEXT:  .LBB12_3: # %entry
-; MIPS4-NEXT:    srlv $1, $9, $3
-; MIPS4-NEXT:    sll $1, $1, 24
-; MIPS4-NEXT:    sra $1, $1, 24
+; MIPS4-NEXT:    srlv $2, $9, $1
+; MIPS4-NEXT:    sll $2, $2, 24
+; MIPS4-NEXT:    sra $2, $2, 24
 ; MIPS4-NEXT:  # %bb.4: # %entry
-; MIPS4-NEXT:    sll $1, $1, 24
 ; MIPS4-NEXT:    jr $ra
-; MIPS4-NEXT:    sra $2, $1, 24
+; MIPS4-NEXT:    nop
 ;
 ; MIPS64-LABEL: AtomicCmpSwap8:
 ; MIPS64:       # %bb.0: # %entry
 ; MIPS64-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicCmpSwap8)))
 ; MIPS64-NEXT:    daddu $1, $1, $25
 ; MIPS64-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicCmpSwap8)))
 ; MIPS64-NEXT:    ld $1, %got_disp(y)($1)
 ; MIPS64-NEXT:    daddiu $2, $zero, -4
-; MIPS64-NEXT:    and $2, $1, $2
+; MIPS64-NEXT:    and $3, $1, $2
 ; MIPS64-NEXT:    andi $1, $1, 3
-; MIPS64-NEXT:    sll $3, $1, 3
-; MIPS64-NEXT:    ori $1, $zero, 255
-; MIPS64-NEXT:    sllv $6, $1, $3
+; MIPS64-NEXT:    sll $1, $1, 3
+; MIPS64-NEXT:    ori $2, $zero, 255
+; MIPS64-NEXT:    sllv $6, $2, $1
 ; MIPS64-NEXT:    nor $7, $zero, $6
-; MIPS64-NEXT:    andi $1, $4, 255
-; MIPS64-NEXT:    sllv $4, $1, $3
-; MIPS64-NEXT:    andi $1, $5, 255
-; MIPS64-NEXT:    sllv $5, $1, $3
+; MIPS64-NEXT:    andi $2, $4, 255
+; MIPS64-NEXT:    sllv $4, $2, $1
+; MIPS64-NEXT:    andi $2, $5, 255
+; MIPS64-NEXT:    sllv $5, $2, $1
 ; MIPS64-NEXT:  .LBB12_1: # %entry
 ; MIPS64-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS64-NEXT:    ll $8, 0($2)
+; MIPS64-NEXT:    ll $8, 0($3)
 ; MIPS64-NEXT:    and $9, $8, $6
 ; MIPS64-NEXT:    bne $9, $4, .LBB12_3
 ; MIPS64-NEXT:    nop
 ; MIPS64-NEXT:  # %bb.2: # %entry
 ; MIPS64-NEXT:    # in Loop: Header=BB12_1 Depth=1
 ; MIPS64-NEXT:    and $8, $8, $7
 ; MIPS64-NEXT:    or $8, $8, $5
-; MIPS64-NEXT:    sc $8, 0($2)
+; MIPS64-NEXT:    sc $8, 0($3)
 ; MIPS64-NEXT:    beqz $8, .LBB12_1
 ; MIPS64-NEXT:    nop
 ; MIPS64-NEXT:  .LBB12_3: # %entry
-; MIPS64-NEXT:    srlv $1, $9, $3
-; MIPS64-NEXT:    sll $1, $1, 24
-; MIPS64-NEXT:    sra $1, $1, 24
+; MIPS64-NEXT:    srlv $2, $9, $1
+; MIPS64-NEXT:    sll $2, $2, 24
+; MIPS64-NEXT:    sra $2, $2, 24
 ; MIPS64-NEXT:  # %bb.4: # %entry
-; MIPS64-NEXT:    sll $1, $1, 24
 ; MIPS64-NEXT:    jr $ra
-; MIPS64-NEXT:    sra $2, $1, 24
+; MIPS64-NEXT:    nop
 ;
 ; MIPS64R2-LABEL: AtomicCmpSwap8:
 ; MIPS64R2:       # %bb.0: # %entry
 ; MIPS64R2-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicCmpSwap8)))
 ; MIPS64R2-NEXT:    daddu $1, $1, $25
 ; MIPS64R2-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicCmpSwap8)))
 ; MIPS64R2-NEXT:    ld $1, %got_disp(y)($1)
 ; MIPS64R2-NEXT:    daddiu $2, $zero, -4

 ;
 ; O1-LABEL: AtomicCmpSwap8:
 ; O1:       # %bb.0: # %entry
 ; O1-NEXT:    lui $2, %hi(_gp_disp)
 ; O1-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O1-NEXT:    addu $1, $2, $25
 ; O1-NEXT:    lw $1, %got(y)($1)
 ; O1-NEXT:    addiu $2, $zero, -4
-; O1-NEXT:    and $2, $1, $2
+; O1-NEXT:    and $3, $1, $2
 ; O1-NEXT:    andi $1, $1, 3
-; O1-NEXT:    sll $3, $1, 3
-; O1-NEXT:    ori $1, $zero, 255
-; O1-NEXT:    sllv $6, $1, $3
+; O1-NEXT:    sll $1, $1, 3
+; O1-NEXT:    ori $2, $zero, 255
+; O1-NEXT:    sllv $6, $2, $1
 ; O1-NEXT:    nor $7, $zero, $6
-; O1-NEXT:    andi $1, $4, 255
-; O1-NEXT:    sllv $4, $1, $3
-; O1-NEXT:    andi $1, $5, 255
-; O1-NEXT:    sllv $5, $1, $3
+; O1-NEXT:    andi $2, $4, 255
+; O1-NEXT:    sllv $4, $2, $1
+; O1-NEXT:    andi $2, $5, 255
+; O1-NEXT:    sllv $5, $2, $1
 ; O1-NEXT:  $BB12_1: # %entry
 ; O1-NEXT:    # =>This Inner Loop Header: Depth=1
-; O1-NEXT:    ll $8, 0($2)
+; O1-NEXT:    ll $8, 0($3)
 ; O1-NEXT:    and $9, $8, $6
 ; O1-NEXT:    bne $9, $4, $BB12_3
 ; O1-NEXT:    nop
 ; O1-NEXT:  # %bb.2: # %entry
 ; O1-NEXT:    # in Loop: Header=BB12_1 Depth=1
 ; O1-NEXT:    and $8, $8, $7
 ; O1-NEXT:    or $8, $8, $5
-; O1-NEXT:    sc $8, 0($2)
+; O1-NEXT:    sc $8, 0($3)
 ; O1-NEXT:    beqz $8, $BB12_1
 ; O1-NEXT:    nop
 ; O1-NEXT:  $BB12_3: # %entry
-; O1-NEXT:    srlv $1, $9, $3
-; O1-NEXT:    sll $1, $1, 24
-; O1-NEXT:    sra $1, $1, 24
+; O1-NEXT:    srlv $2, $9, $1
+; O1-NEXT:    sll $2, $2, 24
+; O1-NEXT:    sra $2, $2, 24
 ; O1-NEXT:  # %bb.4: # %entry
-; O1-NEXT:    sll $1, $1, 24
 ; O1-NEXT:    jr $ra
-; O1-NEXT:    sra $2, $1, 24
+; O1-NEXT:    nop
 ;
 ; O2-LABEL: AtomicCmpSwap8:
 ; O2:       # %bb.0: # %entry
 ; O2-NEXT:    lui $2, %hi(_gp_disp)
 ; O2-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O2-NEXT:    addu $1, $2, $25
 ; O2-NEXT:    lw $1, %got(y)($1)
 ; O2-NEXT:    addiu $2, $zero, -4
-; O2-NEXT:    and $2, $1, $2
+; O2-NEXT:    and $3, $1, $2
 ; O2-NEXT:    andi $1, $1, 3
-; O2-NEXT:    sll $3, $1, 3
-; O2-NEXT:    ori $1, $zero, 255
-; O2-NEXT:    sllv $6, $1, $3
+; O2-NEXT:    sll $1, $1, 3
+; O2-NEXT:    ori $2, $zero, 255
+; O2-NEXT:    sllv $6, $2, $1
 ; O2-NEXT:    nor $7, $zero, $6
-; O2-NEXT:    andi $1, $4, 255
-; O2-NEXT:    sllv $4, $1, $3
-; O2-NEXT:    andi $1, $5, 255
-; O2-NEXT:    sllv $5, $1, $3
+; O2-NEXT:    andi $2, $4, 255
+; O2-NEXT:    sllv $4, $2, $1
+; O2-NEXT:    andi $2, $5, 255
+; O2-NEXT:    sllv $5, $2, $1
 ; O2-NEXT:  $BB12_1: # %entry
 ; O2-NEXT:    # =>This Inner Loop Header: Depth=1
-; O2-NEXT:    ll $8, 0($2)
+; O2-NEXT:    ll $8, 0($3)
 ; O2-NEXT:    and $9, $8, $6
 ; O2-NEXT:    bne $9, $4, $BB12_3
 ; O2-NEXT:    nop
 ; O2-NEXT:  # %bb.2: # %entry
 ; O2-NEXT:    # in Loop: Header=BB12_1 Depth=1
 ; O2-NEXT:    and $8, $8, $7
 ; O2-NEXT:    or $8, $8, $5
-; O2-NEXT:    sc $8, 0($2)
+; O2-NEXT:    sc $8, 0($3)
 ; O2-NEXT:    beqz $8, $BB12_1
 ; O2-NEXT:    nop
 ; O2-NEXT:  $BB12_3: # %entry
-; O2-NEXT:    srlv $1, $9, $3
-; O2-NEXT:    sll $1, $1, 24
-; O2-NEXT:    sra $1, $1, 24
+; O2-NEXT:    srlv $2, $9, $1
+; O2-NEXT:    sll $2, $2, 24
+; O2-NEXT:    sra $2, $2, 24
 ; O2-NEXT:  # %bb.4: # %entry
-; O2-NEXT:    sll $1, $1, 24
 ; O2-NEXT:    jr $ra
-; O2-NEXT:    sra $2, $1, 24
+; O2-NEXT:    nop
 ;
 ; O3-LABEL: AtomicCmpSwap8:
 ; O3:       # %bb.0: # %entry
 ; O3-NEXT:    lui $2, %hi(_gp_disp)
 ; O3-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O3-NEXT:    addu $1, $2, $25
 ; O3-NEXT:    addiu $2, $zero, -4
 ; O3-NEXT:    lw $1, %got(y)($1)
-; O3-NEXT:    and $2, $1, $2
+; O3-NEXT:    and $3, $1, $2
 ; O3-NEXT:    andi $1, $1, 3
-; O3-NEXT:    sll $3, $1, 3
-; O3-NEXT:    ori $1, $zero, 255
-; O3-NEXT:    sllv $6, $1, $3
-; O3-NEXT:    andi $1, $4, 255
-; O3-NEXT:    sllv $4, $1, $3
-; O3-NEXT:    andi $1, $5, 255
+; O3-NEXT:    ori $2, $zero, 255
+; O3-NEXT:    sll $1, $1, 3
+; O3-NEXT:    sllv $6, $2, $1
+; O3-NEXT:    andi $2, $4, 255
+; O3-NEXT:    sllv $4, $2, $1
+; O3-NEXT:    andi $2, $5, 255
 ; O3-NEXT:    nor $7, $zero, $6
-; O3-NEXT:    sllv $5, $1, $3
+; O3-NEXT:    sllv $5, $2, $1
 ; O3-NEXT:  $BB12_1: # %entry
 ; O3-NEXT:    # =>This Inner Loop Header: Depth=1
-; O3-NEXT:    ll $8, 0($2)
+; O3-NEXT:    ll $8, 0($3)
 ; O3-NEXT:    and $9, $8, $6
 ; O3-NEXT:    bne $9, $4, $BB12_3
 ; O3-NEXT:    nop
 ; O3-NEXT:  # %bb.2: # %entry
 ; O3-NEXT:    # in Loop: Header=BB12_1 Depth=1
 ; O3-NEXT:    and $8, $8, $7
 ; O3-NEXT:    or $8, $8, $5
-; O3-NEXT:    sc $8, 0($2)
+; O3-NEXT:    sc $8, 0($3)
 ; O3-NEXT:    beqz $8, $BB12_1
 ; O3-NEXT:    nop
 ; O3-NEXT:  $BB12_3: # %entry
-; O3-NEXT:    srlv $1, $9, $3
-; O3-NEXT:    sll $1, $1, 24
-; O3-NEXT:    sra $1, $1, 24
+; O3-NEXT:    srlv $2, $9, $1
+; O3-NEXT:    sll $2, $2, 24
+; O3-NEXT:    sra $2, $2, 24
 ; O3-NEXT:  # %bb.4: # %entry
-; O3-NEXT:    sll $1, $1, 24
 ; O3-NEXT:    jr $ra
-; O3-NEXT:    sra $2, $1, 24
+; O3-NEXT:    nop
 ;
 ; MIPS32EB-LABEL: AtomicCmpSwap8:
 ; MIPS32EB:       # %bb.0: # %entry
 ; MIPS32EB-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32EB-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32EB-NEXT:    addu $1, $2, $25
 ; MIPS32EB-NEXT:    lw $1, %got(y)($1)
 ; MIPS32EB-NEXT:    addiu $2, $zero, -4
-; MIPS32EB-NEXT:    and $2, $1, $2
+; MIPS32EB-NEXT:    and $3, $1, $2
 ; MIPS32EB-NEXT:    andi $1, $1, 3
 ; MIPS32EB-NEXT:    xori $1, $1, 3
-; MIPS32EB-NEXT:    sll $3, $1, 3
-; MIPS32EB-NEXT:    ori $1, $zero, 255
-; MIPS32EB-NEXT:    sllv $6, $1, $3
+; MIPS32EB-NEXT:    sll $1, $1, 3
+; MIPS32EB-NEXT:    ori $2, $zero, 255
+; MIPS32EB-NEXT:    sllv $6, $2, $1
 ; MIPS32EB-NEXT:    nor $7, $zero, $6
-; MIPS32EB-NEXT:    andi $1, $4, 255
-; MIPS32EB-NEXT:    sllv $4, $1, $3
-; MIPS32EB-NEXT:    andi $1, $5, 255
-; MIPS32EB-NEXT:    sllv $5, $1, $3
+; MIPS32EB-NEXT:    andi $2, $4, 255
+; MIPS32EB-NEXT:    sllv $4, $2, $1
+; MIPS32EB-NEXT:    andi $2, $5, 255
+; MIPS32EB-NEXT:    sllv $5, $2, $1
 ; MIPS32EB-NEXT:  $BB12_1: # %entry
 ; MIPS32EB-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32EB-NEXT:    ll $8, 0($2)
+; MIPS32EB-NEXT:    ll $8, 0($3)
 ; MIPS32EB-NEXT:    and $9, $8, $6
 ; MIPS32EB-NEXT:    bne $9, $4, $BB12_3
 ; MIPS32EB-NEXT:    nop
 ; MIPS32EB-NEXT:  # %bb.2: # %entry
 ; MIPS32EB-NEXT:    # in Loop: Header=BB12_1 Depth=1
 ; MIPS32EB-NEXT:    and $8, $8, $7
 ; MIPS32EB-NEXT:    or $8, $8, $5
-; MIPS32EB-NEXT:    sc $8, 0($2)
+; MIPS32EB-NEXT:    sc $8, 0($3)
 ; MIPS32EB-NEXT:    beqz $8, $BB12_1
 ; MIPS32EB-NEXT:    nop
 ; MIPS32EB-NEXT:  $BB12_3: # %entry
-; MIPS32EB-NEXT:    srlv $1, $9, $3
-; MIPS32EB-NEXT:    sll $1, $1, 24
-; MIPS32EB-NEXT:    sra $1, $1, 24
+; MIPS32EB-NEXT:    srlv $2, $9, $1
+; MIPS32EB-NEXT:    sll $2, $2, 24
+; MIPS32EB-NEXT:    sra $2, $2, 24
 ; MIPS32EB-NEXT:  # %bb.4: # %entry
-; MIPS32EB-NEXT:    sll $1, $1, 24
 ; MIPS32EB-NEXT:    jr $ra
-; MIPS32EB-NEXT:    sra $2, $1, 24
+; MIPS32EB-NEXT:    nop
 entry:
   %pair0 = cmpxchg i8* @y, i8 %oldval, i8 %newval monotonic monotonic
   %0 = extractvalue { i8, i1 } %pair0, 0
   ret i8 %0
 }
 
 define i1 @AtomicCmpSwapRes8(i8* %ptr, i8 signext %oldval, i8 signext %newval) nounwind {
 ; MIPS32-LABEL: AtomicCmpSwapRes8:

 ; MIPS32-NEXT:    sc $9, 0($2)
 ; MIPS32-NEXT:    beqz $9, $BB13_1
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB13_3: # %entry
 ; MIPS32-NEXT:    srlv $1, $10, $3
 ; MIPS32-NEXT:    sll $1, $1, 24
 ; MIPS32-NEXT:    sra $1, $1, 24
 ; MIPS32-NEXT:  # %bb.4: # %entry
-; MIPS32-NEXT:    sll $2, $5, 24
-; MIPS32-NEXT:    sra $2, $2, 24
-; MIPS32-NEXT:    xor $1, $1, $2
+; MIPS32-NEXT:    xor $1, $1, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    sltiu $2, $1, 1
 ;
 ; MIPS32O0-LABEL: AtomicCmpSwapRes8:
 ; MIPS32O0:       # %bb.0: # %entry
 ; MIPS32O0-NEXT:    addiu $sp, $sp, -8
 ; MIPS32O0-NEXT:    move $1, $6
 ; MIPS32O0-NEXT:    move $2, $5

 ; MIPS4-NEXT:    sc $9, 0($2)
 ; MIPS4-NEXT:    beqz $9, .LBB13_1
 ; MIPS4-NEXT:    nop
 ; MIPS4-NEXT:  .LBB13_3: # %entry
 ; MIPS4-NEXT:    srlv $1, $10, $3
 ; MIPS4-NEXT:    sll $1, $1, 24
 ; MIPS4-NEXT:    sra $1, $1, 24
 ; MIPS4-NEXT:  # %bb.4: # %entry
-; MIPS4-NEXT:    sll $2, $5, 24
-; MIPS4-NEXT:    sra $2, $2, 24
-; MIPS4-NEXT:    xor $1, $1, $2
+; MIPS4-NEXT:    xor $1, $1, $5
 ; MIPS4-NEXT:    jr $ra
 ; MIPS4-NEXT:    sltiu $2, $1, 1
 ;
 ; MIPS64-LABEL: AtomicCmpSwapRes8:
 ; MIPS64:       # %bb.0: # %entry
 ; MIPS64-NEXT:    daddiu $1, $zero, -4
 ; MIPS64-NEXT:    and $2, $4, $1
 ; MIPS64-NEXT:    andi $1, $4, 3

 ; MIPS64-NEXT:    sc $9, 0($2)
 ; MIPS64-NEXT:    beqz $9, .LBB13_1
 ; MIPS64-NEXT:    nop
 ; MIPS64-NEXT:  .LBB13_3: # %entry
 ; MIPS64-NEXT:    srlv $1, $10, $3
 ; MIPS64-NEXT:    sll $1, $1, 24
 ; MIPS64-NEXT:    sra $1, $1, 24
 ; MIPS64-NEXT:  # %bb.4: # %entry
-; MIPS64-NEXT:    sll $2, $5, 24
-; MIPS64-NEXT:    sra $2, $2, 24
-; MIPS64-NEXT:    xor $1, $1, $2
+; MIPS64-NEXT:    xor $1, $1, $5
 ; MIPS64-NEXT:    jr $ra
 ; MIPS64-NEXT:    sltiu $2, $1, 1
 ;
 ; MIPS64R2-LABEL: AtomicCmpSwapRes8:
 ; MIPS64R2:       # %bb.0: # %entry
 ; MIPS64R2-NEXT:    daddiu $1, $zero, -4
 ; MIPS64R2-NEXT:    and $2, $4, $1
 ; MIPS64R2-NEXT:    andi $1, $4, 3

 ; O1-NEXT:    sc $9, 0($2)
 ; O1-NEXT:    beqz $9, $BB13_1
 ; O1-NEXT:    nop
 ; O1-NEXT:  $BB13_3: # %entry
 ; O1-NEXT:    srlv $1, $10, $3
 ; O1-NEXT:    sll $1, $1, 24
 ; O1-NEXT:    sra $1, $1, 24
 ; O1-NEXT:  # %bb.4: # %entry
-; O1-NEXT:    sll $2, $5, 24
-; O1-NEXT:    sra $2, $2, 24
-; O1-NEXT:    xor $1, $1, $2
+; O1-NEXT:    xor $1, $1, $5
 ; O1-NEXT:    jr $ra
 ; O1-NEXT:    sltiu $2, $1, 1
 ;
 ; O2-LABEL: AtomicCmpSwapRes8:
 ; O2:       # %bb.0: # %entry
 ; O2-NEXT:    addiu $1, $zero, -4
 ; O2-NEXT:    and $2, $4, $1
 ; O2-NEXT:    andi $1, $4, 3

 ; O2-NEXT:    sc $9, 0($2)
 ; O2-NEXT:    beqz $9, $BB13_1
 ; O2-NEXT:    nop
 ; O2-NEXT:  $BB13_3: # %entry
 ; O2-NEXT:    srlv $1, $10, $3
 ; O2-NEXT:    sll $1, $1, 24
 ; O2-NEXT:    sra $1, $1, 24
 ; O2-NEXT:  # %bb.4: # %entry
-; O2-NEXT:    sll $2, $5, 24
-; O2-NEXT:    sra $2, $2, 24
-; O2-NEXT:    xor $1, $1, $2
+; O2-NEXT:    xor $1, $1, $5
 ; O2-NEXT:    jr $ra
 ; O2-NEXT:    sltiu $2, $1, 1
 ;
 ; O3-LABEL: AtomicCmpSwapRes8:
 ; O3:       # %bb.0: # %entry
 ; O3-NEXT:    addiu $1, $zero, -4
 ; O3-NEXT:    and $2, $4, $1
 ; O3-NEXT:    andi $1, $4, 3

 ; O3-NEXT:    sc $9, 0($2)
 ; O3-NEXT:    beqz $9, $BB13_1
 ; O3-NEXT:    nop
 ; O3-NEXT:  $BB13_3: # %entry
 ; O3-NEXT:    srlv $1, $10, $3
 ; O3-NEXT:    sll $1, $1, 24
 ; O3-NEXT:    sra $1, $1, 24
 ; O3-NEXT:  # %bb.4: # %entry
-; O3-NEXT:    sll $2, $5, 24
-; O3-NEXT:    sra $2, $2, 24
-; O3-NEXT:    xor $1, $1, $2
+; O3-NEXT:    xor $1, $1, $5
 ; O3-NEXT:    jr $ra
 ; O3-NEXT:    sltiu $2, $1, 1
 ;
 ; MIPS32EB-LABEL: AtomicCmpSwapRes8:
 ; MIPS32EB:       # %bb.0: # %entry
 ; MIPS32EB-NEXT:    addiu $1, $zero, -4
 ; MIPS32EB-NEXT:    and $2, $4, $1
 ; MIPS32EB-NEXT:    andi $1, $4, 3

 ; MIPS32EB-NEXT:    sc $9, 0($2)
 ; MIPS32EB-NEXT:    beqz $9, $BB13_1
 ; MIPS32EB-NEXT:    nop
 ; MIPS32EB-NEXT:  $BB13_3: # %entry
 ; MIPS32EB-NEXT:    srlv $1, $10, $3
 ; MIPS32EB-NEXT:    sll $1, $1, 24
 ; MIPS32EB-NEXT:    sra $1, $1, 24
 ; MIPS32EB-NEXT:  # %bb.4: # %entry
-; MIPS32EB-NEXT:    sll $2, $5, 24
-; MIPS32EB-NEXT:    sra $2, $2, 24
-; MIPS32EB-NEXT:    xor $1, $1, $2
+; MIPS32EB-NEXT:    xor $1, $1, $5
 ; MIPS32EB-NEXT:    jr $ra
 ; MIPS32EB-NEXT:    sltiu $2, $1, 1
 entry:
   %0 = cmpxchg i8* %ptr, i8 %oldval, i8 %newval monotonic monotonic
   %1 = extractvalue { i8, i1 } %0, 1
   ret i1 %1
 ; FIXME: -march=mips produces a redundant sign extension here...
 ; FIXME: ...Leading to this split check.

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
 ; RUN:     -verify-machineinstrs < %s | FileCheck %s
 
 define signext i8 @extractelt_nxv1i8_0(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv1i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv1i8_imm(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv1i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv1i8_idx(<vscale x 1 x i8> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv1i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv2i8_0(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv2i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv2i8_imm(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv2i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv2i8_idx(<vscale x 2 x i8> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv2i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv4i8_0(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv4i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv4i8_imm(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv4i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv4i8_idx(<vscale x 4 x i8> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv4i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv8i8_0(<vscale x 8 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv8i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv8i8_imm(<vscale x 8 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv8i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv8i8_idx(<vscale x 8 x i8> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv8i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv16i8_0(<vscale x 16 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv16i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv16i8_imm(<vscale x 16 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv16i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v26
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv16i8_idx(<vscale x 16 x i8> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv16i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v26
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv32i8_0(<vscale x 32 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv32i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv32i8_imm(<vscale x 32 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv32i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v28
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv32i8_idx(<vscale x 32 x i8> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv32i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v28
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv64i8_0(<vscale x 64 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv64i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 64 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv64i8_imm(<vscale x 64 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv64i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 64 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv64i8_idx(<vscale x 64 x i8> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv64i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 64 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i16 @extractelt_nxv1i16_0(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv1i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv1i16_imm(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv1i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv1i16_idx(<vscale x 1 x i16> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv1i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv2i16_0(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv2i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv2i16_imm(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv2i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv2i16_idx(<vscale x 2 x i16> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv2i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv4i16_0(<vscale x 4 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv4i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv4i16_imm(<vscale x 4 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv4i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv4i16_idx(<vscale x 4 x i16> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv4i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv8i16_0(<vscale x 8 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv8i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv8i16_imm(<vscale x 8 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv8i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v26
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv8i16_idx(<vscale x 8 x i16> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv8i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v26
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv16i16_0(<vscale x 16 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv16i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv16i16_imm(<vscale x 16 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv16i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v28
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv16i16_idx(<vscale x 16 x i16> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv16i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v28
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv32i16_0(<vscale x 32 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv32i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv32i16_imm(<vscale x 32 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv32i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv32i16_idx(<vscale x 32 x i16> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv32i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define i32 @extractelt_nxv1i32_0(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv1i32_0:
 ; CHECK:       # %bb.0:

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
 ; RUN:     -verify-machineinstrs < %s | FileCheck %s
 
 define signext i8 @extractelt_nxv1i8_0(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv1i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv1i8_imm(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv1i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv1i8_idx(<vscale x 1 x i8> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv1i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv2i8_0(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv2i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv2i8_imm(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv2i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv2i8_idx(<vscale x 2 x i8> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv2i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv4i8_0(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv4i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv4i8_imm(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv4i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv4i8_idx(<vscale x 4 x i8> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv4i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv8i8_0(<vscale x 8 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv8i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv8i8_imm(<vscale x 8 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv8i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv8i8_idx(<vscale x 8 x i8> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv8i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv16i8_0(<vscale x 16 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv16i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv16i8_imm(<vscale x 16 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv16i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v26
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv16i8_idx(<vscale x 16 x i8> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv16i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v26
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv32i8_0(<vscale x 32 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv32i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv32i8_imm(<vscale x 32 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv32i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v28
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv32i8_idx(<vscale x 32 x i8> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv32i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v28
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv64i8_0(<vscale x 64 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv64i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 64 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv64i8_imm(<vscale x 64 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv64i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 64 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv64i8_idx(<vscale x 64 x i8> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv64i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 64 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i16 @extractelt_nxv1i16_0(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv1i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv1i16_imm(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv1i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv1i16_idx(<vscale x 1 x i16> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv1i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv2i16_0(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv2i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv2i16_imm(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv2i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv2i16_idx(<vscale x 2 x i16> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv2i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv4i16_0(<vscale x 4 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv4i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv4i16_imm(<vscale x 4 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv4i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv4i16_idx(<vscale x 4 x i16> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv4i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv8i16_0(<vscale x 8 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv8i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv8i16_imm(<vscale x 8 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv8i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v26
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv8i16_idx(<vscale x 8 x i16> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv8i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v26
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv16i16_0(<vscale x 16 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv16i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv16i16_imm(<vscale x 16 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv16i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v28
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv16i16_idx(<vscale x 16 x i16> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv16i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v28
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv32i16_0(<vscale x 32 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv32i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv32i16_imm(<vscale x 32 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv32i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv32i16_idx(<vscale x 32 x i16> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv32i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i32 @extractelt_nxv1i32_0(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv1i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i32> %v, i32 0
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv1i32_imm(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv1i32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i32> %v, i32 2
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv1i32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i32> %v, i32 %idx
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv2i32_0(<vscale x 2 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv2i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i32> %v, i32 0
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv2i32_imm(<vscale x 2 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv2i32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i32> %v, i32 2
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv2i32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i32> %v, i32 %idx
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv4i32_0(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv4i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i32> %v, i32 0
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv4i32_imm(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv4i32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v26
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i32> %v, i32 2
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv4i32_idx(<vscale x 4 x i32> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv4i32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v26
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i32> %v, i32 %idx
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv8i32_0(<vscale x 8 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv8i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i32> %v, i32 0
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv8i32_imm(<vscale x 8 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv8i32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v28
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i32> %v, i32 2
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv8i32_idx(<vscale x 8 x i32> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv8i32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v28
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i32> %v, i32 %idx
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv16i32_0(<vscale x 16 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv16i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i32> %v, i32 0
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv16i32_imm(<vscale x 16 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv16i32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i32> %v, i32 2
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv16i32_idx(<vscale x 16 x i32> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv16i32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i32> %v, i32 %idx
   ret i32 %r
 }
 
 define i64 @extractelt_nxv1i64_0(<vscale x 1 x i64> %v) {
 ; CHECK-LABEL: extractelt_nxv1i64_0:
 ; CHECK:       # %bb.0: