[RISCV] Custom lowering of SET_ROUNDING

[jrtc27]

Would a SELECT not be more friendly to optimisations like known-bits analysis, or does that cause too much code to be emitted in the general case?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

376

StdExtD implies StdExtF. So I think you only need to check StdExtF

3204

Why do we need two code paths? Won't the other code constant fold if RMValue is a constant?

[sepavloff]

Updated patch according to reviewer's notes.

[sepavloff]

In D91242#2388630, @jrtc27 wrote:

Would a SELECT not be more friendly to optimisations like known-bits analysis, or does that cause too much code to be emitted in the general case?

Not sure if I understand you correctly, if you mean analyzing the 3 bits of rounding mode bit-by-bit, It think it does not make sense here. It is unlikely that only a part of the bits are known. Rounding mode is specified as a constant or obtained as a result of FLT_ROUNDS or as argument of a function call. Usually it is not obtained by calculations. And yes, in the general case too much code is generated, at least 8 operators, while in this implementation 5 instructions is enough.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

376

Fixed.

3204

Indeed, the general case can be optimized for constant arguments.

[craig.topper]

If this gets used in a function that does floating point, what prevents the machine schedulers from reordering the FP instructions with this? Don't we need to model FRM as a register and make the FP instructions implicitly use it? You'd also need to be using the constrained FP intrinsics which aren't implemented for RISCV yet.

[sepavloff]

Repased patch

[craig.topper]

llvm/include/llvm/ADT/FloatingPointMode.h

41 ↗

(On Diff #338760)

This doesn't appear to be used in this patch. I don't object to adding it just wondering why it is in the RISCV patch.

llvm/test/CodeGen/RISCV/fpenv.ll

59

COMMON doesn't appear in the runline in this test.

[sepavloff]

Aligned the implementation with that of FLT_ROUNDS_

[sepavloff]

llvm/test/CodeGen/RISCV/fpenv.ll

59

I changed patterns to those generated by update_llc_test_checks.py, as the test for FLT_ROUNDS_ already uses it.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.h

SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG,
                                              unsigned VecOpc) const;
   SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
                                             SelectionDAG &DAG) const;
   SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc,
                             bool HasMask = true) const;
   SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG,
                                             unsigned ExtendOpc) const;
   SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
 
   bool isEligibleForTailCallOptimization(
       CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
       const SmallVector<CCValAssign, 16> &ArgLocs) const;
 
   /// Generate error diagnostics if any register used by CC has been marked
   /// reserved.
   void validateCCReservedRegs(

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
   if (Subtarget.is64Bit()) {
     setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
     setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
     setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
     setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
   }
 
   if (Subtarget.hasStdExtF()) {
     setOperationAction(ISD::FLT_ROUNDS_, XLenVT, Custom);
+    setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
   }
 
   setOperationAction(ISD::GlobalAddress, XLenVT, Custom);
   setOperationAction(ISD::BlockAddress, XLenVT, Custom);
   setOperationAction(ISD::ConstantPool, XLenVT, Custom);
   setOperationAction(ISD::JumpTable, XLenVT, Custom);
 
   setOperationAction(ISD::GlobalTLSAddress, XLenVT, Custom);
SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   case ISD::FCOPYSIGN:
     return lowerFixedLengthVectorFCOPYSIGNToRVV(Op, DAG);
   case ISD::MGATHER:
     return lowerMGATHER(Op, DAG);
   case ISD::MSCATTER:
     return lowerMSCATTER(Op, DAG);
   case ISD::FLT_ROUNDS_:
     return lowerGET_ROUNDING(Op, DAG);
+  case ISD::SET_ROUNDING:
+    return lowerSET_ROUNDING(Op, DAG);
   }
 }
 
 static SDValue getTargetNode(GlobalAddressSDNode *N, SDLoc DL, EVT Ty,
                              SelectionDAG &DAG, unsigned Flags) {
   return DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, 0, Flags);
 }
 
SDValue RISCVTargetLowering::lowerVectorMaskVECREDUCE(SDValue Op,
                                                       SelectionDAG &DAG) const {
   SDLoc DL(Op);
   SDValue Vec = Op.getOperand(0);
   MVT VecVT = Vec.getSimpleValueType();
   assert((Op.getOpcode() == ISD::VECREDUCE_AND ||
           Op.getOpcode() == ISD::VECREDUCE_OR ||
           Op.getOpcode() == ISD::VECREDUCE_XOR) &&
          "Unexpected reduction lowering");
 
   MVT XLenVT = Subtarget.getXLenVT();
   assert(Op.getValueType() == XLenVT &&
          "Expected reduction output to be legalized to XLenVT");
 
   MVT ContainerVT = VecVT;
   if (VecVT.isFixedLengthVector()) {
     ContainerVT = getContainerForFixedLengthVector(VecVT);
     Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget);
SDValue RISCVTargetLowering::lowerGET_ROUNDING(SDValue Op,
   SDValue Shifted = DAG.getNode(ISD::SRL, DL, XLenVT,
                                 DAG.getConstant(Table, DL, XLenVT), Shift);
   SDValue Masked = DAG.getNode(ISD::AND, DL, XLenVT, Shifted,
                                DAG.getConstant(7, DL, XLenVT));
 
   return DAG.getMergeValues({Masked, Chain}, DL);
 }
 
+SDValue RISCVTargetLowering::lowerSET_ROUNDING(SDValue Op,
+                                               SelectionDAG &DAG) const {
+  const MVT XLenVT = Subtarget.getXLenVT();
+  SDLoc DL(Op);
+  SDValue Chain = Op->getOperand(0);
+  SDValue RMValue = Op->getOperand(1);
+  SDValue SysRegNo = DAG.getConstant(
+      RISCVSysReg::lookupSysRegByName("FRM")->Encoding, DL, XLenVT);
+
+  // Encoding used for rounding mode in RISCV differs from that used in
+  // FLT_ROUNDS. To convert it the C rounding mode is used as an index in
+  // a table, which consists of a sequence of 4-bit fields, each representing
+  // corresponding RISCV mode.
+  static const unsigned Table =
+      (RISCVFPRndMode::RNE << 4 * int(RoundingMode::NearestTiesToEven)) |
+      (RISCVFPRndMode::RTZ << 4 * int(RoundingMode::TowardZero)) |
+      (RISCVFPRndMode::RDN << 4 * int(RoundingMode::TowardNegative)) |
+      (RISCVFPRndMode::RUP << 4 * int(RoundingMode::TowardPositive)) |
+      (RISCVFPRndMode::RMM << 4 * int(RoundingMode::NearestTiesToAway));
+
+  SDValue Shift = DAG.getNode(ISD::SHL, DL, XLenVT, RMValue,
+                              DAG.getConstant(2, DL, XLenVT));
+  SDValue Shifted = DAG.getNode(ISD::SRL, DL, XLenVT,
+                                DAG.getConstant(Table, DL, XLenVT), Shift);
+  RMValue = DAG.getNode(ISD::AND, DL, XLenVT, Shifted,
+                        DAG.getConstant(0x7, DL, XLenVT));
+  return DAG.getNode(RISCVISD::WRITE_CSR, DL, MVT::Other, Chain, SysRegNo,
+                     RMValue);
+}
+
 // Returns the opcode of the target-specific SDNode that implements the 32-bit
 // form of the given Opcode.
 static RISCVISD::NodeType getRISCVWOpcode(unsigned Opcode) {
   switch (Opcode) {
   default:
     llvm_unreachable("Unexpected opcode");
   case ISD::SHL:
     return RISCVISD::SLLW;

llvm/test/CodeGen/RISCV/fpenv.ll

 ; RV64IF-NEXT:    addiw a1, a1, 769
 ; RV64IF-NEXT:    srl a0, a1, a0
 ; RV64IF-NEXT:    andi a0, a0, 7
 ; RV64IF-NEXT:    ret
   %rm = call i32 @llvm.flt.rounds()
   ret i32 %rm
 }
 
+define void @func_02(i32 %rm) {
+; RV32IF-LABEL: func_02:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    slli a0, a0, 2
+; RV32IF-NEXT:    lui a1, 66
+; RV32IF-NEXT:    addi a1, a1, 769
+; RV32IF-NEXT:    srl a0, a1, a0
+; RV32IF-NEXT:    andi a0, a0, 7
+; RV32IF-NEXT:    fsrm a0
+; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: func_02:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    slli a0, a0, 32
+; RV64IF-NEXT:    srli a0, a0, 30
+; RV64IF-NEXT:    lui a1, 66
+; RV64IF-NEXT:    addiw a1, a1, 769
+; RV64IF-NEXT:    srl a0, a1, a0
+; RV64IF-NEXT:    andi a0, a0, 7
+; RV64IF-NEXT:    fsrm a0
+; RV64IF-NEXT:    ret
+  call void @llvm.set.rounding(i32 %rm)
+  ret void
+}
+
+define void @func_03() {
+; RV32IF-LABEL: func_03:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fsrmi 1
+; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: func_03:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    fsrmi 1
+; RV64IF-NEXT:    ret
+  call void @llvm.set.rounding(i32 0)
+  ret void
+}
+
+define void @func_04() {
+; RV32IF-LABEL: func_04:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fsrmi 0
+; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: func_04:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    fsrmi 0
+; RV64IF-NEXT:    ret
+  call void @llvm.set.rounding(i32 1)
+  ret void
+}
+
+define void @func_05() {
+; RV32IF-LABEL: func_05:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fsrmi 3
+; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: func_05:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    fsrmi 3
+; RV64IF-NEXT:    ret
+  call void @llvm.set.rounding(i32 2)
+  ret void
+}
+
+define void @func_06() {
+; RV32IF-LABEL: func_06:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fsrmi 2
+; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: func_06:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    fsrmi 2
+; RV64IF-NEXT:    ret
+  call void @llvm.set.rounding(i32 3)
+  ret void
+}
+
+define void @func_07() {
+; RV32IF-LABEL: func_07:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fsrmi 4
+; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: func_07:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    fsrmi 4
+; RV64IF-NEXT:    ret
+  call void @llvm.set.rounding(i32 4)
+  ret void
+}
+
+declare void @llvm.set.rounding(i32)
 declare i32 @llvm.flt.rounds()