[RISCV] Custom lowering of SET_ROUNDING

[jrtc27]

Would a SELECT not be more friendly to optimisations like known-bits analysis, or does that cause too much code to be emitted in the general case?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

225

StdExtD implies StdExtF. So I think you only need to check StdExtF

904

Why do we need two code paths? Won't the other code constant fold if RMValue is a constant?

[sepavloff]

Updated patch according to reviewer's notes.

[sepavloff]

In D91242#2388630, @jrtc27 wrote:

Would a SELECT not be more friendly to optimisations like known-bits analysis, or does that cause too much code to be emitted in the general case?

Not sure if I understand you correctly, if you mean analyzing the 3 bits of rounding mode bit-by-bit, It think it does not make sense here. It is unlikely that only a part of the bits are known. Rounding mode is specified as a constant or obtained as a result of FLT_ROUNDS or as argument of a function call. Usually it is not obtained by calculations. And yes, in the general case too much code is generated, at least 8 operators, while in this implementation 5 instructions is enough.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

225

Fixed.

904

Indeed, the general case can be optimized for constant arguments.

[craig.topper]

If this gets used in a function that does floating point, what prevents the machine schedulers from reordering the FP instructions with this? Don't we need to model FRM as a register and make the FP instructions implicitly use it? You'd also need to be using the constrained FP intrinsics which aren't implemented for RISCV yet.

[sepavloff]

Repased patch

[craig.topper]

llvm/include/llvm/ADT/FloatingPointMode.h

41

This doesn't appear to be used in this patch. I don't object to adding it just wondering why it is in the RISCV patch.

llvm/test/CodeGen/RISCV/fpenv.ll

57

COMMON doesn't appear in the runline in this test.

[sepavloff]

Aligned the implementation with that of FLT_ROUNDS_

[sepavloff]

llvm/test/CodeGen/RISCV/fpenv.ll

57

I changed patterns to those generated by update_llc_test_checks.py, as the test for FLT_ROUNDS_ already uses it.

[craig.topper]

LGTM

llvm/include/llvm/ADT/FloatingPointMode.h

 //===- llvm/Support/FloatingPointMode.h -------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // Utilities for dealing with flags related to floating point mode controls.

 /// This value is packed into bitfield in some cases, including \c FPOptions, so
 /// the rounding mode values and the special value \c Dynamic must fit into the
 /// the bit field (now - 3 bits). The value \c Invalid is used only in values
 /// returned by intrinsics to indicate errors, it should never be stored as
 /// rounding mode value, so it does not need to fit the bit fields.
 ///
 enum class RoundingMode : int8_t {
   // Rounding mode defined in IEEE-754.
   TowardZero        = 0,    ///< roundTowardZero.
   NearestTiesToEven = 1,    ///< roundTiesToEven.
   TowardPositive    = 2,    ///< roundTowardPositive.
   TowardNegative    = 3,    ///< roundTowardNegative.
   NearestTiesToAway = 4,    ///< roundTiesToAway.
+  MaxIEEEMode       = NearestTiesToAway,
 
   // Special values.
   Dynamic = 7,    ///< Denotes mode unknown at compile time.
   Invalid = -1    ///< Denotes invalid value.
 };
 
 /// Returns text representation of the given rounding mode.
 inline StringRef spell(RoundingMode RM) {
   switch (RM) {
   case RoundingMode::TowardZero: return "towardzero";
   case RoundingMode::NearestTiesToEven: return "tonearest";

llvm/lib/Target/RISCV/RISCVISelLowering.h

enum NodeType : unsigned {
   // Write value to CSR.
   // The first operand is a chain pointer, the second specifies address of the
   // required CSR and the third is the value to write. The result is chain
   // pointer.
   WRITE_CSR
 };
 }
 
+namespace RISCV {
+// Must agree with definitions in RISCVSystemOperands.td
+enum SysReg {
+  // User Floating-Point CSRs
+  FFLAGS = 0x001,
+  FRM = 0x002,
+  FCSR = 0x003
+};
+
+enum Rounding {
+  RNE = 0, ///< roundTiesToEven.
+  RTZ = 1, ///< roundTowardZero.
+  RDN = 2, ///< roundTowardPositive.
+  RUP = 3, ///< roundTowardPositive.
+  RMM = 4, ///< roundTiesToAway.
+  MaxRounding = RMM,
+  DYN = 7
+};
+} // namespace RISCV
+
 class RISCVTargetLowering : public TargetLowering {
   const RISCVSubtarget &Subtarget;
 
 public:
   explicit RISCVTargetLowering(const TargetMachine &TM,
                                const RISCVSubtarget &STI);
 
   bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
private:
   SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
 
   bool isEligibleForTailCallOptimization(
       CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
       const SmallVector<CCValAssign, 16> &ArgLocs) const;
 
   /// Generate error diagnostics if any register used by CC has been marked
   /// reserved.
   void validateCCReservedRegs(
       const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
       MachineFunction &MF) const;
 };
 }
 
 #endif

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the interfaces that RISCV uses to lower LLVM code into a
RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
   if (Subtarget.is64Bit()) {
     setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
     setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
     setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
     setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
   }
 
+  if (Subtarget.hasStdExtF()) {
+    setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
+  }
+
   setOperationAction(ISD::GlobalAddress, XLenVT, Custom);
   setOperationAction(ISD::BlockAddress, XLenVT, Custom);
   setOperationAction(ISD::ConstantPool, XLenVT, Custom);
 
   setOperationAction(ISD::GlobalTLSAddress, XLenVT, Custom);
 
   // TODO: On M-mode only targets, the cycle[h] CSR may not be present.
   // Unfortunately this can't be determined just from the ISA naming string.
case ISD::BITCAST: {
     if (Op.getValueType() != MVT::f32 || Op0.getValueType() != MVT::i32)
       return SDValue();
     SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
     SDValue FPConv = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, NewOp0);
     return FPConv;
   }
   case ISD::INTRINSIC_WO_CHAIN:
     return LowerINTRINSIC_WO_CHAIN(Op, DAG);
+  case ISD::SET_ROUNDING:
+    return lowerSET_ROUNDING(Op, DAG);
   }
 }
 
 static SDValue getTargetNode(GlobalAddressSDNode *N, SDLoc DL, EVT Ty,
                              SelectionDAG &DAG, unsigned Flags) {
   return DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, 0, Flags);
 }
 
default:
     return SDValue();    // Don't custom lower most intrinsics.
   case Intrinsic::thread_pointer: {
     EVT PtrVT = getPointerTy(DAG.getDataLayout());
     return DAG.getRegister(RISCV::X4, PtrVT);
   }
   }
 }
 
+SDValue RISCVTargetLowering::lowerSET_ROUNDING(SDValue Op,
+                                               SelectionDAG &DAG) const {
+  const MVT IntTy = Subtarget.getXLenVT();
+  SDLoc DL(Op);
+  SDValue Chain = Op->getOperand(0);
+  SDValue RMValue = Op->getOperand(1);
+  SDValue SysRegNo = DAG.getConstant(RISCV::SysReg::FRM, DL, IntTy);
+
+  // Encoding used for rounding mode in RISCV differs from that used in
+  // FLT_ROUNDS. To convert it the C rounding mode is used as an index in
+  // a table, which consists of a sequence of 4-bit fields, each representing
+  // corresponding RISCV mode.
+  static const unsigned Table =
+      (RISCV::Rounding::RNE << 4 * int(RoundingMode::NearestTiesToEven)) |
+      (RISCV::Rounding::RTZ << 4 * int(RoundingMode::TowardZero)) |
+      (RISCV::Rounding::RDN << 4 * int(RoundingMode::TowardNegative)) |
+      (RISCV::Rounding::RUP << 4 * int(RoundingMode::TowardPositive)) |
+      (RISCV::Rounding::RMM << 4 * int(RoundingMode::NearestTiesToAway));
+
+  SDValue Shift = DAG.getNode(ISD::SHL, DL, IntTy, RMValue,
+                              DAG.getConstant(2, DL, IntTy));
+  SDValue Shifted = DAG.getNode(ISD::SRL, DL, IntTy,
+                                DAG.getConstant(Table, DL, IntTy), Shift);
+  RMValue = DAG.getNode(ISD::AND, DL, IntTy, Shifted,
+                        DAG.getConstant(0x7, DL, IntTy));
+  return DAG.getNode(RISCVISD::WRITE_CSR, DL, MVT::Other, Chain, SysRegNo,
+                     RMValue);
+}
+
 // Returns the opcode of the target-specific SDNode that implements the 32-bit
 // form of the given Opcode.
 static RISCVISD::NodeType getRISCVWOpcode(unsigned Opcode) {
   switch (Opcode) {
   default:
     llvm_unreachable("Unexpected opcode");
   case ISD::SHL:
     return RISCVISD::SLLW;

llvm/test/CodeGen/RISCV/fpenv.ll

+; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32IF,COMMON %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64IF,COMMON %s
+
+define void @func_02(i32 %rm) {
+  call void @llvm.set.rounding(i32 %rm)
+  ret void
+}
+
+; RV32IF-LABEL: func_02:
+; RV32IF        slli  a0, a0, 2
+; RV32IF        lui   a1, 66
+; RV32IF        addi  a1, a1, 769
+; RV32IF        srl   a0, a1, a0
+; RV32IF        andi  a0, a0, 7
+; RV32IF        csrw  frm, a0
+; RV32IF        ret
+
+; RV64IF-LABEL: func_02:
+; RV64IF:       slli  a0, a0, 32
+; RV64IF:       srli  a0, a0, 32
+; RV64IF:       slli  a0, a0, 2
+; RV64IF:       lui   a1, 66
+; RV64IF:       addiw a1, a1, 769
+; RV64IF:       srl   a0, a1, a0
+; RV64IF:       andi  a0, a0, 7
+; RV64IF:       csrw  frm, a0
+; RV64IF:       ret
+
+
+define void @func_03() {
+  call void @llvm.set.rounding(i32 0)
+  ret void
+}
+
+; COMMON-LABEL: func_03
+; COMMON:       csrwi  frm, 1
+; COMMON:       ret
+
+
+define void @func_04() {
+  call void @llvm.set.rounding(i32 1)
+  ret void
+}
+
+; COMMON-LABEL: func_04
+; COMMON:       csrwi  frm, 0
+; COMMON:       ret
+
+
+define void @func_05() {
+  call void @llvm.set.rounding(i32 2)
+  ret void
+}
+
+; COMMON-LABEL: func_05
+; COMMON:       csrwi  frm, 3
+; COMMON:       ret
+
+
+define void @func_06() {
+  call void @llvm.set.rounding(i32 3)
+  ret void
+}
+
+; COMMON-LABEL: func_06
+; COMMON:       csrwi  frm, 2
+; COMMON:       ret
+
+
+define void @func_07() {
+  call void @llvm.set.rounding(i32 4)
+  ret void
+}
+
+; COMMON-LABEL: func_07
+; COMMON:       csrwi  frm, 4
+; COMMON:       ret
+
+
+declare void @llvm.set.rounding(i32)