[RISCV] Set dependency on floating point CSRs, 3/3

[sepavloff]

Summary

This change continues implementation of implicit defs/uses for FP
instructions. It implements the support for unary operations.

[sepavloff]

Reduced number of instruction variants from 3 to 2 (generic and default)

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

 multiclass FPALUD_mc<bits<7> funct7, string OpcodeStr> {
   def _gen : FPALU_gen<funct7, OpcodeStr, FPR64>;
   def _def : FPALU_def<funct7, OpcodeStr, FPR64>;
   def      : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
                        (!cast<Instruction>(NAME # "_gen")
                         FPR64:$rd, FPR64:$rs1, FPR64:$rs2, 0b111)>;
 }
 
+multiclass FPUnaryD_mc<bits<7> funct7, RegisterClass rdty, RegisterClass rs1ty,
+                        string OpcodeStr, bits<5> rs2val> {
+  def _gen : FPUnaryOp_gen<funct7, rdty, rs1ty, OpcodeStr, rs2val>;
+  def _def : FPUnaryOp_def<funct7, rdty, rs1ty, OpcodeStr, rs2val>;
+  def      : InstAlias<OpcodeStr#" $rd, $rs1",
+                       (!cast<Instruction>(NAME # "_gen")
+                        rdty:$rd, rs1ty:$rs1, 0b111)>;
+}
+
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class FPALUD_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
     : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR64:$rd),
               (ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class FPCmpD_rr<bits<3> funct3, string opcodestr>
     : RVInstR<0b1010001, funct3, OPC_OP_FP, (outs GPR:$rd),
defm FADD_D : FPALUD_mc<0b0000001, "fadd.d">,
               Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
 defm FSUB_D : FPALUD_mc<0b0000101, "fsub.d">,
               Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
 defm FMUL_D : FPALUD_mc<0b0001001, "fmul.d">,
               Sched<[WriteFMul64, ReadFMul64, ReadFMul64]>;
 defm FDIV_D : FPALUD_mc<0b0001101, "fdiv.d">,
               Sched<[WriteFDiv64, ReadFDiv64, ReadFDiv64]>;
 
-def FSQRT_D : FPUnaryOp_r_frm<0b0101101, FPR64, FPR64, "fsqrt.d">,
-              Sched<[WriteFSqrt64, ReadFSqrt64]> {
-  let rs2 = 0b00000;
-}
-def         : FPUnaryOpDynFrmAlias<FSQRT_D, "fsqrt.d", FPR64, FPR64>;
+defm FSQRT_D : FPUnaryD_mc<0b0101101, FPR64, FPR64, "fsqrt.d", 0b00000>,
+              Sched<[WriteFSqrt64, ReadFSqrt64]>;
 
 def FSGNJ_D  : FPALUD_rr<0b0010001, 0b000, "fsgnj.d">,
                Sched<[WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64]>;
 def FSGNJN_D : FPALUD_rr<0b0010001, 0b001, "fsgnjn.d">,
                Sched<[WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64]>;
 def FSGNJX_D : FPALUD_rr<0b0010001, 0b010, "fsgnjx.d">,
                Sched<[WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64]>;
 def FMIN_D   : FPALUD_rr<0b0010101, 0b000, "fmin.d">,
                Sched<[WriteFMinMax64, ReadFMinMax64, ReadFMinMax64]>;
 def FMAX_D   : FPALUD_rr<0b0010101, 0b001, "fmax.d">,
                Sched<[WriteFMinMax64, ReadFMinMax64, ReadFMinMax64]>;
 
-def FCVT_S_D : FPUnaryOp_r_frm<0b0100000, FPR32, FPR64, "fcvt.s.d">,
-               Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]> {
-  let rs2 = 0b00001;
-}
-def          : FPUnaryOpDynFrmAlias<FCVT_S_D, "fcvt.s.d", FPR32, FPR64>;
+defm FCVT_S_D : FPUnaryD_mc<0b0100000, FPR32, FPR64, "fcvt.s.d", 0b00001>,
+               Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]>;
 
 def FCVT_D_S : FPUnaryOp_r<0b0100001, 0b000, FPR64, FPR32, "fcvt.d.s">,
                Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]> {
   let rs2 = 0b00000;
 }
 
 def FEQ_D : FPCmpD_rr<0b010, "feq.d">;
 def FLT_D : FPCmpD_rr<0b001, "flt.d">;
 def FLE_D : FPCmpD_rr<0b000, "fle.d">;
 
 def FCLASS_D : FPUnaryOp_r<0b1110001, 0b001, GPR, FPR64, "fclass.d">,
                Sched<[WriteFClass64, ReadFClass64]> {
   let rs2 = 0b00000;
 }
 
-def FCVT_W_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.w.d">,
-               Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]> {
-  let rs2 = 0b00000;
-}
-def          : FPUnaryOpDynFrmAlias<FCVT_W_D, "fcvt.w.d", GPR, FPR64>;
-
-def FCVT_WU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.wu.d">,
-                Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]> {
-  let rs2 = 0b00001;
-}
-def           : FPUnaryOpDynFrmAlias<FCVT_WU_D, "fcvt.wu.d", GPR, FPR64>;
+defm FCVT_W_D  : FPUnaryD_mc<0b1100001, GPR, FPR64, "fcvt.w.d", 0b00000>,
+                 Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>;
+defm FCVT_WU_D : FPUnaryD_mc<0b1100001, GPR, FPR64, "fcvt.wu.d", 0b00001>,
+                 Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>;
 
 def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w">,
                Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]> {
   let rs2 = 0b00000;
 }
 
 def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.wu">,
                 Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]> {
   let rs2 = 0b00001;
 }
 } // Predicates = [HasStdExtD]
 
 let Predicates = [HasStdExtD, IsRV64] in {
-def FCVT_L_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.l.d">,
-               Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]> {
-  let rs2 = 0b00010;
-}
-def          : FPUnaryOpDynFrmAlias<FCVT_L_D, "fcvt.l.d", GPR, FPR64>;
-
-def FCVT_LU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.lu.d">,
-                Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]> {
-  let rs2 = 0b00011;
-}
-def           : FPUnaryOpDynFrmAlias<FCVT_LU_D, "fcvt.lu.d", GPR, FPR64>;
+defm FCVT_L_D  : FPUnaryD_mc<0b1100001, GPR, FPR64, "fcvt.l.d", 0b00010>,
+                 Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>;
+defm FCVT_LU_D : FPUnaryD_mc<0b1100001, GPR, FPR64, "fcvt.lu.d", 0b00011>,
+                 Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>;
 
 def FMV_X_D : FPUnaryOp_r<0b1110001, 0b000, GPR, FPR64, "fmv.x.d">,
               Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]> {
   let rs2 = 0b00000;
 }
 
-def FCVT_D_L : FPUnaryOp_r_frm<0b1101001, FPR64, GPR, "fcvt.d.l">,
-               Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]> {
-  let rs2 = 0b00010;
-}
-def          : FPUnaryOpDynFrmAlias<FCVT_D_L, "fcvt.d.l", FPR64, GPR>;
-
-def FCVT_D_LU : FPUnaryOp_r_frm<0b1101001, FPR64, GPR, "fcvt.d.lu">,
-                Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]> {
-  let rs2 = 0b00011;
-}
-def           : FPUnaryOpDynFrmAlias<FCVT_D_LU, "fcvt.d.lu", FPR64, GPR>;
+defm FCVT_D_L  : FPUnaryD_mc<0b1101001, FPR64, GPR, "fcvt.d.l", 0b00010>,
+                 Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>;
+defm FCVT_D_LU : FPUnaryD_mc<0b1101001, FPR64, GPR, "fcvt.d.lu", 0b00011>,
+                 Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>;
 
 def FMV_D_X : FPUnaryOp_r<0b1111001, 0b000, FPR64, GPR, "fmv.d.x">,
               Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64]> {
   let rs2 = 0b00000;
 }
 } // Predicates = [HasStdExtD, IsRV64]
 
 //===----------------------------------------------------------------------===//

 class PatFpr64Fpr64<SDPatternOperator OpNode, RVInstR Inst>
     : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2)>;
 
 let Predicates = [HasStdExtD] in {
 
 /// Float conversion operations
 
 // f64 -> f32, f32 -> f64
-def : Pat<(fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, 0b111)>;
+def : Pat<(fpround FPR64:$rs1), (FCVT_S_D_def FPR64:$rs1)>;
 def : Pat<(fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1)>;
 
 // [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so
 // are defined later.
 
 /// Float arithmetic operations
 
 def : Pat<(fadd FPR64:$rs1, FPR64:$rs2), (FADD_D_def $rs1, $rs2)>;
 def : Pat<(fsub FPR64:$rs1, FPR64:$rs2), (FSUB_D_def $rs1, $rs2)>;
 def : Pat<(fmul FPR64:$rs1, FPR64:$rs2), (FMUL_D_def $rs1, $rs2)>;
 def : Pat<(fdiv FPR64:$rs1, FPR64:$rs2), (FDIV_D_def $rs1, $rs2)>;
 
-def : Pat<(fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, 0b111)>;
+def : Pat<(fsqrt FPR64:$rs1), (FSQRT_D_def FPR64:$rs1)>;
 
 def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>;
 def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>;
 
 def : PatFpr64Fpr64<fcopysign, FSGNJ_D>;
 def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>;
 def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2))>;
-def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2,
-                                                              0b111))>;
+def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D_def $rs2))>;
 
 // fmadd: rs1 * rs2 + rs3
 def : Pat<(fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3),
           (FMADD_D_def $rs1, $rs2, $rs3)>;
 
 // fmsub: rs1 * rs2 - rs3
 def : Pat<(fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)),
           (FMSUB_D_def FPR64:$rs1, FPR64:$rs2, FPR64:$rs3)>;

 } // Predicates = [HasStdExtD]
 
 let Predicates = [HasStdExtD, IsRV32] in {
 
 /// Float constants
 def : Pat<(f64 (fpimm0)), (FCVT_D_W (i32 X0))>;
 
 // double->[u]int. Round-to-zero must be used.
-def : Pat<(i32 (fp_to_sint FPR64:$rs1)), (FCVT_W_D FPR64:$rs1, 0b001)>;
-def : Pat<(i32 (fp_to_uint FPR64:$rs1)), (FCVT_WU_D FPR64:$rs1, 0b001)>;
+def : Pat<(i32 (fp_to_sint FPR64:$rs1)), (FCVT_W_D_gen FPR64:$rs1, 0b001)>;
+def : Pat<(i32 (fp_to_uint FPR64:$rs1)), (FCVT_WU_D_gen FPR64:$rs1, 0b001)>;
 
 // [u]int->double.
 def : Pat<(sint_to_fp (i32 GPR:$rs1)), (FCVT_D_W GPR:$rs1)>;
 def : Pat<(uint_to_fp (i32 GPR:$rs1)), (FCVT_D_WU GPR:$rs1)>;
 } // Predicates = [HasStdExtD, IsRV32]
 
 let Predicates = [HasStdExtD, IsRV64] in {
 
 /// Float constants
 def : Pat<(f64 (fpimm0)), (FMV_D_X (i64 X0))>;
 
 // Moves (no conversion)
 def : Pat<(bitconvert (i64 GPR:$rs1)), (FMV_D_X GPR:$rs1)>;
 def : Pat<(i64 (bitconvert FPR64:$rs1)), (FMV_X_D FPR64:$rs1)>;
 
 // FP->[u]int32 is mostly handled by the FP->[u]int64 patterns. This is safe
 // because fpto[u|s]i produce poison if the value can't fit into the target.
 // We match the single case below because fcvt.wu.d sign-extends its result so
 // is cheaper than fcvt.lu.d+sext.w.
 def : Pat<(sext_inreg (assertzexti32 (fp_to_uint FPR64:$rs1)), i32),
-          (FCVT_WU_D $rs1, 0b001)>;
+          (FCVT_WU_D_gen $rs1, 0b001)>;
 
 // [u]int32->fp
 def : Pat<(sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_D_W $rs1)>;
 def : Pat<(uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_D_WU $rs1)>;
 
-def : Pat<(i64 (fp_to_sint FPR64:$rs1)), (FCVT_L_D FPR64:$rs1, 0b001)>;
-def : Pat<(i64 (fp_to_uint FPR64:$rs1)), (FCVT_LU_D FPR64:$rs1, 0b001)>;
+def : Pat<(i64 (fp_to_sint FPR64:$rs1)), (FCVT_L_D_gen FPR64:$rs1, 0b001)>;
+def : Pat<(i64 (fp_to_uint FPR64:$rs1)), (FCVT_LU_D_gen FPR64:$rs1, 0b001)>;
 
-// [u]int64->fp. Match GCC and default to using dynamic rounding mode.
-def : Pat<(sint_to_fp (i64 GPR:$rs1)), (FCVT_D_L GPR:$rs1, 0b111)>;
-def : Pat<(uint_to_fp (i64 GPR:$rs1)), (FCVT_D_LU GPR:$rs1, 0b111)>;
+// [u]int64->fp.
+def : Pat<(sint_to_fp (i64 GPR:$rs1)), (FCVT_D_L_def GPR:$rs1)>;
+def : Pat<(uint_to_fp (i64 GPR:$rs1)), (FCVT_D_LU_def GPR:$rs1)>;
 } // Predicates = [HasStdExtD, IsRV64]

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

multiclass FPALUS_mc<bits<7> funct7, string OpcodeStr> {
   def _def : FPALU_def<funct7, OpcodeStr, FPR32>;
   def      : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
                        (!cast<Instruction>(NAME # "_gen")
                         FPR32:$rd, FPR32:$rs1, FPR32:$rs2, 0b111)>;
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class FPUnaryOp_r<bits<7> funct7, bits<3> funct3, RegisterClass rdty,
                   RegisterClass rs1ty, string opcodestr>
     : RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd), (ins rs1ty:$rs1),
               opcodestr, "$rd, $rs1">;
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class FPUnaryOp_r_frm<bits<7> funct7, RegisterClass rdty, RegisterClass rs1ty,
-                      string opcodestr>
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+  class FPUnaryOp_gen<bits<7> funct7, RegisterClass rdty, RegisterClass rs1ty,
+                      string opcodestr, bits<5> rs2val>
       : RVInstRFrm<funct7, OPC_OP_FP, (outs rdty:$rd),
                    (ins rs1ty:$rs1, frmarg:$funct3), opcodestr,
-                  "$rd, $rs1, $funct3">;
+                    "$rd, $rs1, $funct3"> {
+    let Defs = [FFLAGSReg];
+    let Uses = [FRMReg];
+    let rs2 = rs2val;
+  }
+
+  class FPUnaryOp_def<bits<7> funct7, RegisterClass rdty, RegisterClass rs1ty,
+                      string opcodestr, bits<5> rs2val>
+      : RVInstRFrm<funct7, OPC_OP_FP, (outs rdty:$rd),
+                   (ins rs1ty:$rs1), opcodestr, "$rd, $rs1, rne"> {
+    let funct3 = 0b000;
+    let rs2 = rs2val;
+  }
+}
 
-class FPUnaryOpDynFrmAlias<FPUnaryOp_r_frm Inst, string OpcodeStr,
-                           RegisterClass rdty, RegisterClass rs1ty>
-    : InstAlias<OpcodeStr#" $rd, $rs1",
-                (Inst rdty:$rd, rs1ty:$rs1, 0b111)>;
+multiclass FPUnaryS_mc<bits<7> funct7, RegisterClass rdty, RegisterClass rs1ty,
+                        string OpcodeStr, bits<5> rs2val> {
+  def _gen : FPUnaryOp_gen<funct7, rdty, rs1ty, OpcodeStr, rs2val>;
+  def _def : FPUnaryOp_def<funct7, rdty, rs1ty, OpcodeStr, rs2val>;
+  def      : InstAlias<OpcodeStr#" $rd, $rs1",
+                       (!cast<Instruction>(NAME # "_gen")
+                        rdty:$rd, rs1ty:$rs1, 0b111)>;
+}
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class FPCmpS_rr<bits<3> funct3, string opcodestr>
     : RVInstR<0b1010000, funct3, OPC_OP_FP, (outs GPR:$rd),
               (ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">,
       Sched<[WriteFCmp32, ReadFCmp32, ReadFCmp32]>;
 
 //===----------------------------------------------------------------------===//
defm FADD_S : FPALUS_mc<0b0000000, "fadd.s">,
               Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
 defm FSUB_S : FPALUS_mc<0b0000100, "fsub.s">,
               Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
 defm FMUL_S : FPALUS_mc<0b0001000, "fmul.s">,
               Sched<[WriteFMul32, ReadFMul32, ReadFMul32]>;
 defm FDIV_S : FPALUS_mc<0b0001100, "fdiv.s">,
               Sched<[WriteFDiv32, ReadFDiv32, ReadFDiv32]>;
 
-def FSQRT_S : FPUnaryOp_r_frm<0b0101100, FPR32, FPR32, "fsqrt.s">,
-              Sched<[WriteFSqrt32, ReadFSqrt32]> {
-  let rs2 = 0b00000;
-}
-def         : FPUnaryOpDynFrmAlias<FSQRT_S, "fsqrt.s", FPR32, FPR32>;
+defm FSQRT_S : FPUnaryS_mc<0b0101100, FPR32, FPR32, "fsqrt.s", 0b00000>,
+               Sched<[WriteFSqrt32, ReadFSqrt32]>;
 
 def FSGNJ_S  : FPALUS_rr<0b0010000, 0b000, "fsgnj.s">,
                Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>;
 def FSGNJN_S : FPALUS_rr<0b0010000, 0b001, "fsgnjn.s">,
                Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>;
 def FSGNJX_S : FPALUS_rr<0b0010000, 0b010, "fsgnjx.s">,
                Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>;
 def FMIN_S   : FPALUS_rr<0b0010100, 0b000, "fmin.s">,
                Sched<[WriteFMinMax32, ReadFMinMax32, ReadFMinMax32]>;
 def FMAX_S   : FPALUS_rr<0b0010100, 0b001, "fmax.s">,
                Sched<[WriteFMinMax32, ReadFMinMax32, ReadFMinMax32]>;
 
-def FCVT_W_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.w.s">,
-               Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]> {
-  let rs2 = 0b00000;
-}
-def          : FPUnaryOpDynFrmAlias<FCVT_W_S, "fcvt.w.s", GPR, FPR32>;
+defm FCVT_W_S  : FPUnaryS_mc<0b1100000, GPR, FPR32, "fcvt.w.s", 0b00000>,
+                 Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]>;
 
-def FCVT_WU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.wu.s">,
-                Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]> {
-  let rs2 = 0b00001;
-}
-def           : FPUnaryOpDynFrmAlias<FCVT_WU_S, "fcvt.wu.s", GPR, FPR32>;
+defm FCVT_WU_S : FPUnaryS_mc<0b1100000, GPR, FPR32, "fcvt.wu.s", 0b00001>,
+                 Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]>;
 
 def FMV_X_W : FPUnaryOp_r<0b1110000, 0b000, GPR, FPR32, "fmv.x.w">,
               Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]> {
   let rs2 = 0b00000;
 }
 
 def FEQ_S : FPCmpS_rr<0b010, "feq.s">;
 def FLT_S : FPCmpS_rr<0b001, "flt.s">;
 def FLE_S : FPCmpS_rr<0b000, "fle.s">;
 
 def FCLASS_S : FPUnaryOp_r<0b1110000, 0b001, GPR, FPR32, "fclass.s">,
                Sched<[WriteFClass32, ReadFClass32]> {
   let rs2 = 0b00000;
 }
 
-def FCVT_S_W : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.w">,
-               Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]> {
-  let rs2 = 0b00000;
-}
-def          : FPUnaryOpDynFrmAlias<FCVT_S_W, "fcvt.s.w", FPR32, GPR>;
+defm FCVT_S_W : FPUnaryS_mc<0b1101000, FPR32, GPR, "fcvt.s.w", 0b00000>,
+                Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]>;
 
-def FCVT_S_WU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.wu">,
-                Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]> {
-  let rs2 = 0b00001;
-}
-def           : FPUnaryOpDynFrmAlias<FCVT_S_WU, "fcvt.s.wu", FPR32, GPR>;
+defm FCVT_S_WU : FPUnaryS_mc<0b1101000, FPR32, GPR, "fcvt.s.wu", 0b00001>,
+                 Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]>;
 
 def FMV_W_X : FPUnaryOp_r<0b1111000, 0b000, FPR32, GPR, "fmv.w.x">,
               Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]> {
   let rs2 = 0b00000;
 }
 } // Predicates = [HasStdExtF]
 
 let Predicates = [HasStdExtF, IsRV64] in {
-def FCVT_L_S  : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.l.s">,
-                Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]> {
-  let rs2 = 0b00010;
-}
-def           : FPUnaryOpDynFrmAlias<FCVT_L_S, "fcvt.l.s", GPR, FPR32>;
-
-def FCVT_LU_S  : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.lu.s">,
-                 Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]> {
-  let rs2 = 0b00011;
-}
-def            : FPUnaryOpDynFrmAlias<FCVT_LU_S, "fcvt.lu.s", GPR, FPR32>;
-
-def FCVT_S_L : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.l">,
-               Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]> {
-  let rs2 = 0b00010;
-}
-def          : FPUnaryOpDynFrmAlias<FCVT_S_L, "fcvt.s.l", FPR32, GPR>;
-
-def FCVT_S_LU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.lu">,
-                Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]> {
-  let rs2 = 0b00011;
-}
-def           : FPUnaryOpDynFrmAlias<FCVT_S_LU, "fcvt.s.lu", FPR32, GPR>;
+defm FCVT_L_S  : FPUnaryS_mc<0b1100000, GPR, FPR32, "fcvt.l.s", 0b00010>,
+                 Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]>;
+defm FCVT_LU_S : FPUnaryS_mc<0b1100000, GPR, FPR32, "fcvt.lu.s", 0b00011>,
+                 Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]>;
+defm FCVT_S_L  : FPUnaryS_mc<0b1101000, FPR32, GPR, "fcvt.s.l", 0b00010>,
+                Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]>;
+defm FCVT_S_LU : FPUnaryS_mc<0b1101000, FPR32, GPR, "fcvt.s.lu", 0b00011>,
+                 Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]>;
 } // Predicates = [HasStdExtF, IsRV64]
 
 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtF] in {
 def : InstAlias<"flw $rd, (${rs1})",  (FLW FPR32:$rd,  GPR:$rs1, 0), 0>;

 
 /// Float arithmetic operations
 
 def : Pat<(fadd FPR32:$rs1, FPR32:$rs2), (FADD_S_def $rs1, $rs2)>;
 def : Pat<(fsub FPR32:$rs1, FPR32:$rs2), (FSUB_S_def $rs1, $rs2)>;
 def : Pat<(fmul FPR32:$rs1, FPR32:$rs2), (FMUL_S_def $rs1, $rs2)>;
 def : Pat<(fdiv FPR32:$rs1, FPR32:$rs2), (FDIV_S_def $rs1, $rs2)>;
 
-def : Pat<(fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b111)>;
+def : Pat<(fsqrt FPR32:$rs1), (FSQRT_S_def FPR32:$rs1)>;
 
 def : Pat<(fneg FPR32:$rs1), (FSGNJN_S $rs1, $rs1)>;
 def : Pat<(fabs FPR32:$rs1), (FSGNJX_S $rs1, $rs1)>;
 
 def : PatFpr32Fpr32<fcopysign, FSGNJ_S>;
 def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>;
 
 // fmadd: rs1 * rs2 + rs3

 } // Predicates = [HasStdExtF]
 
 let Predicates = [HasStdExtF, IsRV32] in {
 // Moves (no conversion)
 def : Pat<(bitconvert (i32 GPR:$rs1)), (FMV_W_X GPR:$rs1)>;
 def : Pat<(i32 (bitconvert FPR32:$rs1)), (FMV_X_W FPR32:$rs1)>;
 
 // float->[u]int. Round-to-zero must be used.
-def : Pat<(i32 (fp_to_sint FPR32:$rs1)), (FCVT_W_S $rs1, 0b001)>;
-def : Pat<(i32 (fp_to_uint FPR32:$rs1)), (FCVT_WU_S $rs1, 0b001)>;
+def : Pat<(i32 (fp_to_sint FPR32:$rs1)), (FCVT_W_S_gen $rs1, 0b001)>;
+def : Pat<(i32 (fp_to_uint FPR32:$rs1)), (FCVT_WU_S_gen $rs1, 0b001)>;
 
-// [u]int->float. Match GCC and default to using dynamic rounding mode.
-def : Pat<(sint_to_fp (i32 GPR:$rs1)), (FCVT_S_W $rs1, 0b111)>;
-def : Pat<(uint_to_fp (i32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b111)>;
+// [u]int->float.
+def : Pat<(sint_to_fp (i32 GPR:$rs1)), (FCVT_S_W_def $rs1)>;
+def : Pat<(uint_to_fp (i32 GPR:$rs1)), (FCVT_S_WU_def $rs1)>;
 } // Predicates = [HasStdExtF, IsRV32]
 
 let Predicates = [HasStdExtF, IsRV64] in {
 // Moves (no conversion)
 def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>;
 def : Pat<(riscv_fmv_x_anyextw_rv64 FPR32:$src), (FMV_X_W FPR32:$src)>;
 def : Pat<(sext_inreg (riscv_fmv_x_anyextw_rv64 FPR32:$src), i32),
           (FMV_X_W FPR32:$src)>;
 
 // FP->[u]int32 is mostly handled by the FP->[u]int64 patterns. This is safe
 // because fpto[u|s]i produces poison if the value can't fit into the target.
 // We match the single case below because fcvt.wu.s sign-extends its result so
 // is cheaper than fcvt.lu.s+sext.w.
 def : Pat<(sext_inreg (assertzexti32 (fp_to_uint FPR32:$rs1)), i32),
-          (FCVT_WU_S $rs1, 0b001)>;
+          (FCVT_WU_S_gen $rs1, 0b001)>;
 
 // FP->[u]int64
-def : Pat<(i64 (fp_to_sint FPR32:$rs1)), (FCVT_L_S $rs1, 0b001)>;
-def : Pat<(i64 (fp_to_uint FPR32:$rs1)), (FCVT_LU_S $rs1, 0b001)>;
+def : Pat<(i64 (fp_to_sint FPR32:$rs1)), (FCVT_L_S_gen $rs1, 0b001)>;
+def : Pat<(i64 (fp_to_uint FPR32:$rs1)), (FCVT_LU_S_gen $rs1, 0b001)>;
 
-// [u]int->fp. Match GCC and default to using dynamic rounding mode.
-def : Pat<(sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_S_W $rs1, 0b111)>;
-def : Pat<(uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_S_WU $rs1, 0b111)>;
-def : Pat<(sint_to_fp (i64 GPR:$rs1)), (FCVT_S_L $rs1, 0b111)>;
-def : Pat<(uint_to_fp (i64 GPR:$rs1)), (FCVT_S_LU $rs1, 0b111)>;
+// [u]int->fp.
+def : Pat<(sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_S_W_def $rs1)>;
+def : Pat<(uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_S_WU_def $rs1)>;
+def : Pat<(sint_to_fp (i64 GPR:$rs1)), (FCVT_S_L_def $rs1)>;
+def : Pat<(uint_to_fp (i64 GPR:$rs1)), (FCVT_S_LU_def $rs1)>;
 } // Predicates = [HasStdExtF, IsRV64]

llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

 multiclass FPALUH_mc<bits<7> funct7, string OpcodeStr> {
   def _gen : FPALU_gen<funct7, OpcodeStr, FPR16>;
   def _def : FPALU_def<funct7, OpcodeStr, FPR16>;
   def      : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
                        (!cast<Instruction>(NAME # "_gen")
                         FPR16:$rd, FPR16:$rs1, FPR16:$rs2, 0b111)>;
 }
 
+multiclass FPUnaryH_mc<bits<7> funct7, RegisterClass rdty, RegisterClass rs1ty,
+                       string OpcodeStr, bits<5> rs2val> {
+  def _gen : FPUnaryOp_gen<funct7, rdty, rs1ty, OpcodeStr, rs2val>;
+  def _def : FPUnaryOp_def<funct7, rdty, rs1ty, OpcodeStr, rs2val>;
+  def      : InstAlias<OpcodeStr#" $rd, $rs1",
+                       (!cast<Instruction>(NAME # "_gen")
+                        rdty:$rd, rs1ty:$rs1, 0b111)>;
+}
+
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class FPALUH_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
     : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR16:$rd),
               (ins FPR16:$rs1, FPR16:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class FPCmpH_rr<bits<3> funct3, string opcodestr>
     : RVInstR<0b1010010, funct3, OPC_OP_FP, (outs GPR:$rd),
defm FADD_H : FPALUH_mc<0b0000010, "fadd.h">,
               Sched<[]>;
 defm FSUB_H : FPALUH_mc<0b0000110, "fsub.h">,
               Sched<[]>;
 defm FMUL_H : FPALUH_mc<0b0001010, "fmul.h">,
               Sched<[]>;
 defm FDIV_H : FPALUH_mc<0b0001110, "fdiv.h">,
               Sched<[]>;
 
-def FSQRT_H : FPUnaryOp_r_frm<0b0101110, FPR16, FPR16, "fsqrt.h">,
-              Sched<[]> {
-  let rs2 = 0b00000;
-}
-def         : FPUnaryOpDynFrmAlias<FSQRT_H, "fsqrt.h", FPR16, FPR16>;
+defm FSQRT_H : FPUnaryH_mc<0b0101110, FPR16, FPR16, "fsqrt.h", 0b00000>,
+              Sched<[]>;
 
 def FSGNJ_H  : FPALUH_rr<0b0010010, 0b000, "fsgnj.h">,
                Sched<[]>;
 def FSGNJN_H : FPALUH_rr<0b0010010, 0b001, "fsgnjn.h">,
                Sched<[]>;
 def FSGNJX_H : FPALUH_rr<0b0010010, 0b010, "fsgnjx.h">,
                Sched<[]>;
 
 def FMIN_H   : FPALUH_rr<0b0010110, 0b000, "fmin.h">,
                Sched<[]>;
 def FMAX_H   : FPALUH_rr<0b0010110, 0b001, "fmax.h">,
                Sched<[]>;
 
-def FCVT_W_H : FPUnaryOp_r_frm<0b1100010, GPR, FPR16, "fcvt.w.h">,
-               Sched<[]> {
-  let rs2 = 0b00000;
-}
-def          : FPUnaryOpDynFrmAlias<FCVT_W_H, "fcvt.w.h", GPR, FPR16>;
-
-def FCVT_WU_H : FPUnaryOp_r_frm<0b1100010, GPR, FPR16, "fcvt.wu.h">,
-                Sched<[]> {
-  let rs2 = 0b00001;
-}
-def           : FPUnaryOpDynFrmAlias<FCVT_WU_H, "fcvt.wu.h", GPR, FPR16>;
-
-def FCVT_H_W : FPUnaryOp_r_frm<0b1101010, FPR16, GPR, "fcvt.h.w">,
-               Sched<[]> {
-  let rs2 = 0b00000;
-}
-def          : FPUnaryOpDynFrmAlias<FCVT_H_W, "fcvt.h.w", FPR16, GPR>;
-
-def FCVT_H_WU : FPUnaryOp_r_frm<0b1101010, FPR16, GPR, "fcvt.h.wu">,
-                Sched<[]> {
-  let rs2 = 0b00001;
-}
-def           : FPUnaryOpDynFrmAlias<FCVT_H_WU, "fcvt.h.wu", FPR16, GPR>;
-
-def FCVT_H_S : FPUnaryOp_r_frm<0b0100010, FPR16, FPR32, "fcvt.h.s">,
-               Sched<[]> {
-  let rs2 = 0b00000;
-}
-def          : FPUnaryOpDynFrmAlias<FCVT_H_S, "fcvt.h.s", FPR16, FPR32>;
+defm FCVT_W_H  : FPUnaryH_mc<0b1100010, GPR, FPR16, "fcvt.w.h", 0b00000>,
+                 Sched<[]>;
+defm FCVT_WU_H : FPUnaryH_mc<0b1100010, GPR, FPR16, "fcvt.wu.h", 0b00001>,
+                 Sched<[]>;
+defm FCVT_H_W  : FPUnaryH_mc<0b1101010, FPR16, GPR, "fcvt.h.w", 0b00000>,
+                 Sched<[]>;
+defm FCVT_H_WU : FPUnaryH_mc<0b1101010, FPR16, GPR, "fcvt.h.wu", 0b00001>,
+                 Sched<[]>;
+defm FCVT_H_S  : FPUnaryH_mc<0b0100010, FPR16, FPR32, "fcvt.h.s", 0b00000>,
+                 Sched<[]>;
 
 def FCVT_S_H : FPUnaryOp_r<0b0100000, 0b000, FPR32, FPR16, "fcvt.s.h">,
                Sched<[]> {
   let rs2 = 0b00010;
 }
 
 def FMV_X_H : FPUnaryOp_r<0b1110010, 0b000, GPR, FPR16, "fmv.x.h">,
               Sched<[]> {

 
 def FCLASS_H : FPUnaryOp_r<0b1110010, 0b001, GPR, FPR16, "fclass.h">,
                Sched<[]> {
   let rs2 = 0b00000;
 }
 } // Predicates = [HasStdExtZfh]
 
 let Predicates = [HasStdExtZfh, IsRV64] in {
-def FCVT_L_H  : FPUnaryOp_r_frm<0b1100010, GPR, FPR16, "fcvt.l.h">,
-                Sched<[]> {
-  let rs2 = 0b00010;
-}
-def           : FPUnaryOpDynFrmAlias<FCVT_L_H, "fcvt.l.h", GPR, FPR16>;
-
-def FCVT_LU_H  : FPUnaryOp_r_frm<0b1100010, GPR, FPR16, "fcvt.lu.h">,
-                 Sched<[]> {
-  let rs2 = 0b00011;
-}
-def            : FPUnaryOpDynFrmAlias<FCVT_LU_H, "fcvt.lu.h", GPR, FPR16>;
-
-def FCVT_H_L : FPUnaryOp_r_frm<0b1101010, FPR16, GPR, "fcvt.h.l">,
-               Sched<[]> {
-  let rs2 = 0b00010;
-}
-def          : FPUnaryOpDynFrmAlias<FCVT_H_L, "fcvt.h.l", FPR16, GPR>;
-
-def FCVT_H_LU : FPUnaryOp_r_frm<0b1101010, FPR16, GPR, "fcvt.h.lu">,
-                Sched<[]> {
-  let rs2 = 0b00011;
-}
-def           : FPUnaryOpDynFrmAlias<FCVT_H_LU, "fcvt.h.lu", FPR16, GPR>;
+defm FCVT_L_H  : FPUnaryH_mc<0b1100010, GPR, FPR16, "fcvt.l.h", 0b00010>,
+                 Sched<[]>;
+defm FCVT_LU_H : FPUnaryH_mc<0b1100010, GPR, FPR16, "fcvt.lu.h", 0b00011>,
+                 Sched<[]>;
+defm FCVT_H_L  : FPUnaryH_mc<0b1101010, FPR16, GPR, "fcvt.h.l", 0b00010>,
+                 Sched<[]>;
+defm FCVT_H_LU : FPUnaryH_mc<0b1101010, FPR16, GPR, "fcvt.h.lu", 0b00011>,
+                 Sched<[]>;
 } // Predicates = [HasStdExtZfh, IsRV64]
 
 let Predicates = [HasStdExtZfh, HasStdExtD] in {
-def FCVT_H_D : FPUnaryOp_r_frm<0b0100010, FPR16, FPR64, "fcvt.h.d">,
-               Sched<[]> {
-  let rs2 = 0b00001;
-}
-def          : FPUnaryOpDynFrmAlias<FCVT_H_D, "fcvt.h.d", FPR16, FPR64>;
+defm FCVT_H_D : FPUnaryH_mc<0b0100010, FPR16, FPR64, "fcvt.h.d", 0b00001>,
+                Sched<[]>;
 
 def FCVT_D_H : FPUnaryOp_r<0b0100001, 0b000, FPR64, FPR16, "fcvt.d.h">,
                Sched<[]> {
   let rs2 = 0b00010;
 }
 } // Predicates = [HasStdExtZfh, HasStdExtD]
 
 //===----------------------------------------------------------------------===//

 
 /// Float arithmetic operations
 
 def : Pat<(fadd FPR16:$rs1, FPR16:$rs2), (FADD_H_def $rs1, $rs2)>;
 def : Pat<(fsub FPR16:$rs1, FPR16:$rs2), (FSUB_H_def $rs1, $rs2)>;
 def : Pat<(fmul FPR16:$rs1, FPR16:$rs2), (FMUL_H_def $rs1, $rs2)>;
 def : Pat<(fdiv FPR16:$rs1, FPR16:$rs2), (FDIV_H_def $rs1, $rs2)>;
 
-def : Pat<(fsqrt FPR16:$rs1), (FSQRT_H FPR16:$rs1, 0b111)>;
+def : Pat<(fsqrt FPR16:$rs1), (FSQRT_H_def FPR16:$rs1)>;
 
 def : Pat<(fneg FPR16:$rs1), (FSGNJN_H $rs1, $rs1)>;
 def : Pat<(fabs FPR16:$rs1), (FSGNJX_H $rs1, $rs1)>;
 
 def : PatFpr16Fpr16<fcopysign, FSGNJ_H>;
 def : Pat<(fcopysign FPR16:$rs1, (fneg FPR16:$rs2)), (FSGNJN_H $rs1, $rs2)>;
 def : Pat<(fcopysign FPR16:$rs1, FPR32:$rs2),
-          (FSGNJ_H $rs1, (FCVT_H_S $rs2, 0b111))>;
+          (FSGNJ_H $rs1, (FCVT_H_S_def $rs2))>;
 def : Pat<(fcopysign FPR16:$rs1, FPR64:$rs2),
-          (FSGNJ_H $rs1, (FCVT_H_D $rs2, 0b111))>;
+          (FSGNJ_H $rs1, (FCVT_H_D_def $rs2))>;
 def : Pat<(fcopysign FPR32:$rs1, FPR16:$rs2), (FSGNJ_S $rs1, (FCVT_S_H $rs2))>;
 def : Pat<(fcopysign FPR64:$rs1, FPR16:$rs2), (FSGNJ_D $rs1, (FCVT_D_H $rs2))>;
 
 // fmadd: rs1 * rs2 + rs3
 def : Pat<(fma FPR16:$rs1, FPR16:$rs2, FPR16:$rs3),
           (FMADD_H_def $rs1, $rs2, $rs3)>;
 
 // fmsub: rs1 * rs2 - rs3

 
 /// Stores
 
 defm : StPat<store, FSH, FPR16, f16>;
 
 /// Float conversion operations
 
 // f32 -> f16, f16 -> f32
-def : Pat<(fpround FPR32:$rs1), (FCVT_H_S FPR32:$rs1, 0b111)>;
+def : Pat<(fpround FPR32:$rs1), (FCVT_H_S_def FPR32:$rs1)>;
 def : Pat<(fpextend FPR16:$rs1), (FCVT_S_H FPR16:$rs1)>;
 
 // Moves (no conversion)
 def : Pat<(riscv_fmv_h_x GPR:$src), (FMV_H_X GPR:$src)>;
 def : Pat<(riscv_fmv_x_anyexth FPR16:$src), (FMV_X_H FPR16:$src)>;
 } // Predicates = [HasStdExtZfh]
 
 let Predicates = [HasStdExtZfh, IsRV32] in {
 // float->[u]int. Round-to-zero must be used.
-def : Pat<(i32 (fp_to_sint FPR16:$rs1)), (FCVT_W_H $rs1, 0b001)>;
-def : Pat<(i32 (fp_to_uint FPR16:$rs1)), (FCVT_WU_H $rs1, 0b001)>;
+def : Pat<(i32 (fp_to_sint FPR16:$rs1)), (FCVT_W_H_gen $rs1, 0b001)>;
+def : Pat<(i32 (fp_to_uint FPR16:$rs1)), (FCVT_WU_H_gen $rs1, 0b001)>;
 
 // [u]int->float. Match GCC and default to using dynamic rounding mode.
-def : Pat<(sint_to_fp (i32 GPR:$rs1)), (FCVT_H_W $rs1, 0b111)>;
-def : Pat<(uint_to_fp (i32 GPR:$rs1)), (FCVT_H_WU $rs1, 0b111)>;
+def : Pat<(sint_to_fp (i32 GPR:$rs1)), (FCVT_H_W_def $rs1)>;
+def : Pat<(uint_to_fp (i32 GPR:$rs1)), (FCVT_H_WU_def $rs1)>;
 } // Predicates = [HasStdExtZfh, IsRV32]
 
 let Predicates = [HasStdExtZfh, IsRV64] in {
 // FP->[u]int32 is mostly handled by the FP->[u]int64 patterns. This is safe
 // because fpto[u|s]i produces poison if the value can't fit into the target.
 // We match the single case below because fcvt.wu.s sign-extends its result so
 // is cheaper than fcvt.lu.h+sext.w.
 def : Pat<(sext_inreg (assertzexti32 (fp_to_uint FPR16:$rs1)), i32),
-          (FCVT_WU_H $rs1, 0b001)>;
+          (FCVT_WU_H_gen $rs1, 0b001)>;
 
 // FP->[u]int64
-def : Pat<(i64 (fp_to_sint FPR16:$rs1)), (FCVT_L_H $rs1, 0b001)>;
-def : Pat<(i64 (fp_to_uint FPR16:$rs1)), (FCVT_LU_H $rs1, 0b001)>;
+def : Pat<(i64 (fp_to_sint FPR16:$rs1)), (FCVT_L_H_gen $rs1, 0b001)>;
+def : Pat<(i64 (fp_to_uint FPR16:$rs1)), (FCVT_LU_H_gen $rs1, 0b001)>;
 
-// [u]int->fp. Match GCC and default to using dynamic rounding mode.
-def : Pat<(sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_H_W $rs1, 0b111)>;
-def : Pat<(uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_H_WU $rs1, 0b111)>;
-def : Pat<(sint_to_fp (i64 GPR:$rs1)), (FCVT_H_L $rs1, 0b111)>;
-def : Pat<(uint_to_fp (i64 GPR:$rs1)), (FCVT_H_LU $rs1, 0b111)>;
+// [u]int->fp.
+def : Pat<(sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_H_W_def $rs1)>;
+def : Pat<(uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_H_WU_def $rs1)>;
+def : Pat<(sint_to_fp (i64 GPR:$rs1)), (FCVT_H_L_def $rs1)>;
+def : Pat<(uint_to_fp (i64 GPR:$rs1)), (FCVT_H_LU_def $rs1)>;
 } // Predicates = [HasStdExtZfh, IsRV64]
 
 let Predicates = [HasStdExtZfh, HasStdExtD] in {
 /// Float conversion operations
 // f64 -> f16, f16 -> f64
-def : Pat<(fpround FPR64:$rs1), (FCVT_H_D FPR64:$rs1, 0b111)>;
+def : Pat<(fpround FPR64:$rs1), (FCVT_H_D_def FPR64:$rs1)>;
 def : Pat<(fpextend FPR16:$rs1), (FCVT_D_H FPR16:$rs1)>;
 }

llvm/test/CodeGen/RISCV/double-arith.ll

 
 define double @fsqrt_d(double %a) nounwind {
 ; RV32IFD-LABEL: fsqrt_d:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
-; RV32IFD-NEXT:    fsqrt.d ft0, ft0
+; RV32IFD-NEXT:    fsqrt.d ft0, ft0, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fsqrt_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a0
-; RV64IFD-NEXT:    fsqrt.d ft0, ft0
+; RV64IFD-NEXT:    fsqrt.d ft0, ft0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = call double @llvm.sqrt.f64(double %a)
   ret double %1
 }
 
 declare double @llvm.copysign.f64(double, double)
 

llvm/test/CodeGen/RISCV/double-convert.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IFD %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IFD %s
 
 define float @fcvt_s_d(double %a) nounwind {
 ; RV32IFD-LABEL: fcvt_s_d:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
-; RV32IFD-NEXT:    fcvt.s.d ft0, ft0
+; RV32IFD-NEXT:    fcvt.s.d ft0, ft0, rne
 ; RV32IFD-NEXT:    fmv.x.w a0, ft0
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcvt_s_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a0
-; RV64IFD-NEXT:    fcvt.s.d ft0, ft0
+; RV64IFD-NEXT:    fcvt.s.d ft0, ft0, rne
 ; RV64IFD-NEXT:    fmv.x.w a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = fptrunc double %a to float
   ret float %1
 }
 
 define double @fcvt_d_s(float %a) nounwind {
 ; RV32IFD-LABEL: fcvt_d_s:

 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw a2, 0(sp)
 ; RV32IFD-NEXT:    sw a3, 4(sp)
 ; RV32IFD-NEXT:    fld ft0, 0(sp)
 ; RV32IFD-NEXT:    sw a0, 0(sp)
 ; RV32IFD-NEXT:    sw a1, 4(sp)
 ; RV32IFD-NEXT:    fld ft1, 0(sp)
-; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0
+; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fmv_x_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a1
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
-; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0
+; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = fadd double %a, %b
   %2 = bitcast double %1 to i64
   ret i64 %2
 }
 
 define double @fcvt_d_l(i64 %a) nounwind {
 ; RV32IFD-LABEL: fcvt_d_l:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    call __floatdidf@plt
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcvt_d_l:
 ; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.d.l ft0, a0
+; RV64IFD-NEXT:    fcvt.d.l ft0, a0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = sitofp i64 %a to double
   ret double %1
 }
 
 define double @fcvt_d_lu(i64 %a) nounwind {
 ; RV32IFD-LABEL: fcvt_d_lu:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    call __floatundidf@plt
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcvt_d_lu:
 ; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.d.lu ft0, a0
+; RV64IFD-NEXT:    fcvt.d.lu ft0, a0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = uitofp i64 %a to double
   ret double %1
 }
 
 define double @fmv_d_x(i64 %a, i64 %b) nounwind {
 ; Ensure fmv.w.x is generated even for a soft double calling convention
 ; RV32IFD-LABEL: fmv_d_x:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -32
 ; RV32IFD-NEXT:    sw a3, 20(sp)
 ; RV32IFD-NEXT:    sw a2, 16(sp)
 ; RV32IFD-NEXT:    sw a1, 28(sp)
 ; RV32IFD-NEXT:    sw a0, 24(sp)
 ; RV32IFD-NEXT:    fld ft0, 16(sp)
 ; RV32IFD-NEXT:    fld ft1, 24(sp)
-; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0
+; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 32
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fmv_d_x:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a0
 ; RV64IFD-NEXT:    fmv.d.x ft1, a1
-; RV64IFD-NEXT:    fadd.d ft0, ft0, ft1
+; RV64IFD-NEXT:    fadd.d ft0, ft0, ft1, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = bitcast i64 %a to double
   %2 = bitcast i64 %b to double
   %3 = fadd double %1, %2
   ret double %3
 }
 

llvm/test/CodeGen/RISCV/float-arith.ll

 }
 
 declare float @llvm.sqrt.f32(float)
 
 define float @fsqrt_s(float %a) nounwind {
 ; RV32IF-LABEL: fsqrt_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a0
-; RV32IF-NEXT:    fsqrt.s ft0, ft0
+; RV32IF-NEXT:    fsqrt.s ft0, ft0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fsqrt_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a0
-; RV64IF-NEXT:    fsqrt.s ft0, ft0
+; RV64IF-NEXT:    fsqrt.s ft0, ft0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %1 = call float @llvm.sqrt.f32(float %a)
   ret float %1
 }
 
 declare float @llvm.copysign.f32(float, float)
 

llvm/test/CodeGen/RISCV/float-convert.ll

; RV64IF-NEXT:    ret
   ret i32 %1
 }
 
 define i32 @fmv_x_w(float %a, float %b) nounwind {
 ; RV32IF-LABEL: fmv_x_w:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
-; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
+; RV32IF-NEXT:    fadd.s ft0, ft1, ft0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fmv_x_w:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
-; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
+; RV64IF-NEXT:    fadd.s ft0, ft1, ft0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
 ; Ensure fmv.x.w is generated even for a soft float calling convention
   %1 = fadd float %a, %b
   %2 = bitcast float %1 to i32
   ret i32 %2
 }
 
 define float @fcvt_s_w(i32 %a) nounwind {
 ; RV32IF-LABEL: fcvt_s_w:
 ; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.w ft0, a0
+; RV32IF-NEXT:    fcvt.s.w ft0, a0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_s_w:
 ; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.w ft0, a0
+; RV64IF-NEXT:    fcvt.s.w ft0, a0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %1 = sitofp i32 %a to float
   ret float %1
 }
 
 define float @fcvt_s_wu(i32 %a) nounwind {
 ; RV32IF-LABEL: fcvt_s_wu:
 ; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.wu ft0, a0
+; RV32IF-NEXT:    fcvt.s.wu ft0, a0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_s_wu:
 ; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.wu ft0, a0
+; RV64IF-NEXT:    fcvt.s.wu ft0, a0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %1 = uitofp i32 %a to float
   ret float %1
 }
 
 define float @fmv_w_x(i32 %a, i32 %b) nounwind {
 ; RV32IF-LABEL: fmv_w_x:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a0
 ; RV32IF-NEXT:    fmv.w.x ft1, a1
-; RV32IF-NEXT:    fadd.s ft0, ft0, ft1
+; RV32IF-NEXT:    fadd.s ft0, ft0, ft1, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fmv_w_x:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a0
 ; RV64IF-NEXT:    fmv.w.x ft1, a1
-; RV64IF-NEXT:    fadd.s ft0, ft0, ft1
+; RV64IF-NEXT:    fadd.s ft0, ft0, ft1, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
 ; Ensure fmv.w.x is generated even for a soft float calling convention
   %1 = bitcast i32 %a to float
   %2 = bitcast i32 %b to float
   %3 = fadd float %1, %2
   ret float %3
 }

 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call __floatdisf@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_s_l:
 ; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.l ft0, a0
+; RV64IF-NEXT:    fcvt.s.l ft0, a0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %1 = sitofp i64 %a to float
   ret float %1
 }
 
 define float @fcvt_s_lu(i64 %a) nounwind {
 ; RV32IF-LABEL: fcvt_s_lu:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call __floatundisf@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_s_lu:
 ; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.lu ft0, a0
+; RV64IF-NEXT:    fcvt.s.lu ft0, a0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %1 = uitofp i64 %a to float
   ret float %1
 }
 
 define float @fcvt_s_w_i8(i8 signext %a) nounwind {
 ; RV32IF-LABEL: fcvt_s_w_i8:

llvm/test/CodeGen/RISCV/half-arith.ll

; RV64IZFH-NEXT:    ret
   ret half %1
 }
 
 declare half @llvm.sqrt.f16(half)
 
 define half @fsqrt_s(half %a) nounwind {
 ; RV32IZFH-LABEL: fsqrt_s:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fsqrt.h fa0, fa0
+; RV32IZFH-NEXT:    fsqrt.h fa0, fa0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fsqrt_s:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fsqrt.h fa0, fa0
+; RV64IZFH-NEXT:    fsqrt.h fa0, fa0, rne
 ; RV64IZFH-NEXT:    ret
   %1 = call half @llvm.sqrt.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.copysign.f16(half, half)
 
 define half @fsgnj_s(half %a, half %b) nounwind {

llvm/test/CodeGen/RISCV/half-convert.ll

; RV64IDZFH-NEXT:    ret
   ret i64 %1
 }
 
 define half @fcvt_h_si(i16 %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_si:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    slli a0, a0, 16
 ; RV32IZFH-NEXT:    srai a0, a0, 16
-; RV32IZFH-NEXT:    fcvt.h.w fa0, a0
+; RV32IZFH-NEXT:    fcvt.h.w fa0, a0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_si:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    slli a0, a0, 16
 ; RV32IDZFH-NEXT:    srai a0, a0, 16
-; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
+; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0, rne
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_h_si:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    slli a0, a0, 48
 ; RV64IZFH-NEXT:    srai a0, a0, 48
-; RV64IZFH-NEXT:    fcvt.h.l fa0, a0
+; RV64IZFH-NEXT:    fcvt.h.l fa0, a0, rne
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_si:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    slli a0, a0, 48
 ; RV64IDZFH-NEXT:    srai a0, a0, 48
-; RV64IDZFH-NEXT:    fcvt.h.l fa0, a0
+; RV64IDZFH-NEXT:    fcvt.h.l fa0, a0, rne
 ; RV64IDZFH-NEXT:    ret
   %1 = sitofp i16 %a to half
   ret half %1
 }
 
 define half @fcvt_h_si_signext(i16 signext %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_si_signext:
 ; RV32IZFH:       # %bb.0:

 }
 
 define half @fcvt_h_ui(i16 %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_ui:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    lui a1, 16
 ; RV32IZFH-NEXT:    addi a1, a1, -1
 ; RV32IZFH-NEXT:    and a0, a0, a1
-; RV32IZFH-NEXT:    fcvt.h.wu fa0, a0
+; RV32IZFH-NEXT:    fcvt.h.wu fa0, a0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_ui:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    lui a1, 16
 ; RV32IDZFH-NEXT:    addi a1, a1, -1
 ; RV32IDZFH-NEXT:    and a0, a0, a1
-; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
+; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0, rne
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_h_ui:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    lui a1, 16
 ; RV64IZFH-NEXT:    addiw a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a0, a1
-; RV64IZFH-NEXT:    fcvt.h.lu fa0, a0
+; RV64IZFH-NEXT:    fcvt.h.lu fa0, a0, rne
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_ui:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    lui a1, 16
 ; RV64IDZFH-NEXT:    addiw a1, a1, -1
 ; RV64IDZFH-NEXT:    and a0, a0, a1
-; RV64IDZFH-NEXT:    fcvt.h.lu fa0, a0
+; RV64IDZFH-NEXT:    fcvt.h.lu fa0, a0, rne
 ; RV64IDZFH-NEXT:    ret
   %1 = uitofp i16 %a to half
   ret half %1
 }
 
 define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_ui_zeroext:
 ; RV32IZFH:       # %bb.0:

 ; RV64IDZFH-NEXT:    ret
   %1 = uitofp i16 %a to half
   ret half %1
 }
 
 define half @fcvt_h_w(i32 %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_w:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.h.w fa0, a0
+; RV32IZFH-NEXT:    fcvt.h.w fa0, a0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_w:
 ; RV32IDZFH:       # %bb.0:
-; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
+; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0, rne
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_h_w:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.h.w fa0, a0
+; RV64IZFH-NEXT:    fcvt.h.w fa0, a0, rne
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_w:
 ; RV64IDZFH:       # %bb.0:
-; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
+; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0, rne
 ; RV64IDZFH-NEXT:    ret
   %1 = sitofp i32 %a to half
   ret half %1
 }
 
 define half @fcvt_h_wu(i32 %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_wu:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.h.wu fa0, a0
+; RV32IZFH-NEXT:    fcvt.h.wu fa0, a0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_wu:
 ; RV32IDZFH:       # %bb.0:
-; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
+; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0, rne
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_h_wu:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.h.wu fa0, a0
+; RV64IZFH-NEXT:    fcvt.h.wu fa0, a0, rne
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_wu:
 ; RV64IDZFH:       # %bb.0:
-; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0
+; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0, rne
 ; RV64IDZFH-NEXT:    ret
   %1 = uitofp i32 %a to half
   ret half %1
 }
 
 define half @fcvt_h_l(i64 %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_l:
 ; RV32IZFH:       # %bb.0:

 ; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    call __floatdihf@plt
 ; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    addi sp, sp, 16
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_h_l:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.h.l fa0, a0
+; RV64IZFH-NEXT:    fcvt.h.l fa0, a0, rne
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_l:
 ; RV64IDZFH:       # %bb.0:
-; RV64IDZFH-NEXT:    fcvt.h.l fa0, a0
+; RV64IDZFH-NEXT:    fcvt.h.l fa0, a0, rne
 ; RV64IDZFH-NEXT:    ret
   %1 = sitofp i64 %a to half
   ret half %1
 }
 
 define half @fcvt_h_lu(i64 %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_lu:
 ; RV32IZFH:       # %bb.0:

 ; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    call __floatundihf@plt
 ; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    addi sp, sp, 16
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_h_lu:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.h.lu fa0, a0
+; RV64IZFH-NEXT:    fcvt.h.lu fa0, a0, rne
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_lu:
 ; RV64IDZFH:       # %bb.0:
-; RV64IDZFH-NEXT:    fcvt.h.lu fa0, a0
+; RV64IDZFH-NEXT:    fcvt.h.lu fa0, a0, rne
 ; RV64IDZFH-NEXT:    ret
   %1 = uitofp i64 %a to half
   ret half %1
 }
 
 define half @fcvt_h_s(float %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_s:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.h.s fa0, fa0
+; RV32IZFH-NEXT:    fcvt.h.s fa0, fa0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_s:
 ; RV32IDZFH:       # %bb.0:
-; RV32IDZFH-NEXT:    fcvt.h.s fa0, fa0
+; RV32IDZFH-NEXT:    fcvt.h.s fa0, fa0, rne
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_h_s:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
+; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0, rne
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_s:
 ; RV64IDZFH:       # %bb.0:
-; RV64IDZFH-NEXT:    fcvt.h.s fa0, fa0
+; RV64IDZFH-NEXT:    fcvt.h.s fa0, fa0, rne
 ; RV64IDZFH-NEXT:    ret
   %1 = fptrunc float %a to half
   ret half %1
 }
 
 define float @fcvt_s_h(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_s_h:
 ; RV32IZFH:       # %bb.0:

 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    call __truncdfhf2@plt
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_d:
 ; RV32IDZFH:       # %bb.0:
-; RV32IDZFH-NEXT:    fcvt.h.d fa0, fa0
+; RV32IDZFH-NEXT:    fcvt.h.d fa0, fa0, rne
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_h_d:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call __truncdfhf2@plt
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_d:
 ; RV64IDZFH:       # %bb.0:
-; RV64IDZFH-NEXT:    fcvt.h.d fa0, fa0
+; RV64IDZFH-NEXT:    fcvt.h.d fa0, fa0, rne
 ; RV64IDZFH-NEXT:    ret
   %1 = fptrunc double %a to half
   ret half %1
 }
 
 define double @fcvt_d_h(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_d_h:
 ; RV32IZFH:       # %bb.0: