[RISCV] Introduce floating point control and state registers

[sepavloff]

Summary

New registers FRM, FFLAGS and FCSR was defined. They represent
corresponding system registers. The new registers are necessary to
properly order floating point instructions in non-default modes.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1192

Should we use the names of the mnemonics that are defined for these operations? Though I guess there's no name defined for "write" just for swap and read.

[sepavloff]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1192

Did you mean frrm and fsrm? Name like Read* are more readable. Besides it seems there are no advantages of having codegen pseudos named identically to corresponding instruction aliases. And you are right, Write* and Swap* correspond to the same mnemonic.

[sepavloff]

Rebased ad added variants with immediate

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1201

Do we have use cases for all of these?

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

543

Is there any significance the 1, 2, and 3 chosen for the first operand here?

[sepavloff]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1201

ReadFRM is used in the implementation of FLT_ROUNDS_ (D90854).
WriteFRM and WrireFRMImm are used in the implementation of set_rounding (D91242).
SwapFRM and SwapFRMImm are not used in any of pending patches but they are useful to implement target-specific optimization of the code pattern:

int old_rm = fegetround();
fesetround(new_rm);
...
fesetround(old_rm);

which is likely to be used in the implementation of #pragma STDC FENV_ROUND.

Operations with FFLAGS are not used now. They would be needed to implement functions like fetestexcept and similar, but now there are no such attempts AFAIK.

Operations would be needed for target specific implementation of intrinsics that access FP control modes (D82525) and FP environment (D71742).

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

543

The first operand of RISCVReg is HWEncoding, 1, 2 and 3 represent hardware addresses of the respective system registers which are specified in the RISCV specification (https://github.com/riscv/riscv-isa-manual/releases/download/draft-20210402-1271737/riscv-spec.pdf), chapter 25 (RV32/64G Instruction Set Listings), table 25.3 (RISC-V control and status register (CSR) address map).

On the other hand, these special registers are not used as operands in any of non-pseudo instruction, so these definitions are not used in instruction emitter. It means that particular values are not important, at least now.

[sepavloff]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1201

Operations would be needed for target specific implementation of intrinsics that access FP control modes (D82525) and FP environment (D71742).

It is about the operation on FCSR.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1201

I don't think we want unused pseudos that might be used someday. We should include them when they're needed.

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

543

I think these should probably just be 0 like the flags registers on other targets. It's only a 5 bit field and the CSR addresses are 12 bits so its purely a coincidence that these CSRs happen to be representable in 5 bits.

[sepavloff]

Use zero for encoding of FFLAGS, FRM and FCSR. Rebased.

[sepavloff]

Does this patch require other changes?

[craig.topper]

In D99083#2697967, @sepavloff wrote:

Does this patch require other changes?

I don't think we should have unused pseudo instructions since they should all have lit tests. So if they can't be tested soon, they should be added when they are needed.

[sepavloff]

Rebased patch

[sepavloff]

In D99083#2699994, @craig.topper wrote:

I don't think we should have unused pseudo instructions since they should all have lit tests. So if they can't be tested soon, they should be added when they are needed.

Patches that implement FLT_ROUNDS_ (D90854) and SET_ROUNDING (D91242) use these instructions and they have tests. It it enough?

[craig.topper]

In D99083#2700786, @sepavloff wrote:

In D99083#2699994, @craig.topper wrote:

I don't think we should have unused pseudo instructions since they should all have lit tests. So if they can't be tested soon, they should be added when they are needed.

Patches that implement FLT_ROUNDS_ (D90854) and SET_ROUNDING (D91242) use these instructions and they have tests. It it enough?

You said that there no patches ready that use the Swap pseudos or the fflags pseudos. Are those patches going to be created soon or should we remove the pseudos until they are used?

[sepavloff]

Remove pseudos that are not used in pending patches

[sepavloff]

In D99083#2701773, @craig.topper wrote:

In D99083#2700786, @sepavloff wrote:

In D99083#2699994, @craig.topper wrote:

I don't think we should have unused pseudo instructions since they should all have lit tests. So if they can't be tested soon, they should be added when they are needed.

Patches that implement FLT_ROUNDS_ (D90854) and SET_ROUNDING (D91242) use these instructions and they have tests. It it enough?

You said that there no patches ready that use the Swap pseudos or the fflags pseudos. Are those patches going to be created soon or should we remove the pseudos until they are used?

Removed those pseudos.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfo.td

class SwapSysReg<SysReg SR, list<Register> Regs>
   : Pseudo<(outs GPR:$rd), (ins GPR:$val),
            [(set GPR:$rd, (riscv_swap_csr (XLenVT SR.Encoding), GPR:$val))]>,
     PseudoInstExpansion<(CSRRW GPR:$rd, SR.Encoding, GPR:$val)> {
   let hasSideEffects = 0;
   let Uses = Regs;
   let Defs = Regs;
 }
 
 class SwapSysRegImm<SysReg SR, list<Register> Regs>
   : Pseudo<(outs GPR:$rd), (ins uimm5:$val),
            [(set GPR:$rd, (riscv_swap_csr (XLenVT SR.Encoding), uimm5:$val))]>,
     PseudoInstExpansion<(CSRRWI GPR:$rd, SR.Encoding, uimm5:$val)> {
   let hasSideEffects = 0;
   let Uses = Regs;
   let Defs = Regs;
 }
 
+def ReadFRM : ReadSysReg<SysRegFRM, [FRM]>;
+def WriteFRM : WriteSysReg<SysRegFRM, [FRM]>;
+def WriteFRMImm : WriteSysRegImm<SysRegFRM, [FRM]>;
+
 /// Other pseudo-instructions
 
 // Pessimistically assume the stack pointer will be clobbered
 let Defs = [X2], Uses = [X2] in {
 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
                               [(callseq_start timm:$amt1, timm:$amt2)]>;
 def ADJCALLSTACKUP   : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
                               [(callseq_end timm:$amt1, timm:$amt2)]>;

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

 def : InstAlias<"fgt.s $rd, $rs, $rt",
                 (FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
 def : InstAlias<"fge.s $rd, $rs, $rt",
                 (FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
 
 // The following csr instructions actually alias instructions from the base ISA.
 // However, it only makes sense to support them when the F extension is enabled.
 // NOTE: "frcsr", "frrm", and "frflags" are more specialized version of "csrr".
-def : InstAlias<"frcsr $rd",      (CSRRS GPR:$rd, FCSR.Encoding, X0), 2>;
-def : InstAlias<"fscsr $rd, $rs", (CSRRW GPR:$rd, FCSR.Encoding, GPR:$rs)>;
-def : InstAlias<"fscsr $rs",      (CSRRW      X0, FCSR.Encoding, GPR:$rs), 2>;
+def : InstAlias<"frcsr $rd",      (CSRRS GPR:$rd, SysRegFCSR.Encoding, X0), 2>;
+def : InstAlias<"fscsr $rd, $rs", (CSRRW GPR:$rd, SysRegFCSR.Encoding, GPR:$rs)>;
+def : InstAlias<"fscsr $rs",      (CSRRW      X0, SysRegFCSR.Encoding, GPR:$rs), 2>;
 
 // frsr, fssr are obsolete aliases replaced by frcsr, fscsr, so give them
 // zero weight.
-def : InstAlias<"frsr $rd",       (CSRRS GPR:$rd, FCSR.Encoding, X0), 0>;
-def : InstAlias<"fssr $rd, $rs",  (CSRRW GPR:$rd, FCSR.Encoding, GPR:$rs), 0>;
-def : InstAlias<"fssr $rs",       (CSRRW      X0, FCSR.Encoding, GPR:$rs), 0>;
-
-def : InstAlias<"frrm $rd",        (CSRRS  GPR:$rd, FRM.Encoding, X0), 2>;
-def : InstAlias<"fsrm $rd, $rs",   (CSRRW  GPR:$rd, FRM.Encoding, GPR:$rs)>;
-def : InstAlias<"fsrm $rs",        (CSRRW       X0, FRM.Encoding, GPR:$rs), 2>;
-def : InstAlias<"fsrmi $rd, $imm", (CSRRWI GPR:$rd, FRM.Encoding, uimm5:$imm)>;
-def : InstAlias<"fsrmi $imm",      (CSRRWI      X0, FRM.Encoding, uimm5:$imm), 2>;
-
-def : InstAlias<"frflags $rd",        (CSRRS  GPR:$rd, FFLAGS.Encoding, X0), 2>;
-def : InstAlias<"fsflags $rd, $rs",   (CSRRW  GPR:$rd, FFLAGS.Encoding, GPR:$rs)>;
-def : InstAlias<"fsflags $rs",        (CSRRW       X0, FFLAGS.Encoding, GPR:$rs), 2>;
-def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, FFLAGS.Encoding, uimm5:$imm)>;
-def : InstAlias<"fsflagsi $imm",      (CSRRWI      X0, FFLAGS.Encoding, uimm5:$imm), 2>;
+def : InstAlias<"frsr $rd",       (CSRRS GPR:$rd, SysRegFCSR.Encoding, X0), 0>;
+def : InstAlias<"fssr $rd, $rs",  (CSRRW GPR:$rd, SysRegFCSR.Encoding, GPR:$rs), 0>;
+def : InstAlias<"fssr $rs",       (CSRRW      X0, SysRegFCSR.Encoding, GPR:$rs), 0>;
+
+def : InstAlias<"frrm $rd",        (CSRRS  GPR:$rd, SysRegFRM.Encoding, X0), 2>;
+def : InstAlias<"fsrm $rd, $rs",   (CSRRW  GPR:$rd, SysRegFRM.Encoding, GPR:$rs)>;
+def : InstAlias<"fsrm $rs",        (CSRRW       X0, SysRegFRM.Encoding, GPR:$rs), 2>;
+def : InstAlias<"fsrmi $rd, $imm", (CSRRWI GPR:$rd, SysRegFRM.Encoding, uimm5:$imm)>;
+def : InstAlias<"fsrmi $imm",      (CSRRWI      X0, SysRegFRM.Encoding, uimm5:$imm), 2>;
+
+def : InstAlias<"frflags $rd",        (CSRRS  GPR:$rd, SysRegFFLAGS.Encoding, X0), 2>;
+def : InstAlias<"fsflags $rd, $rs",   (CSRRW  GPR:$rd, SysRegFFLAGS.Encoding, GPR:$rs)>;
+def : InstAlias<"fsflags $rs",        (CSRRW       X0, SysRegFFLAGS.Encoding, GPR:$rs), 2>;
+def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, SysRegFFLAGS.Encoding, uimm5:$imm)>;
+def : InstAlias<"fsflagsi $imm",      (CSRRWI      X0, SysRegFFLAGS.Encoding, uimm5:$imm), 2>;
 
 // fmv.w.x and fmv.x.w were previously known as fmv.s.x and fmv.x.s. Both
 // spellings should be supported by standard tools.
 def : MnemonicAlias<"fmv.s.x", "fmv.w.x">;
 def : MnemonicAlias<"fmv.x.s", "fmv.x.w">;
 
 def PseudoFLW  : PseudoFloatLoad<"flw", FPR32>;
 def PseudoFSW  : PseudoStore<"fsw", FPR32>;

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

if (TFI->hasBP(MF))
     markSuperRegs(Reserved, RISCVABI::getBPReg()); // bp
 
   // V registers for code generation. We handle them manually.
   markSuperRegs(Reserved, RISCV::VL);
   markSuperRegs(Reserved, RISCV::VTYPE);
   markSuperRegs(Reserved, RISCV::VXSAT);
   markSuperRegs(Reserved, RISCV::VXRM);
 
+  // Floating point environment registers.
+  markSuperRegs(Reserved, RISCV::FRM);
+  markSuperRegs(Reserved, RISCV::FFLAGS);
+  markSuperRegs(Reserved, RISCV::FCSR);
+
   assert(checkAllSuperRegsMarked(Reserved));
   return Reserved;
 }
 
 bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
                                          MCRegister PhysReg) const {
   return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
 }

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

foreach nf = NFList<m>.L in {
     def "VRN" # nf # "M" # m: VReg<[untyped],
                                (add !cast<RegisterTuples>("VN" # nf # "M" # m # "V0"), !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")),
                                     !mul(nf, m)>;
     def "VRN" # nf # "M" # m # "NoV0": VReg<[untyped],
                                (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")),
                                     !mul(nf, m)>;
   }
 }
+
+// Special registers
+def FFLAGS : RISCVReg<0, "fflags">;
+def FRM    : RISCVReg<0, "frm">;
+def FCSR   : RISCVReg<0, "fcsr">;

llvm/lib/Target/RISCV/RISCVSystemOperands.td

 def : SysReg<"ucause", 0x042>;
 def : SysReg<"utval", 0x043>;
 def : SysReg<"uip", 0x044>;
 
 //===--------------------------
 // User Floating-Point CSRs
 //===--------------------------
 
-def FFLAGS : SysReg<"fflags", 0x001>;
-def FRM    : SysReg<"frm", 0x002>;
-def FCSR   : SysReg<"fcsr", 0x003>;
+def SysRegFFLAGS : SysReg<"fflags", 0x001>;
+def SysRegFRM    : SysReg<"frm", 0x002>;
+def SysRegFCSR   : SysReg<"fcsr", 0x003>;
 
 //===--------------------------
 // User Counter/Timers
 //===--------------------------
 def CYCLE   : SysReg<"cycle", 0xC00>;
 def TIME    : SysReg<"time", 0xC01>;
 def INSTRET : SysReg<"instret", 0xC02>;