[RISCV] Custom lowering of FLT_ROUNDS_

[sepavloff]

Small changes similar to those made in D91242

[jrtc27]

llvm/lib/Target/RISCV/RISCVISelLowering.h

267–271

[sepavloff]

Fixed comments

• IEEE-754 rounding direction names are replaced by llvm::RoundingMode enumerators,
• Fixed comment for RDN.

[sepavloff]

Adapted the patch for alternative CSR implementation

[sepavloff]

Rebased patch

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

377

You can use XLenVT instead of picking i64/i32.

4113

Rename IntTy to XLenVT to match what most of the RISCV back does.

4117

Use RISCVSysReg::lookupSysRegByName("FRM")->Encoding it's not common enough to justify having the encoding in 2 places.

4620

Is this code reachable? This would require setOperaction(ISD::FLT_ROUNDS_, MVT::i32, Custom) when Subtarget.is64Bit() is false.

It's also the default behavior for the target independent type legalizer.

llvm/lib/Target/RISCV/RISCVISelLowering.h

266

Can you use RISCVFPRndMode from lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

[craig.topper]

llvm/test/CodeGen/RISCV/fpenv.ll

1

Use update_llc_test_checks.py

[sepavloff]

Addressed reviewer's notes

[sepavloff]

Added missed change

[sepavloff]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4620

Removed this check.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

15

This is already included in RISCV.h because it's very common file to need.

[sepavloff]

Remove superfluous include

[craig.topper]

LGTM.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4622

I missed it before, but you can use Res.getValue(0) and Res.getValue(1) to shorten these lines if you want.

[sepavloff]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4622

Thank you for advice! I will incorporate these changes too.

llvm/lib/Target/RISCV/RISCVISelLowering.h

enum NodeType : unsigned {
   VSE_VL,
 
   // WARNING: Do not add anything in the end unless you want the node to
   // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
   // opcodes will be thought as target memory ops!
 };
 } // namespace RISCVISD
 
+namespace RISCV {
+// Must agree with definitions in RISCVSystemOperands.td
+enum class SysReg {
+  // User Floating-Point CSRs
+  FFLAGS = 0x001,
+  FRM = 0x002,
+  FCSR = 0x003
+};
+
+enum Rounding {
+  RNE = 0, ///< roundTiesToEven.
+  RTZ = 1, ///< roundTowardZero.
+  RDN = 2, ///< roundTowardPositive.
+  RUP = 3, ///< roundTowardPositive.
+  RMM = 4, ///< roundTiesToAway.
+  MaxRounding = RMM,
+  DYN = 7
+};
+} // namespace RISCV
+
 class RISCVTargetLowering : public TargetLowering {
   const RISCVSubtarget &Subtarget;
 
 public:
   explicit RISCVTargetLowering(const TargetMachine &TM,
                                const RISCVSubtarget &STI);
 
   const RISCVSubtarget &getSubtarget() const { return Subtarget; }
SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG,
                                              unsigned MaskOpc,
                                              unsigned VecOpc) const;
   SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
                                             SelectionDAG &DAG) const;
   SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc,
                             bool HasMask = true) const;
   SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG,
                                             unsigned ExtendOpc) const;
+  SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
 
   bool isEligibleForTailCallOptimization(
       CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
       const SmallVector<CCValAssign, 16> &ArgLocs) const;
 
   /// Generate error diagnostics if any register used by CC has been marked
   /// reserved.
   void validateCCReservedRegs(

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the interfaces that RISCV uses to lower LLVM code into a
 // selection DAG.
 //
 //===----------------------------------------------------------------------===//
 
 #include "RISCVISelLowering.h"
 #include "MCTargetDesc/RISCVMatInt.h"
 #include "RISCV.h"
 #include "RISCVMachineFunctionInfo.h"
 #include "RISCVRegisterInfo.h"
 #include "RISCVSubtarget.h"
 #include "RISCVTargetMachine.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/CallingConvLower.h"
RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
   if (Subtarget.is64Bit()) {
     setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
     setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
     setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
     setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
   }
 
+  if (Subtarget.hasStdExtF()) {
+    setOperationAction(ISD::FLT_ROUNDS_,
+                       (Subtarget.is64Bit() ? MVT::i64 : MVT::i32), Custom);
+  }
+
   setOperationAction(ISD::GlobalAddress, XLenVT, Custom);
   setOperationAction(ISD::BlockAddress, XLenVT, Custom);
   setOperationAction(ISD::ConstantPool, XLenVT, Custom);
   setOperationAction(ISD::JumpTable, XLenVT, Custom);
 
   setOperationAction(ISD::GlobalTLSAddress, XLenVT, Custom);
 
   // TODO: On M-mode only targets, the cycle[h] CSR may not be present.
SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   case ISD::VSELECT:
     return lowerFixedLengthVectorSelectToRVV(Op, DAG);
   case ISD::FCOPYSIGN:
     return lowerFixedLengthVectorFCOPYSIGNToRVV(Op, DAG);
   case ISD::MGATHER:
     return lowerMGATHER(Op, DAG);
   case ISD::MSCATTER:
     return lowerMSCATTER(Op, DAG);
+  case ISD::FLT_ROUNDS_:
+    return lowerGET_ROUNDING(Op, DAG);
   }
 }
 
 static SDValue getTargetNode(GlobalAddressSDNode *N, SDLoc DL, EVT Ty,
                              SelectionDAG &DAG, unsigned Flags) {
   return DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, 0, Flags);
 }
 
SDValue RISCVTargetLowering::lowerMSCATTER(SDValue Op,
   if (!IsUnmasked)
     Ops.push_back(Mask);
   Ops.push_back(VL);
 
   return DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID, DL, MSN->getVTList(), Ops,
                                  MSN->getMemoryVT(), MSN->getMemOperand());
 }
 
+SDValue RISCVTargetLowering::lowerGET_ROUNDING(SDValue Op,
+                                               SelectionDAG &DAG) const {
+  const MVT IntTy = Subtarget.getXLenVT();
+  SDLoc DL(Op);
+  SDValue Chain = Op->getOperand(0);
+  SDValue SysRegNo =
+      DAG.getConstant(static_cast<int>(RISCV::SysReg::FRM), DL, IntTy);
+  SDVTList VTs = DAG.getVTList(IntTy, MVT::Other);
+  SDValue RM = DAG.getNode(RISCVISD::READ_CSR, DL, VTs, Chain, SysRegNo);
+
+  // Encoding used for rounding mode in RISCV differs from that used in
+  // FLT_ROUNDS. To convert it the RISCV rounding mode is used as an index in a
+  // table, which consists of a sequence of 4-bit fields, each representing
+  // corresponding FLT_ROUNDS mode.
+  static const int Table =
+      (int(RoundingMode::NearestTiesToEven) << 4 * RISCV::Rounding::RNE) |
+      (int(RoundingMode::TowardZero) << 4 * RISCV::Rounding::RTZ) |
+      (int(RoundingMode::TowardNegative) << 4 * RISCV::Rounding::RDN) |
+      (int(RoundingMode::TowardPositive) << 4 * RISCV::Rounding::RUP) |
+      (int(RoundingMode::NearestTiesToAway) << 4 * RISCV::Rounding::RMM);
+
+  SDValue Shift =
+      DAG.getNode(ISD::SHL, DL, IntTy, RM, DAG.getConstant(2, DL, IntTy));
+  SDValue Shifted = DAG.getNode(ISD::SRL, DL, IntTy,
+                                DAG.getConstant(Table, DL, IntTy), Shift);
+  SDValue Masked =
+      DAG.getNode(ISD::AND, DL, IntTy, Shifted, DAG.getConstant(7, DL, IntTy));
+
+  return DAG.getMergeValues({Masked, Chain}, DL);
+}
+
 // Returns the opcode of the target-specific SDNode that implements the 32-bit
 // form of the given Opcode.
 static RISCVISD::NodeType getRISCVWOpcode(unsigned Opcode) {
   switch (Opcode) {
   default:
     llvm_unreachable("Unexpected opcode");
   case ISD::SHL:
     return RISCVISD::SLLW;
void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
   case ISD::VECREDUCE_XOR:
   case ISD::VECREDUCE_SMAX:
   case ISD::VECREDUCE_UMAX:
   case ISD::VECREDUCE_SMIN:
   case ISD::VECREDUCE_UMIN:
     if (SDValue V = lowerVECREDUCE(SDValue(N, 0), DAG))
       Results.push_back(V);
     break;
+  case ISD::FLT_ROUNDS_: {
+    assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
+           Subtarget.hasStdExtF() && "Unexpected custom legalization");
+    SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other);
+    SDValue Res = DAG.getNode(ISD::FLT_ROUNDS_, DL, VTs, N->getOperand(0));
+    Results.push_back(SDValue(Res.getNode(), 0));
+    Results.push_back(SDValue(Res.getNode(), 1));
+    break;
+  }
   }
 }
 
 // A structure to hold one of the bit-manipulation patterns below. Together, a
 // SHL and non-SHL pattern may form a bit-manipulation pair on a single source:
 //   (or (and (shl x, 1), 0xAAAAAAAA),
 //       (and (srl x, 1), 0x55555555))
 struct RISCVBitmanipPat {

llvm/test/CodeGen/RISCV/fpenv.ll

+; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s | FileCheck -check-prefix=RV32IF %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s | FileCheck -check-prefix=RV64IF %s
+
+define i32 @func_01() {
+  %rm = call i32 @llvm.flt.rounds()
+  ret i32 %rm
+}
+
+; RV32IF-LABEL: func_01:
+; RV32IF:       frrm  a0
+; RV32IF:       slli  a0, a0, 2
+; RV32IF:       lui   a1, 66
+; RV32IF:       addi  a1, a1, 769
+; RV32IF:       srl   a0, a1, a0
+; RV32IF:       andi  a0, a0, 7
+; RV32IF:       ret
+
+; RV64IF-LABEL: func_01:
+; RV64IF:       frrm  a0
+; RV64IF:       slli  a0, a0, 2
+; RV64IF:       lui   a1, 66
+; RV64IF:       addiw a1, a1, 769
+; RV64IF:       srl   a0, a1, a0
+; RV64IF:       andi  a0, a0, 7
+; RV64IF:       ret
+
+declare i32 @llvm.flt.rounds()