[RISCV] Custom lowering of FLT_ROUNDS_

[sepavloff]

Small changes similar to those made in D91242

[jrtc27]

llvm/lib/Target/RISCV/RISCVISelLowering.h

77–81

[sepavloff]

Fixed comments

• IEEE-754 rounding direction names are replaced by llvm::RoundingMode enumerators,
• Fixed comment for RDN.

[sepavloff]

Adapted the patch for alternative CSR implementation

[sepavloff]

Rebased patch

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

227

You can use XLenVT instead of picking i64/i32.

898

Rename IntTy to XLenVT to match what most of the RISCV back does.

902

Use RISCVSysReg::lookupSysRegByName("FRM")->Encoding it's not common enough to justify having the encoding in 2 places.

1067

Is this code reachable? This would require setOperaction(ISD::FLT_ROUNDS_, MVT::i32, Custom) when Subtarget.is64Bit() is false.

It's also the default behavior for the target independent type legalizer.

llvm/lib/Target/RISCV/RISCVISelLowering.h

76

Can you use RISCVFPRndMode from lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

[craig.topper]

llvm/test/CodeGen/RISCV/fpenv.ll

2

Use update_llc_test_checks.py

[sepavloff]

Addressed reviewer's notes

[sepavloff]

Added missed change

[sepavloff]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1067

Removed this check.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

15

This is already included in RISCV.h because it's very common file to need.

[sepavloff]

Remove superfluous include

[craig.topper]

LGTM.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1069

I missed it before, but you can use Res.getValue(0) and Res.getValue(1) to shorten these lines if you want.

[sepavloff]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1069

Thank you for advice! I will incorporate these changes too.

llvm/lib/Target/RISCV/RISCVISelLowering.h

enum NodeType : unsigned {
   // Write value to CSR.
   // The first operand is a chain pointer, the second specifies address of the
   // required CSR and the third is the value to write. The result is chain
   // pointer.
   WRITE_CSR
 };
 }
 
+namespace RISCV {
+// Must agree with definitions in RISCVSystemOperands.td
+enum SysReg {
+  // User Floating-Point CSRs
+  FFLAGS = 0x001,
+  FRM = 0x002,
+  FCSR = 0x003
+};
+
+enum Rounding {
+  RNE = 0, ///< NearestTiesToEven.
+  RTZ = 1, ///< TowardZero.
+  RDN = 2, ///< TowardNegative.
+  RUP = 3, ///< TowardPositive.
+  RMM = 4, ///< NearestTiesToAway.
+  MaxRounding = RMM,
+  DYN = 7
+};
+} // namespace RISCV
+
 class RISCVTargetLowering : public TargetLowering {
   const RISCVSubtarget &Subtarget;
 
 public:
   explicit RISCVTargetLowering(const TargetMachine &TM,
                                const RISCVSubtarget &STI);
 
   bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
private:
   SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
 
   bool isEligibleForTailCallOptimization(
       CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
       const SmallVector<CCValAssign, 16> &ArgLocs) const;
 
   /// Generate error diagnostics if any register used by CC has been marked
   /// reserved.
   void validateCCReservedRegs(
       const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
       MachineFunction &MF) const;
 };
 }
 
 #endif

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the interfaces that RISCV uses to lower LLVM code into a
 // selection DAG.
 //
 //===----------------------------------------------------------------------===//
 
 #include "RISCVISelLowering.h"
 #include "RISCV.h"
 #include "RISCVMachineFunctionInfo.h"
 #include "RISCVRegisterInfo.h"
 #include "RISCVSubtarget.h"
 #include "RISCVTargetMachine.h"
 #include "Utils/RISCVMatInt.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/CallingConvLower.h"
RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
   if (Subtarget.is64Bit()) {
     setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
     setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
     setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
     setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
   }
 
+  if (Subtarget.hasStdExtF()) {
+    setOperationAction(ISD::FLT_ROUNDS_,
+                       (Subtarget.is64Bit() ? MVT::i64 : MVT::i32), Custom);
+  }
+
   setOperationAction(ISD::GlobalAddress, XLenVT, Custom);
   setOperationAction(ISD::BlockAddress, XLenVT, Custom);
   setOperationAction(ISD::ConstantPool, XLenVT, Custom);
 
   setOperationAction(ISD::GlobalTLSAddress, XLenVT, Custom);
 
   // TODO: On M-mode only targets, the cycle[h] CSR may not be present.
   // Unfortunately this can't be determined just from the ISA naming string.
case ISD::BITCAST: {
     if (Op.getValueType() != MVT::f32 || Op0.getValueType() != MVT::i32)
       return SDValue();
     SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
     SDValue FPConv = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, NewOp0);
     return FPConv;
   }
   case ISD::INTRINSIC_WO_CHAIN:
     return LowerINTRINSIC_WO_CHAIN(Op, DAG);
+  case ISD::FLT_ROUNDS_:
+    return lowerGET_ROUNDING(Op, DAG);
   }
 }
 
 static SDValue getTargetNode(GlobalAddressSDNode *N, SDLoc DL, EVT Ty,
                              SelectionDAG &DAG, unsigned Flags) {
   return DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, 0, Flags);
 }
 
default:
     return SDValue();    // Don't custom lower most intrinsics.
   case Intrinsic::thread_pointer: {
     EVT PtrVT = getPointerTy(DAG.getDataLayout());
     return DAG.getRegister(RISCV::X4, PtrVT);
   }
   }
 }
 
+SDValue RISCVTargetLowering::lowerGET_ROUNDING(SDValue Op,
+                                               SelectionDAG &DAG) const {
+  const MVT IntTy = Subtarget.getXLenVT();
+  SDLoc DL(Op);
+  SDValue Chain = Op->getOperand(0);
+  SDValue SysRegNo = DAG.getConstant(RISCV::SysReg::FRM, DL, IntTy);
+  SDVTList VTs = DAG.getVTList(IntTy, MVT::Other);
+  SDValue RM = DAG.getNode(RISCVISD::READ_CSR, DL, VTs, Chain, SysRegNo);
+
+  // Encoding used for rounding mode in RISCV differs from that used in
+  // FLT_ROUNDS. To convert it the RISCV rounding mode is used as an index in a
+  // table, which consists of a sequence of 4-bit fields, each representing
+  // corresponding FLT_ROUNDS mode.
+  static const int Table =
+      (int(RoundingMode::NearestTiesToEven) << 4 * RISCV::Rounding::RNE) |
+      (int(RoundingMode::TowardZero) << 4 * RISCV::Rounding::RTZ) |
+      (int(RoundingMode::TowardNegative) << 4 * RISCV::Rounding::RDN) |
+      (int(RoundingMode::TowardPositive) << 4 * RISCV::Rounding::RUP) |
+      (int(RoundingMode::NearestTiesToAway) << 4 * RISCV::Rounding::RMM);
+
+  SDValue Shift =
+      DAG.getNode(ISD::SHL, DL, IntTy, RM, DAG.getConstant(2, DL, IntTy));
+  SDValue Shifted = DAG.getNode(ISD::SRL, DL, IntTy,
+                                DAG.getConstant(Table, DL, IntTy), Shift);
+  SDValue Masked =
+      DAG.getNode(ISD::AND, DL, IntTy, Shifted, DAG.getConstant(7, DL, IntTy));
+
+  return DAG.getMergeValues({Masked, Chain}, DL);
+}
+
 // Returns the opcode of the target-specific SDNode that implements the 32-bit
 // form of the given Opcode.
 static RISCVISD::NodeType getRISCVWOpcode(unsigned Opcode) {
   switch (Opcode) {
   default:
     llvm_unreachable("Unexpected opcode");
   case ISD::SHL:
     return RISCVISD::SLLW;
case ISD::BITCAST: {
     SDValue Op0 = N->getOperand(0);
     if (Op0.getValueType() != MVT::f32)
       return;
     SDValue FPConv =
         DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Op0);
     Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, FPConv));
     break;
   }
+  case ISD::FLT_ROUNDS_: {
+    assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
+           Subtarget.hasStdExtF() && "Unexpected custom legalization");
+    SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other);
+    SDValue Res = DAG.getNode(ISD::FLT_ROUNDS_, DL, VTs, N->getOperand(0));
+    Results.push_back(SDValue(Res.getNode(), 0));
+    Results.push_back(SDValue(Res.getNode(), 1));
+    break;
+  }
   }
 }
 
 SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
                                                DAGCombinerInfo &DCI) const {
   SelectionDAG &DAG = DCI.DAG;
 
   switch (N->getOpcode()) {

llvm/test/CodeGen/RISCV/fpenv.ll

+; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s | FileCheck -check-prefix=RV32IF %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s | FileCheck -check-prefix=RV64IF %s
+
+define i32 @func_01() {
+  %rm = call i32 @llvm.flt.rounds()
+  ret i32 %rm
+}
+
+; RV32IF-LABEL: func_01:
+; RV32IF:       frrm  a0
+; RV32IF:       slli  a0, a0, 2
+; RV32IF:       lui   a1, 66
+; RV32IF:       addi  a1, a1, 769
+; RV32IF:       srl   a0, a1, a0
+; RV32IF:       andi  a0, a0, 7
+; RV32IF:       ret
+
+; RV64IF-LABEL: func_01:
+; RV64IF:       frrm  a0
+; RV64IF:       slli  a0, a0, 2
+; RV64IF:       lui   a1, 66
+; RV64IF:       addiw a1, a1, 769
+; RV64IF:       srl   a0, a1, a0
+; RV64IF:       andi  a0, a0, 7
+; RV64IF:       ret
+
+declare i32 @llvm.flt.rounds()