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Differential D86824

[GlobalISel] Enable usage of BranchProbabilityInfo in IRTranslator
ClosedPublic

Authored by aemerson on Aug 28 2020, 4:30 PM.

Details

Reviewers
paquette
arsenm
aditya_nandakumar
dsanders
Commits
rGe5784ef8f6c6: [GlobalISel] Enable usage of BranchProbabilityInfo in IRTranslator.
Summary

We weren't using this before, so none of the MachineFunction CFG edges had the branch probability information added. As a result, block placement later in the pipeline was flying blind.

This is enabled only with optimizations enabled like SelectionDAG.

Diff Detail

Event Timeline

aemerson created this revision.Aug 28 2020, 4:30 PM
Herald added subscribers: danielkiss, kerbowa, luismarques and 27 others. · View Herald TranscriptAug 28 2020, 4:30 PM
aemerson requested review of this revision.Aug 28 2020, 4:30 PM
Herald added subscribers: MaskRay, wdng. · View Herald TranscriptAug 28 2020, 4:30 PM
aemerson added a parent revision: D86665: [GlobalISel][IRTranslator] Generate better conditional branch lowering..Aug 28 2020, 4:30 PM
Harbormaster completed remote builds in B69988: Diff 288730.Aug 28 2020, 4:31 PM
arsenm accepted this revision.Aug 28 2020, 4:31 PM
arsenm added inline comments.
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
2922–2927

Ternary operator?

This revision is now accepted and ready to land.Aug 28 2020, 4:31 PM
This revision was landed with ongoing or failed builds.Sep 9 2020, 2:31 PM
Closed by commit rGe5784ef8f6c6: [GlobalISel] Enable usage of BranchProbabilityInfo in IRTranslator. (authored by aemerson). · Explain Why
This revision was automatically updated to reflect the committed changes.
aemerson added a commit: rGe5784ef8f6c6: [GlobalISel] Enable usage of BranchProbabilityInfo in IRTranslator..

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
6 lines
lib/
CodeGen/
GlobalISel/
18 lines
Target/
AArch64/
2 lines
AMDGPU/
2 lines
ARM/
2 lines
Mips/
2 lines
RISCV/
2 lines
X86/
2 lines
test/
CodeGen/
AArch64/
GlobalISel/
14 lines
16 lines
2 lines
AMDGPU/
GlobalISel/
24 lines
X86/
GlobalISel/
28 lines

Diff 290827

llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h

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#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h" #include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h" #include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h"
#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/SwiftErrorValueTracking.h" #include "llvm/CodeGen/SwiftErrorValueTracking.h"
#include "llvm/CodeGen/SwitchLoweringUtils.h" #include "llvm/CodeGen/SwitchLoweringUtils.h"
#include "llvm/IR/Intrinsics.h" #include "llvm/IR/Intrinsics.h"
#include "llvm/Support/Allocator.h" #include "llvm/Support/Allocator.h"
#include "llvm/Support/CodeGen.h"
#include <memory> #include <memory>
#include <utility> #include <utility>
namespace llvm { namespace llvm {
class AllocaInst; class AllocaInst;
class BasicBlock; class BasicBlock;
class CallInst; class CallInst;
▲ Show 20 Lines • Show All 513 Lines • ▼ Show 20 Linesprivate:
/// MachineRegisterInfo used to create virtual registers. /// MachineRegisterInfo used to create virtual registers.
MachineRegisterInfo *MRI = nullptr; MachineRegisterInfo *MRI = nullptr;
const DataLayout *DL; const DataLayout *DL;
/// Current target configuration. Controls how the pass handles errors. /// Current target configuration. Controls how the pass handles errors.
const TargetPassConfig *TPC; const TargetPassConfig *TPC;
CodeGenOpt::Level OptLevel;
/// Current optimization remark emitter. Used to report failures. /// Current optimization remark emitter. Used to report failures.
std::unique_ptr<OptimizationRemarkEmitter> ORE; std::unique_ptr<OptimizationRemarkEmitter> ORE;
FunctionLoweringInfo FuncInfo; FunctionLoweringInfo FuncInfo;
// True when either the Target Machine specifies no optimizations or the // True when either the Target Machine specifies no optimizations or the
// function has the optnone attribute. // function has the optnone attribute.
bool EnableOpts = false; bool EnableOpts = false;
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Linesprivate:
/// blocks. /// blocks.
BranchProbability getEdgeProbability(const MachineBasicBlock *Src, BranchProbability getEdgeProbability(const MachineBasicBlock *Src,
const MachineBasicBlock *Dst) const; const MachineBasicBlock *Dst) const;
void addSuccessorWithProb(MachineBasicBlock *Src, MachineBasicBlock *Dst, void addSuccessorWithProb(MachineBasicBlock *Src, MachineBasicBlock *Dst,
BranchProbability Prob); BranchProbability Prob);
public: public:
// Ctor, nothing fancy. IRTranslator(CodeGenOpt::Level OptLevel = CodeGenOpt::None);
IRTranslator();
StringRef getPassName() const override { return "IRTranslator"; } StringRef getPassName() const override { return "IRTranslator"; }
void getAnalysisUsage(AnalysisUsage &AU) const override; void getAnalysisUsage(AnalysisUsage &AU) const override;
// Algo: // Algo:
// CallLowering = MF.subtarget.getCallLowering() // CallLowering = MF.subtarget.getCallLowering()
// F = MF.getParent() // F = MF.getParent()
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llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

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#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/LowLevelTypeImpl.h" #include "llvm/Support/LowLevelTypeImpl.h"
#include "llvm/Support/MathExtras.h" #include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetIntrinsicInfo.h" #include "llvm/Target/TargetIntrinsicInfo.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include <algorithm> #include <algorithm>
#include <cassert> #include <cassert>
#include <cstddef>
#include <cstdint> #include <cstdint>
#include <iterator> #include <iterator>
#include <string> #include <string>
#include <utility> #include <utility>
#include <vector> #include <vector>
#define DEBUG_TYPE "irtranslator" #define DEBUG_TYPE "irtranslator"
Show All 24 Lines if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
R << (" (in function: " + MF.getName() + ")").str(); R << (" (in function: " + MF.getName() + ")").str();
if (TPC.isGlobalISelAbortEnabled()) if (TPC.isGlobalISelAbortEnabled())
report_fatal_error(R.getMsg()); report_fatal_error(R.getMsg());
else else
ORE.emit(R); ORE.emit(R);
} }
IRTranslator::IRTranslator() : MachineFunctionPass(ID) { } IRTranslator::IRTranslator(CodeGenOpt::Level optlevel)
: MachineFunctionPass(ID), OptLevel(optlevel) {}
#ifndef NDEBUG #ifndef NDEBUG
namespace { namespace {
/// Verify that every instruction created has the same DILocation as the /// Verify that every instruction created has the same DILocation as the
/// instruction being translated. /// instruction being translated.
class DILocationVerifier : public GISelChangeObserver { class DILocationVerifier : public GISelChangeObserver {
const Instruction *CurrInst = nullptr; const Instruction *CurrInst = nullptr;
Show All 27 Lines
} // namespace } // namespace
#endif // ifndef NDEBUG #endif // ifndef NDEBUG
void IRTranslator::getAnalysisUsage(AnalysisUsage &AU) const { void IRTranslator::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<StackProtector>(); AU.addRequired<StackProtector>();
AU.addRequired<TargetPassConfig>(); AU.addRequired<TargetPassConfig>();
AU.addRequired<GISelCSEAnalysisWrapperPass>(); AU.addRequired<GISelCSEAnalysisWrapperPass>();
if (OptLevel != CodeGenOpt::None)
AU.addRequired<BranchProbabilityInfoWrapperPass>();
getSelectionDAGFallbackAnalysisUsage(AU); getSelectionDAGFallbackAnalysisUsage(AU);
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
IRTranslator::ValueToVRegInfo::VRegListT & IRTranslator::ValueToVRegInfo::VRegListT &
IRTranslator::allocateVRegs(const Value &Val) { IRTranslator::allocateVRegs(const Value &Val) {
assert(!VMap.contains(Val) && "Value already allocated in VMap"); assert(!VMap.contains(Val) && "Value already allocated in VMap");
auto *Regs = VMap.getVRegs(Val); auto *Regs = VMap.getVRegs(Val);
▲ Show 20 Lines • Show All 2,738 Lines • ▼ Show 20 Lines if (EnableCSE) {
CurBuilder = std::make_unique<MachineIRBuilder>(); CurBuilder = std::make_unique<MachineIRBuilder>();
} }
CLI = MF->getSubtarget().getCallLowering(); CLI = MF->getSubtarget().getCallLowering();
CurBuilder->setMF(*MF); CurBuilder->setMF(*MF);
EntryBuilder->setMF(*MF); EntryBuilder->setMF(*MF);
MRI = &MF->getRegInfo(); MRI = &MF->getRegInfo();
DL = &F.getParent()->getDataLayout(); DL = &F.getParent()->getDataLayout();
ORE = std::make_unique<OptimizationRemarkEmitter>(&F); ORE = std::make_unique<OptimizationRemarkEmitter>(&F);
const TargetMachine &TM = MF->getTarget();
EnableOpts = OptLevel != CodeGenOpt::None && !skipFunction(F);
FuncInfo.MF = MF; FuncInfo.MF = MF;
if (EnableOpts)
FuncInfo.BPI = &getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI();
else
FuncInfo.BPI = nullptr; FuncInfo.BPI = nullptr;
const auto &TLI = *MF->getSubtarget().getTargetLowering(); const auto &TLI = *MF->getSubtarget().getTargetLowering();
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const TargetMachine &TM = MF->getTarget();
SL = std::make_unique<GISelSwitchLowering>(this, FuncInfo); SL = std::make_unique<GISelSwitchLowering>(this, FuncInfo);
SL->init(TLI, TM, *DL); SL->init(TLI, TM, *DL);
EnableOpts = TM.getOptLevel() != CodeGenOpt::None && !skipFunction(F);
assert(PendingPHIs.empty() && "stale PHIs"); assert(PendingPHIs.empty() && "stale PHIs");
if (!DL->isLittleEndian()) { if (!DL->isLittleEndian()) {
// Currently we don't properly handle big endian code. // Currently we don't properly handle big endian code.
OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure", OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
F.getSubprogram(), &F.getEntryBlock()); F.getSubprogram(), &F.getEntryBlock());
R << "unable to translate in big endian mode"; R << "unable to translate in big endian mode";
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llvm/lib/Target/AArch64/AArch64TargetMachine.cpp

Show First 20 Lines • Show All 538 Lines • ▼ Show 20 Linesbool AArch64PassConfig::addInstSelector() {
if (TM->getTargetTriple().isOSBinFormatELF() && if (TM->getTargetTriple().isOSBinFormatELF() &&
getOptLevel() != CodeGenOpt::None) getOptLevel() != CodeGenOpt::None)
addPass(createAArch64CleanupLocalDynamicTLSPass()); addPass(createAArch64CleanupLocalDynamicTLSPass());
return false; return false;
} }
bool AArch64PassConfig::addIRTranslator() { bool AArch64PassConfig::addIRTranslator() {
addPass(new IRTranslator()); addPass(new IRTranslator(getOptLevel()));
return false; return false;
} }
void AArch64PassConfig::addPreLegalizeMachineIR() { void AArch64PassConfig::addPreLegalizeMachineIR() {
bool IsOptNone = getOptLevel() == CodeGenOpt::None; bool IsOptNone = getOptLevel() == CodeGenOpt::None;
addPass(createAArch64PreLegalizeCombiner(IsOptNone)); addPass(createAArch64PreLegalizeCombiner(IsOptNone));
} }
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llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Show First 20 Lines • Show All 940 Lines • ▼ Show 20 Linesbool GCNPassConfig::addInstSelector() {
AMDGPUPassConfig::addInstSelector(); AMDGPUPassConfig::addInstSelector();
addPass(&SIFixSGPRCopiesID); addPass(&SIFixSGPRCopiesID);
addPass(createSILowerI1CopiesPass()); addPass(createSILowerI1CopiesPass());
addPass(createSIAddIMGInitPass()); addPass(createSIAddIMGInitPass());
return false; return false;
} }
bool GCNPassConfig::addIRTranslator() { bool GCNPassConfig::addIRTranslator() {
addPass(new IRTranslator()); addPass(new IRTranslator(getOptLevel()));
return false; return false;
} }
void GCNPassConfig::addPreLegalizeMachineIR() { void GCNPassConfig::addPreLegalizeMachineIR() {
bool IsOptNone = getOptLevel() == CodeGenOpt::None; bool IsOptNone = getOptLevel() == CodeGenOpt::None;
addPass(createAMDGPUPreLegalizeCombiner(IsOptNone)); addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
addPass(new Localizer()); addPass(new Localizer());
} }
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llvm/lib/Target/ARM/ARMTargetMachine.cpp

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} }
bool ARMPassConfig::addInstSelector() { bool ARMPassConfig::addInstSelector() {
addPass(createARMISelDag(getARMTargetMachine(), getOptLevel())); addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
return false; return false;
} }
bool ARMPassConfig::addIRTranslator() { bool ARMPassConfig::addIRTranslator() {
addPass(new IRTranslator()); addPass(new IRTranslator(getOptLevel()));
return false; return false;
} }
bool ARMPassConfig::addLegalizeMachineIR() { bool ARMPassConfig::addLegalizeMachineIR() {
addPass(new Legalizer()); addPass(new Legalizer());
return false; return false;
} }
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llvm/lib/Target/Mips/MipsTargetMachine.cpp

Show First 20 Lines • Show All 310 Lines • ▼ Show 20 Linesvoid MipsPassConfig::addPreEmitPass() {
// exists. // exists.
// Any new pass should go before this pass. // Any new pass should go before this pass.
addPass(createMipsBranchExpansion()); addPass(createMipsBranchExpansion());
addPass(createMipsConstantIslandPass()); addPass(createMipsConstantIslandPass());
} }
bool MipsPassConfig::addIRTranslator() { bool MipsPassConfig::addIRTranslator() {
addPass(new IRTranslator()); addPass(new IRTranslator(getOptLevel()));
return false; return false;
} }
void MipsPassConfig::addPreLegalizeMachineIR() { void MipsPassConfig::addPreLegalizeMachineIR() {
addPass(createMipsPreLegalizeCombiner()); addPass(createMipsPreLegalizeCombiner());
} }
bool MipsPassConfig::addLegalizeMachineIR() { bool MipsPassConfig::addLegalizeMachineIR() {
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llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

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bool RISCVPassConfig::addInstSelector() { bool RISCVPassConfig::addInstSelector() {
addPass(createRISCVISelDag(getRISCVTargetMachine())); addPass(createRISCVISelDag(getRISCVTargetMachine()));
return false; return false;
} }
bool RISCVPassConfig::addIRTranslator() { bool RISCVPassConfig::addIRTranslator() {
addPass(new IRTranslator()); addPass(new IRTranslator(getOptLevel()));
return false; return false;
} }
bool RISCVPassConfig::addLegalizeMachineIR() { bool RISCVPassConfig::addLegalizeMachineIR() {
addPass(new Legalizer()); addPass(new Legalizer());
return false; return false;
} }
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llvm/lib/Target/X86/X86TargetMachine.cpp

Show First 20 Lines • Show All 438 Lines • ▼ Show 20 Lines if (TM->getTargetTriple().isOSBinFormatELF() &&
getOptLevel() != CodeGenOpt::None) getOptLevel() != CodeGenOpt::None)
addPass(createCleanupLocalDynamicTLSPass()); addPass(createCleanupLocalDynamicTLSPass());
addPass(createX86GlobalBaseRegPass()); addPass(createX86GlobalBaseRegPass());
return false; return false;
} }
bool X86PassConfig::addIRTranslator() { bool X86PassConfig::addIRTranslator() {
addPass(new IRTranslator()); addPass(new IRTranslator(getOptLevel()));
return false; return false;
} }
bool X86PassConfig::addLegalizeMachineIR() { bool X86PassConfig::addLegalizeMachineIR() {
addPass(new Legalizer()); addPass(new Legalizer());
return false; return false;
} }
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llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple aarch64 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s ; RUN: llc -mtriple aarch64 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
declare i32 @bar(...) declare i32 @bar(...)
define void @or_cond(i32 %X, i32 %Y, i32 %Z) nounwind { define void @or_cond(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond ; CHECK-LABEL: name: or_cond
; CHECK: bb.1.entry: ; CHECK: bb.1.entry:
; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000) ; CHECK: successors: %bb.2(0x20000000), %bb.4(0x60000000)
; CHECK: liveins: $w0, $w1, $w2 ; CHECK: liveins: $w0, $w1, $w2
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]] ; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]] ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
; CHECK: G_BRCOND [[ICMP2]](s1), %bb.2 ; CHECK: G_BRCOND [[ICMP2]](s1), %bb.2
; CHECK: G_BR %bb.4 ; CHECK: G_BR %bb.4
; CHECK: bb.4.entry: ; CHECK: bb.4.entry:
; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; CHECK: successors: %bb.2(0x2aaaaaab), %bb.3(0x55555555)
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: G_BRCOND [[ICMP3]](s1), %bb.2 ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.2
; CHECK: G_BR %bb.3 ; CHECK: G_BR %bb.3
; CHECK: bb.2.cond_true: ; CHECK: bb.2.cond_true:
; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp ; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
; CHECK: bb.3.UnifiedReturnBlock: ; CHECK: bb.3.UnifiedReturnBlock:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
entry: entry:
%tmp1 = icmp eq i32 %X, 0 %tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5 %tmp3 = icmp slt i32 %Y, 5
%tmp4 = or i1 %tmp3, %tmp1 %tmp4 = or i1 %tmp3, %tmp1
br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock
cond_true: cond_true:
%tmp5 = tail call i32 (...) @bar( ) %tmp5 = tail call i32 (...) @bar( )
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @and_cond(i32 %X, i32 %Y, i32 %Z) nounwind { define void @and_cond(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: and_cond ; CHECK-LABEL: name: and_cond
; CHECK: bb.1.entry: ; CHECK: bb.1.entry:
; CHECK: successors: %bb.4(0x40000000), %bb.3(0x40000000) ; CHECK: successors: %bb.4(0x60000000), %bb.3(0x20000000)
; CHECK: liveins: $w0, $w1, $w2 ; CHECK: liveins: $w0, $w1, $w2
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
; CHECK: [[AND:%[0-9]+]]:_(s1) = G_AND [[ICMP1]], [[ICMP]] ; CHECK: [[AND:%[0-9]+]]:_(s1) = G_AND [[ICMP1]], [[ICMP]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]] ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
; CHECK: G_BRCOND [[ICMP2]](s1), %bb.4 ; CHECK: G_BRCOND [[ICMP2]](s1), %bb.4
; CHECK: G_BR %bb.3 ; CHECK: G_BR %bb.3
; CHECK: bb.4.entry: ; CHECK: bb.4.entry:
; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; CHECK: successors: %bb.2(0x55555555), %bb.3(0x2aaaaaab)
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: G_BRCOND [[ICMP3]](s1), %bb.2 ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.2
; CHECK: G_BR %bb.3 ; CHECK: G_BR %bb.3
; CHECK: bb.2.cond_true: ; CHECK: bb.2.cond_true:
; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp ; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
; CHECK: bb.3.UnifiedReturnBlock: ; CHECK: bb.3.UnifiedReturnBlock:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
entry: entry:
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UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
; Emit multiple branches for more than 2 cases. ; Emit multiple branches for more than 2 cases.
define void @or_cond_multiple_cases(i32 %X, i32 %Y, i32 %Z) nounwind { define void @or_cond_multiple_cases(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond_multiple_cases ; CHECK-LABEL: name: or_cond_multiple_cases
; CHECK: bb.1.entry: ; CHECK: bb.1.entry:
; CHECK: successors: %bb.2(0x40000000), %bb.5(0x40000000) ; CHECK: successors: %bb.2(0x10000000), %bb.5(0x70000000)
; CHECK: liveins: $w0, $w1, $w2 ; CHECK: liveins: $w0, $w1, $w2
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[C]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[C]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]] ; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]]
; CHECK: [[OR1:%[0-9]+]]:_(s1) = G_OR [[OR]], [[ICMP2]] ; CHECK: [[OR1:%[0-9]+]]:_(s1) = G_OR [[OR]], [[ICMP2]]
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[C]] ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[C]]
; CHECK: G_BRCOND [[ICMP3]](s1), %bb.2 ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.2
; CHECK: G_BR %bb.5 ; CHECK: G_BR %bb.5
; CHECK: bb.5.entry: ; CHECK: bb.5.entry:
; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000) ; CHECK: successors: %bb.2(0x12492492), %bb.4(0x6db6db6e)
; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: G_BRCOND [[ICMP4]](s1), %bb.2 ; CHECK: G_BRCOND [[ICMP4]](s1), %bb.2
; CHECK: G_BR %bb.4 ; CHECK: G_BR %bb.4
; CHECK: bb.4.entry: ; CHECK: bb.4.entry:
; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; CHECK: successors: %bb.2(0x2aaaaaab), %bb.3(0x55555555)
; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; CHECK: G_BRCOND [[ICMP5]](s1), %bb.2 ; CHECK: G_BRCOND [[ICMP5]](s1), %bb.2
; CHECK: G_BR %bb.3 ; CHECK: G_BR %bb.3
; CHECK: bb.2.cond_true: ; CHECK: bb.2.cond_true:
; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp ; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
; CHECK: bb.3.UnifiedReturnBlock: ; CHECK: bb.3.UnifiedReturnBlock:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
entry: entry:
▲ Show 20 Lines • Show All 86 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple aarch64 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s ; RUN: llc -mtriple aarch64 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
define i32 @test_bittest(i16 %p) { define i32 @test_bittest(i16 %p) {
; CHECK-LABEL: name: test_bittest ; CHECK-LABEL: name: test_bittest
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: successors: %bb.4(0x40000000), %bb.5(0x40000000) ; CHECK: successors: %bb.4(0x1b6db6db), %bb.5(0x64924925)
; CHECK: liveins: $w0 ; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 114 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 114
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ZEXT]], [[C3]] ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ZEXT]], [[C3]]
; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](s32) ; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 59 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 59
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[SUB]](s32), [[C4]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[SUB]](s32), [[C4]]
; CHECK: G_BRCOND [[ICMP]](s1), %bb.4 ; CHECK: G_BRCOND [[ICMP]](s1), %bb.4
; CHECK: G_BR %bb.5 ; CHECK: G_BR %bb.5
; CHECK: bb.4 (%ir-block.0): ; CHECK: bb.4 (%ir-block.0):
; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[ZEXT]](s32), [[C]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[ZEXT]](s32), [[C]]
; CHECK: G_BRCOND [[ICMP1]](s1), %bb.3 ; CHECK: G_BRCOND [[ICMP1]](s1), %bb.3
; CHECK: G_BR %bb.2 ; CHECK: G_BR %bb.2
; CHECK: bb.5 (%ir-block.0): ; CHECK: bb.5 (%ir-block.0):
; CHECK: successors: %bb.3(0x40000000), %bb.4(0x40000000) ; CHECK: successors: %bb.3(0x745d1746), %bb.4(0x0ba2e8ba)
; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[C5]], [[ZEXT1]](s64) ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[C5]], [[ZEXT1]](s64)
; CHECK: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 866239240827043840 ; CHECK: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 866239240827043840
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C6]] ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C6]]
; CHECK: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[C7]] ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[C7]]
; CHECK: G_BRCOND [[ICMP2]](s1), %bb.3 ; CHECK: G_BRCOND [[ICMP2]](s1), %bb.3
; CHECK: G_BR %bb.4 ; CHECK: G_BR %bb.4
Show All 19 Lines
} }
declare void @callee() declare void @callee()
define void @test_bittest_2_bt(i32 %p) { define void @test_bittest_2_bt(i32 %p) {
; CHECK-LABEL: name: test_bittest_2_bt ; CHECK-LABEL: name: test_bittest_2_bt
; CHECK: bb.1.entry: ; CHECK: bb.1.entry:
; CHECK: successors: %bb.5(0x40000000), %bb.6(0x40000000) ; CHECK: successors: %bb.5(0x345d1746), %bb.6(0x4ba2e8ba)
; CHECK: liveins: $w0 ; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 176 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 176
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C]] ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[SUB]](s32), [[C1]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[SUB]](s32), [[C1]]
; CHECK: G_BRCOND [[ICMP]](s1), %bb.5 ; CHECK: G_BRCOND [[ICMP]](s1), %bb.5
; CHECK: G_BR %bb.6 ; CHECK: G_BR %bb.6
; CHECK: bb.5.entry: ; CHECK: bb.5.entry:
; CHECK: successors: %bb.4(0x40000000), %bb.7(0x40000000) ; CHECK: successors: %bb.4(0x0ccccccd), %bb.7(0x73333333)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C2]] ; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C2]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SUB1]](s32) ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SUB1]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 38 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 38
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[SUB1]](s32), [[C3]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[SUB1]](s32), [[C3]]
; CHECK: G_BRCOND [[ICMP1]](s1), %bb.4 ; CHECK: G_BRCOND [[ICMP1]](s1), %bb.4
; CHECK: G_BR %bb.7 ; CHECK: G_BR %bb.7
; CHECK: bb.6.entry: ; CHECK: bb.6.entry:
; CHECK: successors: %bb.2(0x40000000), %bb.5(0x40000000) ; CHECK: successors: %bb.2(0x76276276), %bb.5(0x09d89d8a)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C4]], [[SUB]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C4]], [[SUB]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 57351 ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 57351
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C5]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C5]]
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C6]] ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C6]]
; CHECK: G_BRCOND [[ICMP2]](s1), %bb.2 ; CHECK: G_BRCOND [[ICMP2]](s1), %bb.2
; CHECK: G_BR %bb.5 ; CHECK: G_BR %bb.5
; CHECK: bb.7.entry: ; CHECK: bb.7.entry:
; CHECK: successors: %bb.3(0x40000000), %bb.4(0x40000000) ; CHECK: successors: %bb.3(0x71c71c72), %bb.4(0x0e38e38e)
; CHECK: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[C7]], [[ZEXT]](s64) ; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[C7]], [[ZEXT]](s64)
; CHECK: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 365072220160 ; CHECK: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 365072220160
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[C8]] ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[C8]]
; CHECK: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND1]](s64), [[C9]] ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND1]](s64), [[C9]]
; CHECK: G_BRCOND [[ICMP3]](s1), %bb.3 ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.3
; CHECK: G_BR %bb.4 ; CHECK: G_BR %bb.4
Show All 27 Lines
sw.default: ; preds = %entry sw.default: ; preds = %entry
ret void ret void
} }
define i32 @test_bittest_single_bt_only_with_fallthrough(i16 %p) { define i32 @test_bittest_single_bt_only_with_fallthrough(i16 %p) {
; CHECK-LABEL: name: test_bittest_single_bt_only_with_fallthrough ; CHECK-LABEL: name: test_bittest_single_bt_only_with_fallthrough
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000) ; CHECK: successors: %bb.2(0x0aaaaaab), %bb.4(0x75555555)
; CHECK: liveins: $w0 ; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ZEXT]], [[C2]] ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ZEXT]], [[C2]]
; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](s32) ; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 59 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 59
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[SUB]](s32), [[C3]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[SUB]](s32), [[C3]]
; CHECK: G_BRCOND [[ICMP]](s1), %bb.2 ; CHECK: G_BRCOND [[ICMP]](s1), %bb.2
; CHECK: bb.4 (%ir-block.0): ; CHECK: bb.4 (%ir-block.0):
; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) ; CHECK: successors: %bb.3(0x745d1746), %bb.2(0x0ba2e8ba)
; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[C4]], [[ZEXT1]](s64) ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[C4]], [[ZEXT1]](s64)
; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 866239240827043840 ; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 866239240827043840
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C5]] ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C5]]
; CHECK: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[C6]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[C6]]
; CHECK: G_BRCOND [[ICMP1]](s1), %bb.3 ; CHECK: G_BRCOND [[ICMP1]](s1), %bb.3
; CHECK: bb.2.sw.epilog: ; CHECK: bb.2.sw.epilog:
Show All 18 Lines

llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll

Show First 20 Lines • Show All 125 Lines • ▼ Show 20 Lines
; under a certain condition inside a loop. ; under a certain condition inside a loop.
define float @foo_loop(%swift_error** swifterror %error_ptr_ref, i32 %cc, float %cc2) { define float @foo_loop(%swift_error** swifterror %error_ptr_ref, i32 %cc, float %cc2) {
; CHECK-LABEL: foo_loop: ; CHECK-LABEL: foo_loop:
; CHECK: cbz ; CHECK: cbz
; CHECK: mov w0, #16 ; CHECK: mov w0, #16
; CHECK: malloc ; CHECK: malloc
; CHECK: mov x21, x0 ; CHECK: mov x21, x0
; CHECK: strb w{{.*}}, [x0, #8] ; CHECK: strb w{{.*}}, [x0, #8]
; CHECK: fcmp
; CHECK: b.le
; CHECK: ret ; CHECK: ret
entry: entry:
br label %bb_loop br label %bb_loop
bb_loop: bb_loop:
%cond = icmp ne i32 %cc, 0 %cond = icmp ne i32 %cc, 0
br i1 %cond, label %gen_error, label %bb_cont br i1 %cond, label %gen_error, label %bb_cont
▲ Show 20 Lines • Show All 436 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll

Show First 20 Lines • Show All 199 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @break_loop(i32 %arg) { define amdgpu_kernel void @break_loop(i32 %arg) {
; CHECK-LABEL: break_loop: ; CHECK-LABEL: break_loop:
; CHECK: ; %bb.0: ; %bb ; CHECK: ; %bb.0: ; %bb
; CHECK-NEXT: s_load_dword s2, s[4:5], 0x0 ; CHECK-NEXT: s_load_dword s2, s[4:5], 0x0
; CHECK-NEXT: s_mov_b64 s[0:1], 0 ; CHECK-NEXT: s_mov_b64 s[0:1], 0
; CHECK-NEXT: ; implicit-def: $vgpr1 ; CHECK-NEXT: ; implicit-def: $vgpr1
; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_subrev_u32_e32 v0, s2, v0 ; CHECK-NEXT: v_subrev_u32_e32 v0, s2, v0
; CHECK-NEXT: BB5_1: ; %bb1 ; CHECK-NEXT: s_branch BB5_2
; CHECK-NEXT: BB5_1: ; %Flow
; CHECK-NEXT: ; in Loop: Header=BB5_2 Depth=1
; CHECK-NEXT: s_and_b64 s[2:3], exec, s[2:3]
; CHECK-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
; CHECK-NEXT: s_andn2_b64 exec, exec, s[0:1]
; CHECK-NEXT: s_cbranch_execz BB5_4
; CHECK-NEXT: BB5_2: ; %bb1
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: v_add_u32_e32 v1, 1, v1 ; CHECK-NEXT: v_add_u32_e32 v1, 1, v1
; CHECK-NEXT: v_cmp_le_i32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cmp_le_i32_e32 vcc, 0, v1
; CHECK-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, 1 ; CHECK-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, 1
; CHECK-NEXT: s_cbranch_vccnz BB5_3 ; CHECK-NEXT: s_cbranch_vccnz BB5_1
; CHECK-NEXT: ; %bb.2: ; %bb4 ; CHECK-NEXT: ; %bb.3: ; %bb4
; CHECK-NEXT: ; in Loop: Header=BB5_1 Depth=1 ; CHECK-NEXT: ; in Loop: Header=BB5_2 Depth=1
; CHECK-NEXT: global_load_dword v2, v[0:1], off ; CHECK-NEXT: global_load_dword v2, v[0:1], off
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_cmp_ge_i32_e64 s[2:3], v0, v2 ; CHECK-NEXT: v_cmp_ge_i32_e64 s[2:3], v0, v2
; CHECK-NEXT: BB5_3: ; %Flow ; CHECK-NEXT: s_branch BB5_1
; CHECK-NEXT: ; in Loop: Header=BB5_1 Depth=1 ; CHECK-NEXT: BB5_4: ; %bb9
; CHECK-NEXT: s_and_b64 s[2:3], exec, s[2:3]
; CHECK-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
; CHECK-NEXT: s_andn2_b64 exec, exec, s[0:1]
; CHECK-NEXT: s_cbranch_execnz BB5_1
; CHECK-NEXT: ; %bb.4: ; %bb9
; CHECK-NEXT: s_endpgm ; CHECK-NEXT: s_endpgm
bb: bb:
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%tmp = sub i32 %id, %arg %tmp = sub i32 %id, %arg
br label %bb1 br label %bb1
bb1: bb1:
%lsr.iv = phi i32 [ undef, %bb ], [ %lsr.iv.next, %bb4 ] %lsr.iv = phi i32 [ undef, %bb ], [ %lsr.iv.next, %bb4 ]
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llvm/test/CodeGen/X86/GlobalISel/phi.ll

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define i32 @test_i32(i32 %a, i32 %f, i32 %t) { define i32 @test_i32(i32 %a, i32 %f, i32 %t) {
; ALL-LABEL: test_i32: ; ALL-LABEL: test_i32:
; ALL: # %bb.0: # %entry ; ALL: # %bb.0: # %entry
; ALL-NEXT: movl %esi, %eax ; ALL-NEXT: movl %esi, %eax
; ALL-NEXT: xorl %ecx, %ecx ; ALL-NEXT: xorl %ecx, %ecx
; ALL-NEXT: cmpl %ecx, %edi ; ALL-NEXT: cmpl %ecx, %edi
; ALL-NEXT: setg %cl ; ALL-NEXT: setg %cl
; ALL-NEXT: testb $1, %cl ; ALL-NEXT: testb $1, %cl
; ALL-NEXT: jne .LBB2_2 ; ALL-NEXT: je .LBB2_1
; ALL-NEXT: # %bb.1: # %cond.false ; ALL-NEXT: # %bb.2: # %cond.end
; ALL-NEXT: retq
; ALL-NEXT: .LBB2_1: # %cond.false
; ALL-NEXT: movl %edx, %eax ; ALL-NEXT: movl %edx, %eax
; ALL-NEXT: .LBB2_2: # %cond.end
; ALL-NEXT: retq ; ALL-NEXT: retq
entry: entry:
%cmp = icmp sgt i32 %a, 0 %cmp = icmp sgt i32 %a, 0
br i1 %cmp, label %cond.true, label %cond.false br i1 %cmp, label %cond.true, label %cond.false
cond.true: ; preds = %entry cond.true: ; preds = %entry
br label %cond.end br label %cond.end
cond.false: ; preds = %entry cond.false: ; preds = %entry
br label %cond.end br label %cond.end
cond.end: ; preds = %cond.false, %cond.true cond.end: ; preds = %cond.false, %cond.true
%cond = phi i32 [ %f, %cond.true ], [ %t, %cond.false ] %cond = phi i32 [ %f, %cond.true ], [ %t, %cond.false ]
ret i32 %cond ret i32 %cond
} }
define i64 @test_i64(i32 %a, i64 %f, i64 %t) { define i64 @test_i64(i32 %a, i64 %f, i64 %t) {
; ALL-LABEL: test_i64: ; ALL-LABEL: test_i64:
; ALL: # %bb.0: # %entry ; ALL: # %bb.0: # %entry
; ALL-NEXT: movq %rsi, %rax ; ALL-NEXT: movq %rsi, %rax
; ALL-NEXT: xorl %ecx, %ecx ; ALL-NEXT: xorl %ecx, %ecx
; ALL-NEXT: cmpl %ecx, %edi ; ALL-NEXT: cmpl %ecx, %edi
; ALL-NEXT: setg %cl ; ALL-NEXT: setg %cl
; ALL-NEXT: testb $1, %cl ; ALL-NEXT: testb $1, %cl
; ALL-NEXT: jne .LBB3_2 ; ALL-NEXT: je .LBB3_1
; ALL-NEXT: # %bb.1: # %cond.false ; ALL-NEXT: # %bb.2: # %cond.end
; ALL-NEXT: retq
; ALL-NEXT: .LBB3_1: # %cond.false
; ALL-NEXT: movq %rdx, %rax ; ALL-NEXT: movq %rdx, %rax
; ALL-NEXT: .LBB3_2: # %cond.end
; ALL-NEXT: retq ; ALL-NEXT: retq
entry: entry:
%cmp = icmp sgt i32 %a, 0 %cmp = icmp sgt i32 %a, 0
br i1 %cmp, label %cond.true, label %cond.false br i1 %cmp, label %cond.true, label %cond.false
cond.true: ; preds = %entry cond.true: ; preds = %entry
br label %cond.end br label %cond.end
cond.false: ; preds = %entry cond.false: ; preds = %entry
br label %cond.end br label %cond.end
cond.end: ; preds = %cond.false, %cond.true cond.end: ; preds = %cond.false, %cond.true
%cond = phi i64 [ %f, %cond.true ], [ %t, %cond.false ] %cond = phi i64 [ %f, %cond.true ], [ %t, %cond.false ]
ret i64 %cond ret i64 %cond
} }
define float @test_float(i32 %a, float %f, float %t) { define float @test_float(i32 %a, float %f, float %t) {
; ALL-LABEL: test_float: ; ALL-LABEL: test_float:
; ALL: # %bb.0: # %entry ; ALL: # %bb.0: # %entry
; ALL-NEXT: xorl %eax, %eax ; ALL-NEXT: xorl %eax, %eax
; ALL-NEXT: cmpl %eax, %edi ; ALL-NEXT: cmpl %eax, %edi
; ALL-NEXT: setg %al ; ALL-NEXT: setg %al
; ALL-NEXT: testb $1, %al ; ALL-NEXT: testb $1, %al
; ALL-NEXT: jne .LBB4_2 ; ALL-NEXT: je .LBB4_1
; ALL-NEXT: # %bb.1: # %cond.false ; ALL-NEXT: # %bb.2: # %cond.end
; ALL-NEXT: retq
; ALL-NEXT: .LBB4_1: # %cond.false
; ALL-NEXT: movaps %xmm1, %xmm0 ; ALL-NEXT: movaps %xmm1, %xmm0
; ALL-NEXT: .LBB4_2: # %cond.end
; ALL-NEXT: retq ; ALL-NEXT: retq
entry: entry:
%cmp = icmp sgt i32 %a, 0 %cmp = icmp sgt i32 %a, 0
br i1 %cmp, label %cond.true, label %cond.false br i1 %cmp, label %cond.true, label %cond.false
cond.true: ; preds = %entry cond.true: ; preds = %entry
br label %cond.end br label %cond.end
cond.false: ; preds = %entry cond.false: ; preds = %entry
br label %cond.end br label %cond.end
cond.end: ; preds = %cond.false, %cond.true cond.end: ; preds = %cond.false, %cond.true
%cond = phi float [ %f, %cond.true ], [ %t, %cond.false ] %cond = phi float [ %f, %cond.true ], [ %t, %cond.false ]
ret float %cond ret float %cond
} }
define double @test_double(i32 %a, double %f, double %t) { define double @test_double(i32 %a, double %f, double %t) {
; ALL-LABEL: test_double: ; ALL-LABEL: test_double:
; ALL: # %bb.0: # %entry ; ALL: # %bb.0: # %entry
; ALL-NEXT: xorl %eax, %eax ; ALL-NEXT: xorl %eax, %eax
; ALL-NEXT: cmpl %eax, %edi ; ALL-NEXT: cmpl %eax, %edi
; ALL-NEXT: setg %al ; ALL-NEXT: setg %al
; ALL-NEXT: testb $1, %al ; ALL-NEXT: testb $1, %al
; ALL-NEXT: jne .LBB5_2 ; ALL-NEXT: je .LBB5_1
; ALL-NEXT: # %bb.1: # %cond.false ; ALL-NEXT: # %bb.2: # %cond.end
; ALL-NEXT: retq
; ALL-NEXT: .LBB5_1: # %cond.false
; ALL-NEXT: movaps %xmm1, %xmm0 ; ALL-NEXT: movaps %xmm1, %xmm0
; ALL-NEXT: .LBB5_2: # %cond.end
; ALL-NEXT: retq ; ALL-NEXT: retq
entry: entry:
%cmp = icmp sgt i32 %a, 0 %cmp = icmp sgt i32 %a, 0
br i1 %cmp, label %cond.true, label %cond.false br i1 %cmp, label %cond.true, label %cond.false
cond.true: ; preds = %entry cond.true: ; preds = %entry
br label %cond.end br label %cond.end
cond.false: ; preds = %entry cond.false: ; preds = %entry
br label %cond.end br label %cond.end
cond.end: ; preds = %cond.false, %cond.true cond.end: ; preds = %cond.false, %cond.true
%cond = phi double [ %f, %cond.true ], [ %t, %cond.false ] %cond = phi double [ %f, %cond.true ], [ %t, %cond.false ]
ret double %cond ret double %cond
} }