[RISCV] Add MC encodings and tests of the Bit Manipulation extension

[PaoloS]

Summary

Details on the proposed extension: https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.92.pdf

[simoncook]

llvm/lib/Target/RISCV/RISCV.td

48

nitpick: the capitalisation here looks weird.

94

This predicate probably needs a comment

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

18

Probably worth a comment noting that the intent is to move these to the InstrFormats file once B has been ratified.

[lewis-revill]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

18

I'm concerned that with this definition you won't be able to enforce the immediate fitting in the field. A better approach would probably be to add an instruction format from scratch with a uimm6 shamt operand. Likewise for RVBInstFunct5, RVBInstFunct6, RVBInstFunct7, with the appropriate operand types for however many bits the shamt operand requires. Invalid immediate tests should also then be added.

68

Is there an explanation for why this instruction is not re-using RVInstR4 from RISCVInstrFormats.td?

89

Slight typo here, this instruction format is for more than one instruction so should use opcodestr rather than the hard coded "fsriw".

108

Vice-versa here, there is still an opcodestr passed to this instruction format. I prefer the approach of keeping the instruction format generic even if there will only ever be one opcodestr, and having the instruction specify it.

[PaoloS]

Fixed typos, bad indentations and capitalization.
Added uimm6 and uimm7 riscv asm operand types in order to have more precise classes to represent the templates of the instructions with 5-bit, 6-bit and 7-bit immediate fields. The riscv asm operand uimm5 already existed.
Added missing rev pseudo instructions for riscv64.
Fixed the tests accordingly.
Added comments.

[PaoloS]

Fixed the indentation of the tests.

[PaoloS]

Added the latest updates to the encodings of the instructions, including the gorc, gorci, bfp instructions, the 'orc' pseudo instructions based on gorci and the zip/unzip pseudo instructions based on shfli/unshfli. Changed the encoding of grev and bmatxor to make space for gorc. Added the subtarget feature Zbf to support bfp. Added the necessary MC tests.

[PaoloS]

Update the encodings to the latest version of the spec. Fix the tests and encoding conflicts.

[PaoloS]

Fixed immediate values of shfli/unshfli for zip/unzip pseudo instructions.

[PaoloS]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

68

Yes, that was because with RVInstR4 I couldn't use funct3 for encoding. As it is declared in RISCVInstrFormats.td:

class RVInstR4<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins,
               string opcodestr, string argstr>
    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR4> {
  bits<5> rs3;
  bits<5> rs2;
  bits<5> rs1;
  bits<3> funct3;
  bits<5> rd;

  let Inst{31-27} = rs3;
  let Inst{26-25} = funct2;
  let Inst{24-20} = rs2;
  let Inst{19-15} = rs1;
  let Inst{14-12} = funct3;
  let Inst{11-7} = rd;
  let Opcode = opcode.Value;
}

any parameter passed as funct3 would be ignored.
I opted for a new class that allows to use funct3 as an extra opcode field too. It would be good to consider that for the original RVInstR4 too though.

[PaoloS]

Removed new line.

[PaoloS]

Update encodings to RISCV BitManip v0.92:

add the encodings of intstructions packu[w], packh, sext.b, sext.h,
update the encoding of instructions bfp[w] and bdep[w],
update tests accordingly.

[PaoloS]

Added empty scheduling descriptions, just to let it build with the upstream LLVM.

Added zext.* and sext.w pseudo instructions.

[simoncook]

Update Target Features to be of form zb<x> rather than just b<x>.

[simoncook]

(Actually update patch rather than rebase of previous version)

[simoncook]

llvm/lib/Target/RISCV/RISCV.td

102

This isn't doing what you want it to. This patch currently causes MC/RISCV/invalid-instruction-spellcheck.s to fail because of the lack of an AssemblyPredicate so the instruction is always enabled.

Unfortunately it looks like AsmPredicate doesn't support saying if Feature X or Y is enabled, and we can only compose them as needing X and Y on the Instruction definitions themselves. I couldn't find any other backend needing something like this, so it might be that we need a dummy SubtargetFeature, or teach TableGen that AsmPredicates can be composed in an or fashion instead.

[evandro]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

140

The more granular check (hasStdExtZbb()?) should be used here instead.

[simoncook]

• Update patch now AssemblerPredicate update has landed
• Add "experimental-" to all bitmanip SubtargetFeatures

[simoncook]

Address review comments and clang-format changes

[simoncook]

Address own feedback on RISCV.td and cpp files

[lewis-revill]

This looks good to me, as long as it covers the spec. Can you add more reviewers though?

[simoncook]

This is starting to look good. I've checked all the encodings, and other than c.zext.w having the wrong value all the encodings are right.

One thing I would consider is to make reviewing/future changes easier, I would define all the instructions in the order they appear in the Chapter 2.11 Opcode Encodings tables. This way, it will be easier to see for future revisions what has changed and make sure the encodings are up to date. This might end up with a few more let Predicates = directives, but we can rearrange and tidy this up when it is all ratified.

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

87

It seems like this is just RVInstR but with a opcode flag, but its only used with OPC_OP_IMM_32, can this just assume that opcode type and have a better name (assuming the opcode type makes sense)?

117

This looks like it mostly used for just the 'W' variants of instructions, in that case is this the most appropriate name if the opcode type is OPC_OP_32 by default? It seems for others you're doing the right thing and using ALU_rr as the class you derive from

119

remove {}

185

I don't know if splitting up the 12-bit immediate into a 7 and a 5 might make future maintenance of this easier, given that that's how its expressed int he manual?

185

I'm also unsure on the use of the opcode enum when it represents the wrong thing, I don't know if this causes some confusion, but we can see if anyone else has any comments here?

389

This block is missing C.NEG with funct2 01?

393

c.zext.w should have 10 as its funct2. Also zest -> zext

llvm/test/MC/RISCV/rv64bc-valid.s

14

zest -> zext

[asb]

In D65649#1931064, @simoncook wrote:

This is starting to look good. I've checked all the encodings, and other than c.zext.w having the wrong value all the encodings are right.

One thing I would consider is to make reviewing/future changes easier, I would define all the instructions in the order they appear in the Chapter 2.11 Opcode Encodings tables. This way, it will be easier to see for future revisions what has changed and make sure the encodings are up to date. This might end up with a few more let Predicates = directives, but we can rearrange and tidy this up when it is all ratified.

Strong +1 on this. Throughout the RISC-V backend we order the instruction definitions to match the order in the ISA manual, with codegen patterns listed separately in a more meaningful order. As Simon say, it can lead to a few more Predicates directives needed, but makes cross-referencing vs the spec _much_ easier.

[edward-jones]

Looks tidy and a really decent set of tests. I've added a few comments, though they are mainly me agreeing with Simon's points.

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

183

Do these properties need to be specified, or do the values match the values which would be inferred by TableGen anyway (since all the DAG patterns are empty)?

185

I would also recommend avoiding the opcode enum values. It implies a connection to the base instruction encodings which is entirely incidental, and the name is also misleading.

185

I also think it is worth matching the manual and splitting up the 12 bit encoding into separate 7 and 5 bit fields.

389

c.neg will need to be added to the tests too.

[PaoloS]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

87

Well, it is used by immediate instructions, so I think and indication of that should appear in the name. I wouldn't base it on RVInstR if that's what you meant. Anyway, in line with what you suggested about RVInstR I could call it ALU_ri_32, but ALU_ri uses a 12 bits immediate field, unlike the instructions using RVBInstImm5 that only use 5 bits immediates. So it's not just a matter of opcode but also of different fields. I could call it RVBInstShift32, as some of the 32 bit counterparts of such instructions use RVBInstShift. The problem is that instructions like GREVIW and GORCIW, or SBSETIW, SBCLRIW, SBINVIW have little to do with shifts. While SLOIW and SROIW have. At the time RVBInstImm5 seemed a good way to express the main difference of such template: the immediate operand bit width. I'll think about better names.

117

I could relate to ALU_rr with the name ALU_rr_32 or ALU_rr_w, just to specify the difference.

185

I agree. The explicit encoding would avoid some confusion here, even though the fact that this instruction uses the number OPC_OP_IMM for its opcode raises the clash between its immediate format and its "not immediate" usage. This might be subject to some adjustments once we move closer to have the encodings ratified.

185

Splitting the immediate field into fields of 7 and 5 fields seems interesting. I mean, I guess it could prove useful in the future. Never the less it can't be applied anyway to all those templates like RVBInstImm5, RVBInstImm6 and RVBInstImm7, as they expect one of the two fields to be used as an immediate operand. So yes, I could do it, but it applies anyway only to the instructions that use those 12 bits only for flags. Do you agree?

389

Correct. The compressed instructions seem outdated. I'll fix them.

[PaoloS]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

117

Never mind, I'll use ALUW_rr that was already available. Must have missed it.

389

Correction. Adding any of c.not, c.neg, c.zext.w or c.zext.d creates a decoding conflict with the current encoding of c.addi16sp, c.lui and c.lui (hint) already implemented in the C extension. In the current proposed encoding of the compressed instructions a decoding conflict is due. Since these instructions though are meant to be part of the C extensions, not the B extension I think it's better to leave them out of this patch. Once a definitive encoding will be defined for them they should be added with no problems to the C extension.

[PaoloS]

• Sorted the definitions of the instructions and the MC tests according to the order of the encodings in the manual.
• Improved the names of the instruction templates.
• Removed unused operand types and instruction templates.
• The features hasSideEffects, mayLoad and mayStore are now set only on the templates that need it.
• Renamed all the immediate parameters in the templates as 'shamt', for uniformity.
• Split the funct12 field of the unary instruction template into two fields of 7 and 5 bits. For conformity to the manual and for maintainability.
• Added a 4-bit immediate operand for the 32 bit shuffle.
• Added constraints on the size of the immediate operands.
• Added tests on the constraints of the immediate operands.
• Renamed most registers in the tests for uniformity.
• Removed the compressed instructions as they are still a proposal for the C extension and still cause encoding conflicts with the ones aready implemented there.
• Removed tests of compressed instructions.

[PaoloS]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

183

Yes they are needed. TableGen gives error if they are not specified.

[PaoloS]

• Added bitmanip compressed instructions.
• Added compressed instruction emission.
• Added mc tests.
• Added assembler predicate strings to B extension and subextensions.
• Fixed typos.
• Fixed the order of the single bit instructions.

[PaoloS]

Fixed obsolete comments.

[asb]

I'm reviewing this with an eye to merging it, but one big thing that comes to mind is the compressed instructions. The draft bitmanip spec describes these under "Future compressed instructions" and says "It presumably would make sense for a future revision of the “C” extension to include compressed opcodes for those instructions." My reading is that this is more of a sketch of potential encodings and a less firm proposal than the 32-bit encodings described elsewhere in the spec. Do you disagree with that assessment?

[edward-jones]

This looks good to me now.

[simoncook]

In D65649#1943742, @asb wrote:

I'm reviewing this with an eye to merging it, but one big thing that comes to mind is the compressed instructions. The draft bitmanip spec describes these under "Future compressed instructions" and says "It presumably would make sense for a future revision of the “C” extension to include compressed opcodes for those instructions." My reading is that this is more of a sketch of potential encodings and a less firm proposal than the 32-bit encodings described elsewhere in the spec. Do you disagree with that assessment?

This is one thing I've been discussing with Paolo a bit and I'm not 100% sure what the correct approach is here.

I agree, it seems more like a sketch of what they should be, but the mentioning of the size improvements suggested to me perhaps they should be, since evaluating the potential "what the final B extension should look like" it probably should be included. There is the question of where this should be enabled, my first thought (which this patch implements) is Zbb because it seemed the most logical, but maybe given the instructions stated state does another subextension make sense for its evaluation? These are all experimental so I think there's some leeway to some option, but I think it would be good to land it if we think people may be using it/want to evaluate it. I suspect there's many valid routes with this being experimental, we just need to choose one we have concensus around making sense. Perhaps a topic for today's call?

[asb]

Submitting the comments I have so far - need to continue going through in more detail.

llvm/lib/Target/RISCV/RISCV.td

118

Nit: indentation of this list seems arbitrary. I'd have that [ should be aligned with the first " on the line above?

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

2

Doesn't match the filename

10

This should probably say something like "This file describes the RISC-V instructions from the standard 'B' Bitmanip extension, version 0.92. This extension has not yet been ratified (meaning LLVM support is experimental)."

49

You're using a different style here than elsewhere in the backend, where we try to use the basic RISC-V formats as the superclass wherever possible (and where necessary, defining a subclass in RISCVInstrInfo*.td). RVBUnary for instance just seems to be an R-type instruction (albeit, one where the rs2 field is hard coded). Also, for the base instr format class we don't set hasSideEffects/mayLoad/mayStore (these are semantic details that aren't necessarily implied by the isntr format).

52

Should be InstFormatR?

[asb]

In D65649#1943856, @simoncook wrote:

I agree, it seems more like a sketch of what they should be, but the mentioning of the size improvements suggested to me perhaps they should be, since evaluating the potential "what the final B extension should look like" it probably should be included. There is the question of where this should be enabled, my first thought (which this patch implements) is Zbb because it seemed the most logical, but maybe given the instructions stated state does another subextension make sense for its evaluation? These are all experimental so I think there's some leeway to some option, but I think it would be good to land it if we think people may be using it/want to evaluate it. I suspect there's many valid routes with this being experimental, we just need to choose one we have concensus around making sense. Perhaps a topic for today's call?

Yes, let's discuss today. I agree there's value in making it easy to evaluate the compressed instructions too. My concern would be that people implementing experimental support in simulators or CPUs might skip over the section as more speculative, meaning that if we emitted those encodings those users might have a bad experience.

[PaoloS]

• Changed some instruction template classes so that they are not based directly on the basic RVInst.
• Changed the indentation where possible so that it fits in 80 columns.
• Fixed some obsolete comments.
• Added some runs to the Zbp tests.
• Fixed other indentation problems.

[asb]

I think we should land this and continue further development in-tree. There might be a few minor refactorings I want to propose after the fact, but these shouldn't block this going forwards.

LGTM. Thank you for all your work in putting this together and the care you've taken to do so in a way that matches the rest of the backend.

llvm/test/MC/RISCV/rvZbproposedc-invalid.s

1 ↗

(On Diff #253455)

Nit: should be "-mattr=+experimental-zbproposedc,+c" given that +experimental-b won't turn on the proposed C additions by itself.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

bool isUImm5NonZero() const {
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
     if (!isImm())
       return false;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     return IsConstantImm && isUInt<5>(Imm) && (Imm != 0) &&
            VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isUImm6() const {
+    if (!isImm())
+      return false;
+    RISCVMCExpr::VariantKind VK;
+    int64_t Imm;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && isUInt<6>(Imm) &&
+           VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
   bool isSImm6() const {
     if (!isImm())
       return false;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
     int64_t Imm;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     return IsConstantImm && isInt<6>(Imm) &&
            VK == RISCVMCExpr::VK_RISCV_None;
bool isCLUIImm() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     return IsConstantImm && (Imm != 0) &&
            (isUInt<5>(Imm) || (Imm >= 0xfffe0 && Imm <= 0xfffff)) &&
            VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isUImm7() const {
+    if (!isImm())
+      return false;
+    RISCVMCExpr::VariantKind VK;
+    int64_t Imm;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && isUInt<7>(Imm) &&
+           VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
   bool isUImm7Lsb00() const {
     if (!isImm())
       return false;
     int64_t Imm;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     return IsConstantImm && isShiftedUInt<5, 2>(Imm) &&
            VK == RISCVMCExpr::VK_RISCV_None;
if (isRV64())
       return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 6) - 1);
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
   case Match_InvalidUImmLog2XLenNonZero:
     if (isRV64())
       return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 6) - 1);
     return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1);
   case Match_InvalidUImm5:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
+  case Match_InvalidUImm6:
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 6) - 1);
   case Match_InvalidSImm6:
     return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 5),
                                       (1 << 5) - 1);
   case Match_InvalidSImm6NonZero:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, -(1 << 5), (1 << 5) - 1,
         "immediate must be non-zero in the range");
   case Match_InvalidCLUIImm:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, 1, (1 << 5) - 1,
         "immediate must be in [0xfffe0, 0xfffff] or");
+  case Match_InvalidUImm7:
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 7) - 1);
   case Match_InvalidUImm7Lsb00:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, 0, (1 << 7) - 4,
         "immediate must be a multiple of 4 bytes in the range");
   case Match_InvalidUImm8Lsb00:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, 0, (1 << 8) - 4,
         "immediate must be a multiple of 4 bytes in the range");

llvm/lib/Target/RISCV/RISCV.td

def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
                            AssemblerPredicate<"FeatureStdExtD">;
 
 def FeatureStdExtC
     : SubtargetFeature<"c", "HasStdExtC", "true",
                        "'C' (Compressed Instructions)">;
 def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
                            AssemblerPredicate<"FeatureStdExtC">;
 
+def FeatureExtZbb
+    : SubtargetFeature<"bb", "HasStdExtZbb", "true",
+                       "'Zbb' (Base Bit Manipulation Instructions)">;
+def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
+                           AssemblerPredicate<"FeatureExtZbb">;
+
+def FeatureExtZbc
+    : SubtargetFeature<"bc", "HasStdExtZbc", "true",
+                       "'Zbc' (Carry-Less Bit Manipulation Instructions)">;
+def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
+                           AssemblerPredicate<"FeatureExtZbc">;
+
+def FeatureExtZbe
+    : SubtargetFeature<"be", "HasStdExtZbe", "true",
+                       "'Zbe' (Extract-Deposit Bit Manipulation Instructions)">;
+def HasStdExtZbe : Predicate<"Subtarget->hasStdExtZbe()">,
+                           AssemblerPredicate<"FeatureExtZbe">;
+
+def FeatureExtZbf
+    : SubtargetFeature<"bf", "HasStdExtZbf", "true",
+                       "'Zbf' (Bit-Field Bit Manipulation Instructions)">;
+def HasStdExtZbf : Predicate<"Subtarget->hasStdExtZbf()">,
+                           AssemblerPredicate<"FeatureExtZbf">;
+
+def FeatureExtZbm
+    : SubtargetFeature<"bm", "HasStdExtZbm", "true",
+                       "'Zbm' (Matrix Bit Manipulation Instructions)">;
+def HasStdExtZbm : Predicate<"Subtarget->hasStdExtZbm()">,
+                           AssemblerPredicate<"FeatureExtZbm">;
+
+def FeatureExtZbp
+    : SubtargetFeature<"bp", "HasStdExtZbp", "true",
+                       "'Zbp' (Permutation Bit Manipulation Instructions)">;
+def HasStdExtZbp : Predicate<"Subtarget->hasStdExtZbp()">,
+                           AssemblerPredicate<"FeatureExtZbp">;
+
+def FeatureExtZbr
+    : SubtargetFeature<"br", "HasStdExtZbr", "true",
+                       "'Zbr' (Polynomial Reduction Bit Manipulation Instructions)">;
+def HasStdExtZbr : Predicate<"Subtarget->hasStdExtZbr()">,
+                           AssemblerPredicate<"FeatureExtZbr">;
+
+def FeatureExtZbs
+    : SubtargetFeature<"bs", "HasStdExtZbs", "true",
+                       "'Zbs' (Single-Bit Bit Manipulation Instructions)">;
+def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
+                           AssemblerPredicate<"FeatureExtZbs">;
+
+def FeatureExtZbt
+    : SubtargetFeature<"bt", "HasStdExtZbt", "true",
+                       "'Zbt' (Ternary Bit Manipulation Instructions)">;
+def HasStdExtZbt : Predicate<"Subtarget->hasStdExtZbt()">,
+                           AssemblerPredicate<"FeatureExtZbt">;
+
+// For instructions that belong to both the basic and the permutation subextensions.
+// They should be added if any of the two subextension has been specified.
+def HasStdExtZbbOrZbp
+    : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">;
+
+def FeatureStdExtB
+    : SubtargetFeature<"b", "HasStdExtB", "true",
+                       "'B' (Bit Manipulation Instructions)",
+                                [FeatureExtZbb,
+                                 FeatureExtZbc,
+                                 FeatureExtZbe,
+                                 FeatureExtZbf,
+                                 FeatureExtZbm,
+                                 FeatureExtZbp,
+                                 FeatureExtZbr,
+                                 FeatureExtZbs,
+                                 FeatureExtZbt]>;
+def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
+                           AssemblerPredicate<"FeatureStdExtB">;
+
 def FeatureRVCHints
     : SubtargetFeature<"rvc-hints", "EnableRVCHintInstrs", "true",
                        "Enable RVC Hint Instructions.">;
 def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
                             AssemblerPredicate<"FeatureRVCHints">;
 
 def Feature64Bit
     : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
   setOperationAction(ISD::SHL_PARTS, XLenVT, Custom);
   setOperationAction(ISD::SRL_PARTS, XLenVT, Custom);
   setOperationAction(ISD::SRA_PARTS, XLenVT, Custom);
 
   setOperationAction(ISD::ROTL, XLenVT, Expand);
   setOperationAction(ISD::ROTR, XLenVT, Expand);
   setOperationAction(ISD::BSWAP, XLenVT, Expand);
+
+  if(!Subtarget.hasStdExtB()) {
     setOperationAction(ISD::CTTZ, XLenVT, Expand);
     setOperationAction(ISD::CTLZ, XLenVT, Expand);
     setOperationAction(ISD::CTPOP, XLenVT, Expand);
+  }
 
   ISD::CondCode FPCCToExtend[] = {
       ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT,
       ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE, ISD::SETGT,
       ISD::SETGE,  ISD::SETNE};
 
   ISD::NodeType FPOpToExtend[] = {
       ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM};

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 // Standard extensions
 //===----------------------------------------------------------------------===//
 
 include "RISCVInstrInfoM.td"
 include "RISCVInstrInfoA.td"
 include "RISCVInstrInfoF.td"
 include "RISCVInstrInfoD.td"
 include "RISCVInstrInfoC.td"
+include "RISCVInstrInfoB.td"

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

+//===-- RISCVInstrFormatsB.td - RISCV B Instruction Formats --*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+//  This file describes the RISC-V B extension instruction formats.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+def uimm6 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<6>(Imm);}]> {
+  let ParserMatchClass = UImmAsmOperand<6>;
+  let DecoderMethod = "decodeUImmOperand<6>";
+}
+
+def uimm7 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<7>(Imm);}]> {
+  let ParserMatchClass = UImmAsmOperand<7>;
+  let DecoderMethod = "decodeUImmOperand<7>";
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+// These templates should be moved to RISCVInstrFormats.td once the B extension has
+// been ratified.
+
+class RVBInstShift<bits<5> funct5, bits<3> funct3, RISCVOpcode opcode,
+                   string opcodestr>
+    : RVInst<(outs GPR:$rd), (ins GPR:$rs1, uimm6:$imm6),
+             opcodestr, "$rd, $rs1, $imm6", [], InstFormatI> {
+  bits<5> rs1;
+  bits<6> imm6;
+  bits<5> rd;
+
+  let Inst{31-27} = funct5;
+  // NOTE: the shamt bit-field should be 7-bits long, but since that would cause
+  // decoding conflicts all the shift operations are encoded with op(26) = 0
+  // apart from funnel shifts FSL, FSR and FSRI that have op(26) = 1
+  let Inst{26} = 0;
+  let Inst{25-20} = imm6;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+}
+
+class RVBInstImm7<bits<5> funct5, bits<3> funct3, RISCVOpcode opcode,
+                    string opcodestr>
+    : RVInst<(outs GPR:$rd), (ins GPR:$rs1, uimm7:$imm7),
+             opcodestr, "$rd, $rs1, $imm7", [], InstFormatI> {
+  bits<5> rs1;
+  bits<7> imm7;
+  bits<5> rd;
+
+  let Inst{31-27} = funct5;
+  let Inst{26-20} = imm7;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+}
+
+class RVBInstImm6<bits<6> funct6, bits<3> funct3, RISCVOpcode opcode,
+                    string opcodestr>
+    : RVInst<(outs GPR:$rd), (ins GPR:$rs1, uimm6:$imm6),
+              opcodestr, "$rd, $rs1, $imm6", [], InstFormatI> {
+  bits<5> rs1;
+  bits<6> imm6;
+  bits<5> rd;
+
+  let Inst{31-26} = funct6;
+  let Inst{25-20} = imm6;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+}
+
+class RVBInstImm5<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode,
+                    string opcodestr>
+    : RVInst<(outs GPR:$rd), (ins GPR:$rs1, uimm5:$imm5),
+              opcodestr, "$rd, $rs1, $imm5", [], InstFormatI> {
+  bits<5> rs1;
+  bits<5> imm5;
+  bits<5> rd;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = imm5;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+}
+
+class RVBInstFunct12<bits<12> funct12, bits<3> funct3, RISCVOpcode opcode,
+                     string opcodestr>
+    : RVInst<(outs GPR:$rd), (ins GPR:$rs1),
+             opcodestr, "$rd, $rs1", [], InstFormatI> {
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-20} = funct12;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+}
+
+class RVBInstR<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_32, (outs GPR:$rd),
+              (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2"> {}
+
+class RVBInstR4Reg<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode,
+                   string opcodestr, string argstr>
+    : RVInst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, GPR:$rs3), opcodestr,
+             argstr, [], InstFormatR4> {
+  bits<5> rs3;
+  bits<5> rs2;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-27} = rs3;
+  let Inst{26-25} = funct2;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+}
+
+// Currently implemented only for one instruction FSRIW
+class RVBInstR4Imm<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode,
+                   string opcodestr>
+    : RVInst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs3, uimm5:$imm),
+             opcodestr, "$rd, $rs1, $rs3, $imm", [], InstFormatR4> {
+  bits<5> rs3;
+  bits<5> imm;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-27} = rs3;
+  let Inst{26-25} = funct2;
+  let Inst{24-20} = imm;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+}
+
+// Currently implemented only for one instruction FSRI
+class RVBInstR4Imm6<bit funct1, bits<3> funct3, RISCVOpcode opcode,
+                    string opcodestr>
+    : RVInst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs3, uimm5:$imm),
+             opcodestr, "$rd, $rs1, $rs3, $imm", [], InstFormatR4> {
+  bits<5> rs3;
+  bits<6> imm;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-27} = rs3;
+  let Inst{26} = funct1;
+  let Inst{25-20} = imm;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+// Base instructions
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+let Predicates = [HasStdExtZbb] in {
+  def CLZ  : RVBInstFunct12<0b011000000000, 0b001, OPC_OP_IMM, "clz">;
+  def CTZ  : RVBInstFunct12<0b011000000001, 0b001, OPC_OP_IMM, "ctz">;
+  def PCNT : RVBInstFunct12<0b011000000010, 0b001, OPC_OP_IMM, "pcnt">;
+
+  def SLO  : ALU_rr<0b0010000, 0b001, "slo">;
+  def SRO  : ALU_rr<0b0010000, 0b101, "sro">;
+  def SLOI : RVBInstShift<0b00100, 0b001, OPC_OP_IMM, "sloi">;
+  def SROI : RVBInstShift<0b00100, 0b101, OPC_OP_IMM, "sroi">;
+
+  def MIN  : ALU_rr<0b0000101, 0b100, "min">;
+  def MAX  : ALU_rr<0b0000101, 0b101, "max">;
+  def MINU : ALU_rr<0b0000101, 0b110, "minu">;
+  def MAXU : ALU_rr<0b0000101, 0b111, "maxu">;
+}
+
+let Predicates = [HasStdExtZbb, IsRV64] in {
+  def CLZW   : RVBInstFunct12<0b011000000000, 0b001, OPC_OP_IMM_32, "clzw">;
+  def CTZW   : RVBInstFunct12<0b011000000001, 0b001, OPC_OP_IMM_32, "ctzw">;
+  def PCNTW  : RVBInstFunct12<0b011000000010, 0b001, OPC_OP_IMM_32, "pcntw">;
+  def SLOW   : RVBInstR<0b0010000, 0b001, "slow">;
+  def SROW   : RVBInstR<0b0010000, 0b101, "srow">;
+  def SLOIW  : RVBInstImm5<0b0010000, 0b001, OPC_OP_IMM_32, "sloiw">;
+  def SROIW  : RVBInstImm5<0b0010000, 0b101, OPC_OP_IMM_32, "sroiw">;
+  def ADDIWU : RVInstI<0b100, OPC_OP_IMM_32, (outs GPR:$rd),
+                       (ins GPR:$rs1, simm12:$imm12),
+                       "addiwu", "$rd, $rs1, $imm12">;
+
+  def SLLIUW : RVBInstShift<0b00001, 0b001, OPC_OP_IMM_32, "slliu.w">;
+
+  def ADDWU : RVBInstR<0b0000101, 0b000, "addwu">;
+  def SUBWU : RVBInstR<0b0100101, 0b000, "subwu">;
+  def ADDUW : RVBInstR<0b0000100, 0b000, "addu.w">;
+  def SUBUW : RVBInstR<0b0100100, 0b000, "subu.w">;
+}
+
+// Carry-less instructions
+
+let Predicates = [HasStdExtZbc] in {
+  def CLMUL  : ALU_rr<0b0000101, 0b001, "clmul">;
+  def CLMULR : ALU_rr<0b0000101, 0b010, "clmulr">;
+  def CLMULH : ALU_rr<0b0000101, 0b011, "clmulh">;
+}
+
+let Predicates = [HasStdExtZbc, IsRV64] in {
+  def CLMULW  : RVBInstR<0b0000101, 0b001, "clmulw">;
+  def CLMULRW : RVBInstR<0b0000101, 0b010, "clmulrw">;
+  def CLMULHW : RVBInstR<0b0000101, 0b011, "clmulhw">;
+}
+
+// Extract-bit/Deposit-bit instructions
+
+let Predicates = [HasStdExtZbe] in {
+  def BDEP : ALU_rr<0b0000100, 0b010, "bdep">;
+  def BEXT : ALU_rr<0b0000100, 0b110, "bext">;
+}
+
+let Predicates = [HasStdExtZbe, IsRV64] in {
+  def BDEPW : RVBInstR<0b0000100, 0b010, "bdepw">;
+  def BEXTW : RVBInstR<0b0000100, 0b110, "bextw">;
+}
+
+// Bit-Field instructions
+
+let Predicates = [HasStdExtZbf] in {
+  def BFP : ALU_rr<0b0000100, 0b111, "bfp">;
+}
+
+let Predicates = [HasStdExtZbf, IsRV64] in {
+  def BFPW : RVBInstR<0b0000100, 0b111, "bfpw">;
+}
+
+// Matrix Instructions
+
+let Predicates = [HasStdExtZbm, IsRV64] in {
+  def BMATOR   : ALU_rr<0b0000100, 0b011, "bmator">;
+  def BMATXOR  : ALU_rr<0b0100100, 0b011, "bmatxor">;
+  def BMATFLIP : RVBInstFunct12<0b011000000011, 0b001, OPC_OP_IMM, "bmatflip">;
+}
+
+// Bit Permutations Instructions
+
+let Predicates = [HasStdExtZbbOrZbp] in {
+  def ANDN : ALU_rr<0b0100000, 0b111, "andn">;
+  def ORN  : ALU_rr<0b0100000, 0b110, "orn">;
+  def XNOR : ALU_rr<0b0100000, 0b100, "xnor">;
+  def PACK : ALU_rr<0b0000100, 0b100, "pack">;
+  def ROL  : ALU_rr<0b0110000, 0b001, "rol">;
+  def ROR  : ALU_rr<0b0110000, 0b101, "ror">;
+  def RORI : RVBInstImm7<0b01100, 0b101, OPC_OP_IMM, "rori">;
+}
+
+let Predicates = [HasStdExtZbp] in {
+  def GREV   : ALU_rr<0b0110100, 0b101, "grev">;
+  def GORC   : ALU_rr<0b0010100, 0b101, "gorc">;
+  def SHFL   : ALU_rr<0b0000100, 0b001, "shfl">;
+  def UNSHFL : ALU_rr<0b0000100, 0b101, "unshfl">;
+
+  // RVBInstShift sets inst[26] to 0. We use it here to avoid a decoding conflict with FSRI
+  def GREVI   : RVBInstShift<0b01101, 0b101, OPC_OP_IMM, "grevi">;
+  def GORCI   : RVBInstShift<0b00101, 0b101, OPC_OP_IMM, "gorci">;
+
+  def SHFLI   : RVBInstImm6<0b000010, 0b001, OPC_OP_IMM, "shfli">;
+  def UNSHFLI : RVBInstImm6<0b000010, 0b101, OPC_OP_IMM, "unshfli">;
+}
+
+let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
+  def ROLW  : RVBInstR<0b0110000, 0b001, "rolw">;
+  def RORW  : RVBInstR<0b0110000, 0b101, "rorw">;
+  def RORIW : RVBInstImm5<0b0110000, 0b101, OPC_OP_IMM_32, "roriw">;
+
+  def PACKW : RVBInstR<0b0000100, 0b100, "packw">;
+}
+
+let Predicates = [HasStdExtZbp, IsRV64] in {
+  def GREVW  : RVBInstR<0b0110100, 0b101, "grevw">;
+  def GORCW  : RVBInstR<0b0010100, 0b101, "gorcw">;
+  def GREVIW : RVBInstImm5<0b0110100, 0b101, OPC_OP_IMM_32, "greviw">;
+  def GORCIW : RVBInstImm5<0b0010100, 0b101, OPC_OP_IMM_32, "gorciw">;
+
+  def SHFLW   : RVBInstR<0b0000100, 0b001, "shflw">;
+  def UNSHFLW : RVBInstR<0b0000100, 0b101, "unshflw">;
+}
+
+// Polynomial Reduction Instructions
+
+let Predicates = [HasStdExtZbr] in {
+  def CRC32B : RVBInstFunct12<0b011000010000, 0b001, OPC_OP_IMM, "crc32.b">;
+  def CRC32H : RVBInstFunct12<0b011000010001, 0b001, OPC_OP_IMM, "crc32.h">;
+  def CRC32W : RVBInstFunct12<0b011000010010, 0b001, OPC_OP_IMM, "crc32.w">;
+
+  def CRC32CB : RVBInstFunct12<0b011000011000, 0b001, OPC_OP_IMM, "crc32c.b">;
+  def CRC32CH : RVBInstFunct12<0b011000011001, 0b001, OPC_OP_IMM, "crc32c.h">;
+  def CRC32CW : RVBInstFunct12<0b011000011010, 0b001, OPC_OP_IMM, "crc32c.w">;
+}
+
+let Predicates = [HasStdExtZbr, IsRV64] in {
+  def CRC32D  : RVBInstFunct12<0b011000010011, 0b001, OPC_OP_IMM, "crc32.d">;
+  def CRC32CD : RVBInstFunct12<0b011000011011, 0b001, OPC_OP_IMM, "crc32c.d">;
+}
+
+// Single Bit Instructions
+
+let Predicates = [HasStdExtZbs] in {
+  def SBSET : ALU_rr<0b0010100, 0b001, "sbset">;
+  def SBCLR : ALU_rr<0b0100100, 0b001, "sbclr">;
+  def SBINV : ALU_rr<0b0110100, 0b001, "sbinv">;
+  def SBEXT : ALU_rr<0b0100100, 0b101, "sbext">;
+
+  def SBSETI : RVBInstImm7<0b00101, 0b001, OPC_OP_IMM, "sbseti">;
+  def SBCLRI : RVBInstImm7<0b01001, 0b001, OPC_OP_IMM, "sbclri">;
+  def SBINVI : RVBInstImm7<0b01101, 0b001, OPC_OP_IMM, "sbinvi">;
+  def SBEXTI : RVBInstImm7<0b01001, 0b101, OPC_OP_IMM, "sbexti">;
+}
+
+let Predicates = [HasStdExtZbs, IsRV64] in {
+  def SBSETW : RVBInstR<0b0010100, 0b001, "sbsetw">;
+  def SBCLRW : RVBInstR<0b0100100, 0b001, "sbclrw">;
+  def SBINVW : RVBInstR<0b0110100, 0b001, "sbinvw">;
+  def SBEXTW : RVBInstR<0b0100100, 0b101, "sbextw">;
+
+  def SBSETIW : RVBInstImm5<0b0010100, 0b001, OPC_OP_IMM_32, "sbsetiw">;
+  def SBCLRIW : RVBInstImm5<0b0100100, 0b001, OPC_OP_IMM_32, "sbclriw">;
+  def SBINVIW : RVBInstImm5<0b0110100, 0b001, OPC_OP_IMM_32, "sbinviw">;
+}
+
+// Ternary Instructions
+
+let Predicates = [HasStdExtZbt] in {
+  def CMIX : RVBInstR4Reg<0b11, 0b001, OPC_OP, "cmix", "$rd, $rs2, $rs1, $rs3">;
+  def CMOV : RVBInstR4Reg<0b11, 0b101, OPC_OP, "cmov", "$rd, $rs2, $rs1, $rs3">;
+  def FSL  : RVBInstR4Reg<0b10, 0b001, OPC_OP, "fsl", "$rd, $rs1, $rs3, $rs2">;
+  def FSR  : RVBInstR4Reg<0b10, 0b101, OPC_OP, "fsr", "$rd, $rs1, $rs3, $rs2">;
+  def FSRI : RVBInstR4Imm6<0b1, 0b101, OPC_OP_IMM, "fsri">;
+}
+
+let Predicates = [HasStdExtZbt, IsRV64] in {
+  def FSLW  : RVBInstR4Reg<0b10, 0b001, OPC_OP_32, "fslw", "$rd, $rs1, $rs3, $rs2">;
+  def FSRW  : RVBInstR4Reg<0b10, 0b101, OPC_OP_32, "fsrw", "$rd, $rs1, $rs3, $rs2">;
+  def FSRIW : RVBInstR4Imm<0b10, 0b101, OPC_OP_IMM_32, "fsriw">;
+}
+
+//===----------------------------------------------------------------------===//
+// Future compressed instructions
+//===----------------------------------------------------------------------===//
+
+class RVBInstC<bits<2> funct2, string opcodestr>
+    : RVInst16<(outs GPR:$rs_wb), (ins GPR:$rs), opcodestr, "$rs", [],
+               InstFormatCR> {
+  bits<3> rs;
+  let Constraints = "$rs = $rs_wb";
+
+  let Inst{12-15} = 0b0110;
+  let Inst{10-11} = funct2;
+  let Inst{7-9} = rs;
+  let Inst{0-6} = 0b0000001;
+}
+
+let Predicates = [HasStdExtB, HasStdExtC] in {
+  def CNOT : RVBInstC<00, "c.not">;
+}
+
+let Predicates = [HasStdExtB, HasStdExtC, IsRV64] in {
+  def CZESTW : RVBInstC<01, "c.zest.w">;
+}
+}  // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+//===----------------------------------------------------------------------===//
+// Pseudo Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZbbOrZbp, IsRV32] in {
+  def : InstAlias<"rev $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11111)>;
+  def : InstAlias<"rev2 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11110)>;
+  def : InstAlias<"rev4 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11100)>;
+  def : InstAlias<"rev8 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11000)>;
+  def : InstAlias<"rev16 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b10000)>;
+
+  def : InstAlias<"orc $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11111)>;
+  def : InstAlias<"orc2 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11110)>;
+  def : InstAlias<"orc4 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11100)>;
+  def : InstAlias<"orc8 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11000)>;
+  def : InstAlias<"orc16 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b10000)>;
+
+  def : InstAlias<"zip $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1111)>;
+  def : InstAlias<"zip2 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1110)>;
+  def : InstAlias<"zip4 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1100)>;
+  def : InstAlias<"zip8 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1000)>;
+  def : InstAlias<"unzip $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1111)>;
+  def : InstAlias<"unzip2 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1110)>;
+  def : InstAlias<"unzip4 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1100)>;
+  def : InstAlias<"unzip8 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1000)>;
+}
+
+let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
+  def : InstAlias<"rev.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011111)>;
+  def : InstAlias<"rev2.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011110)>;
+  def : InstAlias<"rev4.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011100)>;
+  def : InstAlias<"rev8.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011000)>;
+  def : InstAlias<"rev16.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b010000)>;
+  def : InstAlias<"rev $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111111)>;
+  def : InstAlias<"rev2 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111110)>;
+  def : InstAlias<"rev4 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111100)>;
+  def : InstAlias<"rev8 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111000)>;
+  def : InstAlias<"rev16 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b110000)>;
+  def : InstAlias<"rev32 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b100000)>;
+
+  def : InstAlias<"orc.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011111)>;
+  def : InstAlias<"orc2.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011110)>;
+  def : InstAlias<"orc4.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011100)>;
+  def : InstAlias<"orc8.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011000)>;
+  def : InstAlias<"orc16.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b010000)>;
+  def : InstAlias<"orc $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111111)>;
+  def : InstAlias<"orc2 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111110)>;
+  def : InstAlias<"orc4 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111100)>;
+  def : InstAlias<"orc8 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111000)>;
+  def : InstAlias<"orc16 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b110000)>;
+  def : InstAlias<"orc32 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b100000)>;
+
+  def : InstAlias<"zip.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01111)>;
+  def : InstAlias<"zip2.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01110)>;
+  def : InstAlias<"zip4.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01100)>;
+  def : InstAlias<"zip8.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01000)>;
+  def : InstAlias<"unzip.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01111)>;
+  def : InstAlias<"unzip2.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01110)>;
+  def : InstAlias<"unzip4.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01100)>;
+  def : InstAlias<"unzip8.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01000)>;
+  def : InstAlias<"zip $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11111)>;
+  def : InstAlias<"zip2 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11110)>;
+  def : InstAlias<"zip4 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11100)>;
+  def : InstAlias<"zip8 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11000)>;
+  def : InstAlias<"zip16 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b10000)>;
+  def : InstAlias<"unzip $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11111)>;
+  def : InstAlias<"unzip2 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11110)>;
+  def : InstAlias<"unzip4 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11100)>;
+  def : InstAlias<"unzip8 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11000)>;
+  def : InstAlias<"unzip16 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b10000)>;
+}
+
+let Predicates = [HasStdExtZbbOrZbp] in {
+  def : InstAlias<"rev.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01111)>;
+  def : InstAlias<"rev.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00111)>;
+  def : InstAlias<"rev.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00011)>;
+  def : InstAlias<"rev.p $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00001)>;
+  def : InstAlias<"rev2.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01110)>;
+  def : InstAlias<"rev2.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00110)>;
+  def : InstAlias<"rev2.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00010)>;
+  def : InstAlias<"rev4.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01100)>;
+  def : InstAlias<"rev4.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00100)>;
+  def : InstAlias<"rev8.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01000)>;
+
+  def : InstAlias<"orc.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01111)>;
+  def : InstAlias<"orc.b $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00111)>;
+  def : InstAlias<"orc.n $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00011)>;
+  def : InstAlias<"orc.p $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00001)>;
+  def : InstAlias<"orc2.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01110)>;
+  def : InstAlias<"orc2.b $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00110)>;
+  def : InstAlias<"orc2.n $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00010)>;
+  def : InstAlias<"orc4.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01100)>;
+  def : InstAlias<"orc4.b $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00100)>;
+  def : InstAlias<"orc8.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01000)>;
+
+  def : InstAlias<"zip.h $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0111)>;
+  def : InstAlias<"zip.b $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0011)>;
+  def : InstAlias<"zip.n $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0001)>;
+  def : InstAlias<"zip2.h $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0110)>;
+  def : InstAlias<"zip2.b $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0010)>;
+  def : InstAlias<"zip4.h $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0100)>;
+  def : InstAlias<"unzip.h $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0111)>;
+  def : InstAlias<"unzip.b $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0011)>;
+  def : InstAlias<"unzip.n $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0001)>;
+  def : InstAlias<"unzip2.h $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0110)>;
+  def : InstAlias<"unzip2.b $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0010)>;
+  def : InstAlias<"unzip4.h $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0100)>;
+}

llvm/lib/Target/RISCV/RISCVSubtarget.h

 
 class RISCVSubtarget : public RISCVGenSubtargetInfo {
   virtual void anchor();
   bool HasStdExtM = false;
   bool HasStdExtA = false;
   bool HasStdExtF = false;
   bool HasStdExtD = false;
   bool HasStdExtC = false;
+  bool HasStdExtB = false;
+  bool HasStdExtZbb = false;
+  bool HasStdExtZbc = false;
+  bool HasStdExtZbe = false;
+  bool HasStdExtZbf = false;
+  bool HasStdExtZbm = false;
+  bool HasStdExtZbp = false;
+  bool HasStdExtZbr = false;
+  bool HasStdExtZbs = false;
+  bool HasStdExtZbt = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
   bool EnableRVCHintInstrs = false;
   unsigned XLen = 32;
   MVT XLenVT = MVT::i32;
   RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
   RISCVFrameLowering FrameLowering;
public:
   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
     return &TSInfo;
   }
   bool hasStdExtM() const { return HasStdExtM; }
   bool hasStdExtA() const { return HasStdExtA; }
   bool hasStdExtF() const { return HasStdExtF; }
   bool hasStdExtD() const { return HasStdExtD; }
   bool hasStdExtC() const { return HasStdExtC; }
+  bool hasStdExtB() const { return HasStdExtB; }
+  bool hasStdExtZbb() const { return HasStdExtZbb; }
+  bool hasStdExtZbc() const { return HasStdExtZbc; }
+  bool hasStdExtZbe() const { return HasStdExtZbe; }
+  bool hasStdExtZbf() const { return HasStdExtZbf; }
+  bool hasStdExtZbm() const { return HasStdExtZbm; }
+  bool hasStdExtZbp() const { return HasStdExtZbp; }
+  bool hasStdExtZbr() const { return HasStdExtZbr; }
+  bool hasStdExtZbs() const { return HasStdExtZbs; }
+  bool hasStdExtZbt() const { return HasStdExtZbt; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
   bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
   MVT getXLenVT() const { return XLenVT; }
   unsigned getXLen() const { return XLen; }
   RISCVABI::ABI getTargetABI() const { return TargetABI; }
 

llvm/test/MC/RISCV/rv32Zbb-invalid.s

+# RUN: not llvm-mc -triple riscv32 -mattr=+b,bb < %s 2>&1 | FileCheck %s
+
+# Too few operands
+slo s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sro s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sloi s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sroi s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too many operands
+clz s0, s1, s2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+# Too many operands
+ctz s0, s1, s2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+# Too many operands
+pcnt s0, s1, s2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+# Too few operands
+min s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+max s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+minu s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+maxu s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv32Zbb-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+bb -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+bb < %s \
+# RUN:     | llvm-objdump -mattr=+bb -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: slo t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x20]
+slo t0, t1, t2
+# CHECK-ASM-AND-OBJ: sro t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x20]
+sro t0, t1, t2
+# CHECK-ASM-AND-OBJ: sloi t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x20]
+sloi t0, t1, 0
+# CHECK-ASM-AND-OBJ: sroi t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x20]
+sroi t0, t1, 0
+# CHECK-ASM-AND-OBJ: clz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
+clz t0, t1
+# CHECK-ASM-AND-OBJ: ctz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x13,0x60]
+ctz t0, t1
+# CHECK-ASM-AND-OBJ: pcnt t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x23,0x60]
+pcnt t0, t1
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a]
+max t0, t1, t2
+# CHECK-ASM-AND-OBJ: minu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+minu t0, t1, t2
+# CHECK-ASM-AND-OBJ: maxu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x0a]
+maxu t0, t1, t2

llvm/test/MC/RISCV/rv32Zbbp-invalid.s

+# RUN: not llvm-mc -triple riscv32 -mattr=+b,bb,bp < %s 2>&1 | FileCheck %s
+
+# Too few operands
+andn s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+orn s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+xnor s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+rol s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+ror s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+rori s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+pack s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv32Zbbp-valid.s

+# With B extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip base extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+bb -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+bb < %s \
+# RUN:     | llvm-objdump -mattr=+bb -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip permutation extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+bp -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+bp < %s \
+# RUN:     | llvm-objdump -mattr=+bp -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: andn t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x40]
+andn t0, t1, t2
+# CHECK-ASM-AND-OBJ: orn t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x40]
+orn t0, t1, t2
+# CHECK-ASM-AND-OBJ: xnor t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x40]
+xnor t0, t1, t2
+# CHECK-ASM-AND-OBJ: rol t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x60]
+rol t0, t1, t2
+# CHECK-ASM-AND-OBJ: ror t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x60]
+ror t0, t1, t2
+# CHECK-ASM-AND-OBJ: rori t0, t1, 31
+# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x61]
+rori t0, t1, 31
+# CHECK-ASM-AND-OBJ: rori t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x60]
+rori t0, t1, 0
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2

llvm/test/MC/RISCV/rv32Zbc-invalid.s

+# RUN: not llvm-mc -triple riscv32 -mattr=+b,bc < %s 2>&1 | FileCheck %s
+
+# Too few operands
+clmul s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+clmulr s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+clmulh s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv32Zbc-valid.s

+# With B extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip carry-less multiply extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+bc -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+bc < %s \
+# RUN:     | llvm-objdump -mattr=+bc -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clmul t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x0a]
+clmul t0, t1, t2
+# CHECK-ASM-AND-OBJ: clmulr t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x22,0x73,0x0a]
+clmulr t0, t1, t2
+# CHECK-ASM-AND-OBJ: clmulh t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x32,0x73,0x0a]
+clmulh t0, t1, t2

llvm/test/MC/RISCV/rv32Zbe-invalid.s

+# RUN: not llvm-mc -triple riscv32 -mattr=+b,be < %s 2>&1 | FileCheck %s
+
+# Too few operands
+bdep s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+bext s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv32Zbe-valid.s

+# With B extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip extract/deposit extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+be -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+be < %s \
+# RUN:     | llvm-objdump -mattr=+be -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: bdep t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x22,0x73,0x08]
+bdep t0, t1, t2
+# CHECK-ASM-AND-OBJ: bext t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x08]
+bext t0, t1, t2

llvm/test/MC/RISCV/rv32Zbf-invalid.s

+# RUN: not llvm-mc -triple riscv32 -mattr=+b,bf < %s 2>&1 | FileCheck %s
+
+# Too few operands
+bfp s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv32Zbf-valid.s

+# With B extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bit-Field extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+bf -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+bf < %s \
+# RUN:     | llvm-objdump -mattr=+bf -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: bfp t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x08]
+bfp t0, t1, t2

llvm/test/MC/RISCV/rv32Zbp-invalid.s

+# RUN: not llvm-mc -triple riscv32 -mattr=+b,bp < %s 2>&1 | FileCheck %s
+
+# Too few operands
+grev s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+grevi s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+shfl s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+unshfl s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+shfli t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+unshfli t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv32Zbp-valid.s

+# With Bitmanip permutation extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+bp -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+bp < %s \
+# RUN:     | llvm-objdump -mattr=+bp -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: grev t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x68]
+grev t0, t1, t2
+# CHECK-ASM-AND-OBJ: gorc t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x28]
+gorc t0, t1, t2
+# CHECK-ASM-AND-OBJ: grevi t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x68]
+grevi t0, t1, 0
+# CHECK-ASM-AND-OBJ: gorci t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x28]
+gorci t0, t1, 0
+# CHECK-ASM-AND-OBJ: shfl t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x08]
+shfl t0, t1, t2
+# CHECK-ASM-AND-OBJ: unshfl t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x08]
+unshfl t0, t1, t2
+# CHECK-ASM-AND-OBJ: shfli t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x08]
+shfli t0, t1, 0
+# CHECK-ASM-AND-OBJ: unshfli t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x08]
+unshfli t0, t1, 0

llvm/test/MC/RISCV/rv32Zbr-invalid.s

+# RUN: not llvm-mc -triple riscv32 -mattr=+b,br < %s 2>&1 | FileCheck %s
+
+# Too many operands
+crc32.b s0, s1, s2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+# Too many operands
+crc32.h s0, s1, s2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+# Too many operands
+crc32.w s0, s1, s2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+# Too many operands
+crc32c.b s0, s1, s2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
+# Too many operands
+crc32c.h s0, s1, s2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
+# Too many operands
+crc32c.w s0, s1, s2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction

llvm/test/MC/RISCV/rv32Zbr-valid.s

+# With B extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip CRC extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+br -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+br < %s \
+# RUN:     | llvm-objdump -mattr=+br -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: crc32.b t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x61]
+crc32.b t0, t1
+# CHECK-ASM-AND-OBJ: crc32.h t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x13,0x61]
+crc32.h t0, t1
+# CHECK-ASM-AND-OBJ: crc32.w t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x23,0x61]
+crc32.w t0, t1
+# CHECK-ASM-AND-OBJ: crc32c.b t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x83,0x61]
+crc32c.b t0, t1
+# CHECK-ASM-AND-OBJ: crc32c.h t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x93,0x61]
+crc32c.h t0, t1
+# CHECK-ASM-AND-OBJ: crc32c.w t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0xa3,0x61]
+crc32c.w t0, t1

llvm/test/MC/RISCV/rv32Zbs-invalid.s

+# RUN: not llvm-mc -triple riscv32 -mattr=+b,bs < %s 2>&1 | FileCheck %s
+
+# Too few operands
+sbset s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbclr s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbinv s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbext s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbseti s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbclri s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbinvi s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbexti s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv32Zbs-valid.s

+# With B extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip single bit extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+bs -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+bs < %s \
+# RUN:     | llvm-objdump -mattr=+bs -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: sbset t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x28]
+sbset t0, t1, t2
+# CHECK-ASM-AND-OBJ: sbclr t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x48]
+sbclr t0, t1, t2
+# CHECK-ASM-AND-OBJ: sbinv t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x68]
+sbinv t0, t1, t2
+# CHECK-ASM-AND-OBJ: sbext t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x48]
+sbext t0, t1, t2
+# CHECK-ASM-AND-OBJ: sbseti t0, t1, 1
+# CHECK-ASM: encoding: [0x93,0x12,0x13,0x28]
+sbseti t0, t1, 1
+# CHECK-ASM-AND-OBJ: sbclri t0, t1, 1
+# CHECK-ASM: encoding: [0x93,0x12,0x13,0x48]
+sbclri t0, t1, 1
+# CHECK-ASM-AND-OBJ: sbinvi t0, t1, 1
+# CHECK-ASM: encoding: [0x93,0x12,0x13,0x68]
+sbinvi t0, t1, 1
+# CHECK-ASM-AND-OBJ: sbexti t0, t1, 1
+# CHECK-ASM: encoding: [0x93,0x52,0x13,0x48]
+sbexti t0, t1, 1

llvm/test/MC/RISCV/rv32Zbt-invalid.s

+# RUN: not llvm-mc -triple riscv32 -mattr=+b,bt < %s 2>&1 | FileCheck %s
+
+# Too few operands
+cmix s0, s1, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+cmov s0, s1, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+fsl s0, s1, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+fsr s0, s1, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv32Zbt-valid.s

+# With B extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip ternary extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+bt -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+bt < %s \
+# RUN:     | llvm-objdump -mattr=+bt -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
+# CHECK-ASM-AND-OBJ: cmov t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0xd2,0x63,0xe6]
+cmov t0, t1, t2, t3
+# CHECK-ASM-AND-OBJ: fsl t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x12,0xc3,0x3d]
+fsl t0, t1, t2, t3
+# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
+fsr t0, t1, t2, t3

llvm/test/MC/RISCV/rv32b-aliases-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -riscv-no-aliases \
+# RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+b \
+# RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+b < %s \
+# RUN:     | llvm-objdump -d -r -riscv-no-aliases -mattr=+b - \
+# RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+b < %s \
+# RUN:     | llvm-objdump -d -r -mattr=+b - \
+# RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# The following check prefixes are used in this test:
+# CHECK-S-OBJ            Match both the .s and objdumped object output with
+#                        aliases enabled
+# CHECK-S-OBJ-NOALIAS    Match both the .s and objdumped object output with
+#                        aliases disabled
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 31
+# CHECK-S-OBJ: rev t0, t1
+rev x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 15
+# CHECK-S-OBJ: rev.h t0, t1
+rev.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 7
+# CHECK-S-OBJ: rev.b t0, t1
+rev.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 3
+# CHECK-S-OBJ: rev.n t0, t1
+rev.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 1
+# CHECK-S-OBJ: rev.p t0, t1
+rev.p x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 30
+# CHECK-S-OBJ: rev2 t0, t1
+rev2 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 14
+# CHECK-S-OBJ: rev2.h t0, t1
+rev2.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 6
+# CHECK-S-OBJ: rev2.b t0, t1
+rev2.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 2
+# CHECK-S-OBJ: rev2.n t0, t1
+rev2.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 28
+# CHECK-S-OBJ: rev4 t0, t1
+rev4 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 12
+# CHECK-S-OBJ: rev4.h t0, t1
+rev4.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 4
+# CHECK-S-OBJ: rev4.b t0, t1
+rev4.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 24
+# CHECK-S-OBJ: rev8 t0, t1
+rev8 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 16
+# CHECK-S-OBJ: rev16 t0, t1
+rev16 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 31
+# CHECK-S-OBJ: orc t0, t1
+orc x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 15
+# CHECK-S-OBJ: orc.h t0, t1
+orc.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 7
+# CHECK-S-OBJ: orc.b t0, t1
+orc.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 3
+# CHECK-S-OBJ: orc.n t0, t1
+orc.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 1
+# CHECK-S-OBJ: orc.p t0, t1
+orc.p x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 30
+# CHECK-S-OBJ: orc2 t0, t1
+orc2 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 14
+# CHECK-S-OBJ: orc2.h t0, t1
+orc2.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 6
+# CHECK-S-OBJ: orc2.b t0, t1
+orc2.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 2
+# CHECK-S-OBJ: orc2.n t0, t1
+orc2.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 28
+# CHECK-S-OBJ: orc4 t0, t1
+orc4 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 12
+# CHECK-S-OBJ: orc4.h t0, t1
+orc4.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 4
+# CHECK-S-OBJ: orc4.b t0, t1
+orc4.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 24
+# CHECK-S-OBJ: orc8 t0, t1
+orc8 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 8
+# CHECK-S-OBJ: orc8.h t0, t1
+orc8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 16
+# CHECK-S-OBJ: orc16 t0, t1
+orc16 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 15
+# CHECK-S-OBJ: zip t0, t1
+zip x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 7
+# CHECK-S-OBJ: zip.h t0, t1
+zip.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 3
+# CHECK-S-OBJ: zip.b t0, t1
+zip.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 1
+# CHECK-S-OBJ: zip.n t0, t1
+zip.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 14
+# CHECK-S-OBJ: zip2 t0, t1
+zip2 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 6
+# CHECK-S-OBJ: zip2.h t0, t1
+zip2.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 2
+# CHECK-S-OBJ: zip2.b t0, t1
+zip2.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 12
+# CHECK-S-OBJ: zip4 t0, t1
+zip4 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 4
+# CHECK-S-OBJ: zip4.h t0, t1
+zip4.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 8
+# CHECK-S-OBJ: zip8 t0, t1
+zip8 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 15
+# CHECK-S-OBJ: unzip t0, t1
+unzip x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 7
+# CHECK-S-OBJ: unzip.h t0, t1
+unzip.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 3
+# CHECK-S-OBJ: unzip.b t0, t1
+unzip.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 1
+# CHECK-S-OBJ: unzip.n t0, t1
+unzip.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 14
+# CHECK-S-OBJ: unzip2 t0, t1
+unzip2 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 6
+# CHECK-S-OBJ: unzip2.h t0, t1
+unzip2.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 2
+# CHECK-S-OBJ: unzip2.b t0, t1
+unzip2.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 12
+# CHECK-S-OBJ: unzip4 t0, t1
+unzip4 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 4
+# CHECK-S-OBJ: unzip4.h t0, t1
+unzip4.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 8
+# CHECK-S-OBJ: unzip8 t0, t1
+unzip8 x5, x6

llvm/test/MC/RISCV/rv32bc-invalid.s

+# RUN: not llvm-mc -triple riscv32 -mattr=+b,c < %s 2>&1 | FileCheck %s
+
+# Too many operands
+c.not s0, s1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction

llvm/test/MC/RISCV/rv32bc-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+b,c -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b,c < %s \
+# RUN:     | llvm-objdump -mattr=+b,c -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: c.not t0
+# CHECK-ASM: encoding: [0xc0,0x62]
+c.not t0

llvm/test/MC/RISCV/rv64Zbb-invalid.s

+# RUN: not llvm-mc -triple riscv64 -mattr=+b,bb < %s 2>&1 | FileCheck %s
+
+# Too many operands
+clzw s0, s1, s2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+# Too many operands
+ctzw s0, s1, s2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+# Too many operands
+pcntw s0, s1, s2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+# Too few operands
+slow t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+srow t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sloiw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sroiw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+addiwu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+slliu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+addwu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+subwu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+addu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+subu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv64Zbb-valid.s

+# With B extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip base extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+bb -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+bb < %s \
+# RUN:     | llvm-objdump -mattr=+bb -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clzw t0, t1
+# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x60]
+clzw t0, t1
+# CHECK-ASM-AND-OBJ: ctzw t0, t1
+# CHECK-ASM: encoding: [0x9b,0x12,0x13,0x60]
+ctzw t0, t1
+# CHECK-ASM-AND-OBJ: pcntw t0, t1
+# CHECK-ASM: encoding: [0x9b,0x12,0x23,0x60]
+pcntw t0, t1
+# CHECK-ASM-AND-OBJ: slow t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x20]
+slow t0, t1, t2
+# CHECK-ASM-AND-OBJ: srow t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x20]
+srow t0, t1, t2
+# CHECK-ASM-AND-OBJ: sloiw t0, t1, 0
+# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x20]
+sloiw t0, t1, 0
+# CHECK-ASM-AND-OBJ: sroiw t0, t1, 0
+# CHECK-ASM: encoding: [0x9b,0x52,0x03,0x20]
+sroiw t0, t1, 0
+# CHECK-ASM-AND-OBJ: addiwu t0, t1, 0
+# CHECK-ASM: encoding: [0x9b,0x42,0x03,0x00]
+addiwu t0, t1, 0
+# CHECK-ASM-AND-OBJ: slliu.w t0, t1, 0
+# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x08]
+slliu.w t0, t1, 0
+# CHECK-ASM-AND-OBJ: addwu t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x0a]
+addwu t0, t1, t2
+# CHECK-ASM-AND-OBJ: subwu t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x4a]
+subwu t0, t1, t2
+# CHECK-ASM-AND-OBJ: addu.w t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x08]
+addu.w t0, t1, t2
+# CHECK-ASM-AND-OBJ: subu.w t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x48]
+subu.w t0, t1, t2

llvm/test/MC/RISCV/rv64Zbbp-invalid.s

+# RUN: not llvm-mc -triple riscv64 -mattr=+b,bb,bp < %s 2>&1 | FileCheck %s
+
+# Too few operands
+rolw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+rorw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+roriw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+packw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv64Zbbp-valid.s

+# With B extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip base extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+bb -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+bb < %s \
+# RUN:     | llvm-objdump -mattr=+bb -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip permutation extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+bp -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+bp < %s \
+# RUN:     | llvm-objdump -mattr=+bp -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: rolw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x60]
+rolw t0, t1, t2
+# CHECK-ASM-AND-OBJ: rorw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x60]
+rorw t0, t1, t2
+# CHECK-ASM-AND-OBJ: roriw t0, t1, 31
+# CHECK-ASM: encoding: [0x9b,0x52,0xf3,0x61]
+roriw t0, t1, 31
+# CHECK-ASM-AND-OBJ: roriw t0, t1, 0
+# CHECK-ASM: encoding: [0x9b,0x52,0x03,0x60]
+roriw t0, t1, 0
+# CHECK-ASM-AND-OBJ: packw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x42,0x73,0x08]
+packw t0, t1, t2

llvm/test/MC/RISCV/rv64Zbc-invalid.s

+# RUN: not llvm-mc -triple riscv64 -mattr=+b,bc < %s 2>&1 | FileCheck %s
+
+# Too few operands
+clmulw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+clmulrw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+clmulhw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv64Zbc-valid.s

+# With B extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip carry-less multiply extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+bc -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+bc < %s \
+# RUN:     | llvm-objdump -mattr=+bc -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clmulw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x0a]
+clmulw t0, t1, t2
+# CHECK-ASM-AND-OBJ: clmulrw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x22,0x73,0x0a]
+clmulrw t0, t1, t2
+# CHECK-ASM-AND-OBJ: clmulhw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x32,0x73,0x0a]
+clmulhw t0, t1, t2

llvm/test/MC/RISCV/rv64Zbe-invalid.s

+# RUN: not llvm-mc -triple riscv64 -mattr=+b,be < %s 2>&1 | FileCheck %s
+
+# Too few operands
+bdepw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+bextw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv64Zbe-valid.s

+# With B extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip extract/deposit extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+be -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+be < %s \
+# RUN:     | llvm-objdump -mattr=+be -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: bdepw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x22,0x73,0x08]
+bdepw t0, t1, t2
+# CHECK-ASM-AND-OBJ: bextw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x62,0x73,0x08]
+bextw t0, t1, t2

llvm/test/MC/RISCV/rv64Zbf-invalid.s

+# RUN: not llvm-mc -triple riscv64 -mattr=+b,bf < %s 2>&1 | FileCheck %s
+
+# Too few operands
+bfpw s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+

llvm/test/MC/RISCV/rv64Zbf-valid.s

+# With B extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bit-Field extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+bf -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+bf < %s \
+# RUN:     | llvm-objdump -mattr=+bf -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: bfpw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x72,0x73,0x08]
+bfpw t0, t1, t2

llvm/test/MC/RISCV/rv64Zbm-invalid.s

+# RUN: not llvm-mc -triple riscv64 -mattr=+b,bm < %s 2>&1 | FileCheck %s
+
+# Too few operands
+bmator s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+bmatxor s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too many operands
+bmatflip s0, s1, s2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction

llvm/test/MC/RISCV/rv64Zbm-valid.s

+# With B extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip matix extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+bm -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+bm < %s \
+# RUN:     | llvm-objdump -mattr=+bm -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: bmator t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x32,0x73,0x08]
+bmator t0, t1, t2
+# CHECK-ASM-AND-OBJ: bmatxor t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x32,0x73,0x48]
+bmatxor t0, t1, t2
+# CHECK-ASM-AND-OBJ: bmatflip t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x33,0x60]
+bmatflip t0, t1

llvm/test/MC/RISCV/rv64Zbp-invalid.s

+# RUN: not llvm-mc -triple riscv64 -mattr=+b,bp < %s 2>&1 | FileCheck %s
+
+# Too few operands
+grevw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+gorcw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+greviw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+gorciw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+shflw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+unshflw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv64Zbp-valid.s

+# With Bitmanip permutation extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+bp -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+bp < %s \
+# RUN:     | llvm-objdump -mattr=+bp -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: grevw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x68]
+grevw t0, t1, t2
+# CHECK-ASM-AND-OBJ: gorcw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x28]
+gorcw t0, t1, t2
+# CHECK-ASM-AND-OBJ: greviw t0, t1, 0
+# CHECK-ASM: encoding: [0x9b,0x52,0x03,0x68]
+greviw t0, t1, 0
+# CHECK-ASM-AND-OBJ: gorciw t0, t1, 0
+# CHECK-ASM: encoding: [0x9b,0x52,0x03,0x28]
+gorciw t0, t1, 0
+# CHECK-ASM-AND-OBJ: shflw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x08]
+shflw t0, t1, t2
+# CHECK-ASM-AND-OBJ: unshflw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x08]
+unshflw t0, t1, t2

llvm/test/MC/RISCV/rv64Zbr-invalid.s

+# RUN: not llvm-mc -triple riscv64 -mattr=+b,br < %s 2>&1 | FileCheck %s
+
+# Too many operands
+crc32.d s0, s1, s2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+# Too many operands
+crc32c.d s0, s1, s2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction

llvm/test/MC/RISCV/rv64Zbr-valid.s

+# With B extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip CRC extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+br -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+br < %s \
+# RUN:     | llvm-objdump -mattr=+br -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: crc32.d t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x33,0x61]
+crc32.d t0, t1
+# CHECK-ASM-AND-OBJ: crc32c.d t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0xb3,0x61]
+crc32c.d t0, t1

llvm/test/MC/RISCV/rv64Zbs-invalid.s

+# RUN: not llvm-mc -triple riscv64 -mattr=+b,bs < %s 2>&1 | FileCheck %s
+
+# Too few operands
+sbsetw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbclrw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbinvw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbextw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbsetiw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbclriw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbinviw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv64Zbs-valid.s

+# With B extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip single bit extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+bs -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+bs < %s \
+# RUN:     | llvm-objdump -mattr=+bs -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: sbsetw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x28]
+sbsetw t0, t1, t2
+# CHECK-ASM-AND-OBJ: sbclrw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x48]
+sbclrw t0, t1, t2
+# CHECK-ASM-AND-OBJ: sbinvw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x68]
+sbinvw t0, t1, t2
+# CHECK-ASM-AND-OBJ: sbextw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x48]
+sbextw t0, t1, t2
+# CHECK-ASM-AND-OBJ: sbsetiw  t0, t1, 0
+# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x28]
+sbsetiw t0, t1, 0
+# CHECK-ASM-AND-OBJ: sbclriw  t0, t1, 0
+# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x48]
+sbclriw t0, t1, 0
+# CHECK-ASM-AND-OBJ: sbinviw  t0, t1, 0
+# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x68]
+sbinviw t0, t1, 0

llvm/test/MC/RISCV/rv64Zbt-invalid.s

+# RUN: not llvm-mc -triple riscv64 -mattr=+b,bt < %s 2>&1 | FileCheck %s
+
+# Too few operands
+fslw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+fsrw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv64Zbt-valid.s

+# With B extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip ternary extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+bt -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+bt < %s \
+# RUN:     | llvm-objdump -mattr=+bt -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: fslw t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x12,0xc3,0x3d]
+fslw t0, t1, t2, t3
+# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
+fsrw t0, t1, t2, t3

llvm/test/MC/RISCV/rv64b-aliases-valid.s

+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -riscv-no-aliases \
+# RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s  -triple=riscv64 -mattr=+b \
+# RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -d -r -riscv-no-aliases -mattr=+b - \
+# RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -d -r -mattr=+b - \
+# RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# The following check prefixes are used in this test:
+# CHECK-S-OBJ            Match both the .s and objdumped object output with
+#                        aliases enabled
+# CHECK-S-OBJ-NOALIAS    Match both the .s and objdumped object output with
+#                        aliases disabled
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 63
+# CHECK-S-OBJ: rev t0, t1
+rev x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 31
+# CHECK-S-OBJ: rev.w t0, t1
+rev.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 15
+# CHECK-S-OBJ: rev.h t0, t1
+rev.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 7
+# CHECK-S-OBJ: rev.b t0, t1
+rev.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 3
+# CHECK-S-OBJ: rev.n t0, t1
+rev.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 1
+# CHECK-S-OBJ: rev.p t0, t1
+rev.p x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 62
+# CHECK-S-OBJ: rev2 t0, t1
+rev2 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 30
+# CHECK-S-OBJ: rev2.w t0, t1
+rev2.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 14
+# CHECK-S-OBJ: rev2.h t0, t1
+rev2.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 6
+# CHECK-S-OBJ: rev2.b t0, t1
+rev2.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 2
+# CHECK-S-OBJ: rev2.n t0, t1
+rev2.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 60
+# CHECK-S-OBJ: rev4 t0, t1
+rev4 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 28
+# CHECK-S-OBJ: rev4.w t0, t1
+rev4.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 12
+# CHECK-S-OBJ: rev4.h t0, t1
+rev4.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 4
+# CHECK-S-OBJ: rev4.b t0, t1
+rev4.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 56
+# CHECK-S-OBJ: rev8 t0, t1
+rev8 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 24
+# CHECK-S-OBJ: rev8.w t0, t1
+rev8.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 48
+# CHECK-S-OBJ: rev16 t0, t1
+rev16 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 16
+# CHECK-S-OBJ: rev16.w t0, t1
+rev16.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 32
+# CHECK-S-OBJ: rev32 t0, t1
+rev32 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 63
+# CHECK-S-OBJ: orc t0, t1
+orc x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 31
+# CHECK-S-OBJ: orc.w t0, t1
+orc.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 15
+# CHECK-S-OBJ: orc.h t0, t1
+orc.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 7
+# CHECK-S-OBJ: orc.b t0, t1
+orc.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 3
+# CHECK-S-OBJ: orc.n t0, t1
+orc.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 1
+# CHECK-S-OBJ: orc.p t0, t1
+orc.p x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 62
+# CHECK-S-OBJ: orc2 t0, t1
+orc2 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 30
+# CHECK-S-OBJ: orc2.w t0, t1
+orc2.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 14
+# CHECK-S-OBJ: orc2.h t0, t1
+orc2.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 6
+# CHECK-S-OBJ: orc2.b t0, t1
+orc2.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 2
+# CHECK-S-OBJ: orc2.n t0, t1
+orc2.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 60
+# CHECK-S-OBJ: orc4 t0, t1
+orc4 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 28
+# CHECK-S-OBJ: orc4.w t0, t1
+orc4.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 12
+# CHECK-S-OBJ: orc4.h t0, t1
+orc4.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 4
+# CHECK-S-OBJ: orc4.b t0, t1
+orc4.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 56
+# CHECK-S-OBJ: orc8 t0, t1
+orc8 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 24
+# CHECK-S-OBJ: orc8.w t0, t1
+orc8.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 8
+# CHECK-S-OBJ: orc8.h t0, t1
+orc8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 48
+# CHECK-S-OBJ: orc16 t0, t1
+orc16 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 16
+# CHECK-S-OBJ: orc16.w t0, t1
+orc16.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 32
+# CHECK-S-OBJ: orc32 t0, t1
+orc32 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 31
+# CHECK-S-OBJ: zip t0, t1
+zip x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 15
+# CHECK-S-OBJ: zip.w t0, t1
+zip.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 7
+# CHECK-S-OBJ: zip.h t0, t1
+zip.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 3
+# CHECK-S-OBJ: zip.b t0, t1
+zip.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 1
+# CHECK-S-OBJ: zip.n t0, t1
+zip.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 30
+# CHECK-S-OBJ: zip2 t0, t1
+zip2 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 14
+# CHECK-S-OBJ: zip2.w t0, t1
+zip2.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 6
+# CHECK-S-OBJ: zip2.h t0, t1
+zip2.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 2
+# CHECK-S-OBJ: zip2.b t0, t1
+zip2.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 28
+# CHECK-S-OBJ: zip4 t0, t1
+zip4 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 12
+# CHECK-S-OBJ: zip4.w t0, t1
+zip4.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 4
+# CHECK-S-OBJ: zip4.h t0, t1
+zip4.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 24
+# CHECK-S-OBJ: zip8 t0, t1
+zip8 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 8
+# CHECK-S-OBJ: zip8.w t0, t1
+zip8.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 16
+# CHECK-S-OBJ: zip16 t0, t1
+zip16 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 31
+# CHECK-S-OBJ: unzip t0, t1
+unzip x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 15
+# CHECK-S-OBJ: unzip.w t0, t1
+unzip.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 7
+# CHECK-S-OBJ: unzip.h t0, t1
+unzip.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 3
+# CHECK-S-OBJ: unzip.b t0, t1
+unzip.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 1
+# CHECK-S-OBJ: unzip.n t0, t1
+unzip.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 30
+# CHECK-S-OBJ: unzip2 t0, t1
+unzip2 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 14
+# CHECK-S-OBJ: unzip2.w t0, t1
+unzip2.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 6
+# CHECK-S-OBJ: unzip2.h t0, t1
+unzip2.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 2
+# CHECK-S-OBJ: unzip2.b t0, t1
+unzip2.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 28
+# CHECK-S-OBJ: unzip4 t0, t1
+unzip4 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 12
+# CHECK-S-OBJ: unzip4.w t0, t1
+unzip4.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 4
+# CHECK-S-OBJ: unzip4.h t0, t1
+unzip4.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 24
+# CHECK-S-OBJ: unzip8 t0, t1
+unzip8 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 8
+# CHECK-S-OBJ: unzip8.w t0, t1
+unzip8.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 16
+# CHECK-S-OBJ: unzip16 t0, t1
+unzip16 x5, x6

llvm/test/MC/RISCV/rv64bc-invalid.s

+# RUN: not llvm-mc -triple riscv64 -mattr=+b,c < %s 2>&1 | FileCheck %s
+
+# Too many operands
+c.not t0, t1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+# Too many operands
+c.zest.w t0, t1 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction

llvm/test/MC/RISCV/rv64bc-valid.s

+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b,c -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b,c < %s \
+# RUN:     | llvm-objdump -mattr=+b,c -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: c.not t0
+# CHECK-ASM: encoding: [0xc0,0x62]
+c.not t0
+
+# CHECK-ASM-AND-OBJ: c.zest.w t0
+# CHECK-ASM: encoding: [0xc0,0x6a]
+c.zest.w t0