[RISCV] Support negative constants in CompressInstEmitter

[simoncook]

Summary

Some compressed instructions match against negative values; store
immediates as a signed value such that these patterns will now match
the intended instructions.

[simoncook]

Context for this patch: it's needed for CompressPats for bitmanip - since one of the compressed instructions should match against -1

[asb]

I was thinking about making it clearer why this cast is necessary. The first thought was obviously to add a comment to explain (similar to the comment in your review description). But maybe there's an argument for adding a small helper? Although it would literally just be doing a cast, it's name and description should make it much clearer what is going on. I don't feel super strongly about that approach though - so do speak up if you disagree!

[simoncook]

Actually solve the underlying problem.

Contrary to my original description, it is not TableGen that stores immediates as unsigned values, but the OpData structure. We are implicitly casting all immediates from signed to unsigned values. By correcting the type and removing that implicit cast, no explicit cast is needed later on.

[asb]

This is a much simpler fix! Looks good to me.

[apazos]

To clarify, we were not missing in compressed instructions before, this change is for the future compressed instructions to be added, confirmed? Otherwise I need to check why we missed it with the fuzzer.

[simoncook]

In D76767#1970892, @apazos wrote:

To clarify, we were not missing in compressed instructions before, this change is for the future compressed instructions to be added, confirmed? Otherwise I need to check why we missed it with the fuzzer.

Yes, this only became a thing because one of the bitmanip proposed/wishlist compressed instructions wants to match against -1, all the currently ratified instructions either match immediate 0 or greater, so this wouldn't have come up before.

llvm/utils/TableGen/RISCVCompressInstEmitter.cpp

 
 namespace {
 class RISCVCompressInstEmitter {
   struct OpData {
     enum MapKind { Operand, Imm, Reg };
     MapKind Kind;
     union {
       unsigned Operand; // Operand number mapped to.
-      uint64_t Imm;     // Integer immediate value.
+      int64_t Imm;      // Integer immediate value.
       Record *Reg;      // Physical register.
     } Data;
     int TiedOpIdx = -1; // Tied operand index within the instruction.
   };
   struct CompressPat {
     CodeGenInstruction Source; // The source instruction definition.
     CodeGenInstruction Dest;   // The destination instruction to transform to.
     std::vector<Record *>