[MC] Use local MCSubtargetInfo in writeNops

[peter.smith]

Summary

On some architectures such as Arm and X86 the encoding for a nop may change depending on the subtarget in operation at the time of encoding. This change replaces the per module MCSubtargetInfo retained by the targets AsmBackend in favour of passing through the local MCSubtargetInfo in operation at the time.

On Arm using the architectural NOP instruction can have a performance benefit on some implementations.

For Arm I've deleted the copy of the AsmBackend's MCSubtargetInfo to limit the chances of this causing problems in the future. I've not done this for other targets such as X86 as there is more frequent use of the MCSubtargetInfo and it looks to be for stable properties that we would not expect to vary per function in the way that an Arm NOP might.

I've attempted to take into account the in tree experimental backends.

This patch depends on D45961

[peter.smith]

Rebased [NFC]

[peter.smith]

Rebased, and added support for WebAssembly and RiscV as my default build configuration didn't include them at the time. No other changes.

[efriedma]

LGTM, assuming it rebases cleanly

lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h

22 ↗

(On Diff #173707)

isThumbMode should probably be using the ThumbMode bit of MCSubtargetInfo... but I'm not sure we're actually updating that at the moment. Probably okay to leave it for a followup.

[MaskRay]

lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

348 ↗

(On Diff #173707)

STI->

[peter.smith]

Thanks for the review. I've just got back from vacation and I'm a bit behind. Will rebase this and D45961 hopefully by the end of this week. I'll post it here and will give a heads up if there are any meaningful changes.

[peter.smith]

In D45962#2919645, @peter.smith wrote:

Thanks for the review. I've just got back from vacation and I'm a bit behind. Will rebase this and D45961 hopefully by the end of this week. I'll post it here and will give a heads up if there are any meaningful changes.

Will be early next week. I've rebased D45962 which this depends on.

[peter.smith]

In D45962#2931626, @peter.smith wrote:

In D45962#2919645, @peter.smith wrote:

Thanks for the review. I've just got back from vacation and I'm a bit behind. Will rebase this and D45961 hopefully by the end of this week. I'll post it here and will give a heads up if there are any meaningful changes.

Will be early next week. I've rebased D45962 which this depends on.

I've just had a quick go at rebasing and there is a bit more work than I bargained for. The X86 backend has introduced a couple more MCFragments that will need adapting

• MCBoundaryAlignFragment
• MCNopsFragment

I think I can pass STI through to these wihtout any ill effect but I'd like to submit these as individual patches for review as I don't know X86 well.

The X86 backend has used its per-target STI for some other things as well, so I won't be able to remove it in this patch.

ETA for this will be Friday afternoon (doing this in spare time).

[peter.smith]

Rebased (quite a lot) to account for a couple of years of changes.

I've included the changes to the two new x86 specific MCFragments MCNopsFragment and MCBoundaryAlignFragment that also call emitNops. I can split these changes out if needed but I thought it better to show the magnitude of the change in one go.

As mentioned in D45961 an alternative, less disruptive implementation (the Arm backend does not use MCNopsFragment or MCBoundaryAlignFragment) is to permit the MCSubtargetInfo to be nullptr which would mean retaining the STI in the Arm MCAsmBackend and a test in emitNops() to see if the STI passed in where nullptr.

[peter.smith]

Minor rebase NFC from previous patch. As this + previous rebase was quite a substantial update from the previous patch I'd ideally like a second opinion on whether this is still OK before I commit it and D45961 .

[MaskRay]

LGTM.

[peter.smith]

Rebase, and fix up DWARFExpressionCopyBytesTest.cpp

[peter.smith]

Fixup comments in MCFragment.h to look like D45961 and update patch manually as I'm not sure arc diff did the right thing.

[MaskRay]

llvm/test/CodeGen/ARM/subtarget-align.ll

1

< and -o - can be omitted.

llvm/test/MC/ARM/subtarget-nop.s

1

< and -o - can be omitted.

[peter.smith]

Thanks will apply comments prior to commit.

[mstorsjo]

This broke llvm-ml for assembling real-world files:

$ bin/llvm-ml -D_M_IA32 -DOMPT_SUPPORT=0 -c -Fo out.obj ../../openmp/runtime/src/z_Windows_NT-586_asm.asm
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
Stack dump:
0.      Program arguments: bin/llvm-ml -D_M_IA32 -DOMPT_SUPPORT=0 -c -Fo out.obj ../../openmp/runtime/src/z_Windows_NT-586_asm.asm
 #0 0x000055f22ac9ab1c llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) /home/martin/code/llvm-project/llvm/build-debug/../lib/Support/Unix/Signals.inc:565:0
 #1 0x000055f22ac9abd3 PrintStackTraceSignalHandler(void*) /home/martin/code/llvm-project/llvm/build-debug/../lib/Support/Unix/Signals.inc:632:0
 #2 0x000055f22ac98887 llvm::sys::RunSignalHandlers() /home/martin/code/llvm-project/llvm/build-debug/../lib/Support/Signals.cpp:97:0
 #3 0x000055f22ac9a49d SignalHandler(int) /home/martin/code/llvm-project/llvm/build-debug/../lib/Support/Unix/Signals.inc:407:0
 #4 0x00007f0ff42e3980 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x12980)
 #5 0x000055f22a777efc llvm::FeatureBitset::operator[](unsigned int) const /home/martin/code/llvm-project/llvm/build-debug/../include/llvm/MC/SubtargetFeature.h:87:0
 #6 0x000055f22a920116 (anonymous namespace)::X86AsmBackend::writeNopData(llvm::raw_ostream&, unsigned long, llvm::MCSubtargetInfo const*) const /home/martin/code/llvm-project/llvm/build-debug/../lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp:1145:0
 #7 0x000055f22a9fb58b writeFragment(llvm::raw_ostream&, llvm::MCAssembler const&, llvm::MCAsmLayout const&, llvm::MCFragment const&) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCAssembler.cpp:548:0
 #8 0x000055f22a9fc778 llvm::MCAssembler::writeSectionData(llvm::raw_ostream&, llvm::MCSection const*, llvm::MCAsmLayout const&) const /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCAssembler.cpp:780:0
 #9 0x000055f22aad17fd (anonymous namespace)::WinCOFFObjectWriter::writeSectionContents(llvm::MCAssembler&, llvm::MCAsmLayout const&, llvm::MCSection const&) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/WinCOFFObjectWriter.cpp:614:0
#10 0x000055f22aad1965 (anonymous namespace)::WinCOFFObjectWriter::writeSection(llvm::MCAssembler&, llvm::MCAsmLayout const&, (anonymous namespace)::COFFSection const&, llvm::MCSection const&) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/WinCOFFObjectWriter.cpp:635:0
#11 0x000055f22aad4363 (anonymous namespace)::WinCOFFObjectWriter::writeObject(llvm::MCAssembler&, llvm::MCAsmLayout const&) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/WinCOFFObjectWriter.cpp:1152:0
#12 0x000055f22a9fd579 llvm::MCAssembler::Finish() /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCAssembler.cpp:937:0
#13 0x000055f22aa68b5e llvm::MCObjectStreamer::finishImpl() /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCObjectStreamer.cpp:888:0
#14 0x000055f22aa9eaca llvm::MCWinCOFFStreamer::finishImpl() /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCWinCOFFStreamer.cpp:368:0
#15 0x000055f22a916966 (anonymous namespace)::X86WinCOFFStreamer::finishImpl() /home/martin/code/llvm-project/llvm/build-debug/../lib/Target/X86/MCTargetDesc/X86WinCOFFStreamer.cpp:65:0
#16 0x000055f22aa89d3c llvm::MCStreamer::Finish(llvm::SMLoc) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCStreamer.cpp:1005:0
#17 0x000055f22ab53df0 (anonymous namespace)::MasmParser::Run(bool, bool) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCParser/MasmParser.cpp:1435:0
#18 0x000055f22a701374 AssembleInput(llvm::StringRef, llvm::Target const*, llvm::SourceMgr&, llvm::MCContext&, llvm::MCStreamer&, llvm::MCAsmInfo&, llvm::MCSubtargetInfo&, llvm::MCInstrInfo&, llvm::MCTargetOptions&, llvm::opt::ArgList const&) /home/martin/code/llvm-project/llvm/build-debug/../tools/llvm-ml/llvm-ml.cpp:186:0
#19 0x000055f22a703135 main /home/martin/code/llvm-project/llvm/build-debug/../tools/llvm-ml/llvm-ml.cpp:433:0

@epastor Apparently it would be good with a llvm-ml specific testcase that triggers writing nops.

[peter.smith]

In D45962#2988712, @mstorsjo wrote:

This broke llvm-ml for assembling real-world files:

$ bin/llvm-ml -D_M_IA32 -DOMPT_SUPPORT=0 -c -Fo out.obj ../../openmp/runtime/src/z_Windows_NT-586_asm.asm
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
Stack dump:
0.      Program arguments: bin/llvm-ml -D_M_IA32 -DOMPT_SUPPORT=0 -c -Fo out.obj ../../openmp/runtime/src/z_Windows_NT-586_asm.asm
 #0 0x000055f22ac9ab1c llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) /home/martin/code/llvm-project/llvm/build-debug/../lib/Support/Unix/Signals.inc:565:0
 #1 0x000055f22ac9abd3 PrintStackTraceSignalHandler(void*) /home/martin/code/llvm-project/llvm/build-debug/../lib/Support/Unix/Signals.inc:632:0
 #2 0x000055f22ac98887 llvm::sys::RunSignalHandlers() /home/martin/code/llvm-project/llvm/build-debug/../lib/Support/Signals.cpp:97:0
 #3 0x000055f22ac9a49d SignalHandler(int) /home/martin/code/llvm-project/llvm/build-debug/../lib/Support/Unix/Signals.inc:407:0
 #4 0x00007f0ff42e3980 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x12980)
 #5 0x000055f22a777efc llvm::FeatureBitset::operator[](unsigned int) const /home/martin/code/llvm-project/llvm/build-debug/../include/llvm/MC/SubtargetFeature.h:87:0
 #6 0x000055f22a920116 (anonymous namespace)::X86AsmBackend::writeNopData(llvm::raw_ostream&, unsigned long, llvm::MCSubtargetInfo const*) const /home/martin/code/llvm-project/llvm/build-debug/../lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp:1145:0
 #7 0x000055f22a9fb58b writeFragment(llvm::raw_ostream&, llvm::MCAssembler const&, llvm::MCAsmLayout const&, llvm::MCFragment const&) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCAssembler.cpp:548:0
 #8 0x000055f22a9fc778 llvm::MCAssembler::writeSectionData(llvm::raw_ostream&, llvm::MCSection const*, llvm::MCAsmLayout const&) const /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCAssembler.cpp:780:0
 #9 0x000055f22aad17fd (anonymous namespace)::WinCOFFObjectWriter::writeSectionContents(llvm::MCAssembler&, llvm::MCAsmLayout const&, llvm::MCSection const&) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/WinCOFFObjectWriter.cpp:614:0
#10 0x000055f22aad1965 (anonymous namespace)::WinCOFFObjectWriter::writeSection(llvm::MCAssembler&, llvm::MCAsmLayout const&, (anonymous namespace)::COFFSection const&, llvm::MCSection const&) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/WinCOFFObjectWriter.cpp:635:0
#11 0x000055f22aad4363 (anonymous namespace)::WinCOFFObjectWriter::writeObject(llvm::MCAssembler&, llvm::MCAsmLayout const&) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/WinCOFFObjectWriter.cpp:1152:0
#12 0x000055f22a9fd579 llvm::MCAssembler::Finish() /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCAssembler.cpp:937:0
#13 0x000055f22aa68b5e llvm::MCObjectStreamer::finishImpl() /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCObjectStreamer.cpp:888:0
#14 0x000055f22aa9eaca llvm::MCWinCOFFStreamer::finishImpl() /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCWinCOFFStreamer.cpp:368:0
#15 0x000055f22a916966 (anonymous namespace)::X86WinCOFFStreamer::finishImpl() /home/martin/code/llvm-project/llvm/build-debug/../lib/Target/X86/MCTargetDesc/X86WinCOFFStreamer.cpp:65:0
#16 0x000055f22aa89d3c llvm::MCStreamer::Finish(llvm::SMLoc) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCStreamer.cpp:1005:0
#17 0x000055f22ab53df0 (anonymous namespace)::MasmParser::Run(bool, bool) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCParser/MasmParser.cpp:1435:0
#18 0x000055f22a701374 AssembleInput(llvm::StringRef, llvm::Target const*, llvm::SourceMgr&, llvm::MCContext&, llvm::MCStreamer&, llvm::MCAsmInfo&, llvm::MCSubtargetInfo&, llvm::MCInstrInfo&, llvm::MCTargetOptions&, llvm::opt::ArgList const&) /home/martin/code/llvm-project/llvm/build-debug/../tools/llvm-ml/llvm-ml.cpp:186:0
#19 0x000055f22a703135 main /home/martin/code/llvm-project/llvm/build-debug/../tools/llvm-ml/llvm-ml.cpp:433:0

@epastor Apparently it would be good with a llvm-ml specific testcase that triggers writing nops.

My apologies, will take a look. If I can spot the problem early I'll fix, otherwise will need to revert as it may be Friday before I can spend a lot of time on it.

[peter.smith]

Created D109425 to fix. This is the smallest change I can make in the time I've got this morning. Looks like this only got through because of an unfortunate default parameter. We might be able to prevent that by changing to a const reference.

llvm/include/llvm/MC/MCAsmBackend.h

public:
   /// Return true if this target allows an unrelaxable instruction to be
   /// emitted into RelaxableFragment and then we can increase its size in a
   /// tricky way for optimization.
   virtual bool allowEnhancedRelaxation() const { return false; }
 
   /// Give the target a chance to manipulate state related to instruction
   /// alignment (e.g. padding for optimization), instruction relaxablility, etc.
   /// before and after actually emitting the instruction.
-  virtual void emitInstructionBegin(MCObjectStreamer &OS, const MCInst &Inst) {}
+  virtual void emitInstructionBegin(MCObjectStreamer &OS, const MCInst &Inst,
+                                    const MCSubtargetInfo &STI) {}
   virtual void emitInstructionEnd(MCObjectStreamer &OS, const MCInst &Inst) {}
 
   /// lifetime management
   virtual void reset() {}
 
   /// Create a new MCObjectWriter instance for use by the assembler backend to
   /// emit the final object file.
   std::unique_ptr<MCObjectWriter>
public:
   /// Returns the minimum size of a nop in bytes on this target. The assembler
   /// will use this to emit excess padding in situations where the padding
   /// required for simple alignment would be less than the minimum nop size.
   ///
   virtual unsigned getMinimumNopSize() const { return 1; }
 
   /// Returns the maximum size of a nop in bytes on this target.
   ///
-  virtual unsigned getMaximumNopSize() const { return 0; }
+  virtual unsigned getMaximumNopSize(const MCSubtargetInfo &STI) const {
+    return 0;
+  }
 
   /// Write an (optimal) nop sequence of Count bytes to the given output. If the
   /// target cannot generate such a sequence, it should return an error.
   ///
   /// \return - True on success.
-  virtual bool writeNopData(raw_ostream &OS, uint64_t Count) const = 0;
+  virtual bool writeNopData(raw_ostream &OS, uint64_t Count,
+                            const MCSubtargetInfo *STI) const = 0;
 
   /// Give backend an opportunity to finish layout after relaxation
   virtual void finishLayout(MCAssembler const &Asm,
                             MCAsmLayout &Layout) const {}
 
   /// Handle any target-specific assembler flags. By default, do nothing.
   virtual void handleAssemblerFlag(MCAssemblerFlag Flag) {}
 

llvm/include/llvm/MC/MCFragment.h

class MCNopsFragment : public MCFragment {
   /// The number of bytes to insert.
   int64_t Size;
   /// Maximum number of bytes allowed in each NOP instruction.
   int64_t ControlledNopLength;
 
   /// Source location of the directive that this fragment was created for.
   SMLoc Loc;
 
+  /// When emitting Nops some subtargets have specific nop encodings.
+  const MCSubtargetInfo &STI;
+
 public:
   MCNopsFragment(int64_t NumBytes, int64_t ControlledNopLength, SMLoc L,
-                 MCSection *Sec = nullptr)
+                 const MCSubtargetInfo &STI, MCSection *Sec = nullptr)
       : MCFragment(FT_Nops, false, Sec), Size(NumBytes),
-        ControlledNopLength(ControlledNopLength), Loc(L) {}
+        ControlledNopLength(ControlledNopLength), Loc(L), STI(STI) {}
 
   int64_t getNumBytes() const { return Size; }
   int64_t getControlledNopLength() const { return ControlledNopLength; }
 
   SMLoc getLoc() const { return Loc; }
 
+  const MCSubtargetInfo *getSubtargetInfo() const { return &STI; }
+
   static bool classof(const MCFragment *F) {
     return F->getKind() == MCFragment::FT_Nops;
   }
 };
 
 class MCOrgFragment : public MCFragment {
   /// Value to use for filling bytes.
   int8_t Value;
class MCBoundaryAlignFragment : public MCFragment {
   /// The alignment requirement of the branch to be aligned.
   Align AlignBoundary;
   /// The last fragment in the set of fragments to be aligned.
   const MCFragment *LastFragment = nullptr;
   /// The size of the fragment.  The size is lazily set during relaxation, and
   /// is not meaningful before that.
   uint64_t Size = 0;
 
+  /// When emitting Nops some subtargets have specific nop encodings.
+  const MCSubtargetInfo &STI;
+
 public:
-  MCBoundaryAlignFragment(Align AlignBoundary, MCSection *Sec = nullptr)
-      : MCFragment(FT_BoundaryAlign, false, Sec), AlignBoundary(AlignBoundary) {
-  }
+  MCBoundaryAlignFragment(Align AlignBoundary, const MCSubtargetInfo &STI,
+                          MCSection *Sec = nullptr)
+      : MCFragment(FT_BoundaryAlign, false, Sec), AlignBoundary(AlignBoundary),
+        STI(STI) {}
 
   uint64_t getSize() const { return Size; }
   void setSize(uint64_t Value) { Size = Value; }
 
   Align getAlignment() const { return AlignBoundary; }
   void setAlignment(Align Value) { AlignBoundary = Value; }
 
   const MCFragment *getLastFragment() const { return LastFragment; }
   void setLastFragment(const MCFragment *F) {
     assert(!F || getParent() == F->getParent());
     LastFragment = F;
   }
 
+  const MCSubtargetInfo *getSubtargetInfo() const { return &STI; }
+
   static bool classof(const MCFragment *F) {
     return F->getKind() == MCFragment::FT_BoundaryAlign;
   }
 };
 
 class MCPseudoProbeAddrFragment : public MCEncodedFragmentWithFixups<8, 1> {
   /// The expression for the difference of the two symbols that
   /// make up the address delta between two .pseudoprobe directives.

llvm/include/llvm/MC/MCObjectStreamer.h

public:
   Optional<std::pair<bool, std::string>>
   emitRelocDirective(const MCExpr &Offset, StringRef Name, const MCExpr *Expr,
                      SMLoc Loc, const MCSubtargetInfo &STI) override;
   using MCStreamer::emitFill;
   void emitFill(const MCExpr &NumBytes, uint64_t FillValue,
                 SMLoc Loc = SMLoc()) override;
   void emitFill(const MCExpr &NumValues, int64_t Size, int64_t Expr,
                 SMLoc Loc = SMLoc()) override;
-  void emitNops(int64_t NumBytes, int64_t ControlledNopLength,
-                SMLoc Loc) override;
+  void emitNops(int64_t NumBytes, int64_t ControlledNopLength, SMLoc Loc,
+                const MCSubtargetInfo &STI) override;
   void emitFileDirective(StringRef Filename) override;
   void emitFileDirective(StringRef Filename, StringRef CompilerVerion,
                          StringRef TimeStamp, StringRef Description) override;
 
   void emitAddrsig() override;
   void emitAddrsigSym(const MCSymbol *Sym) override;
 
   void finishImpl() override;

llvm/include/llvm/MC/MCStreamer.h

public:
   ///
   /// \param NumValues - The number of copies of \p Size bytes to emit.
   /// \param Size - The size (in bytes) of each repeated value.
   /// \param Expr - The expression from which \p Size bytes are used.
   virtual void emitFill(const MCExpr &NumValues, int64_t Size, int64_t Expr,
                         SMLoc Loc = SMLoc());
 
   virtual void emitNops(int64_t NumBytes, int64_t ControlledNopLength,
-                        SMLoc Loc);
+                        SMLoc Loc, const MCSubtargetInfo& STI);
 
   /// Emit NumBytes worth of zeros.
   /// This function properly handles data in virtual sections.
   void emitZeros(uint64_t NumBytes);
 
   /// Emit some number of copies of \p Value until the byte alignment \p
   /// ByteAlignment is reached.
   ///

llvm/lib/MC/MCAssembler.cpp

void MCAssembler::writeFragmentPadding(raw_ostream &OS,
   unsigned BundlePadding = EF.getBundlePadding();
   if (BundlePadding > 0) {
     assert(isBundlingEnabled() &&
            "Writing bundle padding with disabled bundling");
     assert(EF.hasInstructions() &&
            "Writing bundle padding for a fragment without instructions");
 
     unsigned TotalLength = BundlePadding + static_cast<unsigned>(FSize);
+    const MCSubtargetInfo *STI = EF.getSubtargetInfo();
     if (EF.alignToBundleEnd() && TotalLength > getBundleAlignSize()) {
       // If the padding itself crosses a bundle boundary, it must be emitted
       // in 2 pieces, since even nop instructions must not cross boundaries.
       //             v--------------v   <- BundleAlignSize
       //        v---------v             <- BundlePadding
       // ----------------------------
       // | Prev |####|####|    F    |
       // ----------------------------
       //        ^-------------------^   <- TotalLength
       unsigned DistanceToBoundary = TotalLength - getBundleAlignSize();
-      if (!getBackend().writeNopData(OS, DistanceToBoundary))
+      if (!getBackend().writeNopData(OS, DistanceToBoundary, STI))
         report_fatal_error("unable to write NOP sequence of " +
                            Twine(DistanceToBoundary) + " bytes");
       BundlePadding -= DistanceToBoundary;
     }
-    if (!getBackend().writeNopData(OS, BundlePadding))
+    if (!getBackend().writeNopData(OS, BundlePadding, STI))
       report_fatal_error("unable to write NOP sequence of " +
                          Twine(BundlePadding) + " bytes");
   }
 }
 
 /// Write the fragment \p F to the output file.
 static void writeFragment(raw_ostream &OS, const MCAssembler &Asm,
                           const MCAsmLayout &Layout, const MCFragment &F) {
if (Count * AF.getValueSize() != FragmentSize)
                         "' is not a divisor of padding size '" +
                         Twine(FragmentSize) + "'");
 
     // See if we are aligning with nops, and if so do that first to try to fill
     // the Count bytes.  Then if that did not fill any bytes or there are any
     // bytes left to fill use the Value and ValueSize to fill the rest.
     // If we are aligning with nops, ask that target to emit the right data.
     if (AF.hasEmitNops()) {
-      if (!Asm.getBackend().writeNopData(OS, Count))
+      if (!Asm.getBackend().writeNopData(OS, Count, AF.getSubtargetInfo()))
         report_fatal_error("unable to write nop sequence of " +
                           Twine(Count) + " bytes");
       break;
     }
 
     // Otherwise, write out in multiples of the value size.
     for (uint64_t i = 0; i != Count; ++i) {
       switch (AF.getValueSize()) {
case MCFragment::FT_Fill: {
     if (TrailingCount)
       OS.write(Data, TrailingCount);
     break;
   }
 
   case MCFragment::FT_Nops: {
     ++stats::EmittedNopsFragments;
     const MCNopsFragment &NF = cast<MCNopsFragment>(F);
+
     int64_t NumBytes = NF.getNumBytes();
     int64_t ControlledNopLength = NF.getControlledNopLength();
-    int64_t MaximumNopLength = Asm.getBackend().getMaximumNopSize();
+    int64_t MaximumNopLength =
+        Asm.getBackend().getMaximumNopSize(*NF.getSubtargetInfo());
 
     assert(NumBytes > 0 && "Expected positive NOPs fragment size");
     assert(ControlledNopLength >= 0 && "Expected non-negative NOP size");
 
     if (ControlledNopLength > MaximumNopLength) {
       Asm.getContext().reportError(NF.getLoc(),
                                    "illegal NOP size " +
                                        std::to_string(ControlledNopLength) +
                                        ". (expected within [0, " +
                                        std::to_string(MaximumNopLength) + "])");
       // Clamp the NOP length as reportError does not stop the execution
       // immediately.
       ControlledNopLength = MaximumNopLength;
     }
 
     // Use maximum value if the size of each NOP is not specified
     if (!ControlledNopLength)
       ControlledNopLength = MaximumNopLength;
 
     while (NumBytes) {
       uint64_t NumBytesToEmit =
           (uint64_t)std::min(NumBytes, ControlledNopLength);
       assert(NumBytesToEmit && "try to emit empty NOP instruction");
-      if (!Asm.getBackend().writeNopData(OS, NumBytesToEmit)) {
+      if (!Asm.getBackend().writeNopData(OS, NumBytesToEmit,
+                                         NF.getSubtargetInfo())) {
         report_fatal_error("unable to write nop sequence of the remaining " +
                            Twine(NumBytesToEmit) + " bytes");
         break;
       }
       NumBytes -= NumBytesToEmit;
     }
     break;
   }
 
   case MCFragment::FT_LEB: {
     const MCLEBFragment &LF = cast<MCLEBFragment>(F);
     OS << LF.getContents();
     break;
   }
 
   case MCFragment::FT_BoundaryAlign: {
-    if (!Asm.getBackend().writeNopData(OS, FragmentSize))
+    const MCBoundaryAlignFragment &BF = cast<MCBoundaryAlignFragment>(F);
+    if (!Asm.getBackend().writeNopData(OS, FragmentSize, BF.getSubtargetInfo()))
       report_fatal_error("unable to write nop sequence of " +
                          Twine(FragmentSize) + " bytes");
     break;
   }
 
   case MCFragment::FT_SymbolId: {
     const MCSymbolIdFragment &SF = cast<MCSymbolIdFragment>(F);
     support::endian::write<uint32_t>(OS, SF.getSymbol()->getIndex(), Endian);

llvm/lib/MC/MCObjectStreamer.cpp

void MCObjectStreamer::emitInstruction(const MCInst &Inst,
                                        const MCSubtargetInfo &STI) {
   const MCSection &Sec = *getCurrentSectionOnly();
   if (Sec.isVirtualSection()) {
     getContext().reportError(Inst.getLoc(), Twine(Sec.getVirtualSectionKind()) +
                                                 " section '" + Sec.getName() +
                                                 "' cannot have instructions");
     return;
   }
-  getAssembler().getBackend().emitInstructionBegin(*this, Inst);
+  getAssembler().getBackend().emitInstructionBegin(*this, Inst, STI);
   emitInstructionImpl(Inst, STI);
   getAssembler().getBackend().emitInstructionEnd(*this, Inst);
 }
 
 void MCObjectStreamer::emitInstructionImpl(const MCInst &Inst,
                                            const MCSubtargetInfo &STI) {
   MCStreamer::emitInstruction(Inst, STI);
 
void MCObjectStreamer::emitFill(const MCExpr &NumValues, int64_t Size,
   MCDataFragment *DF = getOrCreateDataFragment();
   flushPendingLabels(DF, DF->getContents().size());
 
   assert(getCurrentSectionOnly() && "need a section");
   insert(new MCFillFragment(Expr, Size, NumValues, Loc));
 }
 
 void MCObjectStreamer::emitNops(int64_t NumBytes, int64_t ControlledNopLength,
-                                SMLoc Loc) {
+                                SMLoc Loc, const MCSubtargetInfo &STI) {
   // Emit an NOP fragment.
   MCDataFragment *DF = getOrCreateDataFragment();
   flushPendingLabels(DF, DF->getContents().size());
 
   assert(getCurrentSectionOnly() && "need a section");
-  insert(new MCNopsFragment(NumBytes, ControlledNopLength, Loc));
+
+  insert(new MCNopsFragment(NumBytes, ControlledNopLength, Loc, STI));
 }
 
 void MCObjectStreamer::emitFileDirective(StringRef Filename) {
   getAssembler().addFileName(Filename);
 }
 
 void MCObjectStreamer::emitFileDirective(StringRef Filename,
                                          StringRef CompilerVerion,

llvm/lib/MC/MCStreamer.cpp

 
 /// Emit NumBytes bytes worth of the value specified by FillValue.
 /// This implements directives such as '.space'.
 void MCStreamer::emitFill(uint64_t NumBytes, uint8_t FillValue) {
   emitFill(*MCConstantExpr::create(NumBytes, getContext()), FillValue);
 }
 
 void llvm::MCStreamer::emitNops(int64_t NumBytes, int64_t ControlledNopLen,
-                                llvm::SMLoc) {}
+                                llvm::SMLoc, const MCSubtargetInfo& STI) {}
 
 /// The implementation in this class just redirects to emitFill.
 void MCStreamer::emitZeros(uint64_t NumBytes) { emitFill(NumBytes, 0); }
 
 Expected<unsigned>
 MCStreamer::tryEmitDwarfFileDirective(unsigned FileNo, StringRef Directory,
                                       StringRef Filename,
                                       Optional<MD5::MD5Result> Checksum,

llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp

void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
                   uint64_t Value, bool IsResolved,
                   const MCSubtargetInfo *STI) const override;
 
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override;
   void relaxInstruction(MCInst &Inst,
                         const MCSubtargetInfo &STI) const override;
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 
   unsigned getFixupKindContainereSizeInBytes(unsigned Kind) const;
 
   bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
                              const MCValue &Target) override;
 };
 
 } // end anonymous namespace
bool AArch64AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
   return int64_t(Value) != int64_t(int8_t(Value));
 }
 
 void AArch64AsmBackend::relaxInstruction(MCInst &Inst,
                                          const MCSubtargetInfo &STI) const {
   llvm_unreachable("AArch64AsmBackend::relaxInstruction() unimplemented");
 }
 
-bool AArch64AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+bool AArch64AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                     const MCSubtargetInfo *STI) const {
   // If the count is not 4-byte aligned, we must be writing data into the text
   // section (otherwise we have unaligned instructions, and thus have far
   // bigger problems), so just write zeros instead.
   OS.write_zeros(Count % 4);
 
   // We are properly aligned, so write NOPs as requested.
   Count /= 4;
   for (uint64_t i = 0; i != Count; ++i)

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

public:
 
   void relaxInstruction(MCInst &Inst,
                         const MCSubtargetInfo &STI) const override;
 
   bool mayNeedRelaxation(const MCInst &Inst,
                          const MCSubtargetInfo &STI) const override;
 
   unsigned getMinimumNopSize() const override;
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
 };
 
 } //End anonymous namespace
 
 void AMDGPUAsmBackend::relaxInstruction(MCInst &Inst,
                                         const MCSubtargetInfo &STI) const {
const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
 
   return Infos[Kind - FirstTargetFixupKind];
 }
 
 unsigned AMDGPUAsmBackend::getMinimumNopSize() const {
   return 4;
 }
 
-bool AMDGPUAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+bool AMDGPUAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                    const MCSubtargetInfo *STI) const {
   // If the count is not 4-byte aligned, we must be writing data into the text
   // section (otherwise we have unaligned instructions, and thus have far
   // bigger problems), so just write zeros instead.
   OS.write_zeros(Count % 4);
 
   // We are properly aligned, so write NOPs as requested.
   Count /= 4;
 

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h

 #include "MCTargetDesc/ARMMCTargetDesc.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/TargetRegistry.h"
 
 namespace llvm {
 
 class ARMAsmBackend : public MCAsmBackend {
-  // The STI from the target triple the MCAsmBackend was instantiated with
-  // note that MCFragments may have a different local STI that should be
-  // used in preference.
-  const MCSubtargetInfo &STI;
   bool isThumbMode;    // Currently emitting Thumb code.
 public:
-  ARMAsmBackend(const Target &T, const MCSubtargetInfo &STI,
-                support::endianness Endian)
-      : MCAsmBackend(Endian), STI(STI),
-        isThumbMode(STI.getTargetTriple().isThumb()) {}
+  ARMAsmBackend(const Target &T, bool isThumb, support::endianness Endian)
+      : MCAsmBackend(Endian), isThumbMode(isThumb) {}
 
   unsigned getNumFixupKinds() const override {
     return ARM::NumTargetFixupKinds;
   }
 
-  // FIXME: this should be calculated per fragment as the STI may be
-  // different.
-  bool hasNOP() const { return STI.getFeatureBits()[ARM::HasV6T2Ops]; }
+  bool hasNOP(const MCSubtargetInfo *STI) const {
+    return STI->getFeatureBits()[ARM::HasV6T2Ops];
+  }
 
   Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
 
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
 
   bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
                              const MCValue &Target) override;
 
public:
 
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override;
 
   void relaxInstruction(MCInst &Inst,
                         const MCSubtargetInfo &STI) const override;
 
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 
   void handleAssemblerFlag(MCAssemblerFlag Flag) override;
 
   unsigned getPointerSize() const { return 4; }
   bool isThumb() const { return isThumbMode; }
   void setIsThumb(bool it) { isThumbMode = it; }
 };
 } // end namespace llvm
 
 #endif

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

 public:
   ARMELFObjectWriter(uint8_t OSABI)
       : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
                                 /*HasRelocationAddend*/ false) {}
 };
 } // end anonymous namespace
 
 Optional<MCFixupKind> ARMAsmBackend::getFixupKind(StringRef Name) const {
-  if (!STI.getTargetTriple().isOSBinFormatELF())
-    return None;
+}
 
+Optional<MCFixupKind> ARMAsmBackendELF::getFixupKind(StringRef Name) const {
   unsigned Type = llvm::StringSwitch<unsigned>(Name)
 #define ELF_RELOC(X, Y) .Case(#X, Y)
 #include "llvm/BinaryFormat/ELFRelocs/ARM.def"
 #undef ELF_RELOC
                       .Case("BFD_RELOC_NONE", ELF::R_ARM_NONE)
                       .Case("BFD_RELOC_8", ELF::R_ARM_ABS8)
                       .Case("BFD_RELOC_16", ELF::R_ARM_ABS16)
                       .Case("BFD_RELOC_32", ELF::R_ARM_ABS32)
if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
     return;
   }
 
   // The rest of instructions we're relaxing have the same operands.
   // We just need to update to the proper opcode.
   Inst.setOpcode(RelaxedOp);
 }
 
-bool ARMAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+bool ARMAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                 const MCSubtargetInfo *STI) const {
   const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
   const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
   const uint32_t ARMv4_NopEncoding = 0xe1a00000;   // using MOV r0,r0
   const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
   if (isThumb()) {
     const uint16_t nopEncoding =
-        hasNOP() ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding;
+        hasNOP(STI) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding;
     uint64_t NumNops = Count / 2;
     for (uint64_t i = 0; i != NumNops; ++i)
       support::endian::write(OS, nopEncoding, Endian);
     if (Count & 1)
       OS << '\0';
     return true;
   }
   // ARM mode
   const uint32_t nopEncoding =
-      hasNOP() ? ARMv6T2_NopEncoding : ARMv4_NopEncoding;
+      hasNOP(STI) ? ARMv6T2_NopEncoding : ARMv4_NopEncoding;
   uint64_t NumNops = Count / 4;
   for (uint64_t i = 0; i != NumNops; ++i)
     support::endian::write(OS, nopEncoding, Endian);
   // FIXME: should this function return false when unable to write exactly
   // 'Count' bytes with NOP encodings?
   switch (Count % 4) {
   default:
     break; // No leftover bytes to write
static MCAsmBackend *createARMAsmBackend(const Target &T,
   const Triple &TheTriple = STI.getTargetTriple();
   switch (TheTriple.getObjectFormat()) {
   default:
     llvm_unreachable("unsupported object format");
   case Triple::MachO:
     return new ARMAsmBackendDarwin(T, STI, MRI);
   case Triple::COFF:
     assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
-    return new ARMAsmBackendWinCOFF(T, STI);
+    return new ARMAsmBackendWinCOFF(T, STI.getTargetTriple().isThumb());
   case Triple::ELF:
     assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
     uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
-    return new ARMAsmBackendELF(T, STI, OSABI, Endian);
+    return new ARMAsmBackendELF(T, STI.getTargetTriple().isThumb(), OSABI,
+                                Endian);
   }
 }
 
 MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
                                           const MCSubtargetInfo &STI,
                                           const MCRegisterInfo &MRI,
                                           const MCTargetOptions &Options) {
   return createARMAsmBackend(T, STI, MRI, Options, support::little);
 }
 
 MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
                                           const MCSubtargetInfo &STI,
                                           const MCRegisterInfo &MRI,
                                           const MCTargetOptions &Options) {
   return createARMAsmBackend(T, STI, MRI, Options, support::big);
 }

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h

 namespace llvm {
 class ARMAsmBackendDarwin : public ARMAsmBackend {
   const MCRegisterInfo &MRI;
   Triple TT;
 public:
   const MachO::CPUSubTypeARM Subtype;
   ARMAsmBackendDarwin(const Target &T, const MCSubtargetInfo &STI,
                       const MCRegisterInfo &MRI)
-      : ARMAsmBackend(T, STI, support::little), MRI(MRI),
-        TT(STI.getTargetTriple()),
+      : ARMAsmBackend(T, STI.getTargetTriple().isThumb(), support::little),
+        MRI(MRI), TT(STI.getTargetTriple()),
         Subtype((MachO::CPUSubTypeARM)cantFail(
             MachO::getCPUSubType(STI.getTargetTriple()))) {}
 
   std::unique_ptr<MCObjectTargetWriter>
   createObjectTargetWriter() const override {
     return createARMMachObjectWriter(
         /*Is64Bit=*/false, cantFail(MachO::getCPUType(TT)), Subtype);
   }
 
   uint32_t generateCompactUnwindEncoding(
       ArrayRef<MCCFIInstruction> Instrs) const override;
 };
 } // end namespace llvm
 
 #endif

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h

 #include "llvm/MC/MCObjectWriter.h"
 
 using namespace llvm;
 
 namespace {
 class ARMAsmBackendELF : public ARMAsmBackend {
 public:
   uint8_t OSABI;
-  ARMAsmBackendELF(const Target &T, const MCSubtargetInfo &STI, uint8_t OSABI,
+  ARMAsmBackendELF(const Target &T, bool isThumb, uint8_t OSABI,
                    support::endianness Endian)
-      : ARMAsmBackend(T, STI, Endian), OSABI(OSABI) {}
+      : ARMAsmBackend(T, isThumb, Endian), OSABI(OSABI) {}
 
   std::unique_ptr<MCObjectTargetWriter>
   createObjectTargetWriter() const override {
     return createARMELFObjectWriter(OSABI);
   }
+
+  Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
 };
 }
 
 #endif

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h

 
 #include "ARMAsmBackend.h"
 #include "llvm/MC/MCObjectWriter.h"
 using namespace llvm;
 
 namespace {
 class ARMAsmBackendWinCOFF : public ARMAsmBackend {
 public:
-  ARMAsmBackendWinCOFF(const Target &T, const MCSubtargetInfo &STI)
-      : ARMAsmBackend(T, STI, support::little) {}
+  ARMAsmBackendWinCOFF(const Target &T, bool isThumb)
+      : ARMAsmBackend(T, isThumb, support::little) {}
   std::unique_ptr<MCObjectTargetWriter>
   createObjectTargetWriter() const override {
     return createARMWinCOFFObjectWriter();
   }
 };
 }
 
 #endif

llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h

public:
 
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override {
     llvm_unreachable("RelaxInstruction() unimplemented");
     return false;
   }
 
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 
   bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
                              const MCValue &Target) override;
 
 private:
   Triple::OSType OSType;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_AVR_ASM_BACKEND_H

llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp

if (Kind < FirstTargetFixupKind)
     return MCAsmBackend::getFixupKindInfo(Kind);
 
   assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
          "Invalid kind!");
 
   return Infos[Kind - FirstTargetFixupKind];
 }
 
-bool AVRAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+bool AVRAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                 const MCSubtargetInfo *STI) const {
   // If the count is not 2-byte aligned, we must be writing data into the text
   // section (otherwise we have unaligned instructions, and thus have far
   // bigger problems), so just write zeros instead.
   assert((Count % 2) == 0 && "NOP instructions must be 2 bytes");
 
   OS.write_zeros(Count);
   return true;
 }

llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp

public:
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override {
     return false;
   }
 
   unsigned getNumFixupKinds() const override { return 1; }
 
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 };
 
 } // end anonymous namespace
 
-bool BPFAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+bool BPFAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                 const MCSubtargetInfo *STI) const {
   if ((Count % 8) != 0)
     return false;
 
   for (uint64_t i = 0; i < Count; i += 8)
     support::endian::write<uint64_t>(OS, 0x15000000, Endian);
 
   return true;
 }

llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h

public:
 
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override;
 
   void relaxInstruction(MCInst &Inst,
                         const MCSubtargetInfo &STI) const override;
 
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 
   std::unique_ptr<MCObjectTargetWriter>
   createObjectTargetWriter() const override;
 };
 } // namespace llvm
 
 #endif // LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYASMBACKEND_H

llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp

bool CSKYAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
   return false;
 }
 
 void CSKYAsmBackend::relaxInstruction(MCInst &Inst,
                                       const MCSubtargetInfo &STI) const {
   llvm_unreachable("CSKYAsmBackend::relaxInstruction() unimplemented");
 }
 
-bool CSKYAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+bool CSKYAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                  const MCSubtargetInfo *STI) const {
   if (Count % 2)
     return false;
 
   // MOV32 r0, r0
   while (Count >= 4) {
     OS.write("\xc4\x00\x48\x20", 4);
     Count -= 4;
   }

llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp

for (auto &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
       Res.addOperand(MCOperand::createInst(I.getInst()));
     }
 
     Inst = std::move(Res);
     (void)Update;
     assert(Update && "Didn't find relaxation target");
   }
 
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override {
-    static const uint32_t Nopcode  = 0x7f000000, // Hard-coded NOP.
-                          ParseIn  = 0x00004000, // In packet parse-bits.
-                          ParseEnd = 0x0000c000; // End of packet parse-bits.
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override {
+    static const uint32_t Nopcode = 0x7f000000, // Hard-coded NOP.
+        ParseIn = 0x00004000,                   // In packet parse-bits.
+        ParseEnd = 0x0000c000;                  // End of packet parse-bits.
 
     while (Count % HEXAGON_INSTR_SIZE) {
       LLVM_DEBUG(dbgs() << "Alignment not a multiple of the instruction size:"
                         << Count % HEXAGON_INSTR_SIZE << "/"
                         << HEXAGON_INSTR_SIZE << "\n");
       --Count;
       OS << '\0';
     }

llvm/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp

public:
   }
 
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
 
   unsigned getNumFixupKinds() const override {
     return Lanai::NumTargetFixupKinds;
   }
 
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 };
 
-bool LanaiAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+bool LanaiAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                   const MCSubtargetInfo *STI) const {
   if ((Count % 4) != 0)
     return false;
 
   for (uint64_t i = 0; i < Count; i += 4)
     OS.write("\x15\0\0\0", 4);
 
   return true;
 }

llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp

public:
 
   /// Returns the minimum size of a nop in bytes on this target. The assembler
   /// will use this to emit excess padding in situations where the padding
   /// required for simple alignment would be less than the minimum nop size.
   unsigned getMinimumNopSize() const override { return 2; }
 
   /// Write a sequence of optimal nops to the output, covering \p Count bytes.
   /// \return - true on success, false on failure
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 };
 } // end anonymous namespace
 
 /// cc—Carry clear      GE—Greater than or equal
 /// LS—Lower or same    PL—Plus
 /// CS—Carry set        GT—Greater than
 /// LT—Less than
 /// EQ—Equal            HI—Higher
if (RelaxedOp == Inst.getOpcode()) {
     Inst.dump_pretty(OS);
     OS << "\n";
     report_fatal_error("unexpected instruction to relax: " + OS.str());
   }
 
   Inst.setOpcode(RelaxedOp);
 }
 
-bool M68kAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+bool M68kAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                  const MCSubtargetInfo *STI) const {
   // Cannot emit NOP with size being not multiple of 16 bits.
   if (Count % 2 != 0)
     return false;
 
   uint64_t NumNops = Count / 2;
   for (uint64_t i = 0; i != NumNops; ++i) {
     OS << "\x4E\x71";
   }

llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp

static_assert((array_lengthof(Infos)) == MSP430::NumTargetFixupKinds,
                   "Not all fixup kinds added to Infos array");
   
     if (Kind < FirstTargetFixupKind)
       return MCAsmBackend::getFixupKindInfo(Kind);
   
     return Infos[Kind - FirstTargetFixupKind];
   }
 
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 };
 
 uint64_t MSP430AsmBackend::adjustFixupValue(const MCFixup &Fixup,
                                             uint64_t Value,
                                             MCContext &Ctx) const {
   unsigned Kind = Fixup.getKind();
   switch (Kind) {
   case MSP430::fixup_10_pcrel: {
void MSP430AsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
 
   // For each byte of the fragment that the fixup touches, mask in the
   // bits from the fixup value.
   for (unsigned i = 0; i != NumBytes; ++i) {
     Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
   }
 }
 
-bool MSP430AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+bool MSP430AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                    const MCSubtargetInfo *STI) const {
   if ((Count % 2) != 0)
     return false;
 
   // The canonical nop on MSP430 is mov #0, r3
   uint64_t NopCount = Count / 2;
   while (NopCount--)
     OS.write("\x03\x43", 2);
 

llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h

public:
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override {
     // FIXME.
     llvm_unreachable("RelaxInstruction() unimplemented");
     return false;
   }
 
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 
   bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
                              const MCValue &Target) override;
 
   bool isMicroMips(const MCSymbol *Sym) const override;
 }; // class MipsAsmBackend
 
 } // namespace
 
 #endif

llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

getFixupKindInfo(MCFixupKind Kind) const {
   return BigEndianInfos[Kind - FirstTargetFixupKind];
 }
 
 /// WriteNopData - Write an (optimal) nop sequence of Count bytes
 /// to the given output. If the target cannot generate such a sequence,
 /// it should return an error.
 ///
 /// \return - True on success.
-bool MipsAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+bool MipsAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                  const MCSubtargetInfo *STI) const {
   // Check for a less than instruction size number of bytes
   // FIXME: 16 bit instructions are not handled yet here.
   // We shouldn't be using a hard coded number for instruction size.
 
   // If the count is not 4-byte aligned, we must be writing data into the text
   // section (otherwise we have unaligned instructions, and thus have far
   // bigger problems), so just write zeros instead.
   OS.write_zeros(Count);

llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

public:
   }
 
   void relaxInstruction(MCInst &Inst,
                         const MCSubtargetInfo &STI) const override {
     // FIXME.
     llvm_unreachable("relaxInstruction() unimplemented");
   }
 
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override {
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override {
     uint64_t NumNops = Count / 4;
     for (uint64_t i = 0; i != NumNops; ++i)
       support::endian::write<uint32_t>(OS, 0x60000000, Endian);
 
     OS.write_zeros(Count % 4);
 
     return true;
   }

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h

public:
   void relaxInstruction(MCInst &Inst,
                         const MCSubtargetInfo &STI) const override;
 
   bool relaxDwarfLineAddr(MCDwarfLineAddrFragment &DF, MCAsmLayout &Layout,
                           bool &WasRelaxed) const override;
   bool relaxDwarfCFA(MCDwarfCallFrameFragment &DF, MCAsmLayout &Layout,
                      bool &WasRelaxed) const override;
 
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 
   const MCTargetOptions &getTargetOptions() const { return TargetOptions; }
   RISCVABI::ABI getTargetABI() const { return TargetABI; }
 };
 }
 
 #endif

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
   }
 }
 
 bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst,
                                         const MCSubtargetInfo &STI) const {
   return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode();
 }
 
-bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
-  bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC];
+bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                   const MCSubtargetInfo *STI) const {
+  bool HasStdExtC = STI->getFeatureBits()[RISCV::FeatureStdExtC];
   unsigned MinNopLen = HasStdExtC ? 2 : 4;
 
   if ((Count % MinNopLen) != 0)
     return false;
 
   // The canonical nop on RISC-V is addi x0, x0, 0.
   for (; Count >= 4; Count -= 4)
     OS.write("\x13\0\0\0", 4);

llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

bool fixupNeedsRelaxation(const MCFixup &Fixup,
       return false;
     }
     void relaxInstruction(MCInst &Inst,
                           const MCSubtargetInfo &STI) const override {
       // FIXME.
       llvm_unreachable("relaxInstruction() unimplemented");
     }
 
-    bool writeNopData(raw_ostream &OS, uint64_t Count) const override {
+    bool writeNopData(raw_ostream &OS, uint64_t Count,
+                      const MCSubtargetInfo *STI) const override {
       // Cannot emit NOP with size not multiple of 32 bits.
       if (Count % 4 != 0)
         return false;
 
       uint64_t NumNops = Count / 4;
       for (uint64_t i = 0; i != NumNops; ++i)
         support::endian::write<uint32_t>(OS, 0x01000000, Endian);
 

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp

void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
                   const MCValue &Target, MutableArrayRef<char> Data,
                   uint64_t Value, bool IsResolved,
                   const MCSubtargetInfo *STI) const override;
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *Fragment,
                             const MCAsmLayout &Layout) const override {
     return false;
   }
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
   std::unique_ptr<MCObjectTargetWriter>
   createObjectTargetWriter() const override {
     return createSystemZObjectWriter(OSABI);
   }
 };
 } // end anonymous namespace
 
 Optional<MCFixupKind> SystemZMCAsmBackend::getFixupKind(StringRef Name) const {
if (BitSize < 64)
     Value &= ((uint64_t)1 << BitSize) - 1;
   unsigned ShiftValue = (Size * 8) - 8;
   for (unsigned I = 0; I != Size; ++I) {
     Data[Offset + I] |= uint8_t(Value >> ShiftValue);
     ShiftValue -= 8;
   }
 }
 
-bool SystemZMCAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+bool SystemZMCAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                       const MCSubtargetInfo *STI) const {
   for (uint64_t I = 0; I != Count; ++I)
     OS << '\x7';
   return true;
 }
 
 MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T,
                                               const MCSubtargetInfo &STI,
                                               const MCRegisterInfo &MRI,
                                               const MCTargetOptions &Options) {
   uint8_t OSABI =
       MCELFObjectTargetWriter::getOSABI(STI.getTargetTriple().getOS());
   return new SystemZMCAsmBackend(OSABI);
 }

llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp

bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
     return false;
   }
   void relaxInstruction(MCInst &Inst,
                         const MCSubtargetInfo &STI) const override {
     // Aurora VE doesn't support relaxInstruction yet.
     llvm_unreachable("relaxInstruction() should not be called");
   }
 
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override {
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override {
     if ((Count % 8) != 0)
       return false;
 
     for (uint64_t i = 0; i < Count; i += 8)
       support::endian::write<uint64_t>(OS, 0x7900000000000000ULL,
                                        support::little);
 
     return true;

llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp

public:
 
   // No instruction requires relaxation
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override {
     return false;
   }
 
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 };
 
 const MCFixupKindInfo &
 WebAssemblyAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
   const static MCFixupKindInfo Infos[WebAssembly::NumTargetFixupKinds] = {
       // This table *must* be in the order that the fixup_* kinds are defined in
       // WebAssemblyFixupKinds.h.
       //
       // Name                     Offset (bits) Size (bits)     Flags
       {"fixup_sleb128_i32", 0, 5 * 8, 0},
       {"fixup_sleb128_i64", 0, 10 * 8, 0},
       {"fixup_uleb128_i32", 0, 5 * 8, 0},
       {"fixup_uleb128_i64", 0, 10 * 8, 0},
   };
 
   if (Kind < FirstTargetFixupKind)
     return MCAsmBackend::getFixupKindInfo(Kind);
 
   assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
          "Invalid kind!");
   return Infos[Kind - FirstTargetFixupKind];
 }
 
-bool WebAssemblyAsmBackend::writeNopData(raw_ostream &OS,
-                                         uint64_t Count) const {
+bool WebAssemblyAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                         const MCSubtargetInfo *STI) const {
   for (uint64_t I = 0; I < Count; ++I)
     OS << char(WebAssembly::Nop);
 
   return true;
 }
 
 void WebAssemblyAsmBackend::applyFixup(const MCAssembler &Asm,
                                        const MCFixup &Fixup,

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

bool X86AsmParser::parseDirectiveArch() {
   return false;
 }
 
 /// parseDirectiveNops
 ///  ::= .nops size[, control]
 bool X86AsmParser::parseDirectiveNops(SMLoc L) {
   int64_t NumBytes = 0, Control = 0;
   SMLoc NumBytesLoc, ControlLoc;
-  const MCSubtargetInfo STI = getSTI();
+  const MCSubtargetInfo& STI = getSTI();
   NumBytesLoc = getTok().getLoc();
   if (getParser().checkForValidSection() ||
       getParser().parseAbsoluteExpression(NumBytes))
     return true;
 
   if (parseOptionalToken(AsmToken::Comma)) {
     ControlLoc = getTok().getLoc();
     if (getParser().parseAbsoluteExpression(Control))
bool X86AsmParser::parseDirectiveNops(SMLoc L) {
   }
 
   if (Control < 0) {
     Error(ControlLoc, "'.nops' directive with negative NOP size");
     return false;
   }
 
   /// Emit nops
-  getParser().getStreamer().emitNops(NumBytes, Control, L);
+  getParser().getStreamer().emitNops(NumBytes, Control, L, STI);
 
   return false;
 }
 
 /// parseDirectiveEven
 ///  ::= .even
 bool X86AsmParser::parseDirectiveEven(SMLoc L) {
   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))

llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

X86AsmBackend(const Target &T, const MCSubtargetInfo &STI)
     if (X86AlignBranch.getNumOccurrences())
       AlignBranchType = X86AlignBranchKindLoc;
     if (X86PadMaxPrefixSize.getNumOccurrences())
       TargetPrefixMax = X86PadMaxPrefixSize;
   }
 
   bool allowAutoPadding() const override;
   bool allowEnhancedRelaxation() const override;
-  void emitInstructionBegin(MCObjectStreamer &OS, const MCInst &Inst) override;
+  void emitInstructionBegin(MCObjectStreamer &OS, const MCInst &Inst,
+                            const MCSubtargetInfo &STI) override;
   void emitInstructionEnd(MCObjectStreamer &OS, const MCInst &Inst) override;
 
   unsigned getNumFixupKinds() const override {
     return X86::NumTargetFixupKinds;
   }
 
   Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
 
public:
   bool padInstructionViaPrefix(MCRelaxableFragment &RF, MCCodeEmitter &Emitter,
                                unsigned &RemainingSize) const;
 
   bool padInstructionEncoding(MCRelaxableFragment &RF, MCCodeEmitter &Emitter,
                               unsigned &RemainingSize) const;
 
   void finishLayout(MCAssembler const &Asm, MCAsmLayout &Layout) const override;
 
-  unsigned getMaximumNopSize() const override;
+  unsigned getMaximumNopSize(const MCSubtargetInfo &STI) const override;
 
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 };
 } // end anonymous namespace
 
 static unsigned getRelaxedOpcodeBranch(const MCInst &Inst, bool Is16BitMode) {
   unsigned Op = Inst.getOpcode();
   switch (Op) {
   default:
     return Op;
return (Desc.isConditionalBranch() &&
          (Desc.isCall() && (AlignBranchType & X86::AlignBranchCall)) ||
          (Desc.isReturn() && (AlignBranchType & X86::AlignBranchRet)) ||
          (Desc.isIndirectBranch() &&
           (AlignBranchType & X86::AlignBranchIndirect));
 }
 
 /// Insert BoundaryAlignFragment before instructions to align branches.
 void X86AsmBackend::emitInstructionBegin(MCObjectStreamer &OS,
-                                         const MCInst &Inst) {
+                                         const MCInst &Inst, const MCSubtargetInfo &STI) {
   CanPadInst = canPadInst(Inst, OS);
 
   if (!canPadBranches(OS))
     return;
 
   if (!isMacroFused(PrevInst, Inst))
     // Macro fusion doesn't happen indeed, clear the pending.
     PendingBA = nullptr;
if (PendingBA && OS.getCurrentFragment()->getPrevNode() == PendingBA) {
     // with the CMP.
     return;
   }
 
   if (needAlign(Inst) || ((AlignBranchType & X86::AlignBranchFused) &&
                           isFirstMacroFusibleInst(Inst, *MCII))) {
     // If we meet a unfused branch or the first instuction in a fusiable pair,
     // insert a BoundaryAlign fragment.
-    OS.insert(PendingBA = new MCBoundaryAlignFragment(AlignBoundary));
+    OS.insert(PendingBA = new MCBoundaryAlignFragment(AlignBoundary, STI));
   }
 }
 
 /// Set the last fragment to be aligned for the BoundaryAlignFragment.
 void X86AsmBackend::emitInstructionEnd(MCObjectStreamer &OS, const MCInst &Inst) {
   PrevInst = Inst;
   MCFragment *CF = OS.getCurrentFragment();
   PrevInstPosition = std::make_pair(CF, getSizeForInstFragment(CF));
#endif
   // The layout is done. Mark every fragment as valid.
   for (unsigned int i = 0, n = Layout.getSectionOrder().size(); i != n; ++i) {
     MCSection &Section = *Layout.getSectionOrder()[i];
     Layout.getFragmentOffset(&*Section.getFragmentList().rbegin());
     Asm.computeFragmentSize(Layout, *Section.getFragmentList().rbegin());
   }
 }
 
-unsigned X86AsmBackend::getMaximumNopSize() const {
+unsigned X86AsmBackend::getMaximumNopSize(const MCSubtargetInfo &STI) const {
   if (STI.hasFeature(X86::Mode16Bit))
     return 4;
   if (!STI.hasFeature(X86::FeatureNOPL) && !STI.hasFeature(X86::Mode64Bit))
     return 1;
   if (STI.getFeatureBits()[X86::TuningFast7ByteNOP])
     return 7;
   if (STI.getFeatureBits()[X86::TuningFast15ByteNOP])
     return 15;
   if (STI.getFeatureBits()[X86::TuningFast11ByteNOP])
     return 11;
   // FIXME: handle 32-bit mode
   // 15-bytes is the longest single NOP instruction, but 10-bytes is
   // commonly the longest that can be efficiently decoded.
   return 10;
 }
 
 /// Write a sequence of optimal nops to the output, covering \p Count
 /// bytes.
 /// \return - true on success, false on failure
-bool X86AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+bool X86AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                 const MCSubtargetInfo *STI) const {
   static const char Nops32Bit[10][11] = {
       // nop
       "\x90",
       // xchg %ax,%ax
       "\x66\x90",
       // nopl (%[re]ax)
       "\x0f\x1f\x00",
       // nopl 0(%[re]ax)
static const char Nops16Bit[4][11] = {
       "\x66\x90",
       // lea 0(%si),%si
       "\x8d\x74\x00",
       // lea 0w(%si),%si
       "\x8d\xb4\x00\x00",
   };
 
   const char(*Nops)[11] =
-      STI.getFeatureBits()[X86::Mode16Bit] ? Nops16Bit : Nops32Bit;
+      STI->getFeatureBits()[X86::Mode16Bit] ? Nops16Bit : Nops32Bit;
 
-  uint64_t MaxNopLength = (uint64_t)getMaximumNopSize();
+  uint64_t MaxNopLength = (uint64_t)getMaximumNopSize(*STI);
 
   // Emit as many MaxNopLength NOPs as needed, then emit a NOP of the remaining
   // length.
   do {
     const uint8_t ThisNopLength = (uint8_t) std::min(Count, MaxNopLength);
     const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
     for (uint8_t i = 0; i < Prefixes; i++)
       OS << '\x66';

llvm/test/CodeGen/ARM/subtarget-align.ll

+; RUN: llc < %s -mtriple=arm-linux-gnueabihf -filetype=obj -o - | llvm-objdump --triple=armv7 --no-show-raw-insn -d - | FileCheck %s
+
+;; Expect architectural nop to be used between func2 and func3 but not func1
+;; and func2 due to lack of subtarget support in func2.
+
+define i32 @func1() #0 align 16 {
+entry:
+  ret i32 0
+}
+
+define i32 @func2() #1 align 16 {
+entry:
+  ret i32 0
+}
+
+define i32 @func3() #0 align 16 {
+entry:
+  ret i32 0
+}
+
+attributes #0 = { "target-cpu"="generic" "target-features"="+armv7-a,+dsp,+neon,+vfp3,-thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "target-cpu"="arm7tdmi" "target-features"="+armv4t" "use-soft-float"="true" }
+
+
+; CHECK: 00000000 <func1>:
+; CHECK-NEXT:  0: mov     r0, #0
+; CHECK-NEXT:  4: bx      lr
+; CHECK-NEXT:  8: mov     r0, r0
+; CHECK-NEXT:  c: mov     r0, r0
+
+; CHECK: 00000010 <func2>:
+; CHECK-NEXT: 10: mov     r0, #0
+; CHECK-NEXT: 14: bx      lr
+; CHECK-NEXT: 18: nop
+; CHECK-NEXT: 1c: nop
+
+; CHECK: 00000020 <func3>:
+; CHECK-NEXT: 20: mov     r0, #0
+; CHECK-NEXT: 24: bx      lr

llvm/test/MC/ARM/subtarget-nop.s

+// RUN: llvm-mc < %s --triple=arm-linux-gnueabihf -filetype=obj -o - | llvm-objdump --no-show-raw-insn --triple=armv7 -d - | FileCheck %s
+
+// Check that the architectural nop is only produced for subtargets that
+// support it. This includes nop padding for alignment.
+ .syntax unified
+ .arch armv6
+foo:
+ mov r1, r0
+ nop
+ .p2align 4
+ bx lr
+
+ .arch armv7-a
+bar:
+ mov r1, r0
+ nop
+ .p2align 4
+ bx lr
+
+ .arch armv4t
+baz:
+ mov r1, r0
+ nop
+ .p2align 4
+ bx lr
+
+// CHECK: 00000000 <foo>:
+// CHECK-NEXT:  0: mov     r1, r0
+// CHECK-NEXT:  4: mov     r0, r0
+// CHECK-NEXT:  8: mov     r0, r0
+// CHECK-NEXT:  c: mov     r0, r0
+// CHECK-NEXT: 10: bx      lr
+
+// CHECK: 00000014 <bar>:
+// CHECK-NEXT: 14: mov     r1, r0
+// CHECK-NEXT: 18: nop
+// CHECK-NEXT: 1c: nop
+// CHECK-NEXT: 20: bx      lr
+
+// CHECK: 00000024 <baz>:
+// CHECK-NEXT: 24: mov     r1, r0
+// CHECK-NEXT: 28: mov     r0, r0
+// CHECK-NEXT: 2c: mov     r0, r0
+// CHECK-NEXT: 30: bx      lr

llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp

SmallString<0> DWARFExpressionCopyBytesTest::emitObjFile(StringRef ExprBytes) {
   StreamerContext C = createStreamer(VecOS);
   C.Streamer->initSections(false, *STI);
   MCSection *Section = C.MOFI->getTextSection();
   Section->setHasInstructions(true);
   C.Streamer->SwitchSection(Section);
   C.Streamer->emitCFIStartProc(true);
   auto Str = EncodeDefCfaExpr(ExprBytes);
   C.Streamer->emitCFIEscape(Str);
-  C.Streamer->emitNops(4, 1, SMLoc());
+  C.Streamer->emitNops(4, 1, SMLoc(), *STI);
   C.Streamer->emitCFIEndProc();
   C.Streamer->Finish();
   return Storage;
 }
 
 void DWARFExpressionCopyBytesTest::parseCFIsAndCheckExpression(
     const llvm::object::ObjectFile &E, ArrayRef<uint8_t> Expected) {
   auto FetchFirstCfaExpression =