[MC] Use local MCSubtargetInfo in writeNops

[peter.smith]

Summary

On some architectures such as Arm and X86 the encoding for a nop may change depending on the subtarget in operation at the time of encoding. This change replaces the per module MCSubtargetInfo retained by the targets AsmBackend in favour of passing through the local MCSubtargetInfo in operation at the time.

On Arm using the architectural NOP instruction can have a performance benefit on some implementations.

For Arm I've deleted the copy of the AsmBackend's MCSubtargetInfo to limit the chances of this causing problems in the future. I've not done this for other targets such as X86 as there is more frequent use of the MCSubtargetInfo and it looks to be for stable properties that we would not expect to vary per function in the way that an Arm NOP might.

I've attempted to take into account the in tree experimental backends.

This patch depends on D45961

[peter.smith]

Rebased [NFC]

[peter.smith]

Rebased, and added support for WebAssembly and RiscV as my default build configuration didn't include them at the time. No other changes.

[efriedma]

LGTM, assuming it rebases cleanly

lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h

22

isThumbMode should probably be using the ThumbMode bit of MCSubtargetInfo... but I'm not sure we're actually updating that at the moment. Probably okay to leave it for a followup.

[MaskRay]

lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

348

STI->

[peter.smith]

Thanks for the review. I've just got back from vacation and I'm a bit behind. Will rebase this and D45961 hopefully by the end of this week. I'll post it here and will give a heads up if there are any meaningful changes.

[peter.smith]

In D45962#2919645, @peter.smith wrote:

Thanks for the review. I've just got back from vacation and I'm a bit behind. Will rebase this and D45961 hopefully by the end of this week. I'll post it here and will give a heads up if there are any meaningful changes.

Will be early next week. I've rebased D45962 which this depends on.

[peter.smith]

In D45962#2931626, @peter.smith wrote:

In D45962#2919645, @peter.smith wrote:

Thanks for the review. I've just got back from vacation and I'm a bit behind. Will rebase this and D45961 hopefully by the end of this week. I'll post it here and will give a heads up if there are any meaningful changes.

Will be early next week. I've rebased D45962 which this depends on.

I've just had a quick go at rebasing and there is a bit more work than I bargained for. The X86 backend has introduced a couple more MCFragments that will need adapting

• MCBoundaryAlignFragment
• MCNopsFragment

I think I can pass STI through to these wihtout any ill effect but I'd like to submit these as individual patches for review as I don't know X86 well.

The X86 backend has used its per-target STI for some other things as well, so I won't be able to remove it in this patch.

ETA for this will be Friday afternoon (doing this in spare time).

[peter.smith]

Rebased (quite a lot) to account for a couple of years of changes.

I've included the changes to the two new x86 specific MCFragments MCNopsFragment and MCBoundaryAlignFragment that also call emitNops. I can split these changes out if needed but I thought it better to show the magnitude of the change in one go.

As mentioned in D45961 an alternative, less disruptive implementation (the Arm backend does not use MCNopsFragment or MCBoundaryAlignFragment) is to permit the MCSubtargetInfo to be nullptr which would mean retaining the STI in the Arm MCAsmBackend and a test in emitNops() to see if the STI passed in where nullptr.

[peter.smith]

Minor rebase NFC from previous patch. As this + previous rebase was quite a substantial update from the previous patch I'd ideally like a second opinion on whether this is still OK before I commit it and D45961 .

[MaskRay]

LGTM.

[peter.smith]

Rebase, and fix up DWARFExpressionCopyBytesTest.cpp

[peter.smith]

Fixup comments in MCFragment.h to look like D45961 and update patch manually as I'm not sure arc diff did the right thing.

[MaskRay]

llvm/test/CodeGen/ARM/subtarget-align.ll

1 ↗

(On Diff #370924)

< and -o - can be omitted.

llvm/test/MC/ARM/subtarget-nop.s

1 ↗

(On Diff #370924)

< and -o - can be omitted.

[peter.smith]

Thanks will apply comments prior to commit.

[mstorsjo]

This broke llvm-ml for assembling real-world files:

$ bin/llvm-ml -D_M_IA32 -DOMPT_SUPPORT=0 -c -Fo out.obj ../../openmp/runtime/src/z_Windows_NT-586_asm.asm
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
Stack dump:
0.      Program arguments: bin/llvm-ml -D_M_IA32 -DOMPT_SUPPORT=0 -c -Fo out.obj ../../openmp/runtime/src/z_Windows_NT-586_asm.asm
 #0 0x000055f22ac9ab1c llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) /home/martin/code/llvm-project/llvm/build-debug/../lib/Support/Unix/Signals.inc:565:0
 #1 0x000055f22ac9abd3 PrintStackTraceSignalHandler(void*) /home/martin/code/llvm-project/llvm/build-debug/../lib/Support/Unix/Signals.inc:632:0
 #2 0x000055f22ac98887 llvm::sys::RunSignalHandlers() /home/martin/code/llvm-project/llvm/build-debug/../lib/Support/Signals.cpp:97:0
 #3 0x000055f22ac9a49d SignalHandler(int) /home/martin/code/llvm-project/llvm/build-debug/../lib/Support/Unix/Signals.inc:407:0
 #4 0x00007f0ff42e3980 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x12980)
 #5 0x000055f22a777efc llvm::FeatureBitset::operator[](unsigned int) const /home/martin/code/llvm-project/llvm/build-debug/../include/llvm/MC/SubtargetFeature.h:87:0
 #6 0x000055f22a920116 (anonymous namespace)::X86AsmBackend::writeNopData(llvm::raw_ostream&, unsigned long, llvm::MCSubtargetInfo const*) const /home/martin/code/llvm-project/llvm/build-debug/../lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp:1145:0
 #7 0x000055f22a9fb58b writeFragment(llvm::raw_ostream&, llvm::MCAssembler const&, llvm::MCAsmLayout const&, llvm::MCFragment const&) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCAssembler.cpp:548:0
 #8 0x000055f22a9fc778 llvm::MCAssembler::writeSectionData(llvm::raw_ostream&, llvm::MCSection const*, llvm::MCAsmLayout const&) const /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCAssembler.cpp:780:0
 #9 0x000055f22aad17fd (anonymous namespace)::WinCOFFObjectWriter::writeSectionContents(llvm::MCAssembler&, llvm::MCAsmLayout const&, llvm::MCSection const&) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/WinCOFFObjectWriter.cpp:614:0
#10 0x000055f22aad1965 (anonymous namespace)::WinCOFFObjectWriter::writeSection(llvm::MCAssembler&, llvm::MCAsmLayout const&, (anonymous namespace)::COFFSection const&, llvm::MCSection const&) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/WinCOFFObjectWriter.cpp:635:0
#11 0x000055f22aad4363 (anonymous namespace)::WinCOFFObjectWriter::writeObject(llvm::MCAssembler&, llvm::MCAsmLayout const&) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/WinCOFFObjectWriter.cpp:1152:0
#12 0x000055f22a9fd579 llvm::MCAssembler::Finish() /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCAssembler.cpp:937:0
#13 0x000055f22aa68b5e llvm::MCObjectStreamer::finishImpl() /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCObjectStreamer.cpp:888:0
#14 0x000055f22aa9eaca llvm::MCWinCOFFStreamer::finishImpl() /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCWinCOFFStreamer.cpp:368:0
#15 0x000055f22a916966 (anonymous namespace)::X86WinCOFFStreamer::finishImpl() /home/martin/code/llvm-project/llvm/build-debug/../lib/Target/X86/MCTargetDesc/X86WinCOFFStreamer.cpp:65:0
#16 0x000055f22aa89d3c llvm::MCStreamer::Finish(llvm::SMLoc) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCStreamer.cpp:1005:0
#17 0x000055f22ab53df0 (anonymous namespace)::MasmParser::Run(bool, bool) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCParser/MasmParser.cpp:1435:0
#18 0x000055f22a701374 AssembleInput(llvm::StringRef, llvm::Target const*, llvm::SourceMgr&, llvm::MCContext&, llvm::MCStreamer&, llvm::MCAsmInfo&, llvm::MCSubtargetInfo&, llvm::MCInstrInfo&, llvm::MCTargetOptions&, llvm::opt::ArgList const&) /home/martin/code/llvm-project/llvm/build-debug/../tools/llvm-ml/llvm-ml.cpp:186:0
#19 0x000055f22a703135 main /home/martin/code/llvm-project/llvm/build-debug/../tools/llvm-ml/llvm-ml.cpp:433:0

@epastor Apparently it would be good with a llvm-ml specific testcase that triggers writing nops.

[peter.smith]

In D45962#2988712, @mstorsjo wrote:

This broke llvm-ml for assembling real-world files:

$ bin/llvm-ml -D_M_IA32 -DOMPT_SUPPORT=0 -c -Fo out.obj ../../openmp/runtime/src/z_Windows_NT-586_asm.asm
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
Stack dump:
0.      Program arguments: bin/llvm-ml -D_M_IA32 -DOMPT_SUPPORT=0 -c -Fo out.obj ../../openmp/runtime/src/z_Windows_NT-586_asm.asm
 #0 0x000055f22ac9ab1c llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) /home/martin/code/llvm-project/llvm/build-debug/../lib/Support/Unix/Signals.inc:565:0
 #1 0x000055f22ac9abd3 PrintStackTraceSignalHandler(void*) /home/martin/code/llvm-project/llvm/build-debug/../lib/Support/Unix/Signals.inc:632:0
 #2 0x000055f22ac98887 llvm::sys::RunSignalHandlers() /home/martin/code/llvm-project/llvm/build-debug/../lib/Support/Signals.cpp:97:0
 #3 0x000055f22ac9a49d SignalHandler(int) /home/martin/code/llvm-project/llvm/build-debug/../lib/Support/Unix/Signals.inc:407:0
 #4 0x00007f0ff42e3980 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x12980)
 #5 0x000055f22a777efc llvm::FeatureBitset::operator[](unsigned int) const /home/martin/code/llvm-project/llvm/build-debug/../include/llvm/MC/SubtargetFeature.h:87:0
 #6 0x000055f22a920116 (anonymous namespace)::X86AsmBackend::writeNopData(llvm::raw_ostream&, unsigned long, llvm::MCSubtargetInfo const*) const /home/martin/code/llvm-project/llvm/build-debug/../lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp:1145:0
 #7 0x000055f22a9fb58b writeFragment(llvm::raw_ostream&, llvm::MCAssembler const&, llvm::MCAsmLayout const&, llvm::MCFragment const&) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCAssembler.cpp:548:0
 #8 0x000055f22a9fc778 llvm::MCAssembler::writeSectionData(llvm::raw_ostream&, llvm::MCSection const*, llvm::MCAsmLayout const&) const /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCAssembler.cpp:780:0
 #9 0x000055f22aad17fd (anonymous namespace)::WinCOFFObjectWriter::writeSectionContents(llvm::MCAssembler&, llvm::MCAsmLayout const&, llvm::MCSection const&) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/WinCOFFObjectWriter.cpp:614:0
#10 0x000055f22aad1965 (anonymous namespace)::WinCOFFObjectWriter::writeSection(llvm::MCAssembler&, llvm::MCAsmLayout const&, (anonymous namespace)::COFFSection const&, llvm::MCSection const&) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/WinCOFFObjectWriter.cpp:635:0
#11 0x000055f22aad4363 (anonymous namespace)::WinCOFFObjectWriter::writeObject(llvm::MCAssembler&, llvm::MCAsmLayout const&) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/WinCOFFObjectWriter.cpp:1152:0
#12 0x000055f22a9fd579 llvm::MCAssembler::Finish() /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCAssembler.cpp:937:0
#13 0x000055f22aa68b5e llvm::MCObjectStreamer::finishImpl() /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCObjectStreamer.cpp:888:0
#14 0x000055f22aa9eaca llvm::MCWinCOFFStreamer::finishImpl() /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCWinCOFFStreamer.cpp:368:0
#15 0x000055f22a916966 (anonymous namespace)::X86WinCOFFStreamer::finishImpl() /home/martin/code/llvm-project/llvm/build-debug/../lib/Target/X86/MCTargetDesc/X86WinCOFFStreamer.cpp:65:0
#16 0x000055f22aa89d3c llvm::MCStreamer::Finish(llvm::SMLoc) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCStreamer.cpp:1005:0
#17 0x000055f22ab53df0 (anonymous namespace)::MasmParser::Run(bool, bool) /home/martin/code/llvm-project/llvm/build-debug/../lib/MC/MCParser/MasmParser.cpp:1435:0
#18 0x000055f22a701374 AssembleInput(llvm::StringRef, llvm::Target const*, llvm::SourceMgr&, llvm::MCContext&, llvm::MCStreamer&, llvm::MCAsmInfo&, llvm::MCSubtargetInfo&, llvm::MCInstrInfo&, llvm::MCTargetOptions&, llvm::opt::ArgList const&) /home/martin/code/llvm-project/llvm/build-debug/../tools/llvm-ml/llvm-ml.cpp:186:0
#19 0x000055f22a703135 main /home/martin/code/llvm-project/llvm/build-debug/../tools/llvm-ml/llvm-ml.cpp:433:0

@epastor Apparently it would be good with a llvm-ml specific testcase that triggers writing nops.

My apologies, will take a look. If I can spot the problem early I'll fix, otherwise will need to revert as it may be Friday before I can spend a lot of time on it.

[peter.smith]

Created D109425 to fix. This is the smallest change I can make in the time I've got this morning. Looks like this only got through because of an unfortunate default parameter. We might be able to prevent that by changing to a const reference.

include/llvm/MC/MCAsmBackend.h

public:
   /// required for simple alignment would be less than the minimum nop size.
   ///
   virtual unsigned getMinimumNopSize() const { return 1; }
 
   /// Write an (optimal) nop sequence of Count bytes to the given output. If the
   /// target cannot generate such a sequence, it should return an error.
   ///
   /// \return - True on success.
-  virtual bool writeNopData(raw_ostream &OS, uint64_t Count) const = 0;
+  virtual bool writeNopData(raw_ostream &OS, uint64_t Count,
+                            const MCSubtargetInfo *STI) const = 0;
 
   /// Give backend an opportunity to finish layout after relaxation
   virtual void finishLayout(MCAssembler const &Asm,
                             MCAsmLayout &Layout) const {}
 
   /// Handle any target-specific assembler flags. By default, do nothing.
   virtual void handleAssemblerFlag(MCAssemblerFlag Flag) {}
 

lib/MC/MCAssembler.cpp

void MCAssembler::writeFragmentPadding(raw_ostream &OS,
   unsigned BundlePadding = EF.getBundlePadding();
   if (BundlePadding > 0) {
     assert(isBundlingEnabled() &&
            "Writing bundle padding with disabled bundling");
     assert(EF.hasInstructions() &&
            "Writing bundle padding for a fragment without instructions");
 
     unsigned TotalLength = BundlePadding + static_cast<unsigned>(FSize);
+    const MCSubtargetInfo *STI = EF.getSubtargetInfo();
     if (EF.alignToBundleEnd() && TotalLength > getBundleAlignSize()) {
       // If the padding itself crosses a bundle boundary, it must be emitted
       // in 2 pieces, since even nop instructions must not cross boundaries.
       //             v--------------v   <- BundleAlignSize
       //        v---------v             <- BundlePadding
       // ----------------------------
       // | Prev |####|####|    F    |
       // ----------------------------
       //        ^-------------------^   <- TotalLength
       unsigned DistanceToBoundary = TotalLength - getBundleAlignSize();
-      if (!getBackend().writeNopData(OS, DistanceToBoundary))
+      if (!getBackend().writeNopData(OS, DistanceToBoundary, STI))
         report_fatal_error("unable to write NOP sequence of " +
                            Twine(DistanceToBoundary) + " bytes");
       BundlePadding -= DistanceToBoundary;
     }
-    if (!getBackend().writeNopData(OS, BundlePadding))
+    if (!getBackend().writeNopData(OS, BundlePadding, STI))
       report_fatal_error("unable to write NOP sequence of " +
                          Twine(BundlePadding) + " bytes");
   }
 }
 
 /// Write the fragment \p F to the output file.
 static void writeFragment(raw_ostream &OS, const MCAssembler &Asm,
                           const MCAsmLayout &Layout, const MCFragment &F) {
if (Count * AF.getValueSize() != FragmentSize)
                         "' is not a divisor of padding size '" +
                         Twine(FragmentSize) + "'");
 
     // See if we are aligning with nops, and if so do that first to try to fill
     // the Count bytes.  Then if that did not fill any bytes or there are any
     // bytes left to fill use the Value and ValueSize to fill the rest.
     // If we are aligning with nops, ask that target to emit the right data.
     if (AF.hasEmitNops()) {
-      if (!Asm.getBackend().writeNopData(OS, Count))
+      if (!Asm.getBackend().writeNopData(OS, Count, AF.getSubtargetInfo()))
         report_fatal_error("unable to write nop sequence of " +
                           Twine(Count) + " bytes");
       break;
     }
 
     // Otherwise, write out in multiples of the value size.
     for (uint64_t i = 0; i != Count; ++i) {
       switch (AF.getValueSize()) {
static void writeFragment(raw_ostream &OS, const MCAssembler &Asm,
 
   case MCFragment::FT_LEB: {
     const MCLEBFragment &LF = cast<MCLEBFragment>(F);
     OS << LF.getContents();
     break;
   }
 
   case MCFragment::FT_Padding: {
-    if (!Asm.getBackend().writeNopData(OS, FragmentSize))
+    const MCPaddingFragment &PF = cast<MCPaddingFragment>(F);
+    const MCSubtargetInfo *STI = &PF.getSubtargetInfo();
+    if (!Asm.getBackend().writeNopData(OS, FragmentSize, STI))
       report_fatal_error("unable to write nop sequence of " +
                          Twine(FragmentSize) + " bytes");
     break;
   }
 
   case MCFragment::FT_SymbolId: {
     const MCSymbolIdFragment &SF = cast<MCSymbolIdFragment>(F);
     support::endian::write<uint32_t>(OS, SF.getSymbol()->getIndex(), Endian);

lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp

public:
 
   bool mayNeedRelaxation(const MCInst &Inst,
                          const MCSubtargetInfo &STI) const override;
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override;
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override;
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 
   void HandleAssemblerFlag(MCAssemblerFlag Flag) {}
 
   unsigned getPointerSize() const { return 8; }
 
   unsigned getFixupKindContainereSizeInBytes(unsigned Kind) const;
 
   bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,

 }
 
 void AArch64AsmBackend::relaxInstruction(const MCInst &Inst,
                                          const MCSubtargetInfo &STI,
                                          MCInst &Res) const {
   llvm_unreachable("AArch64AsmBackend::relaxInstruction() unimplemented");
 }
 
-bool AArch64AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+bool AArch64AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                     const MCSubtargetInfo *STI) const {
   // If the count is not 4-byte aligned, we must be writing data into the text
   // section (otherwise we have unaligned instructions, and thus have far
   // bigger problems), so just write zeros instead.
   OS.write_zeros(Count % 4);
 
   // We are properly aligned, so write NOPs as requested.
   Count /= 4;
   for (uint64_t i = 0; i != Count; ++i)

lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
     llvm_unreachable("Not implemented");
   }
   bool mayNeedRelaxation(const MCInst &Inst,
                          const MCSubtargetInfo &STI) const override {
     return false;
   }
 
   unsigned getMinimumNopSize() const override;
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
 };
 
 } //End anonymous namespace
 
 static unsigned getFixupKindNumBytes(unsigned Kind) {
   switch (Kind) {
const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
 
   return Infos[Kind - FirstTargetFixupKind];
 }
 
 unsigned AMDGPUAsmBackend::getMinimumNopSize() const {
   return 4;
 }
 
-bool AMDGPUAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+bool AMDGPUAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                    const MCSubtargetInfo *STI) const {
   // If the count is not 4-byte aligned, we must be writing data into the text
   // section (otherwise we have unaligned instructions, and thus have far
   // bigger problems), so just write zeros instead.
   OS.write_zeros(Count % 4);
 
   // We are properly aligned, so write NOPs as requested.
   Count /= 4;
 

lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h

 #include "MCTargetDesc/ARMMCTargetDesc.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/TargetRegistry.h"
 
 namespace llvm {
 
 class ARMAsmBackend : public MCAsmBackend {
-  // The STI from the target triple the MCAsmBackend was instantiated with
-  // note that MCFragments may have a different local STI that should be
-  // used in preference.
-  const MCSubtargetInfo &STI;
   bool isThumbMode;    // Currently emitting Thumb code.
 public:
-  ARMAsmBackend(const Target &T, const MCSubtargetInfo &STI,
-                support::endianness Endian)
-      : MCAsmBackend(Endian), STI(STI),
-        isThumbMode(STI.getTargetTriple().isThumb()) {}
+  ARMAsmBackend(const Target &T, bool IsThumb, support::endianness Endian)
+      : MCAsmBackend(Endian), isThumbMode(IsThumb) {}
 
   unsigned getNumFixupKinds() const override {
     return ARM::NumTargetFixupKinds;
   }
 
-  // FIXME: this should be calculated per fragment as the STI may be
-  // different.
-  bool hasNOP() const { return STI.getFeatureBits()[ARM::HasV6T2Ops]; }
+  bool hasNOP(const MCSubtargetInfo *STI) const {
+    return STI->getFeatureBits()[ARM::HasV6T2Ops];
+  }
 
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
 
   bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
                              const MCValue &Target) override;
 
   unsigned adjustFixupValue(const MCAssembler &Asm, const MCFixup &Fixup,
                             const MCValue &Target, uint64_t Value,
public:
 
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override;
 
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override;
 
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 
   void handleAssemblerFlag(MCAssemblerFlag Flag) override;
 
   unsigned getPointerSize() const { return 4; }
   bool isThumb() const { return isThumbMode; }
   void setIsThumb(bool it) { isThumbMode = it; }
 };
 } // end namespace llvm
 
 #endif

lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

void ARMAsmBackend::relaxInstruction(const MCInst &Inst,
   }
 
   // The rest of instructions we're relaxing have the same operands.
   // We just need to update to the proper opcode.
   Res = Inst;
   Res.setOpcode(RelaxedOp);
 }
 
-bool ARMAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+
+bool ARMAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                 const MCSubtargetInfo *STI) const {
   const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
   const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
   const uint32_t ARMv4_NopEncoding = 0xe1a00000;   // using MOV r0,r0
   const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
   if (isThumb()) {
     const uint16_t nopEncoding =
-        hasNOP() ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding;
+        hasNOP(STI) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding;
     uint64_t NumNops = Count / 2;
     for (uint64_t i = 0; i != NumNops; ++i)
       support::endian::write(OS, nopEncoding, Endian);
     if (Count & 1)
       OS << '\0';
     return true;
   }
   // ARM mode
   const uint32_t nopEncoding =
-      hasNOP() ? ARMv6T2_NopEncoding : ARMv4_NopEncoding;
+      hasNOP(STI) ? ARMv6T2_NopEncoding : ARMv4_NopEncoding;
   uint64_t NumNops = Count / 4;
   for (uint64_t i = 0; i != NumNops; ++i)
     support::endian::write(OS, nopEncoding, Endian);
   // FIXME: should this function return false when unable to write exactly
   // 'Count' bytes with NOP encodings?
   switch (Count % 4) {
   default:
     break; // No leftover bytes to write
static MCAsmBackend *createARMAsmBackend(const Target &T,
                                          const MCTargetOptions &Options,
                                          support::endianness Endian) {
   const Triple &TheTriple = STI.getTargetTriple();
   switch (TheTriple.getObjectFormat()) {
   default:
     llvm_unreachable("unsupported object format");
   case Triple::MachO: {
     MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TheTriple.getArchName());
-    return new ARMAsmBackendDarwin(T, STI, MRI, CS);
+    return new ARMAsmBackendDarwin(T, STI.getTargetTriple().isThumb(), MRI, CS);
   }
   case Triple::COFF:
     assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
-    return new ARMAsmBackendWinCOFF(T, STI);
+    return new ARMAsmBackendWinCOFF(T, STI.getTargetTriple().isThumb());
   case Triple::ELF:
     assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
     uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
-    return new ARMAsmBackendELF(T, STI, OSABI, Endian);
+    return new ARMAsmBackendELF(T, STI.getTargetTriple().isThumb(), OSABI,
+                                Endian);
   }
 }
 
 MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
                                           const MCSubtargetInfo &STI,
                                           const MCRegisterInfo &MRI,
                                           const MCTargetOptions &Options) {
   return createARMAsmBackend(T, STI, MRI, Options, support::little);
 }
 
 MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
                                           const MCSubtargetInfo &STI,
                                           const MCRegisterInfo &MRI,
                                           const MCTargetOptions &Options) {
   return createARMAsmBackend(T, STI, MRI, Options, support::big);
 }

lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h

 #include "llvm/BinaryFormat/MachO.h"
 #include "llvm/MC/MCObjectWriter.h"
 
 namespace llvm {
 class ARMAsmBackendDarwin : public ARMAsmBackend {
   const MCRegisterInfo &MRI;
 public:
   const MachO::CPUSubTypeARM Subtype;
-  ARMAsmBackendDarwin(const Target &T, const MCSubtargetInfo &STI,
-                      const MCRegisterInfo &MRI, MachO::CPUSubTypeARM st)
-      : ARMAsmBackend(T, STI, support::little), MRI(MRI), Subtype(st) {}
+  ARMAsmBackendDarwin(const Target &T, bool IsThumb, const MCRegisterInfo &MRI,
+                      MachO::CPUSubTypeARM st)
+      : ARMAsmBackend(T, IsThumb, support::little), MRI(MRI),
+        Subtype(st) {}
 
   std::unique_ptr<MCObjectTargetWriter>
   createObjectTargetWriter() const override {
     return createARMMachObjectWriter(/*Is64Bit=*/false, MachO::CPU_TYPE_ARM,
                                      Subtype);
   }
 
   uint32_t generateCompactUnwindEncoding(
       ArrayRef<MCCFIInstruction> Instrs) const override;
 };
 } // end namespace llvm
 
 #endif

lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h

 #include "llvm/MC/MCObjectWriter.h"
 
 using namespace llvm;
 
 namespace {
 class ARMAsmBackendELF : public ARMAsmBackend {
 public:
   uint8_t OSABI;
-  ARMAsmBackendELF(const Target &T, const MCSubtargetInfo &STI, uint8_t OSABI,
+  ARMAsmBackendELF(const Target &T, bool IsThumb, uint8_t OSABI,
                    support::endianness Endian)
-      : ARMAsmBackend(T, STI, Endian), OSABI(OSABI) {}
+      : ARMAsmBackend(T, IsThumb, Endian), OSABI(OSABI) {}
 
   std::unique_ptr<MCObjectTargetWriter>
   createObjectTargetWriter() const override {
     return createARMELFObjectWriter(OSABI);
   }
 };
 }
 
 #endif

lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h

 
 #include "ARMAsmBackend.h"
 #include "llvm/MC/MCObjectWriter.h"
 using namespace llvm;
 
 namespace {
 class ARMAsmBackendWinCOFF : public ARMAsmBackend {
 public:
-  ARMAsmBackendWinCOFF(const Target &T, const MCSubtargetInfo &STI)
-      : ARMAsmBackend(T, STI, support::little) {}
+  ARMAsmBackendWinCOFF(const Target &T, bool IsThumb)
+      : ARMAsmBackend(T, IsThumb, support::little) {}
   std::unique_ptr<MCObjectTargetWriter>
   createObjectTargetWriter() const override {
     return createARMWinCOFFObjectWriter(/*Is64Bit=*/false);
   }
 };
 }
 
 #endif

lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp

public:
   bool mayNeedRelaxation(const MCInst &Inst,
                          const MCSubtargetInfo &STI) const override {
     return false;
   }
 
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override {}
 
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 };
 
 } // end anonymous namespace
 
-bool BPFAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+bool BPFAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                 const MCSubtargetInfo *STI) const {
   if ((Count % 8) != 0)
     return false;
 
   for (uint64_t i = 0; i < Count; i += 8)
     support::endian::write<uint64_t>(OS, 0x15000000, Endian);
 
   return true;
 }

lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp

for (auto &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
       }
       // now copy over the original instruction(the one we may have extended)
       Res.addOperand(MCOperand::createInst(I.getInst()));
     }
     (void)Update;
     assert(Update && "Didn't find relaxation target");
   }
 
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override {
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override {
     static const uint32_t Nopcode  = 0x7f000000, // Hard-coded NOP.
                           ParseIn  = 0x00004000, // In packet parse-bits.
                           ParseEnd = 0x0000c000; // End of packet parse-bits.
 
     while(Count % HEXAGON_INSTR_SIZE) {
       LLVM_DEBUG(dbgs() << "Alignment not a multiple of the instruction size:"
                         << Count % HEXAGON_INSTR_SIZE << "/"
                         << HEXAGON_INSTR_SIZE << "\n");

lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp

bool mayNeedRelaxation(const MCInst & /*Inst*/,
                          const MCSubtargetInfo &STI) const override {
     return false;
   }
 
   void relaxInstruction(const MCInst & /*Inst*/,
                         const MCSubtargetInfo & /*STI*/,
                         MCInst & /*Res*/) const override {}
 
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 };
 
-bool LanaiAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+bool LanaiAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                   const MCSubtargetInfo *STI) const {
   if ((Count % 4) != 0)
     return false;
 
   for (uint64_t i = 0; i < Count; i += 4)
     OS.write("\x15\0\0\0", 4);
 
   return true;
 }

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h

public:
   /// \param Inst - The instruction to relax, which may be the same
   /// as the output.
   /// \param [out] Res On return, the relaxed instruction.
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override {}
 
   /// @}
 
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 
   bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
                              const MCValue &Target) override;
 
   bool isMicroMips(const MCSymbol *Sym) const override;
 }; // class MipsAsmBackend
 
 } // namespace
 
 #endif

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

getFixupKindInfo(MCFixupKind Kind) const {
   return BigEndianInfos[Kind - FirstTargetFixupKind];
 }
 
 /// WriteNopData - Write an (optimal) nop sequence of Count bytes
 /// to the given output. If the target cannot generate such a sequence,
 /// it should return an error.
 ///
 /// \return - True on success.
-bool MipsAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+bool MipsAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                  const MCSubtargetInfo *STI) const {
   // Check for a less than instruction size number of bytes
   // FIXME: 16 bit instructions are not handled yet here.
   // We shouldn't be using a hard coded number for instruction size.
 
   // If the count is not 4-byte aligned, we must be writing data into the text
   // section (otherwise we have unaligned instructions, and thus have far
   // bigger problems), so just write zeros instead.
   OS.write_zeros(Count);

lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

public:
   }
 
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override {
     // FIXME.
     llvm_unreachable("relaxInstruction() unimplemented");
   }
 
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override {
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override {
     uint64_t NumNops = Count / 4;
     for (uint64_t i = 0; i != NumNops; ++i)
       support::endian::write<uint32_t>(OS, 0x60000000, Endian);
 
     OS.write_zeros(Count % 4);
 
     return true;
   }

lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h

public:
 
   bool mayNeedRelaxation(const MCInst &Inst,
                          const MCSubtargetInfo &STI) const override;
   unsigned getRelaxedOpcode(unsigned Op) const;
 
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override;
 
-
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 };
-}
+} // namespace llvm
 
 #endif

lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
   }
 }
 
 bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst,
                                         const MCSubtargetInfo &STI) const {
   return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode();
 }
 
-bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
-  bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC];
+bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                   const MCSubtargetInfo *STI) const {
+  bool HasStdExtC = STI->getFeatureBits()[RISCV::FeatureStdExtC];
   unsigned MinNopLen = HasStdExtC ? 2 : 4;
 
   if ((Count % MinNopLen) != 0)
     return false;
 
   // The canonical nop on RISC-V is addi x0, x0, 0.
   uint64_t Nop32Count = Count / 4;
   for (uint64_t i = Nop32Count; i != 0; --i)

lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

bool fixupNeedsRelaxation(const MCFixup &Fixup,
       return false;
     }
     void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                           MCInst &Res) const override {
       // FIXME.
       llvm_unreachable("relaxInstruction() unimplemented");
     }
 
-    bool writeNopData(raw_ostream &OS, uint64_t Count) const override {
+    bool writeNopData(raw_ostream &OS, uint64_t Count,
+                      const MCSubtargetInfo *STI) const override {
       // Cannot emit NOP with size not multiple of 32 bits.
       if (Count % 4 != 0)
         return false;
 
       uint64_t NumNops = Count / 4;
       for (uint64_t i = 0; i != NumNops; ++i)
         support::endian::write<uint32_t>(OS, 0x01000000, Endian);
 

lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp

bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *Fragment,
                             const MCAsmLayout &Layout) const override {
     return false;
   }
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override {
     llvm_unreachable("SystemZ does do not have assembler relaxation");
   }
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
   std::unique_ptr<MCObjectTargetWriter>
   createObjectTargetWriter() const override {
     return createSystemZObjectWriter(OSABI);
   }
 };
 } // end anonymous namespace
 
 const MCFixupKindInfo &
if (BitSize < 64)
     Value &= ((uint64_t)1 << BitSize) - 1;
   unsigned ShiftValue = (Size * 8) - 8;
   for (unsigned I = 0; I != Size; ++I) {
     Data[Offset + I] |= uint8_t(Value >> ShiftValue);
     ShiftValue -= 8;
   }
 }
 
-bool SystemZMCAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+bool SystemZMCAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                       const MCSubtargetInfo *STI) const {
   for (uint64_t I = 0; I != Count; ++I)
     OS << '\x7';
   return true;
 }
 
 MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T,
                                               const MCSubtargetInfo &STI,
                                               const MCRegisterInfo &MRI,
                                               const MCTargetOptions &Options) {
   uint8_t OSABI =
       MCELFObjectTargetWriter::getOSABI(STI.getTargetTriple().getOS());
   return new SystemZMCAsmBackend(OSABI);
 }

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp

public:
   bool mayNeedRelaxation(const MCInst &Inst,
                          const MCSubtargetInfo &STI) const override {
     return false;
   }
 
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override {}
 
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 };
 
 const MCFixupKindInfo &
 WebAssemblyAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
   const static MCFixupKindInfo Infos[WebAssembly::NumTargetFixupKinds] = {
       // This table *must* be in the order that the fixup_* kinds are defined in
       // WebAssemblyFixupKinds.h.
       //
       // Name                     Offset (bits) Size (bits)     Flags
       {"fixup_code_sleb128_i32", 0, 5 * 8, 0},
       {"fixup_code_sleb128_i64", 0, 10 * 8, 0},
       {"fixup_code_uleb128_i32", 0, 5 * 8, 0},
   };
 
   if (Kind < FirstTargetFixupKind)
     return MCAsmBackend::getFixupKindInfo(Kind);
 
   assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
          "Invalid kind!");
   return Infos[Kind - FirstTargetFixupKind];
 }
 
-bool WebAssemblyAsmBackend::writeNopData(raw_ostream &OS,
-                                         uint64_t Count) const {
+bool WebAssemblyAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                         const MCSubtargetInfo *STI) const {
   for (uint64_t i = 0; i < Count; ++i)
     OS << char(WebAssembly::Nop);
 
   return true;
 }
 
 void WebAssemblyAsmBackend::applyFixup(const MCAssembler &Asm,
                                        const MCFixup &Fixup,

lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

 class X86ELFObjectWriter : public MCELFObjectTargetWriter {
 public:
   X86ELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine,
                      bool HasRelocationAddend, bool foobar)
     : MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {}
 };
 
 class X86AsmBackend : public MCAsmBackend {
-  const MCSubtargetInfo &STI;
 public:
-  X86AsmBackend(const Target &T, const MCSubtargetInfo &STI)
-      : MCAsmBackend(support::little), STI(STI) {}
+  X86AsmBackend(const Target &T)
+      : MCAsmBackend(support::little) {}
 
   unsigned getNumFixupKinds() const override {
     return X86::NumTargetFixupKinds;
   }
 
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
     const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
         {"reloc_riprel_4byte", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
public:
 
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override;
 
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override;
 
-  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count,
+                    const MCSubtargetInfo *STI) const override;
 };
 } // end anonymous namespace
 
 static unsigned getRelaxedOpcodeBranch(const MCInst &Inst, bool is16BitMode) {
   unsigned Op = Inst.getOpcode();
   switch (Op) {
   default:
     return Op;
void X86AsmBackend::relaxInstruction(const MCInst &Inst,
 
   Res = Inst;
   Res.setOpcode(RelaxedOp);
 }
 
 /// Write a sequence of optimal nops to the output, covering \p Count
 /// bytes.
 /// \return - true on success, false on failure
-bool X86AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+bool X86AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                 const MCSubtargetInfo *STI) const {
   static const char Nops[10][11] = {
     // nop
     "\x90",
     // xchg %ax,%ax
     "\x66\x90",
     // nopl (%[re]ax)
     "\x0f\x1f\x00",
     // nopl 0(%[re]ax)
static const char Nops[10][11] = {
     // nopw 0L(%[re]ax,%[re]ax,1)
     "\x66\x0f\x1f\x84\x00\x00\x00\x00\x00",
     // nopw %cs:0L(%[re]ax,%[re]ax,1)
     "\x66\x2e\x0f\x1f\x84\x00\x00\x00\x00\x00",
   };
 
   // This CPU doesn't support long nops. If needed add more.
   // FIXME: We could generated something better than plain 0x90.
-  if (!STI.getFeatureBits()[X86::FeatureNOPL]) {
+  if (!(*STI).getFeatureBits()[X86::FeatureNOPL]) {
     for (uint64_t i = 0; i < Count; ++i)
       OS << '\x90';
     return true;
   }
 
   // 15-bytes is the longest single NOP instruction, but 10-bytes is
   // commonly the longest that can be efficiently decoded.
   uint64_t MaxNopLength = 10;
-  if (STI.getFeatureBits()[X86::ProcIntelSLM])
+  if ((*STI).getFeatureBits()[X86::ProcIntelSLM])
     MaxNopLength = 7;
-  else if (STI.getFeatureBits()[X86::FeatureFast15ByteNOP])
+  else if ((*STI).getFeatureBits()[X86::FeatureFast15ByteNOP])
     MaxNopLength = 15;
-  else if (STI.getFeatureBits()[X86::FeatureFast11ByteNOP])
+  else if ((*STI).getFeatureBits()[X86::FeatureFast11ByteNOP])
     MaxNopLength = 11;
 
   // Emit as many MaxNopLength NOPs as needed, then emit a NOP of the remaining
   // length.
   do {
     const uint8_t ThisNopLength = (uint8_t) std::min(Count, MaxNopLength);
     const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
     for (uint8_t i = 0; i < Prefixes; i++)

 
 /* *** */
 
 namespace {
 
 class ELFX86AsmBackend : public X86AsmBackend {
 public:
   uint8_t OSABI;
-  ELFX86AsmBackend(const Target &T, uint8_t OSABI, const MCSubtargetInfo &STI)
-      : X86AsmBackend(T, STI), OSABI(OSABI) {}
+  ELFX86AsmBackend(const Target &T, uint8_t OSABI)
+      : X86AsmBackend(T), OSABI(OSABI) {}
 };
 
 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
 public:
-  ELFX86_32AsmBackend(const Target &T, uint8_t OSABI,
-                      const MCSubtargetInfo &STI)
-    : ELFX86AsmBackend(T, OSABI, STI) {}
+  ELFX86_32AsmBackend(const Target &T, uint8_t OSABI)
+    : ELFX86AsmBackend(T, OSABI) {}
 
   std::unique_ptr<MCObjectTargetWriter>
   createObjectTargetWriter() const override {
     return createX86ELFObjectWriter(/*IsELF64*/ false, OSABI, ELF::EM_386);
   }
 };
 
 class ELFX86_X32AsmBackend : public ELFX86AsmBackend {
 public:
-  ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI,
-                       const MCSubtargetInfo &STI)
-      : ELFX86AsmBackend(T, OSABI, STI) {}
+  ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI)
+      : ELFX86AsmBackend(T, OSABI) {}
 
   std::unique_ptr<MCObjectTargetWriter>
   createObjectTargetWriter() const override {
     return createX86ELFObjectWriter(/*IsELF64*/ false, OSABI,
                                     ELF::EM_X86_64);
   }
 };
 
 class ELFX86_IAMCUAsmBackend : public ELFX86AsmBackend {
 public:
-  ELFX86_IAMCUAsmBackend(const Target &T, uint8_t OSABI,
-                         const MCSubtargetInfo &STI)
-      : ELFX86AsmBackend(T, OSABI, STI) {}
+  ELFX86_IAMCUAsmBackend(const Target &T, uint8_t OSABI)
+      : ELFX86AsmBackend(T, OSABI) {}
 
   std::unique_ptr<MCObjectTargetWriter>
   createObjectTargetWriter() const override {
     return createX86ELFObjectWriter(/*IsELF64*/ false, OSABI,
                                     ELF::EM_IAMCU);
   }
 };
 
 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
 public:
-  ELFX86_64AsmBackend(const Target &T, uint8_t OSABI,
-                      const MCSubtargetInfo &STI)
-    : ELFX86AsmBackend(T, OSABI, STI) {}
+  ELFX86_64AsmBackend(const Target &T, uint8_t OSABI)
+    : ELFX86AsmBackend(T, OSABI) {}
 
   std::unique_ptr<MCObjectTargetWriter>
   createObjectTargetWriter() const override {
     return createX86ELFObjectWriter(/*IsELF64*/ true, OSABI, ELF::EM_X86_64);
   }
 };
 
 class WindowsX86AsmBackend : public X86AsmBackend {
   bool Is64Bit;
 
 public:
-  WindowsX86AsmBackend(const Target &T, bool is64Bit,
-                       const MCSubtargetInfo &STI)
-    : X86AsmBackend(T, STI)
+  WindowsX86AsmBackend(const Target &T, bool is64Bit)
+    : X86AsmBackend(T)
     , Is64Bit(is64Bit) {
   }
 
   Optional<MCFixupKind> getFixupKind(StringRef Name) const override {
     return StringSwitch<Optional<MCFixupKind>>(Name)
         .Case("dir32", FK_Data_4)
         .Case("secrel32", FK_SecRel_4)
         .Case("secidx", FK_SecRel_2)
uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned RegCount) const {
     }
 
     assert((permutationEncoding & 0x3FF) == permutationEncoding &&
            "Invalid compact register encoding!");
     return permutationEncoding;
   }
 
 public:
-  DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                      const MCSubtargetInfo &STI, bool Is64Bit)
-    : X86AsmBackend(T, STI), MRI(MRI), Is64Bit(Is64Bit) {
+  DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, bool Is64Bit)
+    : X86AsmBackend(T), MRI(MRI), Is64Bit(Is64Bit) {
     memset(SavedRegs, 0, sizeof(SavedRegs));
     OffsetSize = Is64Bit ? 8 : 4;
     MoveInstrSize = Is64Bit ? 3 : 2;
     StackDivide = Is64Bit ? 8 : 4;
   }
 };
 
 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
 public:
   DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
                          const MCSubtargetInfo &STI)
-      : DarwinX86AsmBackend(T, MRI, STI, false) {}
+      : DarwinX86AsmBackend(T, MRI, false) {}
 
   std::unique_ptr<MCObjectTargetWriter>
   createObjectTargetWriter() const override {
     return createX86MachObjectWriter(/*Is64Bit=*/false,
                                      MachO::CPU_TYPE_I386,
                                      MachO::CPU_SUBTYPE_I386_ALL);
   }
 
   /// Generate the compact unwind encoding for the CFI instructions.
   uint32_t generateCompactUnwindEncoding(
                              ArrayRef<MCCFIInstruction> Instrs) const override {
     return generateCompactUnwindEncodingImpl(Instrs);
   }
 };
 
 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
   const MachO::CPUSubTypeX86 Subtype;
 public:
   DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                         const MCSubtargetInfo &STI, MachO::CPUSubTypeX86 st)
-      : DarwinX86AsmBackend(T, MRI, STI, true), Subtype(st) {}
+                         MachO::CPUSubTypeX86 st)
+      : DarwinX86AsmBackend(T, MRI, true), Subtype(st) {}
 
   std::unique_ptr<MCObjectTargetWriter>
   createObjectTargetWriter() const override {
     return createX86MachObjectWriter(/*Is64Bit=*/true, MachO::CPU_TYPE_X86_64,
                                      Subtype);
   }
 
   /// Generate the compact unwind encoding for the CFI instructions.
MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
                                            const MCSubtargetInfo &STI,
                                            const MCRegisterInfo &MRI,
                                            const MCTargetOptions &Options) {
   const Triple &TheTriple = STI.getTargetTriple();
   if (TheTriple.isOSBinFormatMachO())
     return new DarwinX86_32AsmBackend(T, MRI, STI);
 
   if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF())
-    return new WindowsX86AsmBackend(T, false, STI);
+    return new WindowsX86AsmBackend(T, false);
 
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
 
   if (TheTriple.isOSIAMCU())
-    return new ELFX86_IAMCUAsmBackend(T, OSABI, STI);
+    return new ELFX86_IAMCUAsmBackend(T, OSABI);
 
-  return new ELFX86_32AsmBackend(T, OSABI, STI);
+  return new ELFX86_32AsmBackend(T, OSABI);
 }
 
 MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
                                            const MCSubtargetInfo &STI,
                                            const MCRegisterInfo &MRI,
                                            const MCTargetOptions &Options) {
   const Triple &TheTriple = STI.getTargetTriple();
   if (TheTriple.isOSBinFormatMachO()) {
     MachO::CPUSubTypeX86 CS =
         StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName())
             .Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H)
             .Default(MachO::CPU_SUBTYPE_X86_64_ALL);
-    return new DarwinX86_64AsmBackend(T, MRI, STI, CS);
+    return new DarwinX86_64AsmBackend(T, MRI, CS);
   }
 
   if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF())
-    return new WindowsX86AsmBackend(T, true, STI);
+    return new WindowsX86AsmBackend(T, true);
 
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
 
   if (TheTriple.getEnvironment() == Triple::GNUX32)
-    return new ELFX86_X32AsmBackend(T, OSABI, STI);
-  return new ELFX86_64AsmBackend(T, OSABI, STI);
+    return new ELFX86_X32AsmBackend(T, OSABI);
+  return new ELFX86_64AsmBackend(T, OSABI);
 }

test/CodeGen/ARM/subtarget-align.ll

+; RUN: llc < %s -mtriple=arm-linux-gnueabihf -filetype=obj -o - | \
+; RUN:    llvm-objdump -triple=armv7 -no-show-raw-insn -disassemble - | \
+; RUN:       FileCheck %s
+
+; Expect architectural nop to be used between func2 and func3 but not func1
+; and func2 due to lack of subtarget support in func2.
+
+define i32 @func1() #0 align 16 {
+entry:
+  ret i32 0
+}
+
+define i32 @func2() #1 align 16 {
+entry:
+  ret i32 0
+}
+
+define i32 @func3() #0 align 16 {
+entry:
+  ret i32 0
+}
+
+attributes #0 = { "target-cpu"="generic" "target-features"="+armv7-a,+dsp,+neon,+vfp3,-thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "target-cpu"="arm7tdmi" "target-features"="+armv4t" "use-soft-float"="true" }
+
+; CHECK: Disassembly of section .text:
+; CHECK-NEXT: func1:
+; CHECK-NEXT:        0:        mov     r0, #0
+; CHECK-NEXT:        4:        bx      lr
+; CHECK-NEXT:        8:        mov     r0, r0
+; CHECK-NEXT:        c:        mov     r0, r0
+
+; CHECK: func2:
+; CHECK-NEXT:       10:        mov     r0, #0
+; CHECK-NEXT:       14:        bx      lr
+; CHECK-NEXT:       18:        nop
+; CHECK-NEXT:       1c:        nop
+
+; CHECK: func3:
+; CHECK-NEXT:       20:        mov     r0, #0
+; CHECK-NEXT:       24:        bx      lr

test/MC/ARM/subtarget-nop.s

+# RUN: llvm-mc < %s -triple arm-linux-gnueabihf -filetype=obj -o - \
+# RUN: | llvm-objdump -no-show-raw-insn -triple armv7 -disassemble - | FileCheck %s
+
+# Check that the architectural nop is only produced for subtargets that support
+# it. This includes nop padding for alignment.
+ .syntax unified
+ .arch armv6
+foo:
+ mov r1, r0
+ nop
+ .p2align 4
+ bx lr
+
+ .arch armv7-a
+bar:
+ mov r1, r0
+ nop
+ .p2align 4
+ bx lr
+
+ .arch armv4t
+baz:
+ mov r1, r0
+ nop
+ .p2align 4
+ bx lr
+
+# CHECK: foo:
+# CHECK-NEXT:        0:        mov     r1, r0
+# CHECK-NEXT:        4:        mov     r0, r0
+# CHECK-NEXT:        8:        mov     r0, r0
+# CHECK-NEXT:        c:        mov     r0, r0
+# CHECK-NEXT:       10:        bx      lr
+
+# CHECK: bar:
+# CHECK-NEXT:       14:        mov     r1, r0
+# CHECK-NEXT:       18:        nop
+# CHECK-NEXT:       1c:        nop
+# CHECK-NEXT:       20:        bx      lr
+
+# CHECK: baz:
+# CHECK-NEXT:       24:        mov     r1, r0
+# CHECK-NEXT:       28:        mov     r0, r0
+# CHECK-NEXT:       2c:        mov     r0, r0
+# CHECK-NEXT:       30:        bx      lr