[RISCV] Add support for XCValu extension in CV32E40P

[realqhc]

Summary

Implement XCValu intrinsics for CV32E40P according to the specification.

This is a commit of the patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, Nandni Jamnadas, Serkan Muhcu, @jeremybennett, @lewis-revill, @liaolucy, @simoncook, @xmj

[kito-cheng]

You might need to add extension in RISCVISAInfo.cpp for -march support?

llvm/docs/RISCVUsage.rst

275

@jeremybennett say it's 1.0 here?

https://github.com/riscv-non-isa/riscv-toolchain-conventions/blob/master/README.mkd#list-of-vendor-extensions

[realqhc]

llvm/docs/RISCVUsage.rst

275

This might need to be updated as if you check https://github.com/openhwgroup/cv32e40p/releases, there has been release of v1.3.2 last week.

[realqhc]

In D153748#4467842, @kito-cheng wrote:

You might need to add extension in RISCVISAInfo.cpp for -march support?

We plan to add extension to RISCVISAInfo.cpp in the second batch of upstreaming patches along with the LLVM Intrinsics for the extension.

[kito-cheng]

llvm/docs/RISCVUsage.rst

275

I saw binutils from openhwgroup still using 1.0[1], and that patch is committed 5 days ago? I am not intend to block this patch, but I would like to figure out what's the right version for those extension.

[1] https://github.com/openhwgroup/corev-binutils-gdb/commit/9b120787924eed13455de3062523539dc39bc7f8

[craig.topper]

llvm/docs/RISCVUsage.rst

275

The cv.mac part was copied from another description and does not apply here.

[realqhc]

llvm/docs/RISCVUsage.rst

275

Should I change it to cv. like XCVbitmanip or do you think cv.alu is more appropriate here?

[liaolucy]

llvm/docs/RISCVUsage.rst

275

Thanks, about the version, we have a group meeting on Friday, we will confirm it internally and come back to synchronize the information

[realqhc]

fix error in riscvusage.rst to reflect actual prefix of XCValu extension instructions.

[jeremybennett]

llvm/docs/RISCVUsage.rst

275

The document referred to is the entire specification of the CV32E40P, of which its ISA extensions are just a small section. The main document is subject to numerous small changes, and bumps its minor version and patch version from time to time. However the ISA extensions from a software perspective have a single version, 1.0, which is the only version that will be supported by the tool chain.

I'm open to advice on how we should handle this. I note that XCVbitmanip and XCVmac have both been merged using the full document reference (1.3.1). It might be clearer to reference the software spec on ISA extension naming, which explicitly notes that versioning is *not* supported for CORE-V: https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-isa-extension-naming.md

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

207

Can we name all of these CVInst* instead of RVInst* to match some of the earlier classes like CVBitManipRII?

227

Can this inherit from RVInstR which will simplify a lot of the body.

257

Can this inherit from RVInstR with a let rs2 = 0b00000?

[craig.topper]

In D153748#4470438, @realqhc wrote:

In D153748#4467842, @kito-cheng wrote:

You might need to add extension in RISCVISAInfo.cpp for -march support?

We plan to add extension to RISCVISAInfo.cpp in the second batch of upstreaming patches along with the LLVM Intrinsics for the extension.

I think the assembler also needs to RISCVISAInfo.cpp changes to print the correct version for the ELF attributes to list what extensions are enabled in the binary.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

348

Please wrap this to 80 columns and in general try to keep lines close to 80 columns.

[realqhc]

In D153748#4472470, @craig.topper wrote:

In D153748#4470438, @realqhc wrote:

In D153748#4467842, @kito-cheng wrote:

You might need to add extension in RISCVISAInfo.cpp for -march support?

We plan to add extension to RISCVISAInfo.cpp in the second batch of upstreaming patches along with the LLVM Intrinsics for the extension.

I think the assembler also needs to RISCVISAInfo.cpp changes to print the correct version for the ELF attributes to list what extensions are enabled in the binary.

Thanks for the suggesion, will get the versioning updated after discussion with core-v.

[realqhc]

rename RVInst to CVInst, add core-v to instruction description, use RVInstR to simplify CVInstALU_rr and CVInstAlu_r

[realqhc]

update tests

[jeremybennett]

llvm/docs/RISCVUsage.rst

275

Just to clarify. The CORE-V ISA extensions do not support versioning, which in a RISC-V context means the version is always 1.0.

[realqhc]

update ISA version accordingly

[craig.topper]

llvm/lib/Target/RISCV/RISCVFeatures.td

795

Can you put CORE-V in this string too

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

256

I would have expected cv.sle and cv.sleu for these mnemonics. The t feels out of place. In the base isa for slt/sltu it's part of "less than". Is the instruction name here "set less equal than" instead "set less than or equal"?

The vector spec uses "sle" and "sleu"

Is the spec frozen?

283

I'm surprised this instruction exists. Isn't this andi rs1, 255?

328

Wrap to 80 columns. by putting (ins GPR:$rd, GPR:$rs1, GPR:$rs2), on a new line.

[realqhc]

fix the problem of code being wrongly wrapped to 120 columns

[realqhc]

fix previous errorneus update

[realqhc]

applied general cleanup like in D155283, rebase.

[realqhc]

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

256

The current naming is copied from PULP RI5CY and it is close to be frozen[1].
[1]: https://github.com/openhwgroup/cv32e40p/issues/833

283

I believe this is also a leftover from PULP RI5CY.

[realqhc]

remove Opcode to reflect changes

[craig.topper]

LGTM

llvm/docs/RISCVUsage.rst

277

Keep this with the other XCV extensions

[realqhc]

Simplify tablegen for alu

[realqhc]

move xcvalu in RISCVUsage.rst so that it is with other XCV extensions

llvm/docs/RISCVUsage.rst

 
 ``XCVbitmanip``
   LLVM implements `version 1.0.0 of the CORE-V Bit Manipulation custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group.  All instructions are prefixed with `cv.` as described in the specification.
 
 ``XCVmac``
   LLVM implements `version 1.0.0 of the CORE-V Multiply-Accumulate (MAC) custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/4f024fe4b15a68b76615b0630c07a6745c620da7/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group.  All instructions are prefixed with `cv.mac` as described in the specification. These instructions are only available for riscv32 at this time.
 
 ``XSfcie``
   LLVM implements `version 1.0.0 of the SiFive Custom Instruction Extension (CIE) Software Specification <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.  All custom instruction are added as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for S76 processor at this time.
+
+``XCValu``
+  LLVM implements `version 1.0.0 of the Core-V ALU custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/4f024fe4b15a68b76615b0630c07a6745c620da7/docs/source/instruction_set_extensions.rst>`_ by Core-V.  All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.

llvm/lib/Support/RISCVISAInfo.cpp

static const RISCVSupportedExtension SupportedExtensions[] = {
 
     {"svinval", RISCVExtensionVersion{1, 0}},
     {"svnapot", RISCVExtensionVersion{1, 0}},
     {"svpbmt", RISCVExtensionVersion{1, 0}},
 
     {"v", RISCVExtensionVersion{1, 0}},
 
     // vendor-defined ('X') extensions
+    {"xcvalu", RISCVExtensionVersion{1, 0}},
     {"xcvbitmanip", RISCVExtensionVersion{1, 0}},
     {"xcvmac", RISCVExtensionVersion{1, 0}},
     {"xsfcie", RISCVExtensionVersion{1, 0}},
     {"xsfvcp", RISCVExtensionVersion{1, 0}},
     {"xtheadba", RISCVExtensionVersion{1, 0}},
     {"xtheadbb", RISCVExtensionVersion{1, 0}},
     {"xtheadbs", RISCVExtensionVersion{1, 0}},
     {"xtheadcmo", RISCVExtensionVersion{1, 0}},

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
                           "SiFive VCIX custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcie, DecoderTableXSfcie32,
                           "Sifive CIE custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
                           DecoderTableXCVbitmanip32,
                           "CORE-V Bit Manipulation custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32,
                           "CORE-V MAC custom opcode table");
+    TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32,
+                          "CORE-V ALU custom opcode table");
     TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
 
     return MCDisassembler::Fail;
   }
 
   if (Bytes.size() < 2) {
     Size = 0;
     return MCDisassembler::Fail;

llvm/lib/Target/RISCV/RISCVFeatures.td

 
 def FeatureVendorXCVmac
     : SubtargetFeature<"xcvmac", "HasVendorXCVmac", "true",
                        "'XCVmac' (CORE-V Multiply-Accumulate)">;
 def HasVendorXCVmac : Predicate<"Subtarget->hasVendorXCVmac()">,
                                 AssemblerPredicate<(all_of FeatureVendorXCVmac),
                                 "'XCVmac' (CORE-V Multiply-Accumulate)">;
 
+def FeatureVendorXCValu
+    : SubtargetFeature<"xcvalu", "HasVendorXCValu", "true",
+                       "'XCValu' (CORE-V ALU Operations)">;
+def HasVendorXCValu : Predicate<"Subtarget->hasVendorXCValu()">,
+                                AssemblerPredicate<(all_of FeatureVendorXCValu),
+                                "'XCValu' (CORE-V ALU Operations)">;
+
 //===----------------------------------------------------------------------===//
 // LLVM specific features and extensions
 //===----------------------------------------------------------------------===//
 
 // Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
 // tuning CPU names.
 def Feature32Bit
     : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

def : InstAlias<"cv.mulhhs $rd1, $rs1, $rs2",
                   (CV_MULHHSN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
 
   // Unsigned 16x16 bit muls
   def : InstAlias<"cv.mulu $rd1, $rs1, $rs2",
                   (CV_MULUN GPR:$rd1,   GPR:$rs1, GPR:$rs2, 0)>;
   def : InstAlias<"cv.mulhhu $rd1, $rs1, $rs2",
                   (CV_MULHHUN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
 } // Predicates = [HasVendorXCVmac, IsRV32]
+
+let DecoderNamespace = "XCValu" in {
+  class CVInstAlu_rri<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
+                      string opcodestr, string argstr>
+      : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+    bits<5> imm5;
+    bits<5> rs2;
+    bits<5> rs1;
+    bits<5> rd;
+
+    let Inst{31-30} = funct2;
+    let Inst{29-25} = imm5;
+    let Inst{24-20} = rs2;
+    let Inst{19-15} = rs1;
+    let Inst{14-12} = funct3;
+    let Inst{11-7} = rd;
+    let Inst{6-0} = OPC_CUSTOM_2.Value;
+  }
+
+  class CVInstAlu_rr<bits<7> funct7, bits<3> funct3, dag outs, dag ins,
+                     string opcodestr, string argstr>
+    : RVInstR<funct7, funct3, OPC_CUSTOM_1, outs, ins, opcodestr, argstr>;
+
+  class CVInstAlu_ri<bits<7> funct7, bits<3> funct3, dag outs, dag ins,
+                     string opcodestr, string argstr>
+      : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+    bits<5> imm5;
+    bits<5> rs1;
+    bits<5> rd;
+
+    let Inst{31-25} = funct7;
+    let Inst{24-20} = imm5;
+    let Inst{19-15} = rs1;
+    let Inst{14-12} = funct3;
+    let Inst{11-7} = rd;
+    let Inst{6-0} = OPC_CUSTOM_1.Value;
+  }
+
+  class CVInstAlu_r<bits<7> funct7, bits<3> funct3, dag outs, dag ins, string opcodestr, string argstr>
+    : RVInstR<funct7, funct3, OPC_CUSTOM_1, outs, ins, opcodestr, argstr> {
+     let rs2 = 0b00000;
+  }
+
+} // DecoderNamespace = "XCValu"
+
+let Predicates = [HasVendorXCValu],
+  hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+  // General ALU Operations
+  def CV_ABS    : CVInstAlu_r<0b0101000, 0b011, (outs GPR:$rd),
+                              (ins GPR:$rs1),
+                              "cv.abs", "$rd, $rs1">,
+                  Sched<[]>;
+  def CV_SLET   : CVInstAlu_rr<0b0101001, 0b011, (outs GPR:$rd),
+                               (ins GPR:$rs1, GPR:$rs2),
+                               "cv.slet", "$rd, $rs1, $rs2">,
+                  Sched<[]>;
+  def CV_SLETU  : CVInstAlu_rr<0b0101010, 0b011, (outs GPR:$rd),
+                               (ins GPR:$rs1, GPR:$rs2),
+                               "cv.sletu", "$rd, $rs1, $rs2">,
+                  Sched<[]>;
+  def CV_MIN    : CVInstAlu_rr<0b0101011, 0b011, (outs GPR:$rd),
+                               (ins GPR:$rs1, GPR:$rs2),
+                               "cv.min", "$rd, $rs1, $rs2">,
+                  Sched<[]>;
+  def CV_MINU   : CVInstAlu_rr<0b0101100, 0b011, (outs GPR:$rd),
+                               (ins GPR:$rs1, GPR:$rs2),
+                               "cv.minu", "$rd, $rs1, $rs2">,
+                  Sched<[]>;
+  def CV_MAX    : CVInstAlu_rr<0b0101101, 0b011, (outs GPR:$rd),
+                               (ins GPR:$rs1, GPR:$rs2),
+                               "cv.max", "$rd, $rs1, $rs2">,
+                  Sched<[]>;
+  def CV_MAXU   : CVInstAlu_rr<0b0101110, 0b011, (outs GPR:$rd),
+                               (ins GPR:$rs1, GPR:$rs2),
+                               "cv.maxu", "$rd, $rs1, $rs2">,
+                  Sched<[]>;
+  def CV_EXTHS  : CVInstAlu_r<0b0110000, 0b011, (outs GPR:$rd),
+                              (ins GPR:$rs1),
+                              "cv.exths", "$rd, $rs1">,
+                  Sched<[]>;
+  def CV_EXTHZ  : CVInstAlu_r<0b0110001, 0b011, (outs GPR:$rd),
+                              (ins GPR:$rs1),
+                              "cv.exthz", "$rd, $rs1">,
+                  Sched<[]>;
+  def CV_EXTBS  : CVInstAlu_r<0b0110010, 0b011, (outs GPR:$rd),
+                              (ins GPR:$rs1),
+                              "cv.extbs", "$rd, $rs1">,
+                  Sched<[]>;
+  def CV_EXTBZ  : CVInstAlu_r<0b0110011, 0b011, (outs GPR:$rd),
+                              (ins GPR:$rs1),
+                              "cv.extbz", "$rd, $rs1">,
+                  Sched<[]>;
+
+  def CV_CLIP   : CVInstAlu_ri<0b0111000, 0b011, (outs GPR:$rd),
+                               (ins GPR:$rs1, uimm5:$imm5),
+                               "cv.clip", "$rd, $rs1, $imm5">,
+                  Sched<[]>;
+  def CV_CLIPU  : CVInstAlu_ri<0b0111001, 0b011, (outs GPR:$rd),
+                               (ins GPR:$rs1, uimm5:$imm5),
+                               "cv.clipu", "$rd, $rs1, $imm5">,
+                  Sched<[]>;
+  def CV_CLIPR  : CVInstAlu_rr<0b0111010, 0b011, (outs GPR:$rd),
+                               (ins GPR:$rs1, GPR:$rs2),
+                               "cv.clipr", "$rd, $rs1, $rs2">,
+                  Sched<[]>;
+  def CV_CLIPUR : CVInstAlu_rr<0b0111011, 0b011, (outs GPR:$rd),
+                               (ins GPR:$rs1, GPR:$rs2),
+                               "cv.clipur", "$rd, $rs1, $rs2">,
+                  Sched<[]>;
+
+  def CV_ADDN   : CVInstAlu_rri<0b00, 0b010, (outs GPR:$rd),
+                                (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                "cv.addn", "$rd, $rs1, $rs2, $imm5">,
+                  Sched<[]>;
+  def CV_ADDUN  : CVInstAlu_rri<0b01, 0b010, (outs GPR:$rd),
+                                (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                "cv.addun", "$rd, $rs1, $rs2, $imm5">,
+                  Sched<[]>;
+  def CV_ADDRN  : CVInstAlu_rri<0b10, 0b010, (outs GPR:$rd),
+                                (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                "cv.addrn", "$rd, $rs1, $rs2, $imm5">,
+                  Sched<[]>;
+  def CV_ADDURN : CVInstAlu_rri<0b11, 0b010, (outs GPR:$rd),
+                                (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                "cv.addurn", "$rd, $rs1, $rs2, $imm5">,
+                  Sched<[]>;
+  def CV_SUBN   : CVInstAlu_rri<0b00, 0b011, (outs GPR:$rd),
+                                (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                "cv.subn", "$rd, $rs1, $rs2, $imm5">,
+                  Sched<[]>;
+  def CV_SUBUN  : CVInstAlu_rri<0b01, 0b011, (outs GPR:$rd),
+                                (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                "cv.subun", "$rd, $rs1, $rs2, $imm5">,
+                  Sched<[]>;
+  def CV_SUBRN  : CVInstAlu_rri<0b10, 0b011, (outs GPR:$rd),
+                                (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                "cv.subrn", "$rd, $rs1, $rs2, $imm5">,
+                  Sched<[]>;
+  def CV_SUBURN : CVInstAlu_rri<0b11, 0b011, (outs GPR:$rd),
+                                (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                "cv.suburn", "$rd, $rs1, $rs2, $imm5">,
+                  Sched<[]>;
+} // Predicates = [HasVendorXCValu],
+  //   hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+let Predicates = [HasVendorXCValu],
+  hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+  Constraints = "$rd = $rd_wb" in {
+  def CV_ADDNR   : CVInstAlu_rr<0b1000000, 0b011, (outs GPR:$rd_wb),
+                                (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+                                "cv.addnr", "$rd, $rs1, $rs2">,
+                   Sched<[]>;
+  def CV_ADDUNR  : CVInstAlu_rr<0b1000001, 0b011, (outs GPR:$rd_wb),
+                                (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+                                "cv.addunr", "$rd, $rs1, $rs2">,
+                   Sched<[]>;
+  def CV_ADDRNR  : CVInstAlu_rr<0b1000010, 0b011, (outs GPR:$rd_wb),
+                                (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+                                "cv.addrnr", "$rd, $rs1, $rs2">,
+                   Sched<[]>;
+  def CV_ADDURNR : CVInstAlu_rr<0b1000011, 0b011, (outs GPR:$rd_wb),
+                                (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+                                "cv.addurnr", "$rd, $rs1, $rs2">,
+                   Sched<[]>;
+  def CV_SUBNR   : CVInstAlu_rr<0b1000100, 0b011, (outs GPR:$rd_wb),
+                                (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+                                "cv.subnr", "$rd, $rs1, $rs2">,
+                   Sched<[]>;
+  def CV_SUBUNR  : CVInstAlu_rr<0b1000101, 0b011, (outs GPR:$rd_wb),
+                                (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+                                "cv.subunr", "$rd, $rs1, $rs2">,
+                   Sched<[]>;
+  def CV_SUBRNR  : CVInstAlu_rr<0b1000110, 0b011, (outs GPR:$rd_wb),
+                                (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+                                "cv.subrnr", "$rd, $rs1, $rs2">,
+                   Sched<[]>;
+  def CV_SUBURNR : CVInstAlu_rr<0b1000111, 0b011, (outs GPR:$rd_wb),
+                                (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+                                "cv.suburnr", "$rd, $rs1, $rs2">,
+                   Sched<[]>;
+
+} // Predicates = [HasVendorXCValu],
+  //   hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+  //   Constraints = "$rd = $rd_wb"

llvm/test/CodeGen/RISCV/attributes.ll

 ; RUN: llc -mtriple=riscv32 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o - | FileCheck --check-prefixes=CHECK,RV32COMBINEINTOZKN %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zbkb,+zbkc,+zbkx,+zksed,+zksh %s -o - | FileCheck --check-prefixes=CHECK,RV32COMBINEINTOZKS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV32SVNAPOT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SVPBMT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV32SVINVAL %s
+; RUN: llc -mtriple=riscv32 -mattr=+xcvalu %s -o - | FileCheck --check-prefix=RV32XCVALU %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xcvbitmanip %s -o - | FileCheck --check-prefix=RV32XCVBITMANIP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xcvmac %s -o - | FileCheck --check-prefix=RV32XCVMAC %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadcmo %s -o - | FileCheck --check-prefix=RV32XTHEADCMO %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadcondmov %s -o - | FileCheck --check-prefix=RV32XTHEADCONDMOV %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadfmemidx %s -o - | FileCheck --check-prefix=RV32XTHEADFMEMIDX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmac %s -o - | FileCheck --check-prefixes=CHECK,RV32XTHEADMAC %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmemidx %s -o - | FileCheck --check-prefix=RV32XTHEADMEMIDX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmempair %s -o - | FileCheck --check-prefix=RV32XTHEADMEMPAIR %s

 ; RV32COMBINEINTOZKN: .attribute 5, "rv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
 ; RV32COMBINEINTOZKS: .attribute 5, "rv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
 ; RV32ZICBOM: .attribute 5, "rv32i2p1_zicbom1p0"
 ; RV32ZICBOZ: .attribute 5, "rv32i2p1_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p1_zicbop1p0"
 ; RV32SVNAPOT: .attribute 5, "rv32i2p1_svnapot1p0"
 ; RV32SVPBMT: .attribute 5, "rv32i2p1_svpbmt1p0"
 ; RV32SVINVAL: .attribute 5, "rv32i2p1_svinval1p0"
+; RV32XCVALU: .attribute 5, "rv32i2p1_xcvalu1p0"
 ; RV32XCVBITMANIP: .attribute 5, "rv32i2p1_xcvbitmanip1p0"
 ; RV32XCVMAC: .attribute 5, "rv32i2p1_xcvmac1p0"
 ; RV32XTHEADCMO: .attribute 5, "rv32i2p1_xtheadcmo1p0"
 ; RV32XTHEADCONDMOV: .attribute 5, "rv32i2p1_xtheadcondmov1p0"
 ; RV32XTHEADFMEMIDX: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xtheadfmemidx1p0"
 ; RV32XTHEADMAC: .attribute 5, "rv32i2p1_xtheadmac1p0"
 ; RV32XTHEADMEMIDX: .attribute 5, "rv32i2p1_xtheadmemidx1p0"
 ; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0"

llvm/test/MC/RISCV/attribute-arch.s

 # CHECK: .attribute     5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfwma0p6_zvl32b1p0"
 
 .attribute arch, "rv64i_xsfcie"
 # CHECK: attribute      5, "rv64i2p1_xsfcie1p0"
 
 .attribute arch, "rv32izacas1p0"
 # CHECK: attribute      5, "rv32i2p1_a2p1_zacas1p0"
 
+.attribute arch, "rv32i_xcvalu"
+# CHECK: attribute      5, "rv32i2p1_xcvalu1p0"
+
 .attribute arch, "rv32i_xcvbitmanip"
 # CHECK: attribute      5, "rv32i2p1_xcvbitmanip1p0"
 
 .attribute arch, "rv32i_xcvmac"
 # CHECK: attribute      5, "rv32i2p1_xcvmac1p0"

llvm/test/MC/RISCV/corev/XCValu-invalid.s

+# RUN: not llvm-mc -triple=riscv32 --mattr=+xcvalu %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
+
+cv.addrnr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addrnr t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addrnr 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addrnr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.addrnr t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addun t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addun t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addun t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addun t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addun t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addun 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addun t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.addun t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.extbz t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.extbz 0, t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.extbz t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.extbz t0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addnr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addnr t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addnr 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addnr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.addnr t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipu t0, t1, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.clipu t0, t1, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.clipu t0, t1, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.clipu t0, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipu 0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipu t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.clipu t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.minu t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.minu t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.minu 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.minu t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.minu t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.abs t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.abs 0, t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.abs t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.abs t0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addrn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addrn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addrn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addrn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addrn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addrn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addrn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.addrn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.suburn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.suburn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.suburn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.suburn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.suburn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.suburn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.suburn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.suburn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clip t0, t1, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.clip t0, t1, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.clip t0, t1, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.clip t0, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clip 0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clip t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.clip t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addunr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addunr t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addunr 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addunr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.addunr t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addurn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addurn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addurn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addurn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addurn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addurn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addurn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.addurn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subun t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.subun t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.subun t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.subun t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subun t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subun 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subun t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.subun t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.subn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.subn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.subn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.subn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subrnr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subrnr t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subrnr 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subrnr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.subrnr t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.slet t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.slet t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.slet 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.slet t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.slet t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.suburnr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.suburnr t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.suburnr 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.suburnr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.suburnr t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.maxu t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.maxu t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.maxu 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.maxu t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.maxu t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.extbs t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.extbs 0, t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.extbs t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.extbs t0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.exths t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.exths 0, t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.exths t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.exths t0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.max t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.max t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.max 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.max t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.max t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subunr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subunr t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subunr 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subunr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.subunr t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.exthz t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.exthz 0, t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.exthz t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.exthz t0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipur t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipur t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipur 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipur t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.clipur t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addurnr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addurnr t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addurnr 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addurnr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.addurnr t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.addn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subrn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.subrn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.subrn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.subrn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subrn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subrn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subrn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.subrn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subnr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subnr t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subnr 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subnr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.subnr t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipr t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipr 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.clipr t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sletu t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sletu t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sletu 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sletu t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.sletu t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.min t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.min t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.min 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.min t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.min t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction

llvm/test/MC/RISCV/corev/XCValu-valid.s

+# RUN: llvm-mc -triple=riscv32 --mattr=+xcvalu -riscv-no-aliases -show-encoding %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvalu < %s \
+# RUN:     | llvm-objdump --mattr=+xcvalu -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-INSTR %s
+# RUN: not llvm-mc -triple riscv32 %s 2>&1 \
+# RUN:     | FileCheck -check-prefix=CHECK-NO-EXT %s
+
+cv.addurnr t0, t1, t2
+# CHECK-INSTR: cv.addurnr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x86]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addurnr a0, a1, a2
+# CHECK-INSTR: cv.addurnr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x86]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.maxu t0, t1, t2
+# CHECK-INSTR: cv.maxu t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x5c]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.maxu a0, a1, a2
+# CHECK-INSTR: cv.maxu a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x5c]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subrnr t0, t1, t2
+# CHECK-INSTR: cv.subrnr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x8c]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subrnr a0, a1, a2
+# CHECK-INSTR: cv.subrnr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x8c]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.slet t0, t1, t2
+# CHECK-INSTR: cv.slet t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x52]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.slet a0, a1, a2
+# CHECK-INSTR: cv.slet a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x52]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subrn t0, t1, t2, 0
+# CHECK-INSTR: cv.subrn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x32,0x73,0x80]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subrn t0, t1, t2, 16
+# CHECK-INSTR: cv.subrn t0, t1, t2, 16
+# CHECK-ENCODING: [0xdb,0x32,0x73,0xa0]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subrn a0, a1, zero, 31
+# CHECK-INSTR: cv.subrn a0, a1, zero, 31
+# CHECK-ENCODING: [0x5b,0xb5,0x05,0xbe]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subnr t0, t1, t2
+# CHECK-INSTR: cv.subnr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x88]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subnr a0, a1, a2
+# CHECK-INSTR: cv.subnr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x88]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addunr t0, t1, t2
+# CHECK-INSTR: cv.addunr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x82]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addunr a0, a1, a2
+# CHECK-INSTR: cv.addunr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x82]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addurn t0, t1, t2, 0
+# CHECK-INSTR: cv.addurn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x22,0x73,0xc0]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addurn t0, t1, t2, 16
+# CHECK-INSTR: cv.addurn t0, t1, t2, 16
+# CHECK-ENCODING: [0xdb,0x22,0x73,0xe0]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addurn a0, a1, zero, 31
+# CHECK-INSTR: cv.addurn a0, a1, zero, 31
+# CHECK-ENCODING: [0x5b,0xa5,0x05,0xfe]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addun t0, t1, t2, 0
+# CHECK-INSTR: cv.addun t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x22,0x73,0x40]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addun t0, t1, t2, 16
+# CHECK-INSTR: cv.addun t0, t1, t2, 16
+# CHECK-ENCODING: [0xdb,0x22,0x73,0x60]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addun a0, a1, zero, 31
+# CHECK-INSTR: cv.addun a0, a1, zero, 31
+# CHECK-ENCODING: [0x5b,0xa5,0x05,0x7e]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.clipu t0, t1, 0
+# CHECK-INSTR: cv.clipu t0, t1, 0
+# CHECK-ENCODING: [0xab,0x32,0x03,0x72]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.clipu t0, t1, 16
+# CHECK-INSTR: cv.clipu t0, t1, 16
+# CHECK-ENCODING: [0xab,0x32,0x03,0x73]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.clipu a0, zero, 31
+# CHECK-INSTR: cv.clipu a0, zero, 31
+# CHECK-ENCODING: [0x2b,0x35,0xf0,0x73]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.clip t0, t1, 0
+# CHECK-INSTR: cv.clip t0, t1, 0
+# CHECK-ENCODING: [0xab,0x32,0x03,0x70]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.clip t0, t1, 16
+# CHECK-INSTR: cv.clip t0, t1, 16
+# CHECK-ENCODING: [0xab,0x32,0x03,0x71]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.clip a0, zero, 31
+# CHECK-INSTR: cv.clip a0, zero, 31
+# CHECK-ENCODING: [0x2b,0x35,0xf0,0x71]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.exthz t0, t1
+# CHECK-INSTR: cv.exthz t0, t1
+# CHECK-ENCODING: [0xab,0x32,0x03,0x62]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.exthz a0, a1
+# CHECK-INSTR: cv.exthz a0, a1
+# CHECK-ENCODING: [0x2b,0xb5,0x05,0x62]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.max t0, t1, t2
+# CHECK-INSTR: cv.max t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x5a]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.max a0, a1, a2
+# CHECK-INSTR: cv.max a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x5a]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.clipr t0, t1, t2
+# CHECK-INSTR: cv.clipr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x74]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.clipr a0, a1, a2
+# CHECK-INSTR: cv.clipr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x74]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subn t0, t1, t2, 0
+# CHECK-INSTR: cv.subn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x32,0x73,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subn t0, t1, t2, 16
+# CHECK-INSTR: cv.subn t0, t1, t2, 16
+# CHECK-ENCODING: [0xdb,0x32,0x73,0x20]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subn a0, a1, zero, 31
+# CHECK-INSTR: cv.subn a0, a1, zero, 31
+# CHECK-ENCODING: [0x5b,0xb5,0x05,0x3e]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.extbz t0, t1
+# CHECK-INSTR: cv.extbz t0, t1
+# CHECK-ENCODING: [0xab,0x32,0x03,0x66]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.extbz a0, a1
+# CHECK-INSTR: cv.extbz a0, a1
+# CHECK-ENCODING: [0x2b,0xb5,0x05,0x66]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.abs t0, t1
+# CHECK-INSTR: cv.abs t0, t1
+# CHECK-ENCODING: [0xab,0x32,0x03,0x50]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.abs a0, a1
+# CHECK-INSTR: cv.abs a0, a1
+# CHECK-ENCODING: [0x2b,0xb5,0x05,0x50]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.clipur t0, t1, t2
+# CHECK-INSTR: cv.clipur t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x76]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.clipur a0, a1, a2
+# CHECK-INSTR: cv.clipur a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x76]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.minu t0, t1, t2
+# CHECK-INSTR: cv.minu t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x58]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.minu a0, a1, a2
+# CHECK-INSTR: cv.minu a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x58]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addn t0, t1, t2, 0
+# CHECK-INSTR: cv.addn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x22,0x73,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addn t0, t1, t2, 16
+# CHECK-INSTR: cv.addn t0, t1, t2, 16
+# CHECK-ENCODING: [0xdb,0x22,0x73,0x20]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addn a0, a1, zero, 31
+# CHECK-INSTR: cv.addn a0, a1, zero, 31
+# CHECK-ENCODING: [0x5b,0xa5,0x05,0x3e]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subunr t0, t1, t2
+# CHECK-INSTR: cv.subunr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x8a]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subunr a0, a1, a2
+# CHECK-INSTR: cv.subunr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x8a]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.extbs t0, t1
+# CHECK-INSTR: cv.extbs t0, t1
+# CHECK-ENCODING: [0xab,0x32,0x03,0x64]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.extbs a0, a1
+# CHECK-INSTR: cv.extbs a0, a1
+# CHECK-ENCODING: [0x2b,0xb5,0x05,0x64]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.sletu t0, t1, t2
+# CHECK-INSTR: cv.sletu t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x54]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.sletu a0, a1, a2
+# CHECK-INSTR: cv.sletu a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x54]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.min t0, t1, t2
+# CHECK-INSTR: cv.min t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x56]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.min a0, a1, a2
+# CHECK-INSTR: cv.min a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x56]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.suburnr t0, t1, t2
+# CHECK-INSTR: cv.suburnr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x8e]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.suburnr a0, a1, a2
+# CHECK-INSTR: cv.suburnr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x8e]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addrnr t0, t1, t2
+# CHECK-INSTR: cv.addrnr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x84]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addrnr a0, a1, a2
+# CHECK-INSTR: cv.addrnr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x84]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.exths t0, t1
+# CHECK-INSTR: cv.exths t0, t1
+# CHECK-ENCODING: [0xab,0x32,0x03,0x60]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.exths a0, a1
+# CHECK-INSTR: cv.exths a0, a1
+# CHECK-ENCODING: [0x2b,0xb5,0x05,0x60]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addrn t0, t1, t2, 0
+# CHECK-INSTR: cv.addrn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x22,0x73,0x80]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addrn t0, t1, t2, 16
+# CHECK-INSTR: cv.addrn t0, t1, t2, 16
+# CHECK-ENCODING: [0xdb,0x22,0x73,0xa0]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addrn a0, a1, zero, 31
+# CHECK-INSTR: cv.addrn a0, a1, zero, 31
+# CHECK-ENCODING: [0x5b,0xa5,0x05,0xbe]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.suburn t0, t1, t2, 0
+# CHECK-INSTR: cv.suburn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x32,0x73,0xc0]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.suburn t0, t1, t2, 16
+# CHECK-INSTR: cv.suburn t0, t1, t2, 16
+# CHECK-ENCODING: [0xdb,0x32,0x73,0xe0]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.suburn a0, a1, zero, 31
+# CHECK-INSTR: cv.suburn a0, a1, zero, 31
+# CHECK-ENCODING: [0x5b,0xb5,0x05,0xfe]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addnr t0, t1, t2
+# CHECK-INSTR: cv.addnr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x80]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addnr a0, a1, a2
+# CHECK-INSTR: cv.addnr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x80]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subun t0, t1, t2, 0
+# CHECK-INSTR: cv.subun t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x32,0x73,0x40]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subun t0, t1, t2, 16
+# CHECK-INSTR: cv.subun t0, t1, t2, 16
+# CHECK-ENCODING: [0xdb,0x32,0x73,0x60]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subun a0, a1, zero, 31
+# CHECK-INSTR: cv.subun a0, a1, zero, 31
+# CHECK-ENCODING: [0x5b,0xb5,0x05,0x7e]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}