[RISCV] Add support for XCValu extension in CV32E40P

[realqhc]

Summary

Implement XCValu intrinsics for CV32E40P according to the specification.

This is a commit of the patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, Nandni Jamnadas, Serkan Muhcu, @jeremybennett, @lewis-revill, @liaolucy, @simoncook, @xmj

[kito-cheng]

You might need to add extension in RISCVISAInfo.cpp for -march support?

llvm/docs/RISCVUsage.rst

278 ↗

(On Diff #534461)

@jeremybennett say it's 1.0 here?

https://github.com/riscv-non-isa/riscv-toolchain-conventions/blob/master/README.mkd#list-of-vendor-extensions

[realqhc]

llvm/docs/RISCVUsage.rst

278 ↗

(On Diff #534461)

This might need to be updated as if you check https://github.com/openhwgroup/cv32e40p/releases, there has been release of v1.3.2 last week.

[realqhc]

In D153748#4467842, @kito-cheng wrote:

You might need to add extension in RISCVISAInfo.cpp for -march support?

We plan to add extension to RISCVISAInfo.cpp in the second batch of upstreaming patches along with the LLVM Intrinsics for the extension.

[kito-cheng]

llvm/docs/RISCVUsage.rst

278 ↗

(On Diff #534461)

I saw binutils from openhwgroup still using 1.0[1], and that patch is committed 5 days ago? I am not intend to block this patch, but I would like to figure out what's the right version for those extension.

[1] https://github.com/openhwgroup/corev-binutils-gdb/commit/9b120787924eed13455de3062523539dc39bc7f8

[craig.topper]

llvm/docs/RISCVUsage.rst

278 ↗

(On Diff #534461)

The cv.mac part was copied from another description and does not apply here.

[realqhc]

llvm/docs/RISCVUsage.rst

278 ↗

(On Diff #534461)

Should I change it to cv. like XCVbitmanip or do you think cv.alu is more appropriate here?

[liaolucy]

llvm/docs/RISCVUsage.rst

278 ↗

(On Diff #534461)

Thanks, about the version, we have a group meeting on Friday, we will confirm it internally and come back to synchronize the information

[realqhc]

fix error in riscvusage.rst to reflect actual prefix of XCValu extension instructions.

[jeremybennett]

llvm/docs/RISCVUsage.rst

278 ↗

(On Diff #534461)

The document referred to is the entire specification of the CV32E40P, of which its ISA extensions are just a small section. The main document is subject to numerous small changes, and bumps its minor version and patch version from time to time. However the ISA extensions from a software perspective have a single version, 1.0, which is the only version that will be supported by the tool chain.

I'm open to advice on how we should handle this. I note that XCVbitmanip and XCVmac have both been merged using the full document reference (1.3.1). It might be clearer to reference the software spec on ISA extension naming, which explicitly notes that versioning is *not* supported for CORE-V: https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-isa-extension-naming.md

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

184

Can we name all of these CVInst* instead of RVInst* to match some of the earlier classes like CVBitManipRII?

204

Can this inherit from RVInstR which will simplify a lot of the body.

234

Can this inherit from RVInstR with a let rs2 = 0b00000?

[craig.topper]

In D153748#4470438, @realqhc wrote:

In D153748#4467842, @kito-cheng wrote:

You might need to add extension in RISCVISAInfo.cpp for -march support?

We plan to add extension to RISCVISAInfo.cpp in the second batch of upstreaming patches along with the LLVM Intrinsics for the extension.

I think the assembler also needs to RISCVISAInfo.cpp changes to print the correct version for the ELF attributes to list what extensions are enabled in the binary.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

325

Please wrap this to 80 columns and in general try to keep lines close to 80 columns.

[realqhc]

In D153748#4472470, @craig.topper wrote:

In D153748#4470438, @realqhc wrote:

In D153748#4467842, @kito-cheng wrote:

You might need to add extension in RISCVISAInfo.cpp for -march support?

We plan to add extension to RISCVISAInfo.cpp in the second batch of upstreaming patches along with the LLVM Intrinsics for the extension.

I think the assembler also needs to RISCVISAInfo.cpp changes to print the correct version for the ELF attributes to list what extensions are enabled in the binary.

Thanks for the suggesion, will get the versioning updated after discussion with core-v.

[realqhc]

rename RVInst to CVInst, add core-v to instruction description, use RVInstR to simplify CVInstALU_rr and CVInstAlu_r

[realqhc]

update tests

[jeremybennett]

llvm/docs/RISCVUsage.rst

278 ↗

(On Diff #534461)

Just to clarify. The CORE-V ISA extensions do not support versioning, which in a RISC-V context means the version is always 1.0.

[realqhc]

update ISA version accordingly

[craig.topper]

llvm/lib/Target/RISCV/RISCVFeatures.td

772 ↗

(On Diff #538044)

Can you put CORE-V in this string too

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

233

I would have expected cv.sle and cv.sleu for these mnemonics. The t feels out of place. In the base isa for slt/sltu it's part of "less than". Is the instruction name here "set less equal than" instead "set less than or equal"?

The vector spec uses "sle" and "sleu"

Is the spec frozen?

260

I'm surprised this instruction exists. Isn't this andi rs1, 255?

305

Wrap to 80 columns. by putting (ins GPR:$rd, GPR:$rs1, GPR:$rs2), on a new line.

[realqhc]

fix the problem of code being wrongly wrapped to 120 columns

[realqhc]

fix previous errorneus update

[realqhc]

applied general cleanup like in D155283, rebase.

[realqhc]

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

233

The current naming is copied from PULP RI5CY and it is close to be frozen[1].
[1]: https://github.com/openhwgroup/cv32e40p/issues/833

260

I believe this is also a leftover from PULP RI5CY.

[realqhc]

remove Opcode to reflect changes

[craig.topper]

LGTM

llvm/docs/RISCVUsage.rst

277 ↗

(On Diff #543813)

Keep this with the other XCV extensions

[realqhc]

Simplify tablegen for alu

[realqhc]

move xcvalu in RISCVUsage.rst so that it is with other XCV extensions

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

let Predicates = [HasVendorXCVmac, IsRV32] in {
   def : InstAlias<"cv.muls $rd1, $rs1, $rs2",   (CV_MULSN GPR:$rd1,   GPR:$rs1, GPR:$rs2, 0)>;
   def : InstAlias<"cv.mulhhs $rd1, $rs1, $rs2", (CV_MULHHSN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
 
   // Unsigned 16x16 bit muls
   def : InstAlias<"cv.mulu $rd1, $rs1, $rs2",   (CV_MULUN GPR:$rd1,   GPR:$rs1, GPR:$rs2, 0)>;
   def : InstAlias<"cv.mulhhu $rd1, $rs1, $rs2", (CV_MULHHUN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
 } // Predicates = [HasVendorXCVmac, IsRV32]
 
 let DecoderNamespace = "XCValu" in {
   class CVInstAlu_rri<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
                       string opcodestr, string argstr>
       : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
     bits<5> imm5;
     bits<5> rs2;
     bits<5> rs1;
     bits<5> rd;
 
     let Inst{31-30} = funct2;
     let Inst{29-25} = imm5;
     let Inst{24-20} = rs2;
     let Inst{19-15} = rs1;
     let Inst{14-12} = funct3;
     let Inst{11-7} = rd;
     let Opcode = OPC_CUSTOM_2.Value;
   }
 
   class CVInstAlu_rr<bits<7> funct7, bits<3> funct3, dag outs, dag ins,
                      string opcodestr, string argstr>
     : RVInstR<funct7, funct3, OPC_CUSTOM_1, outs, ins, opcodestr, argstr>;
 
   class CVInstAlu_ri<bits<7> funct7, bits<3> funct3, dag outs, dag ins,
                      string opcodestr, string argstr>
       : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
     bits<5> imm5;
     bits<5> rs1;
     bits<5> rd;
 
     let Inst{31-25} = funct7;
     let Inst{24-20} = imm5;
     let Inst{19-15} = rs1;
     let Inst{14-12} = funct3;
     let Inst{11-7} = rd;
     let Opcode = OPC_CUSTOM_1.Value;
   }
 
   class CVInstAlu_r<bits<7> funct7, bits<3> funct3, dag outs, dag ins, string opcodestr, string argstr>
     : RVInstR<funct7, funct3, OPC_CUSTOM_1, outs, ins, opcodestr, argstr> {
      let rs2 = 0b00000;
   }
 
 } // DecoderNamespace = "XCValu"
 
-let Predicates = [HasVendorXCValu], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+let Predicates = [HasVendorXCValu],
+  hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
   // General ALU Operations
-  def CV_ABS    : CVInstAlu_r<0b0101000, 0b011, (outs GPR:$rd), (ins GPR:$rs1),
+  def CV_ABS    : CVInstAlu_r<0b0101000, 0b011, (outs GPR:$rd),
+                              (ins GPR:$rs1),
                               "cv.abs", "$rd, $rs1">,
                   Sched<[]>;
-  def CV_SLET   : CVInstAlu_rr<0b0101001, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+  def CV_SLET   : CVInstAlu_rr<0b0101001, 0b011, (outs GPR:$rd),
+                               (ins GPR:$rs1, GPR:$rs2),
                                "cv.slet", "$rd, $rs1, $rs2">,
                   Sched<[]>;
-  def CV_SLETU  : CVInstAlu_rr<0b0101010, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+  def CV_SLETU  : CVInstAlu_rr<0b0101010, 0b011, (outs GPR:$rd),
+                               (ins GPR:$rs1, GPR:$rs2),
                                "cv.sletu", "$rd, $rs1, $rs2">,
                   Sched<[]>;
-  def CV_MIN    : CVInstAlu_rr<0b0101011, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+  def CV_MIN    : CVInstAlu_rr<0b0101011, 0b011, (outs GPR:$rd),
+                               (ins GPR:$rs1, GPR:$rs2),
                                "cv.min", "$rd, $rs1, $rs2">,
                   Sched<[]>;
-  def CV_MINU   : CVInstAlu_rr<0b0101100, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+  def CV_MINU   : CVInstAlu_rr<0b0101100, 0b011, (outs GPR:$rd),
+                               (ins GPR:$rs1, GPR:$rs2),
                                "cv.minu", "$rd, $rs1, $rs2">,
                   Sched<[]>;
-  def CV_MAX    : CVInstAlu_rr<0b0101101, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+  def CV_MAX    : CVInstAlu_rr<0b0101101, 0b011, (outs GPR:$rd),
+                               (ins GPR:$rs1, GPR:$rs2),
                                "cv.max", "$rd, $rs1, $rs2">,
                   Sched<[]>;
-  def CV_MAXU   : CVInstAlu_rr<0b0101110, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+  def CV_MAXU   : CVInstAlu_rr<0b0101110, 0b011, (outs GPR:$rd),
+                               (ins GPR:$rs1, GPR:$rs2),
                                "cv.maxu", "$rd, $rs1, $rs2">,
                   Sched<[]>;
-  def CV_EXTHS  : CVInstAlu_r<0b0110000, 0b011, (outs GPR:$rd), (ins GPR:$rs1),
+  def CV_EXTHS  : CVInstAlu_r<0b0110000, 0b011, (outs GPR:$rd),
+                              (ins GPR:$rs1),
                               "cv.exths", "$rd, $rs1">,
                   Sched<[]>;
-  def CV_EXTHZ  : CVInstAlu_r<0b0110001, 0b011, (outs GPR:$rd), (ins GPR:$rs1),
+  def CV_EXTHZ  : CVInstAlu_r<0b0110001, 0b011, (outs GPR:$rd),
+                              (ins GPR:$rs1),
                               "cv.exthz", "$rd, $rs1">,
                   Sched<[]>;
-  def CV_EXTBS  : CVInstAlu_r<0b0110010, 0b011, (outs GPR:$rd), (ins GPR:$rs1),
+  def CV_EXTBS  : CVInstAlu_r<0b0110010, 0b011, (outs GPR:$rd),
+                              (ins GPR:$rs1),
                               "cv.extbs", "$rd, $rs1">,
                   Sched<[]>;
-  def CV_EXTBZ  : CVInstAlu_r<0b0110011, 0b011, (outs GPR:$rd), (ins GPR:$rs1),
+  def CV_EXTBZ  : CVInstAlu_r<0b0110011, 0b011, (outs GPR:$rd),
+                              (ins GPR:$rs1),
                               "cv.extbz", "$rd, $rs1">,
                   Sched<[]>;
 
-  def CV_CLIP   : CVInstAlu_ri<0b0111000, 0b011, (outs GPR:$rd), (ins GPR:$rs1, uimm5:$imm5),
+  def CV_CLIP   : CVInstAlu_ri<0b0111000, 0b011, (outs GPR:$rd),
+                               (ins GPR:$rs1, uimm5:$imm5),
                                "cv.clip", "$rd, $rs1, $imm5">,
                   Sched<[]>;
-  def CV_CLIPU  : CVInstAlu_ri<0b0111001, 0b011, (outs GPR:$rd), (ins GPR:$rs1, uimm5:$imm5),
+  def CV_CLIPU  : CVInstAlu_ri<0b0111001, 0b011, (outs GPR:$rd),
+                               (ins GPR:$rs1, uimm5:$imm5),
                                "cv.clipu", "$rd, $rs1, $imm5">,
                   Sched<[]>;
-  def CV_CLIPR  : CVInstAlu_rr<0b0111010, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+  def CV_CLIPR  : CVInstAlu_rr<0b0111010, 0b011, (outs GPR:$rd),
+                               (ins GPR:$rs1, GPR:$rs2),
                                "cv.clipr", "$rd, $rs1, $rs2">,
                   Sched<[]>;
-  def CV_CLIPUR : CVInstAlu_rr<0b0111011, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+  def CV_CLIPUR : CVInstAlu_rr<0b0111011, 0b011, (outs GPR:$rd),
+                               (ins GPR:$rs1, GPR:$rs2),
                                "cv.clipur", "$rd, $rs1, $rs2">,
                   Sched<[]>;
 
-  def CV_ADDN   : CVInstAlu_rri<0b00, 0b010, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+  def CV_ADDN   : CVInstAlu_rri<0b00, 0b010, (outs GPR:$rd),
+                                (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
                                 "cv.addn", "$rd, $rs1, $rs2, $imm5">,
                   Sched<[]>;
-  def CV_ADDUN  : CVInstAlu_rri<0b01, 0b010, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+  def CV_ADDUN  : CVInstAlu_rri<0b01, 0b010, (outs GPR:$rd),
+                                (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
                                 "cv.addun", "$rd, $rs1, $rs2, $imm5">,
                   Sched<[]>;
-  def CV_ADDRN  : CVInstAlu_rri<0b10, 0b010, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+  def CV_ADDRN  : CVInstAlu_rri<0b10, 0b010, (outs GPR:$rd),
+                                (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
                                 "cv.addrn", "$rd, $rs1, $rs2, $imm5">,
                   Sched<[]>;
-  def CV_ADDURN : CVInstAlu_rri<0b11, 0b010, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+  def CV_ADDURN : CVInstAlu_rri<0b11, 0b010, (outs GPR:$rd),
+                                (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
                                 "cv.addurn", "$rd, $rs1, $rs2, $imm5">,
                   Sched<[]>;
-  def CV_SUBN   : CVInstAlu_rri<0b00, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+  def CV_SUBN   : CVInstAlu_rri<0b00, 0b011, (outs GPR:$rd),
+                                (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
                                 "cv.subn", "$rd, $rs1, $rs2, $imm5">,
                   Sched<[]>;
-  def CV_SUBUN  : CVInstAlu_rri<0b01, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+  def CV_SUBUN  : CVInstAlu_rri<0b01, 0b011, (outs GPR:$rd),
+                                (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
                                 "cv.subun", "$rd, $rs1, $rs2, $imm5">,
                   Sched<[]>;
-  def CV_SUBRN  : CVInstAlu_rri<0b10, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+  def CV_SUBRN  : CVInstAlu_rri<0b10, 0b011, (outs GPR:$rd),
+                                (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
                                 "cv.subrn", "$rd, $rs1, $rs2, $imm5">,
                   Sched<[]>;
-  def CV_SUBURN : CVInstAlu_rri<0b11, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+  def CV_SUBURN : CVInstAlu_rri<0b11, 0b011, (outs GPR:$rd),
+                                (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
                                 "cv.suburn", "$rd, $rs1, $rs2, $imm5">,
                   Sched<[]>;
-} // Predicates = [HasVendorXCValu], hasSideEffects = 0, mayLoad = 0, mayStore = 0
+} // Predicates = [HasVendorXCValu],
+  //   hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
 let Predicates = [HasVendorXCValu],
-  hasSideEffects = 0, mayLoad = 0, mayStore = 0, Opcode = OPC_CUSTOM_1.Value, Constraints = "$rd = $rd_wb" in {
-  def CV_ADDNR   : CVInstAlu_rr<0b1000000, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+  hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+  Opcode = OPC_CUSTOM_1.Value, Constraints = "$rd = $rd_wb" in {
+  def CV_ADDNR   : CVInstAlu_rr<0b1000000, 0b011, (outs GPR:$rd_wb),
+                                (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
                                 "cv.addnr", "$rd, $rs1, $rs2">,
                    Sched<[]>;
-  def CV_ADDUNR  : CVInstAlu_rr<0b1000001, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+  def CV_ADDUNR  : CVInstAlu_rr<0b1000001, 0b011, (outs GPR:$rd_wb),
+                                (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
                                 "cv.addunr", "$rd, $rs1, $rs2">,
                    Sched<[]>;
-  def CV_ADDRNR  : CVInstAlu_rr<0b1000010, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+  def CV_ADDRNR  : CVInstAlu_rr<0b1000010, 0b011, (outs GPR:$rd_wb),
+                                (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
                                 "cv.addrnr", "$rd, $rs1, $rs2">,
                    Sched<[]>;
-  def CV_ADDURNR : CVInstAlu_rr<0b1000011, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+  def CV_ADDURNR : CVInstAlu_rr<0b1000011, 0b011, (outs GPR:$rd_wb),
+                                (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
                                 "cv.addurnr", "$rd, $rs1, $rs2">,
                    Sched<[]>;
-  def CV_SUBNR   : CVInstAlu_rr<0b1000100, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+  def CV_SUBNR   : CVInstAlu_rr<0b1000100, 0b011, (outs GPR:$rd_wb),
+                                (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
                                 "cv.subnr", "$rd, $rs1, $rs2">,
                    Sched<[]>;
-  def CV_SUBUNR  : CVInstAlu_rr<0b1000101, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+  def CV_SUBUNR  : CVInstAlu_rr<0b1000101, 0b011, (outs GPR:$rd_wb),
+                                (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
                                 "cv.subunr", "$rd, $rs1, $rs2">,
                    Sched<[]>;
-  def CV_SUBRNR  : CVInstAlu_rr<0b1000110, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+  def CV_SUBRNR  : CVInstAlu_rr<0b1000110, 0b011, (outs GPR:$rd_wb),
+                                (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
                                 "cv.subrnr", "$rd, $rs1, $rs2">,
                    Sched<[]>;
-  def CV_SUBURNR : CVInstAlu_rr<0b1000111, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+  def CV_SUBURNR : CVInstAlu_rr<0b1000111, 0b011, (outs GPR:$rd_wb),
+                                (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
                                 "cv.suburnr", "$rd, $rs1, $rs2">,
                    Sched<[]>;
 
 } // Predicates = [HasVendorXCValu],
-  // hasSideEffects = 0, mayLoad = 0, mayStore = 0, Opcode = OPC_CUSTOM_1.Value, Constraints = "$rd = $rd_wb"
+  //   hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+  //   Opcode = OPC_CUSTOM_1.Value, Constraints = "$rd = $rd_wb"