[RISCV] Remove side effects from vsetvli intrinsics.

[craig.topper]

Summary

Delete the opt intrinsics since they are now identical.

I left the side effects due to user expectations about how these
interact with things like inline assembly or function calls. Or
that they wouldn't be hoisted. I think we should look at other
ways to address thoughs.

If I could, I'd rename them these somehow to distance them from
the vsetvli instruction. In some sense they only query the VL for
a particular SEW and LMUL. They don't guarantee a vsetvli
instruction will be emitted.

Fixes https://github.com/llvm/llvm-project/issues/59359

[kito-cheng]

LGTM, I like this change, GCC also implement this way too, and it's more close to our RVV intrinsic programming model - abstract VL and VTYPE status from the front-end and middle-end.

[rogfer01]

Thanks @craig.topper.

I believe that "unfettered" reads (and other uncontrolled changes) to the vl / vtype should not prevent us from creating an efficient intrinsics-based programming model for RVV and this change aligns with this view.

[reames]

No objection here. I don't have a strong opinion on how this should work through the C intrinsic interface.

If we do land this, we should revisit the implementation of the InsertVSETVLI pass. We are deliberately very conservative there around user VSETVLIs, and this patch would remove that restriction. This would seem to unblock some optimizations, and we can probably simplify the implementation a bit too.

[frasercrmck]

Bit late to the party, but thanks for doing this

llvm/docs/ReleaseNotes.rst

 
 * ...
 
 Changes to the RISC-V Backend
 -----------------------------
 
 * Assembler support for version 1.0.1 of the Zcb extension was added.
 * Zca, Zcf, and Zcd extensions were upgraded to version 1.0.1.
+* vsetvli intrinsics no longer have side effects. They may now be combined,
+  moved, deleted, etc. by optimizations.
 
 Changes to the WebAssembly Backend
 ----------------------------------
 
 * ...
 
 Changes to the Windows Target
 -----------------------------

llvm/include/llvm/IR/IntrinsicsRISCV.td

 }
 
 let TargetPrefix = "riscv" in {
   // We use anyint here but we only support XLen.
   def int_riscv_vsetvli   : Intrinsic<[llvm_anyint_ty],
                            /* AVL */  [LLVMMatchType<0>,
                            /* VSEW */  LLVMMatchType<0>,
                            /* VLMUL */ LLVMMatchType<0>],
-                                      [IntrNoMem, IntrHasSideEffects,
-                                       ImmArg<ArgIndex<1>>,
-                                       ImmArg<ArgIndex<2>>]>;
-  def int_riscv_vsetvlimax : Intrinsic<[llvm_anyint_ty],
-                            /* VSEW */ [LLVMMatchType<0>,
-                            /* VLMUL */ LLVMMatchType<0>],
-                                      [IntrNoMem, IntrHasSideEffects,
-                                       ImmArg<ArgIndex<0>>,
-                                       ImmArg<ArgIndex<1>>]>;
-
-  // Versions without side effects: better optimizable and usable if only the
-  // returned vector length is important.
-  def int_riscv_vsetvli_opt   : Intrinsic<[llvm_anyint_ty],
-                               /* AVL */  [LLVMMatchType<0>,
-                               /* VSEW */  LLVMMatchType<0>,
-                               /* VLMUL */ LLVMMatchType<0>],
-                                          [IntrNoMem,
-                                           ImmArg<ArgIndex<1>>,
-                                           ImmArg<ArgIndex<2>>]>;
-  def int_riscv_vsetvlimax_opt : Intrinsic<[llvm_anyint_ty],
-                                /* VSEW */ [LLVMMatchType<0>,
-                                /* VLMUL */ LLVMMatchType<0>],
-                                          [IntrNoMem,
-                                           ImmArg<ArgIndex<0>>,
-                                           ImmArg<ArgIndex<1>>]>;
+  def int_riscv_vsetvlimax : Intrinsic<[llvm_anyint_ty],
 
   // For unit stride mask load
   // Input: (pointer, vl)
   class RISCVUSMLoad
         : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
                     [LLVMPointerType<LLVMMatchType<0>>,
                      llvm_anyint_ty],
                     [NoCapture<ArgIndex<0>>, IntrReadMem]>, RISCVVIntrinsic {

llvm/lib/Analysis/ValueTracking.cpp

 //===- ValueTracking.cpp - Walk computations to compute properties --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
         computeKnownBits(I->getOperand(0), Known, Depth + 1, Q);
         computeKnownBits(I->getOperand(1), Known2, Depth + 1, Q);
         Known = KnownBits::smax(Known, Known2);
         break;
       case Intrinsic::x86_sse42_crc32_64_64:
         Known.Zero.setBitsFrom(32);
         break;
       case Intrinsic::riscv_vsetvli:
-      case Intrinsic::riscv_vsetvli_opt:
       case Intrinsic::riscv_vsetvlimax:
-      case Intrinsic::riscv_vsetvlimax_opt:
         // Assume that VL output is >= 65536.
         // TODO: Take SEW and LMUL into account.
         if (BitWidth > 17)
           Known.Zero.setBitsFrom(17);
         break;
       case Intrinsic::vscale: {
         if (!II->getParent() || !II->getFunction() ||
             !II->getFunction()->hasFnAttribute(Attribute::VScaleRange))

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

 //===-- RISCVISelDAGToDAG.cpp - A dag to dag inst selector for RISCV ------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
void RISCVDAGToDAGISel::selectVSETVLI(SDNode *Node) {
   SDLoc DL(Node);
   MVT XLenVT = Subtarget->getXLenVT();
 
   bool HasChain = Node->getOpcode() == ISD::INTRINSIC_W_CHAIN;
   unsigned IntNoOffset = HasChain ? 1 : 0;
   unsigned IntNo = Node->getConstantOperandVal(IntNoOffset);
 
   assert((IntNo == Intrinsic::riscv_vsetvli ||
-          IntNo == Intrinsic::riscv_vsetvlimax ||
-          IntNo == Intrinsic::riscv_vsetvli_opt ||
-          IntNo == Intrinsic::riscv_vsetvlimax_opt) &&
+          IntNo == Intrinsic::riscv_vsetvlimax) &&
          "Unexpected vsetvli intrinsic");
 
-  bool VLMax = IntNo == Intrinsic::riscv_vsetvlimax ||
-               IntNo == Intrinsic::riscv_vsetvlimax_opt;
+  bool VLMax = IntNo == Intrinsic::riscv_vsetvlimax;
   unsigned Offset = IntNoOffset + (VLMax ? 1 : 2);
 
   assert(Node->getNumOperands() == Offset + 2 &&
          "Unexpected number of operands");
 
   unsigned SEW =
       RISCVVType::decodeVSEW(Node->getConstantOperandVal(Offset) & 0x7);
   RISCVII::VLMUL VLMul = static_cast<RISCVII::VLMUL>(
#undef CASE_VMXOR_VMANDN_VMOR_OPCODES
           CurDAG->getMachineNode(VMSLTMaskOpcode, DL, VT,
                                  {MaskedOff, Src1, Src2, V0, VL, SEW, Glue}),
           0);
       // vmxor.mm vd, vd, v0 is used to update active value.
       ReplaceNode(Node, CurDAG->getMachineNode(VMXOROpcode, DL, VT,
                                                {Cmp, Mask, VL, MaskSEW}));
       return;
     }
-    case Intrinsic::riscv_vsetvli_opt:
-    case Intrinsic::riscv_vsetvlimax_opt:
+    case Intrinsic::riscv_vsetvli:
+    case Intrinsic::riscv_vsetvlimax:
       return selectVSETVLI(Node);
     }
     break;
   }
   case ISD::INTRINSIC_W_CHAIN: {
     unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
     switch (IntNo) {
       // By default we do not custom select any intrinsic.
     default:
       break;
-    case Intrinsic::riscv_vsetvli:
-    case Intrinsic::riscv_vsetvlimax:
-      return selectVSETVLI(Node);
     case Intrinsic::riscv_vlseg2:
     case Intrinsic::riscv_vlseg3:
     case Intrinsic::riscv_vlseg4:
     case Intrinsic::riscv_vlseg5:
     case Intrinsic::riscv_vlseg6:
     case Intrinsic::riscv_vlseg7:
     case Intrinsic::riscv_vlseg8: {
       selectVLSEG(Node, /*IsMasked*/ false, /*IsStrided*/ false);

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (isa<ConstantSDNode>(AVL)) {
         I32VL = DAG.getConstant(2 * AVLInt, DL, XLenVT);
       } else if (AVLInt >= 2 * MaxVLMAX) {
         // Just set vl to VLMAX in this situation
         RISCVII::VLMUL Lmul = RISCVTargetLowering::getLMUL(I32VT);
         SDValue LMUL = DAG.getConstant(Lmul, DL, XLenVT);
         unsigned Sew = RISCVVType::encodeSEW(I32VT.getScalarSizeInBits());
         SDValue SEW = DAG.getConstant(Sew, DL, XLenVT);
         SDValue SETVLMAX = DAG.getTargetConstant(
-            Intrinsic::riscv_vsetvlimax_opt, DL, MVT::i32);
+            Intrinsic::riscv_vsetvlimax, DL, MVT::i32);
         I32VL = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, XLenVT, SETVLMAX, SEW,
                             LMUL);
       } else {
         // For AVL between (MinVLMAX, 2 * MaxVLMAX), the actual working vl
         // is related to the hardware implementation.
         // So let the following code handle
       }
     }
     if (!I32VL) {
       RISCVII::VLMUL Lmul = RISCVTargetLowering::getLMUL(VT);
       SDValue LMUL = DAG.getConstant(Lmul, DL, XLenVT);
       unsigned Sew = RISCVVType::encodeSEW(VT.getScalarSizeInBits());
       SDValue SEW = DAG.getConstant(Sew, DL, XLenVT);
       SDValue SETVL =
-          DAG.getTargetConstant(Intrinsic::riscv_vsetvli_opt, DL, MVT::i32);
+          DAG.getTargetConstant(Intrinsic::riscv_vsetvli, DL, MVT::i32);
       // Using vsetvli instruction to get actually used length which related to
       // the hardware implementation
       SDValue VL = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, XLenVT, SETVL, AVL,
                                SEW, LMUL);
       I32VL =
           DAG.getNode(ISD::SHL, DL, XLenVT, VL, DAG.getConstant(1, DL, XLenVT));
     }
 
case ISD::INTRINSIC_WO_CHAIN: {
     unsigned IntNo =
         Op.getConstantOperandVal(Opc == ISD::INTRINSIC_WO_CHAIN ? 0 : 1);
     switch (IntNo) {
     default:
       // We can't do anything for most intrinsics.
       break;
     case Intrinsic::riscv_vsetvli:
     case Intrinsic::riscv_vsetvlimax:
-    case Intrinsic::riscv_vsetvli_opt:
-    case Intrinsic::riscv_vsetvlimax_opt:
       // Assume that VL output is >= 65536.
       // TODO: Take SEW and LMUL into account.
       if (BitWidth > 17)
         Known.Zero.setBitsFrom(17);
       break;
     }
     break;
   }

llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll

 ; CHECK-NEXT:    vl2r.v v10, (a1) # Unknown-size Folded Reload
 ; CHECK-NEXT:    add a1, a1, a2
 ; CHECK-NEXT:    vl2r.v v12, (a1) # Unknown-size Folded Reload
 ; CHECK-NEXT:    add a1, a1, a2
 ; CHECK-NEXT:    vl2r.v v14, (a1) # Unknown-size Folded Reload
 ; CHECK-NEXT:    add a1, a1, a2
 ; CHECK-NEXT:    vl2r.v v16, (a1) # Unknown-size Folded Reload
 ; CHECK-NEXT:    vle16.v v16, (a0)
-; CHECK-NEXT:    vsetivli zero, 2, e16, m2, ta, mu
 ; CHECK-NEXT:    lui a0, %hi(.L__const._Z3foov.var_40)
 ; CHECK-NEXT:    addi a0, a0, %lo(.L__const._Z3foov.var_40)
 ; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    vsetivli zero, 2, e16, m2, ta, mu
 ; CHECK-NEXT:    lui a0, 1048572
 ; CHECK-NEXT:    addiw a0, a0, 928
 ; CHECK-NEXT:    vmsbc.vx v0, v8, a0
-; CHECK-NEXT:    vsetivli zero, 2, e16, m2, tu, mu
+; CHECK-NEXT:    vsetvli zero, zero, e16, m2, tu, mu
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    slli a0, a0, 3
 ; CHECK-NEXT:    add a0, sp, a0
 ; CHECK-NEXT:    addi a0, a0, 16
 ; CHECK-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
 ; CHECK-NEXT:    vsext.vf2 v10, v8, v0.t
 ; CHECK-NEXT:    lui a0, %hi(var_47)
 ; CHECK-NEXT:    addi a0, a0, %lo(var_47)

llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s
 @__const.test.var_45 = private unnamed_addr constant [2 x i8] c"\D1S", align 1
 @__const.test.var_101 = private unnamed_addr constant [2 x i8] c"\830", align 1
 
 ; Function Attrs: nounwind vscale_range(2,1024)
 define dso_local void @test(ptr nocapture noundef %var_99) {
 ; CHECK-LABEL: test:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lui a1, %hi(.L__const.test.var_45)
 ; CHECK-NEXT:    addi a1, a1, %lo(.L__const.test.var_45)
 ; CHECK-NEXT:    vsetivli zero, 2, e8, m4, ta, ma
 ; CHECK-NEXT:    vle8.v v8, (a1)
-; CHECK-NEXT:    li a1, 1
-; CHECK-NEXT:    vmul.vx v12, v8, a1
 ; CHECK-NEXT:    lui a1, %hi(.L__const.test.var_101)
 ; CHECK-NEXT:    addi a1, a1, %lo(.L__const.test.var_101)
-; CHECK-NEXT:    vle8.v v16, (a1)
-; CHECK-NEXT:    li a1, 32
-; CHECK-NEXT:    vsetivli zero, 2, e8, m4, ta, ma
-; CHECK-NEXT:    vmv.x.s a1, v12
+; CHECK-NEXT:    vle8.v v12, (a1)
+; CHECK-NEXT:    li a1, 1
+; CHECK-NEXT:    vmul.vx v16, v8, a1
+; CHECK-NEXT:    vmv.x.s a1, v16
 ; CHECK-NEXT:    vmsleu.vx v0, v8, a1
-; CHECK-NEXT:    vssra.vv v8, v16, v8
+; CHECK-NEXT:    vssra.vv v8, v12, v8
 ; CHECK-NEXT:    vmerge.vvm v8, v8, v8, v0
 ; CHECK-NEXT:    vse8.v v8, (a0)
 ; CHECK-NEXT:    ret
 entry:
   %0 = tail call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.i64(<vscale x 32 x i8> undef, ptr nonnull @__const.test.var_45, i64 2)
   %1 = tail call <vscale x 32 x i8> @llvm.riscv.vmul.nxv32i8.i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8> %0, i8 1, i64 2)
   %2 = tail call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.i64(<vscale x 32 x i8> undef, ptr nonnull @__const.test.var_101, i64 2)
   %3 = tail call i64 @llvm.riscv.vsetvli.i64(i64 32, i64 0, i64 2)

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

%res = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32(
                <vscale x 4 x i32> undef, <vscale x 4 x i32> %a.mod,
                <vscale x 4 x i32> %b, <vscale x 4 x i1> %mask, i64 %vl, i64 0)
   ret <vscale x 4 x i32> %res
 }
 
 define <vscale x 2 x i32> @pre_lmul(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y, i1 %cond) nounwind {
 ; CHECK-LABEL: pre_lmul:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    andi a1, a0, 1
-; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
 ; CHECK-NEXT:    vadd.vv v8, v8, v9
-; CHECK-NEXT:    beqz a1, .LBB18_2
-; CHECK-NEXT:  # %bb.1: # %if
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT:  .LBB18_2: # %if.end
-; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
 ; CHECK-NEXT:    vadd.vv v8, v8, v9
 ; CHECK-NEXT:    ret
 entry:
   %vl = tail call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
   %a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, i64 %vl)
   br i1 %cond, label %if, label %if.end
 
 if:

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

for.body:                                         ; preds = %entry, %for.body
   %8 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %n, i64 2, i64 0)
   %cmp.not = icmp eq i64 %8, 0
   br i1 %cmp.not, label %for.cond.cleanup, label %for.body
 }
 
 define <vscale x 1 x i64> @test7(<vscale x 1 x i64> %a, i64 %b, <vscale x 1 x i1> %mask) nounwind {
 ; CHECK-LABEL: test7:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, zero, e64, m1, tu, ma
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, tu, ma
 ; CHECK-NEXT:    vmv.s.x v8, a0
 ; CHECK-NEXT:    ret
 entry:
   %x = tail call i64 @llvm.riscv.vsetvlimax(i64 3, i64 0)
   %y = call <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(
     <vscale x 1 x i64> %a,
     i64 %b, i64 1)
 
   ret <vscale x 1 x i64> %y
 }
 
 define <vscale x 1 x i64> @test8(<vscale x 1 x i64> %a, i64 %b, <vscale x 1 x i1> %mask) nounwind {
 ; CHECK-LABEL: test8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetivli zero, 6, e64, m1, tu, ma
+; CHECK-NEXT:    vsetivli zero, 2, e64, m1, tu, ma
 ; CHECK-NEXT:    vmv.s.x v8, a0
 ; CHECK-NEXT:    ret
 entry:
   %x = tail call i64 @llvm.riscv.vsetvli(i64 6, i64 3, i64 0)
   %y = call <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(<vscale x 1 x i64> %a, i64 %b, i64 2)
   ret <vscale x 1 x i64> %y
 }
 
%x = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64(
     i64 0)
   %y = call <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(<vscale x 1 x i64> %x, i64 %b, i64 2)
   ret <vscale x 1 x i64> %y
 }
 
 define <vscale x 1 x double> @test10(<vscale x 1 x double> %a, double %b) nounwind {
 ; CHECK-LABEL: test10:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a0, zero, e64, m1, tu, ma
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, tu, ma
 ; CHECK-NEXT:    vfmv.s.f v8, fa0
 ; CHECK-NEXT:    ret
 entry:
   %x = tail call i64 @llvm.riscv.vsetvlimax(i64 3, i64 0)
   %y = call <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64(
     <vscale x 1 x double> %a, double %b, i64 1)
   ret <vscale x 1 x double> %y
 }
 
 define <vscale x 1 x double> @test11(<vscale x 1 x double> %a, double %b) nounwind {
 ; CHECK-LABEL: test11:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetivli zero, 6, e64, m1, tu, ma
+; CHECK-NEXT:    vsetivli zero, 2, e64, m1, tu, ma
 ; CHECK-NEXT:    vfmv.s.f v8, fa0
 ; CHECK-NEXT:    ret
 entry:
   %x = tail call i64 @llvm.riscv.vsetvli(i64 6, i64 3, i64 0)
   %y = call <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64(
     <vscale x 1 x double> %a, double %b, i64 2)
   ret <vscale x 1 x double> %y
 }
%y2 = call <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64(
     <vscale x 1 x double> %f2, double %b, i64 1)
   %res = fadd <vscale x 1 x double> %y, %y2
   ret <vscale x 1 x double> %res
 }
 
 define <vscale x 1 x double> @test19(<vscale x 1 x double> %a, double %b) nounwind {
 ; CHECK-LABEL: test19:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetivli zero, 6, e64, m1, tu, ma
+; CHECK-NEXT:    vsetivli zero, 2, e64, m1, tu, ma
 ; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
 ; CHECK-NEXT:    vfadd.vv v8, v9, v8
 ; CHECK-NEXT:    ret
 entry:
   %x = tail call i64 @llvm.riscv.vsetvli(i64 6, i64 3, i64 0)
   %y = call <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64(

llvm/test/CodeGen/RISCV/rvv/vsetvli-intrinsics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
 ; RUN:   -verify-machineinstrs | FileCheck %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
 ; RUN:   -verify-machineinstrs | FileCheck %s
 
 declare iXLen @llvm.riscv.vsetvli.iXLen(iXLen, iXLen, iXLen)
 declare iXLen @llvm.riscv.vsetvlimax.iXLen(iXLen, iXLen)
-declare iXLen @llvm.riscv.vsetvli.opt.iXLen(iXLen, iXLen, iXLen)
-declare iXLen @llvm.riscv.vsetvlimax.opt.iXLen(iXLen, iXLen)
 
-define void @test_vsetvli_e8m1(iXLen %avl) nounwind {
+define iXLen @test_vsetvli_e8m1(iXLen %avl) nounwind {
 ; CHECK-LABEL: test_vsetvli_e8m1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT:    vsetvli a0, a0, e8, m1, ta, mu
 ; CHECK-NEXT:    ret
-  call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %avl, iXLen 0, iXLen 0)
-  ret void
+  %vl = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %avl, iXLen 0, iXLen 0)
+  ret iXLen %vl
 }
 
-define void @test_vsetvli_e16mf4(iXLen %avl) nounwind {
+define iXLen @test_vsetvli_e16mf4(iXLen %avl) nounwind {
 ; CHECK-LABEL: test_vsetvli_e16mf4:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu
+; CHECK-NEXT:    vsetvli a0, a0, e16, mf4, ta, mu
 ; CHECK-NEXT:    ret
-  call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %avl, iXLen 1, iXLen 6)
-  ret void
+  %vl = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %avl, iXLen 1, iXLen 6)
+  ret iXLen %vl
 }
 
-define void @test_vsetvli_e64mf8(iXLen %avl) nounwind {
+define iXLen @test_vsetvli_e64mf8(iXLen %avl) nounwind {
 ; CHECK-LABEL: test_vsetvli_e64mf8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, a0, e64, mf8, ta, mu
+; CHECK-NEXT:    vsetvli a0, a0, e64, mf8, ta, mu
 ; CHECK-NEXT:    ret
-  call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %avl, iXLen 3, iXLen 5)
-  ret void
+  %vl = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %avl, iXLen 3, iXLen 5)
+  ret iXLen %vl
 }
 
-define void @test_vsetvli_e8mf2_zero_avl() nounwind {
+define iXLen @test_vsetvli_e8mf2_zero_avl() nounwind {
 ; CHECK-LABEL: test_vsetvli_e8mf2_zero_avl:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 0, e8, mf2, ta, mu
+; CHECK-NEXT:    vsetivli a0, 0, e8, mf2, ta, mu
 ; CHECK-NEXT:    ret
-  call iXLen @llvm.riscv.vsetvli.iXLen(iXLen 0, iXLen 0, iXLen 7)
-  ret void
+  %vl = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen 0, iXLen 0, iXLen 7)
+  ret iXLen %vl
 }
 
-define void @test_vsetvli_e32mf8_zero_avl() nounwind {
+define iXLen @test_vsetvli_e32mf8_zero_avl() nounwind {
 ; CHECK-LABEL: test_vsetvli_e32mf8_zero_avl:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 0, e16, mf4, ta, mu
+; CHECK-NEXT:    vsetivli a0, 0, e16, mf4, ta, mu
 ; CHECK-NEXT:    ret
-  call iXLen @llvm.riscv.vsetvli.iXLen(iXLen 0, iXLen 1, iXLen 6)
-  ret void
+  %vl = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen 0, iXLen 1, iXLen 6)
+  ret iXLen %vl
 }
 
-define void @test_vsetvlimax_e32m2() nounwind {
+define iXLen @test_vsetvlimax_e32m2() nounwind {
 ; CHECK-LABEL: test_vsetvlimax_e32m2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
 ; CHECK-NEXT:    ret
-  call iXLen @llvm.riscv.vsetvlimax.iXLen(iXLen 2, iXLen 1)
-  ret void
+  %vl = call iXLen @llvm.riscv.vsetvlimax.iXLen(iXLen 2, iXLen 1)
+  ret iXLen %vl
 }
 
-define void @test_vsetvlimax_e64m4() nounwind {
+define iXLen @test_vsetvlimax_e64m4() nounwind {
 ; CHECK-LABEL: test_vsetvlimax_e64m4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
 ; CHECK-NEXT:    ret
-  call iXLen @llvm.riscv.vsetvlimax.iXLen(iXLen 3, iXLen 2)
-  ret void
+  %vl = call iXLen @llvm.riscv.vsetvlimax.iXLen(iXLen 3, iXLen 2)
+  ret iXLen %vl
 }
 
-define void @test_vsetvlimax_e64m8() nounwind {
+define iXLen @test_vsetvlimax_e64m8() nounwind {
 ; CHECK-LABEL: test_vsetvlimax_e64m8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
 ; CHECK-NEXT:    ret
-  call iXLen @llvm.riscv.vsetvlimax.iXLen(iXLen 3, iXLen 3)
-  ret void
-}
-
-define iXLen @test_vsetvli_opt_e8m1(iXLen %avl) nounwind {
-; CHECK-LABEL: test_vsetvli_opt_e8m1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, a0, e8, m1, ta, mu
-; CHECK-NEXT:    ret
-  %vl = call iXLen @llvm.riscv.vsetvli.opt.iXLen(iXLen %avl, iXLen 0, iXLen 0)
+  %vl = call iXLen @llvm.riscv.vsetvlimax.iXLen(iXLen 3, iXLen 3)
   ret iXLen %vl
 }
 
 ; Check that we remove the intrinsic if it's unused.
-define void @test_vsetvli_opt_e8m1_nouse(iXLen %avl) nounwind {
-; CHECK-LABEL: test_vsetvli_opt_e8m1_nouse:
+define void @test_vsetvli_e8m1_nouse(iXLen %avl) nounwind {
+; CHECK-LABEL: test_vsetvli_e8m1_nouse:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ret
-  call iXLen @llvm.riscv.vsetvli.opt.iXLen(iXLen %avl, iXLen 0, iXLen 0)
+  call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %avl, iXLen 0, iXLen 0)
   ret void
 }
 
-define iXLen @test_vsetvli_opt_e16mf4(iXLen %avl) nounwind {
-; CHECK-LABEL: test_vsetvli_opt_e16mf4:
+define void @test_vsetvlimax_e32m2_nouse() nounwind {
+; CHECK-LABEL: test_vsetvlimax_e32m2_nouse:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, a0, e16, mf4, ta, mu
-; CHECK-NEXT:    ret
-  %vl = call iXLen @llvm.riscv.vsetvli.opt.iXLen(iXLen %avl, iXLen 1, iXLen 6)
-  ret iXLen %vl
-}
-
-define iXLen @test_vsetvli_opt_e32mf8_zero_avl() nounwind {
-; CHECK-LABEL: test_vsetvli_opt_e32mf8_zero_avl:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli a0, 0, e16, mf4, ta, mu
-; CHECK-NEXT:    ret
-  %vl = call iXLen @llvm.riscv.vsetvli.opt.iXLen(iXLen 0, iXLen 1, iXLen 6)
-  ret iXLen %vl
-}
-
-define iXLen @test_vsetvlimax_opt_e32m2() nounwind {
-; CHECK-LABEL: test_vsetvlimax_opt_e32m2:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
 ; CHECK-NEXT:    ret
-  %vl = call iXLen @llvm.riscv.vsetvlimax.opt.iXLen(iXLen 2, iXLen 1)
-  ret iXLen %vl
-}
-
-define void @test_vsetvlimax_opt_e32m2_nouse() nounwind {
-; CHECK-LABEL: test_vsetvlimax_opt_e32m2_nouse:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    ret
-  call iXLen @llvm.riscv.vsetvlimax.opt.iXLen(iXLen 2, iXLen 1)
+  call iXLen @llvm.riscv.vsetvlimax.iXLen(iXLen 2, iXLen 1)
   ret void
 }
 
-define iXLen @test_vsetvlimax_opt_e64m4() nounwind {
-; CHECK-LABEL: test_vsetvlimax_opt_e64m4:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT:    ret
-  %vl = call iXLen @llvm.riscv.vsetvlimax.opt.iXLen(iXLen 3, iXLen 2)
-  ret iXLen %vl
-}
-
 declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.iXLen(<vscale x 4 x i32>, <vscale x 4 x i32>*, iXLen)
 
 ; Check that we remove the redundant vsetvli when followed by another operation
 define <vscale x 4 x i32> @redundant_vsetvli(iXLen %avl, <vscale x 4 x i32>* %ptr) nounwind {
 ; CHECK-LABEL: redundant_vsetvli:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu
 ; CHECK-NEXT:    vle32.v v8, (a1)

llvm/test/Transforms/InstCombine/RISCV/riscv-vsetvli-knownbits.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
 
 declare i32 @llvm.riscv.vsetvli.i32(i32, i32, i32)
 declare i64 @llvm.riscv.vsetvli.i64(i64, i64, i64)
 declare i32 @llvm.riscv.vsetvlimax.i32(i32, i32)
 declare i64 @llvm.riscv.vsetvlimax.i64(i64, i64)
-declare i32 @llvm.riscv.vsetvli.opt.i32(i32, i32, i32)
-declare i64 @llvm.riscv.vsetvli.opt.i64(i64, i64, i64)
-declare i32 @llvm.riscv.vsetvlimax.opt.i32(i32, i32)
-declare i64 @llvm.riscv.vsetvlimax.opt.i64(i64, i64)
 
 define i32 @vsetvli_i32() nounwind {
 ; CHECK-LABEL: @vsetvli_i32(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.vsetvli.i32(i32 1, i32 1, i32 1)
 ; CHECK-NEXT:    ret i32 [[TMP0]]
 ;
 entry:

 ; CHECK-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1)
 ; CHECK-NEXT:    ret i64 [[TMP0]]
 ;
 entry:
   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1)
   %1 = and i64 %0, 131071
   ret i64 %1
 }
-
-define i32 @vsetvli_opt_i32() nounwind {
-; CHECK-LABEL: @vsetvli_opt_i32(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.vsetvli.opt.i32(i32 1, i32 1, i32 1)
-; CHECK-NEXT:    ret i32 [[TMP0]]
-;
-entry:
-  %0 = call i32 @llvm.riscv.vsetvli.opt.i32(i32 1, i32 1, i32 1)
-  %1 = and i32 %0, 2147483647
-  ret i32 %1
-}
-
-define i64 @vsetvli_opt_sext_i64() nounwind {
-; CHECK-LABEL: @vsetvli_opt_sext_i64(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.opt.i64(i64 1, i64 1, i64 1)
-; CHECK-NEXT:    ret i64 [[TMP0]]
-;
-entry:
-  %0 = call i64 @llvm.riscv.vsetvli.opt.i64(i64 1, i64 1, i64 1)
-  %1 = trunc i64 %0 to i32
-  %2 = sext i32 %1 to i64
-  ret i64 %2
-}
-
-define i64 @vsetvli_opt_zext_i64() nounwind {
-; CHECK-LABEL: @vsetvli_opt_zext_i64(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.opt.i64(i64 1, i64 1, i64 1)
-; CHECK-NEXT:    ret i64 [[TMP0]]
-;
-entry:
-  %0 = call i64 @llvm.riscv.vsetvli.opt.i64(i64 1, i64 1, i64 1)
-  %1 = trunc i64 %0 to i32
-  %2 = zext i32 %1 to i64
-  ret i64 %2
-}
-
-define i32 @vsetvli_opt_and17_i32() nounwind {
-; CHECK-LABEL: @vsetvli_opt_and17_i32(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.vsetvli.opt.i32(i32 1, i32 1, i32 1)
-; CHECK-NEXT:    ret i32 [[TMP0]]
-;
-entry:
-  %0 = call i32 @llvm.riscv.vsetvli.opt.i32(i32 1, i32 1, i32 1)
-  %1 = and i32 %0, 131071
-  ret i32 %1
-}
-
-define i64 @vsetvli_opt_and17_i64() nounwind {
-; CHECK-LABEL: @vsetvli_opt_and17_i64(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.opt.i64(i64 1, i64 1, i64 1)
-; CHECK-NEXT:    ret i64 [[TMP0]]
-;
-entry:
-  %0 = call i64 @llvm.riscv.vsetvli.opt.i64(i64 1, i64 1, i64 1)
-  %1 = and i64 %0, 131071
-  ret i64 %1
-}
-
-define i32 @vsetvlimax_opt_i32() nounwind {
-; CHECK-LABEL: @vsetvlimax_opt_i32(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.vsetvlimax.opt.i32(i32 1, i32 1)
-; CHECK-NEXT:    ret i32 [[TMP0]]
-;
-entry:
-  %0 = call i32 @llvm.riscv.vsetvlimax.opt.i32(i32 1, i32 1)
-  %1 = and i32 %0, 2147483647
-  ret i32 %1
-}
-
-define i64 @vsetvlimax_opt_sext_i64() nounwind {
-; CHECK-LABEL: @vsetvlimax_opt_sext_i64(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.opt.i64(i64 1, i64 1)
-; CHECK-NEXT:    ret i64 [[TMP0]]
-;
-entry:
-  %0 = call i64 @llvm.riscv.vsetvlimax.opt.i64(i64 1, i64 1)
-  %1 = trunc i64 %0 to i32
-  %2 = sext i32 %1 to i64
-  ret i64 %2
-}
-
-define i64 @vsetvlimax_opt_zext_i64() nounwind {
-; CHECK-LABEL: @vsetvlimax_opt_zext_i64(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.opt.i64(i64 1, i64 1)
-; CHECK-NEXT:    ret i64 [[TMP0]]
-;
-entry:
-  %0 = call i64 @llvm.riscv.vsetvlimax.opt.i64(i64 1, i64 1)
-  %1 = trunc i64 %0 to i32
-  %2 = zext i32 %1 to i64
-  ret i64 %2
-}
-
-define i32 @vsetvlimax_opt_and17_i32() nounwind {
-; CHECK-LABEL: @vsetvlimax_opt_and17_i32(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.vsetvlimax.opt.i32(i32 1, i32 1)
-; CHECK-NEXT:    ret i32 [[TMP0]]
-;
-entry:
-  %0 = call i32 @llvm.riscv.vsetvlimax.opt.i32(i32 1, i32 1)
-  %1 = and i32 %0, 131071
-  ret i32 %1
-}
-
-define i64 @vsetvlimax_opt_and17_i64() nounwind {
-; CHECK-LABEL: @vsetvlimax_opt_and17_i64(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.opt.i64(i64 1, i64 1)
-; CHECK-NEXT:    ret i64 [[TMP0]]
-;
-entry:
-  %0 = call i64 @llvm.riscv.vsetvlimax.opt.i64(i64 1, i64 1)
-  %1 = and i64 %0, 131071
-  ret i64 %1
-}