[RISCV] Add vendor-defined XTHeadBs (single-bit) extension

[philipp.tomsich]

Summary

The vendor-defined XTHeadBs (predating the standard Zbs extension)
extension adds a bit-test instruction (th.tst) with similar semantics
as bexti from Zbs. It is supported by the C9xx cores (e.g., found in
the wild in the Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBs is
available from:

https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:

https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

[jrtc27]

The current (as of this commit) public documentation for XTHeadBa is

Copy/paste error

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

828–829

Update comment to include th.tst

958–959

Update comment

[philipp.tomsich]

• fix typo 'Ba -> Bs' in commit message
• update comments in ISelDAGToDAG to refer to bexti _and th.tst_

[• pcwang-thead]

llvm/test/CodeGen/RISCV/rv32xtheadbs.ll

8

Rename these tests from bexti to th_tst?

[philipp.tomsich]

• updated the test cases to have function names matching the instructions

[craig.topper]

Any plan to support RISCVTargetLowering::isMaskAndCmp0FoldingBeneficial, RISCVTargetLowering::hasBitTest, performTRUNCATECombine or performANDCombine?

[philipp.tomsich]

In D143036#4099959, @craig.topper wrote:

Any plan to support RISCVTargetLowering::isMaskAndCmp0FoldingBeneficial, RISCVTargetLowering::hasBitTest, performTRUNCATECombine or performANDCombine?

Yes, this is planned in a follow-up optimization ... if that is ok?
The plan is to get the basic support (such as in these initial patches) in and then add more optimizations as we run SPEC against the full set of extensions.

For XTHeadBb (which is the next one from the series that will go to Phabricator), there is some DAGToDAG work to support bit-extract instructions (i.e. similar to how AArch64 handles the formation of UBFM and SBFM nodes).
This will also be split off into a separate patch.

Ok to defer? Or would you rather have this go in with the initial enablement?

[philipp.tomsich]

Thinking some more about this, I'll just add the associated changes onto the initial patch for th.tst.
I have to double-check hasBitTest(), as XTHeadBs only has an immediate-form of the instruction (i.e., bexti only, but no bext).

[philipp.tomsich]

• wire up to existing optimisations in RISCVISelLowering.cpp
• rewrite RISCVTargetLowering::hasBitTest() to differentiate between immediate and non-immediate cases

[reames]

This generally looks reasonable to me, and I support adding this vendor extension once normal code review is complete.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1249–1253

Style wise, a series of early returns here would be easy to follow.

llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

80

Missing decoder namerspace

llvm/test/CodeGen/RISCV/rv32xtheadbs.ll

2

In this diff, you have coverage for both 32 and 64, but is this extension actually defined for RV32? The previous diff (THeadBa) was only tested on RV64. Why are these two handled differently here?

[philipp.tomsich]

• added decoder namespaces

llvm/test/CodeGen/RISCV/rv32xtheadbs.ll

2

In this diff, you have coverage for both 32 and 64, but is this extension actually defined for RV32? The previous diff (THeadBa) was only tested on RV64. Why are these two handled differently here?

Test cases to THeadBa have been added in the latest revisison.

[philipp.tomsich]

• add missing handling of the XTHeadBs decoder namespace in RISCV disassembler

[philipp.tomsich]

• include llvm/test/CodeGen/RISCV/bittest.ll into the test-coverage for XTHeadBs

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

830

Maybe put into a variable like bool HasBitTest = Subtarget->hasStdExtZbs() || Subtarget->hasVendorXTHeadBs() then use it here and on line 969 for the Skip?

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1252

We don't use NULL in llvm. Use nullptr.

8602

I think this code was for variable shifts is it relevant for this extension?

8846

I think this code was for variable shifts is it relevant for this extension?

[philipp.tomsich]

• rerun clang-format

[philipp.tomsich]

• update the 'Depends on' to (hopefully) fix automatic the CI for the stack

[philipp.tomsich]

• address Craig's review comments (style, NULL->nullptr and 2 variable shift paths)

[craig.topper]

Why does this patch depend on the MULCombine patch?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

959–960

These two lines can be merged

Skip |= HasBitTest && Leading == XLen - 1

[philipp.tomsich]

Reopening as this was accidentially pushed and reverted when doing 'arc patch on D143534'.

[philipp.tomsich]

• merged HasBitTest tests

[craig.topper]

LGTM

llvm/docs/RISCVUsage.rst

 
 It is our intention to follow the naming conventions described in `riscv-non-isa/riscv-toolchain-conventions <https://github.com/riscv-non-isa/riscv-toolchain-conventions#conventions-for-vendor-extensions>`_.  Exceptions to this naming will need to be strongly motivated.
 
 The current vendor extensions supported are:
 
 ``XTHeadBa``
   LLVM implements `the THeadBa (address-generation) vendor-defined instructions specified in <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf>`_  by T-HEAD of Alibaba.  Instructions are prefixed with `th.` as described in the specification.
 
+``XTHeadBs``
+  LLVM implements `the THeadBs (single-bit operations) vendor-defined instructions specified in <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf>`_  by T-HEAD of Alibaba.  Instructions are prefixed with `th.` as described in the specification.
+
 ``XTHeadVdot``
   LLVM implements `version 1.0.0 of the THeadV-family custom instructions specification <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.0/xthead-2022-12-04-2.2.0.pdf>`_ by T-HEAD of Alibaba.  All instructions are prefixed with `th.` as described in the specification, and the riscv-toolchain-convention document linked above.
 
 ``XVentanaCondOps``
   LLVM implements `version 1.0.0 of the VTx-family custom instructions specification <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf>`_ by Ventana Micro Systems.  All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchain-convention document linked above.  These instructions are only available for riscv64 at this time.
 
 Specification Documents
 =======================
 For ratified specifications, please refer to the `official RISC-V International
 page <https://riscv.org/technical/specifications/>`_.  Make sure to check the
 `wiki for not yet integrated extensions
 <https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions>`_.
 

llvm/docs/ReleaseNotes.rst

 Changes to the RISC-V Backend
 -----------------------------
 
 * Assembler support for version 1.0.1 of the Zcb extension was added.
 * Zca, Zcf, and Zcd extensions were upgraded to version 1.0.1.
 * vsetvli intrinsics no longer have side effects. They may now be combined,
   moved, deleted, etc. by optimizations.
 * Adds support for the vendor-defined XTHeadBa (address-generation) extension.
+* Adds support for the vendor-defined XTHeadBs (single-bit) extension.
 
 Changes to the WebAssembly Backend
 ----------------------------------
 
 * ...
 
 Changes to the Windows Target
 -----------------------------

llvm/lib/Support/RISCVISAInfo.cpp

static const RISCVSupportedExtension SupportedExtensions[] = {
     {"zicbop", RISCVExtensionVersion{1, 0}},
 
     {"svnapot", RISCVExtensionVersion{1, 0}},
     {"svpbmt", RISCVExtensionVersion{1, 0}},
     {"svinval", RISCVExtensionVersion{1, 0}},
 
     // vendor-defined ('X') extensions
     {"xtheadba", RISCVExtensionVersion{1, 0}},
+    {"xtheadbs", RISCVExtensionVersion{1, 0}},
     {"xtheadvdot", RISCVExtensionVersion{1, 0}},
     {"xventanacondops", RISCVExtensionVersion{1, 0}},
 };
 
 static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
     {"zihintntl", RISCVExtensionVersion{0, 2}},
 
     {"zca", RISCVExtensionVersion{1, 0}},

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

if ((Bytes[0] & 0x3) == 0x3) {
     }
     if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadBa]) {
       LLVM_DEBUG(dbgs() << "Trying XTHeadBa custom opcode table:\n");
       Result = decodeInstruction(DecoderTableTHeadBa32, MI, Insn, Address, this,
                                  STI);
       if (Result != MCDisassembler::Fail)
         return Result;
     }
+    if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadBs]) {
+      LLVM_DEBUG(dbgs() << "Trying XTHeadBs custom opcode table:\n");
+      Result = decodeInstruction(DecoderTableTHeadBs32, MI, Insn, Address, this,
+                                 STI);
+      if (Result != MCDisassembler::Fail)
+        return Result;
+    }
     if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadVdot]) {
       LLVM_DEBUG(dbgs() << "Trying XTHeadVdot custom opcode table:\n");
       Result =
           decodeInstruction(DecoderTableTHeadV32, MI, Insn, Address, this, STI);
       if (Result != MCDisassembler::Fail)
         return Result;
     }
 

llvm/lib/Target/RISCV/RISCVFeatures.td

 
 def FeatureVendorXTHeadBa
     : SubtargetFeature<"xtheadba", "HasVendorXTHeadBa", "true",
                        "'xtheadba' (T-Head address calculation instructions)">;
 def HasVendorXTHeadBa : Predicate<"Subtarget->hasVendorXTHeadBa()">,
                                   AssemblerPredicate<(all_of FeatureVendorXTHeadBa),
                                   "'xtheadba' (T-Head address calculation instructions)">;
 
+def FeatureVendorXTHeadBs
+    : SubtargetFeature<"xtheadbs", "HasVendorXTHeadBs", "true",
+                       "'xtheadbs' (T-Head single-bit instructions)">;
+def HasVendorXTHeadBs : Predicate<"Subtarget->hasVendorXTHeadBs()">,
+                                  AssemblerPredicate<(all_of FeatureVendorXTHeadBs),
+                                  "'xtheadbs' (T-Head single-bit instructions)">;
+
 def FeatureVendorXTHeadVdot
     : SubtargetFeature<"xtheadvdot", "HasVendorXTHeadVdot", "true",
                        "'xtheadvdot' (T-Head Vector Extensions for Dot)",
                        [FeatureStdExtV]>;
 def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">,
                                     AssemblerPredicate<(all_of FeatureVendorXTHeadVdot),
                                     "'xtheadvdot' (T-Head Vector Extensions for Dot)">;
 

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

void RISCVDAGToDAGISel::Select(SDNode *Node) {
 
   // Instruction Selection not handled by the auto-generated tablegen selection
   // should be handled here.
   unsigned Opcode = Node->getOpcode();
   MVT XLenVT = Subtarget->getXLenVT();
   SDLoc DL(Node);
   MVT VT = Node->getSimpleValueType(0);
 
+  bool HasBitTest = Subtarget->hasStdExtZbs() || Subtarget->hasVendorXTHeadBs();
+
   switch (Opcode) {
   case ISD::Constant: {
     assert(VT == Subtarget->getXLenVT() && "Unexpected VT");
     auto *ConstNode = cast<ConstantSDNode>(Node);
     if (ConstNode->isZero()) {
       SDValue New =
           CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, RISCV::X0, VT);
       ReplaceNode(Node, New.getNode());
if (TrailingOnes == 32) {
                                  CurDAG->getTargetConstant(ShAmt, DL, VT));
       ReplaceNode(Node, SRLIW);
       return;
     }
 
     // Only do the remaining transforms if the AND has one use.
     if (!N0.hasOneUse())
       break;
 
-    // If C2 is (1 << ShAmt) use bexti if possible.
-    if (Subtarget->hasStdExtZbs() && ShAmt + 1 == TrailingOnes) {
-      SDNode *BEXTI =
-          CurDAG->getMachineNode(RISCV::BEXTI, DL, VT, N0->getOperand(0),
-                                 CurDAG->getTargetConstant(ShAmt, DL, VT));
+    // If C2 is (1 << ShAmt) use bexti or th.tst if possible.
+    if (HasBitTest && ShAmt + 1 == TrailingOnes) {
+      SDNode *BEXTI = CurDAG->getMachineNode(
+          Subtarget->hasStdExtZbs() ? RISCV::BEXTI : RISCV::TH_TST, DL, VT,
+          N0->getOperand(0), CurDAG->getTargetConstant(ShAmt, DL, VT));
       ReplaceNode(Node, BEXTI);
       return;
     }
+
     unsigned LShAmt = Subtarget->getXLen() - TrailingOnes;
     SDNode *SLLI =
         CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0->getOperand(0),
                                CurDAG->getTargetConstant(LShAmt, DL, VT));
     SDNode *SRLI = CurDAG->getMachineNode(
         RISCV::SRLI, DL, VT, SDValue(SLLI, 0),
         CurDAG->getTargetConstant(LShAmt + ShAmt, DL, VT));
     ReplaceNode(Node, SRLI);
if (LeftShift || N0.getOpcode() == ISD::SRL) {
             ReplaceNode(Node, SRLIW);
             return;
           }
 
           // (srli (slli x, c3-c2), c3).
           // Skip if we could use (zext.w (sraiw X, C2)).
           bool Skip = Subtarget->hasStdExtZba() && Leading == 32 &&
                       X.getOpcode() == ISD::SIGN_EXTEND_INREG &&
                       cast<VTSDNode>(X.getOperand(1))->getVT() == MVT::i32;
-          // Also Skip if we can use bexti.
-          Skip |= Subtarget->hasStdExtZbs() && Leading == XLen - 1;
+          // Also Skip if we can use bexti or th.tst.
+          Skip |= HasBitTest && Leading == XLen - 1;
           if (OneUseOrZExtW && !Skip) {
             SDNode *SLLI = CurDAG->getMachineNode(
                 RISCV::SLLI, DL, VT, X,
                 CurDAG->getTargetConstant(Leading - C2, DL, VT));
             SDNode *SRLI = CurDAG->getMachineNode(
                 RISCV::SRLI, DL, VT, SDValue(SLLI, 0),
                 CurDAG->getTargetConstant(Leading, DL, VT));
             ReplaceNode(Node, SRLI);

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 bool RISCVTargetLowering::isMaskAndCmp0FoldingBeneficial(
     const Instruction &AndI) const {
   // We expect to be able to match a bit extraction instruction if the Zbs
   // extension is supported and the mask is a power of two. However, we
   // conservatively return false if the mask would fit in an ANDI instruction,
   // on the basis that it's possible the sinking+duplication of the AND in
   // CodeGenPrepare triggered by this hook wouldn't decrease the instruction
   // count and would increase code size (e.g. ANDI+BNEZ => BEXTI+BNEZ).
-  if (!Subtarget.hasStdExtZbs())
+  if (!Subtarget.hasStdExtZbs() && !Subtarget.hasVendorXTHeadBs())
     return false;
   ConstantInt *Mask = dyn_cast<ConstantInt>(AndI.getOperand(1));
   if (!Mask)
     return false;
   return !Mask->getValue().isSignedIntN(12) && Mask->getValue().isPowerOf2();
 }
 
 bool RISCVTargetLowering::hasAndNotCompare(SDValue Y) const {
   EVT VT = Y.getValueType();
 
   // FIXME: Support vectors once we have tests.
   if (VT.isVector())
     return false;
 
   return (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb()) &&
          !isa<ConstantSDNode>(Y);
 }
 
 bool RISCVTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
   // Zbs provides BEXT[_I], which can be used with SEQZ/SNEZ as a bit test.
   if (Subtarget.hasStdExtZbs())
     return X.getValueType().isScalarInteger();
-  // We can use ANDI+SEQZ/SNEZ as a bit test. Y contains the bit position.
   auto *C = dyn_cast<ConstantSDNode>(Y);
+  // XTheadBs provides th.tst (similar to bexti), if Y is a constant
+  if (Subtarget.hasVendorXTHeadBs())
+    return C != nullptr;
+  // We can use ANDI+SEQZ/SNEZ as a bit test. Y contains the bit position.
   return C && C->getAPIntValue().ule(10);
 }
 
 bool RISCVTargetLowering::shouldFoldSelectWithIdentityConstant(unsigned Opcode,
                                                                EVT VT) const {
   // Only enable for rvv.
   if (!VT.isVector() || !Subtarget.hasVInstructions())
     return false;
static SDValue performTRUNCATECombine(SDNode *N, SelectionDAG &DAG,
   // Pre-promote (i1 (truncate (srl X, Y))) on RV64 with Zbs without zero
   // extending X. This is safe since we only need the LSB after the shift and
   // shift amounts larger than 31 would produce poison. If we wait until
   // type legalization, we'll create RISCVISD::SRLW and we can't recover it
   // to use a BEXT instruction.
   if (Subtarget.is64Bit() && Subtarget.hasStdExtZbs() && VT == MVT::i1 &&
       N0.getValueType() == MVT::i32 && N0.getOpcode() == ISD::SRL &&
       !isa<ConstantSDNode>(N0.getOperand(1)) && N0.hasOneUse()) {
     SDLoc DL(N0);
     SDValue Op0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N0.getOperand(0));
     SDValue Op1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N0.getOperand(1));
     SDValue Srl = DAG.getNode(ISD::SRL, DL, MVT::i64, Op0, Op1);
     return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Srl);
   }
 
   return SDValue();
 }
static SDValue performANDCombine(SDNode *N,
 
   SDValue N0 = N->getOperand(0);
   // Pre-promote (i32 (and (srl X, Y), 1)) on RV64 with Zbs without zero
   // extending X. This is safe since we only need the LSB after the shift and
   // shift amounts larger than 31 would produce poison. If we wait until
   // type legalization, we'll create RISCVISD::SRLW and we can't recover it
   // to use a BEXT instruction.
   if (Subtarget.is64Bit() && Subtarget.hasStdExtZbs() &&
       N->getValueType(0) == MVT::i32 && isOneConstant(N->getOperand(1)) &&
       N0.getOpcode() == ISD::SRL && !isa<ConstantSDNode>(N0.getOperand(1)) &&
       N0.hasOneUse()) {
     SDLoc DL(N);
     SDValue Op0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N0.getOperand(0));
     SDValue Op1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N0.getOperand(1));
     SDValue Srl = DAG.getNode(ISD::SRL, DL, MVT::i64, Op0, Op1);
     SDValue And = DAG.getNode(ISD::AND, DL, MVT::i64, Srl,
                               DAG.getConstant(1, DL, MVT::i64));

llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 let Predicates = [HasVendorXTHeadBa] in {
 def TH_ADDSL : THShiftALU_rri<0b001, "th.addsl">,
                Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
 } // Predicates = [HasVendorXTHeadBa]
 
+let Predicates = [HasVendorXTHeadBs], DecoderNamespace = "THeadBs" in {
+let IsSignExtendingOpW = 1 in
+def TH_TST : RVBShift_ri<0b10001, 0b001, OPC_CUSTOM_0, "th.tst">,
+             Sched<[WriteSingleBitImm, ReadSingleBitImm]>;
+} // Predicates = [HasVendorXTHeadBs]
+
 let Predicates = [HasVendorXTHeadVdot],
     Constraints = "@earlyclobber $vd",
     RVVConstraint = WidenV in {
 defm THVdotVMAQA      : THVdotVMAQA<"th.vmaqa",     0b100000>;
 defm THVdotVMAQAU     : THVdotVMAQA<"th.vmaqau",    0b100010>;
 defm THVdotVMAQASU    : THVdotVMAQA<"th.vmaqasu",   0b100100>;
 defm THVdotVMAQAUS    : THVdotVMAQA_VX<"th.vmaqaus",0b100110>;
 }

 def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 81)),
     (TH_ADDSL (TH_ADDSL GPR:$r, GPR:$r, 3), (TH_ADDSL GPR:$r, GPR:$r, 3), 3)>;
 
 def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 200)),
     (SLLI (TH_ADDSL (TH_ADDSL GPR:$r, GPR:$r, 2),
            (TH_ADDSL GPR:$r, GPR:$r, 2), 2), 3)>;
 } // Predicates = [HasVendorXTHeadBa]
 
+let Predicates = [HasVendorXTHeadBs] in {
+def : Pat<(and (srl GPR:$rs1, uimmlog2xlen:$shamt), 1),
+          (TH_TST GPR:$rs1, uimmlog2xlen:$shamt)>;
+def : Pat<(seteq (and GPR:$rs1, SingleBitSetMask:$mask), 0),
+          (TH_TST (XORI GPR:$rs1, -1), SingleBitSetMask:$mask)>;
+} // Predicates = [HasVendorXTHeadBs]
+
+
 defm PseudoTHVdotVMAQA      : VPseudoVMAQA_VV_VX;
 defm PseudoTHVdotVMAQAU     : VPseudoVMAQA_VV_VX;
 defm PseudoTHVdotVMAQASU    : VPseudoVMAQA_VV_VX;
 defm PseudoTHVdotVMAQAUS    : VPseudoVMAQA_VX;
 
 let Predicates = [HasVendorXTHeadVdot] in {
 defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqa",  "PseudoTHVdotVMAQA",  AllQuadWidenableInt8NoVLMulVectors>;
 defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqau", "PseudoTHVdotVMAQAU", AllQuadWidenableInt8NoVLMulVectors>;
 defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqasu","PseudoTHVdotVMAQASU",AllQuadWidenableInt8NoVLMulVectors>;
 defm : VPatTernaryVMAQA_VX<"int_riscv_th_vmaqaus",   "PseudoTHVdotVMAQAUS",AllQuadWidenableInt8NoVLMulVectors>;
 }

llvm/test/CodeGen/RISCV/attributes.ll

 ; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICBOM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICBOP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV64SVNAPOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV64SVPBMT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV64SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefixes=CHECK,RV64XVENTANACONDOPS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xtheadba %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADBA %s
+; RUN: llc -mtriple=riscv64 -mattr=+xtheadbs %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADBS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADVDOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefixes=CHECK,RV64ZTSO %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCB %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCD %s
 
 ; CHECK: .attribute 4, 16

 ; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
 ; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
 ; RV64SVPBMT: .attribute 5, "rv64i2p0_svpbmt1p0"
 ; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
 ; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
 ; RV64XTHEADBA: .attribute 5, "rv64i2p0_xtheadba1p0"
+; RV64XTHEADBS: .attribute 5, "rv64i2p0_xtheadbs1p0"
 ; RV64XTHEADVDOT: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 ; RV64ZCA: .attribute 5, "rv64i2p0_zca1p0"
 ; RV64ZCB: .attribute 5, "rv64i2p0_zca1p0_zcb1p0"
 ; RV64ZCD: .attribute 5, "rv64i2p0_zcd1p0"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
   ret i32 %1
 }

llvm/test/CodeGen/RISCV/bittest.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32,RV32I
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64,RV64I
 ; RUN: llc -mtriple=riscv32 -mattr=+zbs -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefixes=CHECK,ZBS,RV32,RV32ZBS
 ; RUN: llc -mtriple=riscv64 -mattr=+zbs -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefixes=CHECK,ZBS,RV64,RV64ZBS
+; RUN: llc -mtriple=riscv32 -mattr=+xtheadbs -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefixes=CHECK,XTHEADBS,RV32,RV32XTHEADBS
+; RUN: llc -mtriple=riscv64 -mattr=+xtheadbs -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefixes=CHECK,XTHEADBS,RV64,RV64XTHEADBS
 
 define signext i32 @bittest_7_i32(i32 signext %a) nounwind {
 ; CHECK-LABEL: bittest_7_i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi a0, a0, 128
 ; CHECK-NEXT:    seqz a0, a0
 ; CHECK-NEXT:    ret
   %shr = lshr i32 %a, 7

 ; RV64I-NEXT:    srli a0, a0, 63
 ; RV64I-NEXT:    ret
 ;
 ; ZBS-LABEL: bittest_11_i32:
 ; ZBS:       # %bb.0:
 ; ZBS-NEXT:    not a0, a0
 ; ZBS-NEXT:    bexti a0, a0, 11
 ; ZBS-NEXT:    ret
+;
+; XTHEADBS-LABEL: bittest_11_i32:
+; XTHEADBS:       # %bb.0:
+; XTHEADBS-NEXT:    not a0, a0
+; XTHEADBS-NEXT:    th.tst a0, a0, 11
+; XTHEADBS-NEXT:    ret
   %shr = lshr i32 %a, 11
   %not = xor i32 %shr, -1
   %and = and i32 %not, 1
   ret i32 %and
 }
 
 define signext i32 @bittest_31_i32(i32 signext %a) nounwind {
 ; RV32-LABEL: bittest_31_i32:

 ; RV32ZBS-NEXT:    li a1, 0
 ; RV32ZBS-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bittest_11_i64:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    not a0, a0
 ; RV64ZBS-NEXT:    bexti a0, a0, 11
 ; RV64ZBS-NEXT:    ret
+;
+; RV32XTHEADBS-LABEL: bittest_11_i64:
+; RV32XTHEADBS:       # %bb.0:
+; RV32XTHEADBS-NEXT:    not a0, a0
+; RV32XTHEADBS-NEXT:    th.tst a0, a0, 11
+; RV32XTHEADBS-NEXT:    li a1, 0
+; RV32XTHEADBS-NEXT:    ret
+;
+; RV64XTHEADBS-LABEL: bittest_11_i64:
+; RV64XTHEADBS:       # %bb.0:
+; RV64XTHEADBS-NEXT:    not a0, a0
+; RV64XTHEADBS-NEXT:    th.tst a0, a0, 11
+; RV64XTHEADBS-NEXT:    ret
   %shr = lshr i64 %a, 11
   %not = xor i64 %shr, -1
   %and = and i64 %not, 1
   ret i64 %and
 }
 
 define i64 @bittest_31_i64(i64 %a) nounwind {
 ; RV32-LABEL: bittest_31_i64:

 ; RV64I-NEXT:    srliw a0, a0, 31
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bittest_31_i64:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    not a0, a0
 ; RV64ZBS-NEXT:    bexti a0, a0, 31
 ; RV64ZBS-NEXT:    ret
+;
+; RV64XTHEADBS-LABEL: bittest_31_i64:
+; RV64XTHEADBS:       # %bb.0:
+; RV64XTHEADBS-NEXT:    not a0, a0
+; RV64XTHEADBS-NEXT:    th.tst a0, a0, 31
+; RV64XTHEADBS-NEXT:    ret
   %shr = lshr i64 %a, 31
   %not = xor i64 %shr, -1
   %and = and i64 %not, 1
   ret i64 %and
 }
 
 define i64 @bittest_32_i64(i64 %a) nounwind {
 ; RV32-LABEL: bittest_32_i64:

 ; RV64I-NEXT:    srli a0, a0, 63
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bittest_32_i64:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    not a0, a0
 ; RV64ZBS-NEXT:    bexti a0, a0, 32
 ; RV64ZBS-NEXT:    ret
+;
+; RV64XTHEADBS-LABEL: bittest_32_i64:
+; RV64XTHEADBS:       # %bb.0:
+; RV64XTHEADBS-NEXT:    not a0, a0
+; RV64XTHEADBS-NEXT:    th.tst a0, a0, 32
+; RV64XTHEADBS-NEXT:    ret
   %shr = lshr i64 %a, 32
   %not = xor i64 %shr, -1
   %and = and i64 %not, 1
   ret i64 %and
 }
 
 define i64 @bittest_63_i64(i64 %a) nounwind {
 ; RV32-LABEL: bittest_63_i64:

 ; RV32ZBS-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bittest_constant_by_var_shr_i32:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    lui a1, 301408
 ; RV64ZBS-NEXT:    addiw a1, a1, 722
 ; RV64ZBS-NEXT:    bext a0, a1, a0
 ; RV64ZBS-NEXT:    ret
+;
+; RV32XTHEADBS-LABEL: bittest_constant_by_var_shr_i32:
+; RV32XTHEADBS:       # %bb.0:
+; RV32XTHEADBS-NEXT:    lui a1, 301408
+; RV32XTHEADBS-NEXT:    addi a1, a1, 722
+; RV32XTHEADBS-NEXT:    srl a0, a1, a0
+; RV32XTHEADBS-NEXT:    andi a0, a0, 1
+; RV32XTHEADBS-NEXT:    ret
+;
+; RV64XTHEADBS-LABEL: bittest_constant_by_var_shr_i32:
+; RV64XTHEADBS:       # %bb.0:
+; RV64XTHEADBS-NEXT:    lui a1, 301408
+; RV64XTHEADBS-NEXT:    addiw a1, a1, 722
+; RV64XTHEADBS-NEXT:    srlw a0, a1, a0
+; RV64XTHEADBS-NEXT:    andi a0, a0, 1
+; RV64XTHEADBS-NEXT:    ret
   %shl = lshr i32 1234567890, %b
   %and = and i32 %shl, 1
   %cmp = icmp ne i32 %and, 0
   ret i1 %cmp
 }
 
 ; Make sure we use (andi (srl X, Y), 1) or bext.
 define i1 @bittest_constant_by_var_shl_i32(i32 signext %b) nounwind {

 ; RV32ZBS-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bittest_constant_by_var_shl_i32:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    lui a1, 301408
 ; RV64ZBS-NEXT:    addiw a1, a1, 722
 ; RV64ZBS-NEXT:    bext a0, a1, a0
 ; RV64ZBS-NEXT:    ret
+;
+; RV32XTHEADBS-LABEL: bittest_constant_by_var_shl_i32:
+; RV32XTHEADBS:       # %bb.0:
+; RV32XTHEADBS-NEXT:    lui a1, 301408
+; RV32XTHEADBS-NEXT:    addi a1, a1, 722
+; RV32XTHEADBS-NEXT:    srl a0, a1, a0
+; RV32XTHEADBS-NEXT:    andi a0, a0, 1
+; RV32XTHEADBS-NEXT:    ret
+;
+; RV64XTHEADBS-LABEL: bittest_constant_by_var_shl_i32:
+; RV64XTHEADBS:       # %bb.0:
+; RV64XTHEADBS-NEXT:    lui a1, 301408
+; RV64XTHEADBS-NEXT:    addiw a1, a1, 722
+; RV64XTHEADBS-NEXT:    srlw a0, a1, a0
+; RV64XTHEADBS-NEXT:    andi a0, a0, 1
+; RV64XTHEADBS-NEXT:    ret
   %shl = shl i32 1, %b
   %and = and i32 %shl, 1234567890
   %cmp = icmp ne i32 %and, 0
   ret i1 %cmp
 }
 
 ; Make sure we use (andi (srl X, Y), 1) or bext.
 define i1 @bittest_constant_by_var_shr_i64(i64 %b) nounwind {

 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bittest_constant_by_var_shr_i64:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    lui a1, 301408
 ; RV64ZBS-NEXT:    addiw a1, a1, 722
 ; RV64ZBS-NEXT:    bext a0, a1, a0
 ; RV64ZBS-NEXT:    ret
+;
+; RV64XTHEADBS-LABEL: bittest_constant_by_var_shr_i64:
+; RV64XTHEADBS:       # %bb.0:
+; RV64XTHEADBS-NEXT:    lui a1, 301408
+; RV64XTHEADBS-NEXT:    addiw a1, a1, 722
+; RV64XTHEADBS-NEXT:    srl a0, a1, a0
+; RV64XTHEADBS-NEXT:    andi a0, a0, 1
+; RV64XTHEADBS-NEXT:    ret
   %shl = lshr i64 1234567890, %b
   %and = and i64 %shl, 1
   %cmp = icmp ne i64 %and, 0
   ret i1 %cmp
 }
 
 ; Make sure we use (andi (srl X, Y), 1) or bext.
 define i1 @bittest_constant_by_var_shl_i64(i64 %b) nounwind {

 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bittest_constant_by_var_shl_i64:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    lui a1, 301408
 ; RV64ZBS-NEXT:    addiw a1, a1, 722
 ; RV64ZBS-NEXT:    bext a0, a1, a0
 ; RV64ZBS-NEXT:    ret
+;
+; RV64XTHEADBS-LABEL: bittest_constant_by_var_shl_i64:
+; RV64XTHEADBS:       # %bb.0:
+; RV64XTHEADBS-NEXT:    lui a1, 301408
+; RV64XTHEADBS-NEXT:    addiw a1, a1, 722
+; RV64XTHEADBS-NEXT:    srl a0, a1, a0
+; RV64XTHEADBS-NEXT:    andi a0, a0, 1
+; RV64XTHEADBS-NEXT:    ret
   %shl = shl i64 1, %b
   %and = and i64 %shl, 1234567890
   %cmp = icmp ne i64 %and, 0
   ret i1 %cmp
 }
 
 ; We want to use (andi (srl X, Y), 1) or bext before the beqz.
 define void @bittest_switch(i32 signext %0) {

 ; RV64ZBS-NEXT:    addiw a1, a1, 51
 ; RV64ZBS-NEXT:    slli a1, a1, 8
 ; RV64ZBS-NEXT:    bext a0, a1, a0
 ; RV64ZBS-NEXT:    beqz a0, .LBB14_3
 ; RV64ZBS-NEXT:  # %bb.2:
 ; RV64ZBS-NEXT:    tail bar@plt
 ; RV64ZBS-NEXT:  .LBB14_3:
 ; RV64ZBS-NEXT:    ret
+;
+; RV32XTHEADBS-LABEL: bittest_switch:
+; RV32XTHEADBS:       # %bb.0:
+; RV32XTHEADBS-NEXT:    li a1, 31
+; RV32XTHEADBS-NEXT:    bltu a1, a0, .LBB14_3
+; RV32XTHEADBS-NEXT:  # %bb.1:
+; RV32XTHEADBS-NEXT:    lui a1, 524291
+; RV32XTHEADBS-NEXT:    addi a1, a1, 768
+; RV32XTHEADBS-NEXT:    srl a0, a1, a0
+; RV32XTHEADBS-NEXT:    andi a0, a0, 1
+; RV32XTHEADBS-NEXT:    beqz a0, .LBB14_3
+; RV32XTHEADBS-NEXT:  # %bb.2:
+; RV32XTHEADBS-NEXT:    tail bar@plt
+; RV32XTHEADBS-NEXT:  .LBB14_3:
+; RV32XTHEADBS-NEXT:    ret
+;
+; RV64XTHEADBS-LABEL: bittest_switch:
+; RV64XTHEADBS:       # %bb.0:
+; RV64XTHEADBS-NEXT:    li a1, 31
+; RV64XTHEADBS-NEXT:    bltu a1, a0, .LBB14_3
+; RV64XTHEADBS-NEXT:  # %bb.1:
+; RV64XTHEADBS-NEXT:    lui a1, 2048
+; RV64XTHEADBS-NEXT:    addiw a1, a1, 51
+; RV64XTHEADBS-NEXT:    slli a1, a1, 8
+; RV64XTHEADBS-NEXT:    srl a0, a1, a0
+; RV64XTHEADBS-NEXT:    andi a0, a0, 1
+; RV64XTHEADBS-NEXT:    beqz a0, .LBB14_3
+; RV64XTHEADBS-NEXT:  # %bb.2:
+; RV64XTHEADBS-NEXT:    tail bar@plt
+; RV64XTHEADBS-NEXT:  .LBB14_3:
+; RV64XTHEADBS-NEXT:    ret
   switch i32 %0, label %3 [
     i32 8, label %2
     i32 9, label %2
     i32 12, label %2
     i32 13, label %2
     i32 31, label %2
   ]
 

 ; RV32ZBS-NEXT:    mv a1, a3
 ; RV32ZBS-NEXT:    mv a0, a2
 ; RV32ZBS-NEXT:    bnez a6, .LBB24_2
 ; RV32ZBS-NEXT:  # %bb.1:
 ; RV32ZBS-NEXT:    mv a0, a4
 ; RV32ZBS-NEXT:    mv a1, a5
 ; RV32ZBS-NEXT:  .LBB24_2:
 ; RV32ZBS-NEXT:    ret
+;
+; RV32XTHEADBS-LABEL: bit_10_nz_select_i64:
+; RV32XTHEADBS:       # %bb.0:
+; RV32XTHEADBS-NEXT:    th.tst a6, a0, 10
+; RV32XTHEADBS-NEXT:    mv a1, a3
+; RV32XTHEADBS-NEXT:    mv a0, a2
+; RV32XTHEADBS-NEXT:    bnez a6, .LBB24_2
+; RV32XTHEADBS-NEXT:  # %bb.1:
+; RV32XTHEADBS-NEXT:    mv a0, a4
+; RV32XTHEADBS-NEXT:    mv a1, a5
+; RV32XTHEADBS-NEXT:  .LBB24_2:
+; RV32XTHEADBS-NEXT:    ret
   %1 = and i64 %a, 1024
   %2 = icmp ne i64 %1, 0
   %3 = select i1 %2, i64 %b, i64 %c
   ret i64 %3
 }
 
 define i64 @bit_11_z_select_i64(i64 %a, i64 %b, i64 %c) {
 ; RV32-LABEL: bit_11_z_select_i64:

 ; RV32ZBS-NEXT:    mv a1, a3
 ; RV32ZBS-NEXT:    mv a0, a2
 ; RV32ZBS-NEXT:    bnez a6, .LBB26_2
 ; RV32ZBS-NEXT:  # %bb.1:
 ; RV32ZBS-NEXT:    mv a0, a4
 ; RV32ZBS-NEXT:    mv a1, a5
 ; RV32ZBS-NEXT:  .LBB26_2:
 ; RV32ZBS-NEXT:    ret
+;
+; RV32XTHEADBS-LABEL: bit_11_nz_select_i64:
+; RV32XTHEADBS:       # %bb.0:
+; RV32XTHEADBS-NEXT:    th.tst a6, a0, 11
+; RV32XTHEADBS-NEXT:    mv a1, a3
+; RV32XTHEADBS-NEXT:    mv a0, a2
+; RV32XTHEADBS-NEXT:    bnez a6, .LBB26_2
+; RV32XTHEADBS-NEXT:  # %bb.1:
+; RV32XTHEADBS-NEXT:    mv a0, a4
+; RV32XTHEADBS-NEXT:    mv a1, a5
+; RV32XTHEADBS-NEXT:  .LBB26_2:
+; RV32XTHEADBS-NEXT:    ret
   %1 = and i64 %a, 2048
   %2 = icmp ne i64 %1, 0
   %3 = select i1 %2, i64 %b, i64 %c
   ret i64 %3
 }
 
 define i64 @bit_20_z_select_i64(i64 %a, i64 %b, i64 %c) {
 ; RV32-LABEL: bit_20_z_select_i64:

 ; RV32ZBS-NEXT:    mv a1, a3
 ; RV32ZBS-NEXT:    mv a0, a2
 ; RV32ZBS-NEXT:    bnez a6, .LBB28_2
 ; RV32ZBS-NEXT:  # %bb.1:
 ; RV32ZBS-NEXT:    mv a0, a4
 ; RV32ZBS-NEXT:    mv a1, a5
 ; RV32ZBS-NEXT:  .LBB28_2:
 ; RV32ZBS-NEXT:    ret
+;
+; RV32XTHEADBS-LABEL: bit_20_nz_select_i64:
+; RV32XTHEADBS:       # %bb.0:
+; RV32XTHEADBS-NEXT:    th.tst a6, a0, 20
+; RV32XTHEADBS-NEXT:    mv a1, a3
+; RV32XTHEADBS-NEXT:    mv a0, a2
+; RV32XTHEADBS-NEXT:    bnez a6, .LBB28_2
+; RV32XTHEADBS-NEXT:  # %bb.1:
+; RV32XTHEADBS-NEXT:    mv a0, a4
+; RV32XTHEADBS-NEXT:    mv a1, a5
+; RV32XTHEADBS-NEXT:  .LBB28_2:
+; RV32XTHEADBS-NEXT:    ret
   %1 = and i64 %a, 1048576
   %2 = icmp ne i64 %1, 0
   %3 = select i1 %2, i64 %b, i64 %c
   ret i64 %3
 }
 
 define i64 @bit_31_z_select_i64(i64 %a, i64 %b, i64 %c) {
 ; RV32-LABEL: bit_31_z_select_i64:

 ; RV32ZBS-NEXT:    mv a1, a3
 ; RV32ZBS-NEXT:    mv a0, a2
 ; RV32ZBS-NEXT:    bnez a6, .LBB34_2
 ; RV32ZBS-NEXT:  # %bb.1:
 ; RV32ZBS-NEXT:    mv a0, a4
 ; RV32ZBS-NEXT:    mv a1, a5
 ; RV32ZBS-NEXT:  .LBB34_2:
 ; RV32ZBS-NEXT:    ret
+;
+; RV32XTHEADBS-LABEL: bit_55_nz_select_i64:
+; RV32XTHEADBS:       # %bb.0:
+; RV32XTHEADBS-NEXT:    th.tst a6, a1, 23
+; RV32XTHEADBS-NEXT:    mv a1, a3
+; RV32XTHEADBS-NEXT:    mv a0, a2
+; RV32XTHEADBS-NEXT:    bnez a6, .LBB34_2
+; RV32XTHEADBS-NEXT:  # %bb.1:
+; RV32XTHEADBS-NEXT:    mv a0, a4
+; RV32XTHEADBS-NEXT:    mv a1, a5
+; RV32XTHEADBS-NEXT:  .LBB34_2:
+; RV32XTHEADBS-NEXT:    ret
   %1 = and i64 %a, 36028797018963968
   %2 = icmp ne i64 %1, 0
   %3 = select i1 %2, i64 %b, i64 %c
   ret i64 %3
 }
 
 define i64 @bit_63_z_select_i64(i64 %a, i64 %b, i64 %c) {
 ; RV32-LABEL: bit_63_z_select_i64:

 ; RV32ZBS-NEXT:    mv a1, a3
 ; RV32ZBS-NEXT:    mv a0, a2
 ; RV32ZBS-NEXT:    beqz a6, .LBB85_2
 ; RV32ZBS-NEXT:  # %bb.1:
 ; RV32ZBS-NEXT:    mv a0, a4
 ; RV32ZBS-NEXT:    mv a1, a5
 ; RV32ZBS-NEXT:  .LBB85_2:
 ; RV32ZBS-NEXT:    ret
+;
+; RV32XTHEADBS-LABEL: bit_63_1_z_select_i64:
+; RV32XTHEADBS:       # %bb.0:
+; RV32XTHEADBS-NEXT:    slli a1, a1, 1
+; RV32XTHEADBS-NEXT:    srli a1, a1, 1
+; RV32XTHEADBS-NEXT:    or a6, a0, a1
+; RV32XTHEADBS-NEXT:    mv a1, a3
+; RV32XTHEADBS-NEXT:    mv a0, a2
+; RV32XTHEADBS-NEXT:    beqz a6, .LBB85_2
+; RV32XTHEADBS-NEXT:  # %bb.1:
+; RV32XTHEADBS-NEXT:    mv a0, a4
+; RV32XTHEADBS-NEXT:    mv a1, a5
+; RV32XTHEADBS-NEXT:  .LBB85_2:
+; RV32XTHEADBS-NEXT:    ret
   %1 = and i64 %a, 9223372036854775807
   %2 = icmp eq i64 %1, 0
   %3 = select i1 %2, i64 %b, i64 %c
   ret i64 %3
 }
 
 define i64 @bit_63_1_nz_select_i64(i64 %a, i64 %b, i64 %c) {
 ; RV32I-LABEL: bit_63_1_nz_select_i64:

 ; RV32ZBS-NEXT:    mv a1, a3
 ; RV32ZBS-NEXT:    mv a0, a2
 ; RV32ZBS-NEXT:    bnez a6, .LBB86_2
 ; RV32ZBS-NEXT:  # %bb.1:
 ; RV32ZBS-NEXT:    mv a0, a4
 ; RV32ZBS-NEXT:    mv a1, a5
 ; RV32ZBS-NEXT:  .LBB86_2:
 ; RV32ZBS-NEXT:    ret
+;
+; RV32XTHEADBS-LABEL: bit_63_1_nz_select_i64:
+; RV32XTHEADBS:       # %bb.0:
+; RV32XTHEADBS-NEXT:    slli a1, a1, 1
+; RV32XTHEADBS-NEXT:    srli a1, a1, 1
+; RV32XTHEADBS-NEXT:    or a6, a0, a1
+; RV32XTHEADBS-NEXT:    mv a1, a3
+; RV32XTHEADBS-NEXT:    mv a0, a2
+; RV32XTHEADBS-NEXT:    bnez a6, .LBB86_2
+; RV32XTHEADBS-NEXT:  # %bb.1:
+; RV32XTHEADBS-NEXT:    mv a0, a4
+; RV32XTHEADBS-NEXT:    mv a1, a5
+; RV32XTHEADBS-NEXT:  .LBB86_2:
+; RV32XTHEADBS-NEXT:    ret
   %1 = and i64 %a, 9223372036854775807
   %2 = icmp ne i64 %1, 0
   %3 = select i1 %2, i64 %b, i64 %c
   ret i64 %3
 }
 
 define i64 @bit_64_1_z_select_i64(i64 %a, i64 %b, i64 %c) {
 ; RV32-LABEL: bit_64_1_z_select_i64:

 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bclri a1, a1, 31
 ; RV32ZBS-NEXT:    or a0, a0, a1
 ; RV32ZBS-NEXT:    beqz a0, .LBB115_2
 ; RV32ZBS-NEXT:  # %bb.1:
 ; RV32ZBS-NEXT:    ret
 ; RV32ZBS-NEXT:  .LBB115_2:
 ; RV32ZBS-NEXT:    tail bar@plt
+;
+; RV32XTHEADBS-LABEL: bit_63_1_z_branch_i64:
+; RV32XTHEADBS:       # %bb.0:
+; RV32XTHEADBS-NEXT:    slli a1, a1, 1
+; RV32XTHEADBS-NEXT:    srli a1, a1, 1
+; RV32XTHEADBS-NEXT:    or a0, a0, a1
+; RV32XTHEADBS-NEXT:    beqz a0, .LBB115_2
+; RV32XTHEADBS-NEXT:  # %bb.1:
+; RV32XTHEADBS-NEXT:    ret
+; RV32XTHEADBS-NEXT:  .LBB115_2:
+; RV32XTHEADBS-NEXT:    tail bar@plt
   %2 = and i64 %0, 9223372036854775807
   %3 = icmp eq i64 %2, 0
   br i1 %3, label %4, label %5
 
 4:
   tail call void @bar()
   br label %5
 

 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bclri a1, a1, 31
 ; RV32ZBS-NEXT:    or a0, a0, a1
 ; RV32ZBS-NEXT:    beqz a0, .LBB116_2
 ; RV32ZBS-NEXT:  # %bb.1:
 ; RV32ZBS-NEXT:    tail bar@plt
 ; RV32ZBS-NEXT:  .LBB116_2:
 ; RV32ZBS-NEXT:    ret
+;
+; RV32XTHEADBS-LABEL: bit_63_1_nz_branch_i64:
+; RV32XTHEADBS:       # %bb.0:
+; RV32XTHEADBS-NEXT:    slli a1, a1, 1
+; RV32XTHEADBS-NEXT:    srli a1, a1, 1
+; RV32XTHEADBS-NEXT:    or a0, a0, a1
+; RV32XTHEADBS-NEXT:    beqz a0, .LBB116_2
+; RV32XTHEADBS-NEXT:  # %bb.1:
+; RV32XTHEADBS-NEXT:    tail bar@plt
+; RV32XTHEADBS-NEXT:  .LBB116_2:
+; RV32XTHEADBS-NEXT:    ret
   %2 = and i64 %0, 9223372036854775807
   %3 = icmp ne i64 %2, 0
   br i1 %3, label %4, label %5
 
 4:
   tail call void @bar()
   br label %5
 

llvm/test/CodeGen/RISCV/rv32xtheadbs.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefixes=RV32I
+; RUN: llc -mtriple=riscv32 -mattr=+xtheadbs -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefixes=RV32XTHEADBS
+
+define i32 @th_tst_i32(i32 %a) nounwind {
+; RV32I-LABEL: th_tst_i32:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a0, a0, 26
+; RV32I-NEXT:    srli a0, a0, 31
+; RV32I-NEXT:    ret
+;
+; RV32XTHEADBS-LABEL: th_tst_i32:
+; RV32XTHEADBS:       # %bb.0:
+; RV32XTHEADBS-NEXT:    th.tst a0, a0, 5
+; RV32XTHEADBS-NEXT:    ret
+  %shr = lshr i32 %a, 5
+  %and = and i32 %shr, 1
+  ret i32 %and
+}
+
+define i64 @th_tst_i64(i64 %a) nounwind {
+; RV32I-LABEL: th_tst_i64:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a0, a0, 26
+; RV32I-NEXT:    srli a0, a0, 31
+; RV32I-NEXT:    li a1, 0
+; RV32I-NEXT:    ret
+;
+; RV32XTHEADBS-LABEL: th_tst_i64:
+; RV32XTHEADBS:       # %bb.0:
+; RV32XTHEADBS-NEXT:    th.tst a0, a0, 5
+; RV32XTHEADBS-NEXT:    li a1, 0
+; RV32XTHEADBS-NEXT:    ret
+  %shr = lshr i64 %a, 5
+  %and = and i64 %shr, 1
+  ret i64 %and
+}
+
+define signext i32 @th_tst_i32_cmp(i32 signext %a) nounwind {
+; RV32I-LABEL: th_tst_i32_cmp:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a0, a0, 26
+; RV32I-NEXT:    srli a0, a0, 31
+; RV32I-NEXT:    ret
+;
+; RV32XTHEADBS-LABEL: th_tst_i32_cmp:
+; RV32XTHEADBS:       # %bb.0:
+; RV32XTHEADBS-NEXT:    th.tst a0, a0, 5
+; RV32XTHEADBS-NEXT:    ret
+  %and = and i32 %a, 32
+  %cmp = icmp ne i32 %and, 0
+  %zext = zext i1 %cmp to i32
+  ret i32 %zext
+}
+
+define i64 @th_tst_i64_cmp(i64 %a) nounwind {
+; RV32I-LABEL: th_tst_i64_cmp:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a0, a0, 26
+; RV32I-NEXT:    srli a0, a0, 31
+; RV32I-NEXT:    li a1, 0
+; RV32I-NEXT:    ret
+;
+; RV32XTHEADBS-LABEL: th_tst_i64_cmp:
+; RV32XTHEADBS:       # %bb.0:
+; RV32XTHEADBS-NEXT:    th.tst a0, a0, 5
+; RV32XTHEADBS-NEXT:    li a1, 0
+; RV32XTHEADBS-NEXT:    ret
+  %and = and i64 %a, 32
+  %cmp = icmp ne i64 %and, 0
+  %zext = zext i1 %cmp to i64
+  ret i64 %zext
+}
+

llvm/test/CodeGen/RISCV/rv64xtheadbs.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefixes=RV64I
+; RUN: llc -mtriple=riscv64 -mattr=+xtheadbs -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefixes=RV64XTHEADBS
+
+define signext i32 @th_tst_i32(i32 signext %a) nounwind {
+; RV64I-LABEL: th_tst_i32:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 58
+; RV64I-NEXT:    srli a0, a0, 63
+; RV64I-NEXT:    ret
+;
+; RV64XTHEADBS-LABEL: th_tst_i32:
+; RV64XTHEADBS:       # %bb.0:
+; RV64XTHEADBS-NEXT:    th.tst a0, a0, 5
+; RV64XTHEADBS-NEXT:    ret
+  %shr = lshr i32 %a, 5
+  %and = and i32 %shr, 1
+  ret i32 %and
+}
+
+define i64 @the_tst_i64(i64 %a) nounwind {
+; RV64I-LABEL: the_tst_i64:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 58
+; RV64I-NEXT:    srli a0, a0, 63
+; RV64I-NEXT:    ret
+;
+; RV64XTHEADBS-LABEL: the_tst_i64:
+; RV64XTHEADBS:       # %bb.0:
+; RV64XTHEADBS-NEXT:    th.tst a0, a0, 5
+; RV64XTHEADBS-NEXT:    ret
+  %shr = lshr i64 %a, 5
+  %and = and i64 %shr, 1
+  ret i64 %and
+}
+
+define signext i32 @th_tst_i32_cmp(i32 signext %a) nounwind {
+; RV64I-LABEL: th_tst_i32_cmp:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 58
+; RV64I-NEXT:    srli a0, a0, 63
+; RV64I-NEXT:    ret
+;
+; RV64XTHEADBS-LABEL: th_tst_i32_cmp:
+; RV64XTHEADBS:       # %bb.0:
+; RV64XTHEADBS-NEXT:    th.tst a0, a0, 5
+; RV64XTHEADBS-NEXT:    ret
+  %and = and i32 %a, 32
+  %cmp = icmp ne i32 %and, 0
+  %zext = zext i1 %cmp to i32
+  ret i32 %zext
+}
+
+define i64 @th_tst_i64_cmp(i64 %a) nounwind {
+; RV64I-LABEL: th_tst_i64_cmp:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 58
+; RV64I-NEXT:    srli a0, a0, 63
+; RV64I-NEXT:    ret
+;
+; RV64XTHEADBS-LABEL: th_tst_i64_cmp:
+; RV64XTHEADBS:       # %bb.0:
+; RV64XTHEADBS-NEXT:    th.tst a0, a0, 5
+; RV64XTHEADBS-NEXT:    ret
+  %and = and i64 %a, 32
+  %cmp = icmp ne i64 %and, 0
+  %zext = zext i1 %cmp to i64
+  ret i64 %zext
+}
+

llvm/test/MC/RISCV/rv32xtheadbs-invalid.s

+# RUN: not llvm-mc -triple riscv32 -mattr=+xtheadbs < %s 2>&1 | FileCheck %s
+
+# Too few operands
+th.tst t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Immediate operand out of range
+th.tst t0, t1, 32 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
+th.tst t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]

llvm/test/MC/RISCV/rv32xtheadbs-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+xtheadbs -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xtheadbs -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xtheadbs < %s \
+# RUN:     | llvm-objdump --mattr=+xtheadbs -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xtheadbs < %s \
+# RUN:     | llvm-objdump --mattr=+xtheadbs -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: th.tst t0, t1, 1
+# CHECK-ASM: encoding: [0x8b,0x12,0x13,0x88]
+th.tst t0, t1, 1
+# CHECK-ASM-AND-OBJ: th.tst t0, t1, 31
+# CHECK-ASM: encoding: [0x8b,0x12,0xf3,0x89]
+th.tst t0, t1, 31

llvm/test/MC/RISCV/rv64xtheadbs-invalid.s

+# RUN: not llvm-mc -triple riscv64 -mattr=+xtheadbs < %s 2>&1 | FileCheck %s
+
+# Immediate operand out of range
+th.tst t0, t1, 64 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 63]
+th.tst t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 63]