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[RISCV] Add vendor-defined XTheadFMemIdx (FP Indexed Memory Operations) extension

Authored by mtsamis on Feb 23 2023, 7:49 AM.



The vendor-defined XTHeadFMemIdx (no comparable standard extension exists
at the time of writing) extension adds indexed load/store instructions
for floating-point registers.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:

Support for these instructions has already landed in GNU Binutils:;a=commit;h=f511f80fa3fcaf6bcbe727fb902b8bd5ec8f9c20

Depends on D144249

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Event Timeline

mtsamis created this revision.Feb 23 2023, 7:49 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 23 2023, 7:49 AM
mtsamis requested review of this revision.Feb 23 2023, 7:49 AM
This revision is now accepted and ready to land.Feb 23 2023, 2:03 PM
This revision was landed with ongoing or failed builds.Feb 23 2023, 3:35 PM
This revision was automatically updated to reflect the committed changes.