[RISCV] Proper support of extensions Zicsr and Zifencei

[eklepilkina]

Summary

Specification describes extensions Zicsr and Zifencei, but LLVM now include all instructions from these extensions by default. GCC supports both of these extensions as described in specification.

[eklepilkina]

We are interested in proper support for Zicsr and Zifencei. Could someone look at patch or explain why these extensions were included by default?

[jrtc27]

Because they used to be part of I and then a later version of the RISC-V spec split them out in an incompatible way. GCC/binutils bit the bullet and split them out last(?) year but LLVM has yet to make that breaking change.

[asb]

In D141666#4050692, @eklepilkina wrote:

We are interested in proper support for Zicsr and Zifencei. Could someone look at patch or explain why these extensions were included by default?

As Jessica says, the reason they're not split out is that when the backend was first implemented, they were part of the I specification. I'm not at all a fan of how this happened, but we are where we are, and as noted GCC has made this change. The key aspect this patch misses right now is the versioning issue - I is still marked as 2.0. So really, this needs someone to propose a what the change will look like in full. A few misc thoughts (and all of these would need some more discussion with others active in the RISC-V backend). e.g. do we need/want -misa-version, or is there a proposal to just move to I 2.1 by default?

It might also be interesting to explore options that temporarly sidestep the versioning discussion and improve compatibility with GCC -march strings. e.g. an initial patch that adds zicsr and zifencei but enables it by default (or otherwise handles zicsr and zifencei as a no-op). I _think_ I'd be happy with something along those lines, but I can't speak for others involved in the RISC-V backend.

[eklepilkina]

Thank you for comments!

The key aspect this patch misses right now is the versioning issue - I is still marked as 2.0.

I can update I extension version or separate diffrent isa versions as you mentioned. I can fix comments and make proposed by community changes. We are interested in supporting compatibility with GCC.

It might also be interesting to explore options that temporarly sidestep the versioning discussion and improve compatibility with GCC -march strings. e.g. an initial patch that adds zicsr and zifencei but enables it by default (or otherwise handles zicsr and zifencei as a no-op)

We internally made something similar, just added extensions in the list and ignore warnings in some places. But still these extensions are already ratified so proper support is needed to be done some time

[eklepilkina]

• Updated I extension verson

[kito-cheng]

Maybe multi-lib handling should split into another patch?

[eklepilkina]

Maybe multi-lib handling should split into another patch?

I can do this. But if I separate I still can't choose one that should be merged firstly, they will be needed to merge both at once, because tests will fail. If separate them right way (fixes for multilibs in baremetal.cpp and gnu.cpp). Shall I separate?

[eklepilkina]

Gently ping

[reames]

JFYI, I have a change out which just documents current status while we wait for a resolution. https://reviews.llvm.org/D143924

[eklepilkina]

@reames Thank you for fixing documentation, missed this

[eklepilkina]

• [RISCV] Prepare work to be ready for adding separate Zicsr and Zifencei extensions
• [RISCV] Proper support of extensions Zicsr and Zifencei
• Updated I extension verson
• Fixing after updating

[eklepilkina]

Gently ping

[eklepilkina]

Another implementation was merged to upsteam

clang/lib/Driver/ToolChains/Arch/RISCV.cpp

StringRef riscv::getRISCVArch(const llvm::opt::ArgList &Args,
   //
   // ilp32e -> rv32e
   // ilp32 | ilp32f | ilp32d -> rv32imafdc
   // lp64 | lp64f | lp64d -> rv64imafdc
   if (const Arg *A = Args.getLastArg(options::OPT_mabi_EQ)) {
     StringRef MABI = A->getValue();
 
     if (MABI.equals_insensitive("ilp32e"))
-      return "rv32e";
+      return "rv32e_zicsr_zifencei";
     else if (MABI.startswith_insensitive("ilp32"))
-      return "rv32imafdc";
+      return "rv32imafdc_zicsr_zifencei";
     else if (MABI.startswith_insensitive("lp64"))
-      return "rv64imafdc";
+      return "rv64imafdc_zicsr_zifencei";
   }
 
   // 4. Choose a default based on the triple
   //
   // We deviate from GCC's defaults here:
   // - On `riscv{XLEN}-unknown-elf` we default to `rv{XLEN}imac`
   // - On all other OSs we use `rv{XLEN}imafdc` (equivalent to `rv{XLEN}gc`)
   if (Triple.isRISCV32()) {
     if (Triple.getOS() == llvm::Triple::UnknownOS)
-      return "rv32imac";
+      return "rv32imac_zicsr_zifencei";
     else
-      return "rv32imafdc";
+      return "rv32imafdc_zicsr_zifencei";
   } else {
     if (Triple.getOS() == llvm::Triple::UnknownOS)
-      return "rv64imac";
+      return "rv64imac_zicsr_zifencei";
     else
-      return "rv64imafdc";
+      return "rv64imafdc_zicsr_zifencei";
   }
 }
 
 std::string riscv::getRISCVTargetCPU(const llvm::opt::ArgList &Args,
                                      const llvm::Triple &Triple) {
   std::string CPU;
   // If we have -mcpu, use that.
   if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ))

clang/lib/Driver/ToolChains/BareMetal.cpp

static bool findRISCVMultilibs(const Driver &D,
                                const llvm::Triple &TargetTriple,
                                const ArgList &Args, DetectedMultilibs &Result) {
   Multilib::flags_list Flags;
   StringRef Arch = riscv::getRISCVArch(Args, TargetTriple);
   StringRef Abi = tools::riscv::getRISCVABI(Args, TargetTriple);
 
   if (TargetTriple.isRISCV64()) {
     Multilib Imac = makeMultilib("").flag("+march=rv64imac").flag("+mabi=lp64");
-    Multilib Imafdc = makeMultilib("/rv64imafdc/lp64d")
-                          .flag("+march=rv64imafdc")
+    Multilib Imafdc = makeMultilib("/rv64imafdc_zicsr_zifencei/lp64d")
+                          .flag("+march=rv64imafdc_zicsr_zifencei")
                           .flag("+mabi=lp64d");
 
     // Multilib reuse
-    bool UseImafdc =
-        (Arch == "rv64imafdc") || (Arch == "rv64gc"); // gc => imafdc
+    bool UseImafdc = (Arch == "rv64imafdc_zicsr_zifencei") ||
+                     (Arch == "rv64gc"); // gc => imafdc
 
     addMultilibFlag((Arch == "rv64imac"), "march=rv64imac", Flags);
-    addMultilibFlag(UseImafdc, "march=rv64imafdc", Flags);
+    addMultilibFlag(UseImafdc, "march=rv64imafdc_zicsr_zifencei", Flags);
     addMultilibFlag(Abi == "lp64", "mabi=lp64", Flags);
     addMultilibFlag(Abi == "lp64d", "mabi=lp64d", Flags);
 
     Result.Multilibs = MultilibSet().Either(Imac, Imafdc);
     return Result.Multilibs.select(Flags, Result.SelectedMultilib);
   }
   if (TargetTriple.isRISCV32()) {
     Multilib Imac =
         makeMultilib("").flag("+march=rv32imac").flag("+mabi=ilp32");
     Multilib I =
         makeMultilib("/rv32i/ilp32").flag("+march=rv32i").flag("+mabi=ilp32");
     Multilib Im =
         makeMultilib("/rv32im/ilp32").flag("+march=rv32im").flag("+mabi=ilp32");
     Multilib Iac = makeMultilib("/rv32iac/ilp32")
                        .flag("+march=rv32iac")
                        .flag("+mabi=ilp32");
-    Multilib Imafc = makeMultilib("/rv32imafc/ilp32f")
-                         .flag("+march=rv32imafc")
+    Multilib Imafc = makeMultilib("/rv32imafc_zicsr_zifencei/ilp32f")
+                         .flag("+march=rv32imafc_zicsr_zifencei")
                          .flag("+mabi=ilp32f");
 
     // Multilib reuse
     bool UseI = (Arch == "rv32i") || (Arch == "rv32ic");    // ic => i
     bool UseIm = (Arch == "rv32im") || (Arch == "rv32imc"); // imc => im
-    bool UseImafc = (Arch == "rv32imafc") || (Arch == "rv32imafdc") ||
+    bool UseImafc = (Arch == "rv32imafc_zicsr_zifencei") ||
+                    (Arch == "rv32imafdc_zicsr_zifencei") ||
                     (Arch == "rv32gc"); // imafdc,gc => imafc
 
     addMultilibFlag(UseI, "march=rv32i", Flags);
     addMultilibFlag(UseIm, "march=rv32im", Flags);
     addMultilibFlag((Arch == "rv32iac"), "march=rv32iac", Flags);
     addMultilibFlag((Arch == "rv32imac"), "march=rv32imac", Flags);
-    addMultilibFlag(UseImafc, "march=rv32imafc", Flags);
+    addMultilibFlag(UseImafc, "march=rv32imafc_zicsr_zifencei", Flags);
     addMultilibFlag(Abi == "ilp32", "mabi=ilp32", Flags);
     addMultilibFlag(Abi == "ilp32f", "mabi=ilp32f", Flags);
 
     Result.Multilibs = MultilibSet().Either(I, Im, Iac, Imac, Imafc);
     return Result.Multilibs.select(Flags, Result.SelectedMultilib);
   }
   return false;
 }

clang/lib/Driver/ToolChains/Gnu.cpp

MultilibSet RISCVMultilibs =
                  "/../../../../riscv32-unknown-elf/lib" + M.gccSuffix()});
           });
 
 
   Multilib::flags_list Flags;
   llvm::StringSet<> Added_ABIs;
   StringRef ABIName = tools::riscv::getRISCVABI(Args, TargetTriple);
   StringRef MArch = tools::riscv::getRISCVArch(Args, TargetTriple);
+  auto marchIsSubset = [](StringRef MArch, StringRef MultilibMarch) {
+    return (MArch == MultilibMarch) ||
+           MArch == (MultilibMarch + "_zicsr").str() ||
+           MArch == (MultilibMarch + "_zicsr_zifencei").str();
+  };
+
   for (auto Element : RISCVMultilibSet) {
-    addMultilibFlag(MArch == Element.march,
+    addMultilibFlag(marchIsSubset(MArch, Element.march),
                     Twine("march=", Element.march).str().c_str(), Flags);
     if (!Added_ABIs.count(Element.mabi)) {
       Added_ABIs.insert(Element.mabi);
       addMultilibFlag(ABIName == Element.mabi,
                       Twine("mabi=", Element.mabi).str().c_str(), Flags);
     }
   }
 

clang/test/Driver/baremetal.cpp

 // RUN:     -nodefaultlibs \
 // RUN:   | FileCheck --check-prefix=CHECK-RV64-NDL %s
 // CHECK-RV64-NDL: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]"
 // CHECK-RV64-NDL: ld{{(.exe)?}}" "{{.*}}.o" "-Bstatic"
 // CHECK-RV64-NDL-SAME: "-L{{[^"]*}}{{[/\\]+}}Inputs{{[/\\]+}}basic_riscv64_tree{{[/\\]+}}riscv64-unknown-elf{{[/\\]+}}lib"
 // CHECK-RV64-NDL-SAME: "-L[[RESOURCE_DIR]]{{[/\\]+}}lib{{[/\\]+}}baremetal"
 
 // RUN: %clang %s -### 2>&1 --target=riscv64-unknown-elf \
-// RUN:     -march=rv64imafdc -mabi=lp64d \
+// RUN:     -march=rv64imafdc_zicsr_zifencei -mabi=lp64d \
 // RUN:     --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf \
 // RUN:   | FileCheck --check-prefix=CHECK-RV64FD %s
 
 // RUN: %clang %s -### 2>&1 --target=riscv64-unknown-elf \
 // RUN:     -march=rv64gc -mabi=lp64d \
 // RUN:     --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf \
 // RUN:   | FileCheck --check-prefix=CHECK-RV64FD %s
 
 // CHECK-RV64FD:      "-cc1" "-triple" "riscv64-unknown-unknown-elf"
 // CHECK-RV64FD-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]"
 // CHECK-RV64FD-SAME: "-isysroot" "[[SYSROOT:[^"]*]]"
-// CHECK-RV64FD-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}rv64imafdc{{[/\\]+}}lp64d{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1"
-// CHECk-RV64FD-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}rv64imafdc{{[/\\]+}}lp64d{{[/\\]+}}include"
+// CHECK-RV64FD-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}rv64imafdc_zicsr_zifencei{{[/\\]+}}lp64d{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1"
+// CHECk-RV64FD-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}rv64imafdc_zicsr_zifencei{{[/\\]+}}lp64d{{[/\\]+}}include"
 // CHECK-RV64FD-SAME: "-x" "c++" "{{.*}}baremetal.cpp"
 // CHECK-RV64FD-NEXT: ld{{(.exe)?}}" "{{.*}}.o" "-Bstatic"
-// CHECK-RV64FD-SAME: "-L[[SYSROOT:[^"]+]]{{[/\\]+}}rv64imafdc{{[/\\]+}}lp64d{{[/\\]+}}lib"
-// CHECK-RV64FD-SAME: "-L[[RESOURCE_DIR:[^"]+]]{{[/\\]+}}lib{{[/\\]+}}baremetal{{[/\\]+}}rv64imafdc{{[/\\]+}}lp64d"
+// CHECK-RV64FD-SAME: "-L[[SYSROOT:[^"]+]]{{[/\\]+}}rv64imafdc_zicsr_zifencei{{[/\\]+}}lp64d{{[/\\]+}}lib"
+// CHECK-RV64FD-SAME: "-L[[RESOURCE_DIR:[^"]+]]{{[/\\]+}}lib{{[/\\]+}}baremetal{{[/\\]+}}rv64imafdc_zicsr_zifencei{{[/\\]+}}lp64d"
 
 // RUN: %clang %s -### 2>&1 --target=riscv32-unknown-elf \
 // RUN:     -march=rv32i -mabi=ilp32 \
 // RUN:     --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf \
 // RUN:   | FileCheck --check-prefix=CHECK-RV32I %s
 
 // RUN: %clang %s -### 2>&1 --target=riscv32-unknown-elf \
 // RUN:     -march=rv32ic -mabi=ilp32 \

 // CHECK-RV32IAC-SAME: "-isysroot" "[[SYSROOT:[^"]*]]"
 // CHECK-RV32IAC-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}rv32iac{{[/\\]+}}ilp32{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1"
 // CHECK-RV32IAC-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}rv32iac{{[/\\]+}}ilp32{{[/\\]+}}include"
 // CHECK-RV32IAC-SAME: "-x" "c++" "{{.*}}baremetal.cpp"
 // CHECK-RV32IAC-NEXT: ld{{(.exe)?}}" "{{.*}}.o" "-Bstatic"
 // CHECK-RV32IAC-SAME: "-L[[SYSROOT:[^"]+]]{{[/\\]+}}rv32iac{{[/\\]+}}ilp32{{[/\\]+}}lib"
 // CHECK-RV32IAC-SAME: "-L[[RESOURCE_DIR:[^"]+]]{{[/\\]+}}lib{{[/\\]+}}baremetal{{[/\\]+}}rv32iac{{[/\\]+}}ilp32"
 
-// RUN: %clang %s -### 2>&1 --target=riscv32-unknown-elf -march=rv32imafc -mabi=ilp32f \
+// RUN: %clang %s -### 2>&1 --target=riscv32-unknown-elf -march=rv32imafc_zicsr_zifencei -mabi=ilp32f \
 // RUN:     --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf \
 // RUN:   | FileCheck --check-prefix=CHECK-RV32IMAFC %s
 
-// RUN: %clang %s -### 2>&1 --target=riscv32-unknown-elf -march=rv32imafdc -mabi=ilp32f \
+// RUN: %clang %s -### 2>&1 --target=riscv32-unknown-elf -march=rv32imafdc_zicsr_zifencei -mabi=ilp32f \
 // RUN:     --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf \
 // RUN:   | FileCheck --check-prefix=CHECK-RV32IMAFC %s
 
 // RUN: %clang %s -### 2>&1 --target=riscv32-unknown-elf -march=rv32gc -mabi=ilp32f \
 // RUN:     --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf \
 // RUN:   | FileCheck --check-prefix=CHECK-RV32IMAFC %s
 
 // CHECK-RV32IMAFC:      "-cc1" "-triple" "riscv32-unknown-unknown-elf"
 // CHECK-RV32IMAFC-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]"
 // CHECK-RV32IMAFC-SAME: "-isysroot" "[[SYSROOT:[^"]*]]"
-// CHECK-RV32IMAFC-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}rv32imafc{{[/\\]+}}ilp32f{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1"
-// CHECK-RV32IMAFC-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}rv32imafc{{[/\\]+}}ilp32f{{[/\\]+}}include"
+// CHECK-RV32IMAFC-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}rv32imafc_zicsr_zifencei{{[/\\]+}}ilp32f{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1"
+// CHECK-RV32IMAFC-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}rv32imafc_zicsr_zifencei{{[/\\]+}}ilp32f{{[/\\]+}}include"
 // CHECK-RV32IMAFC-SAME: "-x" "c++" "{{.*}}baremetal.cpp"
 // CHECK-RV32IMAFC-NEXT: ld{{(.exe)?}}" "{{.*}}.o" "-Bstatic"
-// CHECK-RV32IMAFC-SAME: "-L[[SYSROOT:[^"]+]]{{[/\\]+}}rv32imafc{{[/\\]+}}ilp32f{{[/\\]+}}lib"
-// CHECK-RV32IMAFC-SAME: "-L[[RESOURCE_DIR:[^"]+]]{{[/\\]+}}lib{{[/\\]+}}baremetal{{[/\\]+}}rv32imafc{{[/\\]+}}ilp32f"
+// CHECK-RV32IMAFC-SAME: "-L[[SYSROOT:[^"]+]]{{[/\\]+}}rv32imafc_zicsr_zifencei{{[/\\]+}}ilp32f{{[/\\]+}}lib"
+// CHECK-RV32IMAFC-SAME: "-L[[RESOURCE_DIR:[^"]+]]{{[/\\]+}}lib{{[/\\]+}}baremetal{{[/\\]+}}rv32imafc_zicsr_zifencei{{[/\\]+}}ilp32f"
 
 // Check that compiler-rt library without the arch filename suffix will
 // be used if present.
 // RUN: rm -rf %T/baremetal_clang_rt_noarch
 // RUN: mkdir -p %T/baremetal_clang_rt_noarch/lib
 // RUN: touch %T/baremetal_clang_rt_noarch/lib/libclang_rt.builtins.a
 // RUN: %clang %s -### 2>&1 \
 // RUN:     --target=armv6m-none-eabi \

clang/test/Driver/riscv-default-features.c

 // RUN: %clang --target=riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32
 // RUN: %clang --target=riscv64-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64
 
-// RV32: "target-features"="+32bit,+a,+c,+m,+relax,
+// RV32: "target-features"="+32bit,+a,+c,+m,+relax,+zicsr,+zifencei
 // RV32-SAME: -save-restore
-// RV64: "target-features"="+64bit,+a,+c,+m,+relax,
+// RV64: "target-features"="+64bit,+a,+c,+m,+relax,+zicsr,+zifencei
 // RV64-SAME: -save-restore
 
 // Dummy function
 int foo(void){
   return  3;
 }

clang/test/Driver/riscv-gnutools.c

 // Check default when -march=rv32g specified
 // RUN: %clang --target=riscv32-unknown-elf --gcc-toolchain=%S/Inputs/basic_riscv32_tree -fno-integrated-as %s -### -c -march=rv32g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32G-ILP32D %s
 
 // Check -mno-relax is passed when -fno-integrated-as specified
 // RUN: %clang -target riscv32-unknown-elf --gcc-toolchain=%S/Inputs/basic_riscv32_tree -mno-relax -fno-integrated-as %s -### -c \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32-NO-RELAX %s
 
-// CHECK-RV32IMAC-ILP32: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" "rv32imac"
-// CHECK-RV32IMAFDC-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32imafdc"
+// CHECK-RV32IMAC-ILP32: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" "rv32imac_zicsr_zifencei"
+// CHECK-RV32IMAFDC-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32imafdc_zicsr_zifencei"
 // CHECK-RV32G-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32g"
 // CHECK-RV32-NO-RELAX: "{{.*}}as{{(.exe)?}}" "{{.*}}" "-mno-relax"
 
 
 // 64-bit checks
 
 // Check default on riscv64-unknown-elf
 // RUN: %clang --target=riscv64-unknown-elf --gcc-toolchain=%S/Inputs/basic_riscv64_tree -fno-integrated-as %s -### -c \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64IMAC-LP64 %s
 
 // Check default on riscv64-unknown-linux-gnu
 // RUN: %clang --target=riscv64-unknown-linux-gnu --gcc-toolchain=%S/Inputs/basic_riscv64_tree -fno-integrated-as %s -### -c \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64IMAFDC-LP64D %s
 
 // Check default when -march=rv64g specified
 // RUN: %clang --target=riscv64-unknown-elf --gcc-toolchain=%S/Inputs/basic_riscv64_tree -fno-integrated-as %s -### -c -march=rv64g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64G-LP64D %s
 
 // Check -mno-relax is not passed when -fno-integrated-as specified
 // RUN: %clang -target riscv64-unknown-elf --gcc-toolchain=%S/Inputs/basic_riscv64_tree -mno-relax -mrelax -fno-integrated-as %s -### -c \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64-RELAX %s
 
-// CHECK-RV64IMAC-LP64: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" "rv64imac"
-// CHECK-RV64IMAFDC-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64imafdc"
+// CHECK-RV64IMAC-LP64: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" "rv64imac_zicsr_zifencei"
+// CHECK-RV64IMAFDC-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64imafdc_zicsr_zifencei"
 // CHECK-RV64G-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64g"
 // CHECK-RV64-RELAX: "{{.*}}as{{(.exe)?}}"
 // CHECK-RV64-RELAX-NOT: "-mno-relax"

llvm/docs/RISCVUsage.rst

 .. _riscv-vlen-32-note:
 
 ``Zve32x``, ``Zve32f``, ``Zvl32b``
   LLVM currently assumes a minimum VLEN (vector register width) of 64 bits during compilation, and as a result ``Zve32x`` and ``Zve32f`` are supported only for VLEN>=64.  Assembly support doesn't have this restriction.
 
 .. _riscv-i2p1-note:
 
 ``zicsr``, ``zifencei``
-  Between versions 2.0 and 2.1 of the base I specification, a backwards incompatible change was made to remove selected instructions and CSRs from the base ISA.  These instructions were grouped into a set of new extensions, but were no longer required by the base ISA.  This change is described in "Preface to Document Version 20190608-Base-Ratified" from the specification document.  LLVM currently implements version 2.0 of the base specification.  Thus, instructions from these extensions are accepted as part of the base ISA, but attempts to explicitly enable the extensions will error.
+  Between versions 2.0 and 2.1 of the base I specification, a backwards incompatible change was made to remove selected instructions and CSRs from the base ISA.  These instructions were grouped into a set of new extensions, but were no longer required by the base ISA.  This change is described in "Preface to Document Version 20190608-Base-Ratified" from the specification document.  LLVM currently implements version 2.1 of the base specification. Thus, to use instructions from these extensions they should be explicitly enabled.
 
 Experimental Extensions
 =======================
 
 LLVM supports (to various degrees) a number of experimental extensions.  All experimental extensions have ``experimental-`` as a prefix.  There is explicitly no compatibility promised between versions of the toolchain, and regular users are strongly advised *not* to make use of experimental extensions before they reach ratification.
 
 The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases.  Experimental extensions are expected to either transition to ratified status, or be eventually removed.  The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised.
 

llvm/lib/Support/RISCVISAInfo.cpp

struct RISCVSupportedExtension {
   RISCVExtensionVersion Version;
 };
 
 } // end anonymous namespace
 
 static constexpr StringLiteral AllStdExts = "mafdqlcbkjtpvnh";
 
 static const RISCVSupportedExtension SupportedExtensions[] = {
-    {"i", RISCVExtensionVersion{2, 0}},
+    {"i", RISCVExtensionVersion{2, 1}},
     {"e", RISCVExtensionVersion{1, 9}},
     {"m", RISCVExtensionVersion{2, 0}},
     {"a", RISCVExtensionVersion{2, 0}},
     {"f", RISCVExtensionVersion{2, 0}},
     {"d", RISCVExtensionVersion{2, 0}},
     {"c", RISCVExtensionVersion{2, 0}},
 
     {"h", RISCVExtensionVersion{1, 0}},
static const RISCVSupportedExtension SupportedExtensions[] = {
     {"zba", RISCVExtensionVersion{1, 0}},
     {"zbb", RISCVExtensionVersion{1, 0}},
     {"zbc", RISCVExtensionVersion{1, 0}},
     {"zbs", RISCVExtensionVersion{1, 0}},
 
     {"zbkb", RISCVExtensionVersion{1, 0}},
     {"zbkc", RISCVExtensionVersion{1, 0}},
     {"zbkx", RISCVExtensionVersion{1, 0}},
+    {"zicsr", RISCVExtensionVersion{2, 0}},
+    {"zifencei", RISCVExtensionVersion{2, 0}},
     {"zknd", RISCVExtensionVersion{1, 0}},
     {"zkne", RISCVExtensionVersion{1, 0}},
     {"zknh", RISCVExtensionVersion{1, 0}},
     {"zksed", RISCVExtensionVersion{1, 0}},
     {"zksh", RISCVExtensionVersion{1, 0}},
     {"zkr", RISCVExtensionVersion{1, 0}},
     {"zkn", RISCVExtensionVersion{1, 0}},
     {"zks", RISCVExtensionVersion{1, 0}},

llvm/lib/Target/RISCV/RISCVFeatures.td

 
 def FeatureStdExtA
     : SubtargetFeature<"a", "HasStdExtA", "true",
                        "'A' (Atomic Instructions)">;
 def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
                            AssemblerPredicate<(all_of FeatureStdExtA),
                            "'A' (Atomic Instructions)">;
 
+def FeatureStdExtZicsr
+    : SubtargetFeature<"zicsr", "HasStdExtZicsr", "true",
+                       "'Zicsr' (Control and Status Register (CSR) Instructions)">;
+def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
+                               AssemblerPredicate<(all_of FeatureStdExtZicsr),
+                               "'Zicsr' (Control and Status Register (CSR) Instructions)">;
+
+def FeatureStdExtZifencei
+    : SubtargetFeature<"zifencei", "HasStdExtZifencei", "true",
+                       "'Zifencei' (Instruction-Fetch Fence)">;
+
+def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
+                               AssemblerPredicate<(all_of FeatureStdExtZifencei),
+                               "'Zifencei' (Instruction-Fetch Fence)">;
+
 def FeatureStdExtF
     : SubtargetFeature<"f", "HasStdExtF", "true",
-                       "'F' (Single-Precision Floating-Point)">;
+                       "'F' (Single-Precision Floating-Point)",
+                       [FeatureStdExtZicsr]>;
 def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
                            AssemblerPredicate<(all_of FeatureStdExtF),
                            "'F' (Single-Precision Floating-Point)">;
 
 def FeatureStdExtD
     : SubtargetFeature<"d", "HasStdExtD", "true",
                        "'D' (Double-Precision Floating-Point)",
                        [FeatureStdExtF]>;

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

SDValue RISCVTargetLowering::lowerGET_ROUNDING(SDValue Op,
   SDValue Masked = DAG.getNode(ISD::AND, DL, XLenVT, Shifted,
                                DAG.getConstant(7, DL, XLenVT));
 
   return DAG.getMergeValues({Masked, Chain}, DL);
 }
 
 SDValue RISCVTargetLowering::lowerSET_ROUNDING(SDValue Op,
                                                SelectionDAG &DAG) const {
+  assert(Subtarget.hasStdExtZicsr() &&
+         "SET_ROUNDING can be used only with Zicsr");
   const MVT XLenVT = Subtarget.getXLenVT();
   SDLoc DL(Op);
   SDValue Chain = Op->getOperand(0);
   SDValue RMValue = Op->getOperand(1);
   SDValue SysRegNo = DAG.getTargetConstant(
       RISCVSysReg::lookupSysRegByName("FRM")->Encoding, DL, XLenVT);
 
   // Encoding used for rounding mode in RISCV differs from that used in

 RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
                                                  MachineBasicBlock *BB) const {
   switch (MI.getOpcode()) {
   default:
     llvm_unreachable("Unexpected instr type to insert");
   case RISCV::ReadCycleWide:
     assert(!Subtarget.is64Bit() &&
            "ReadCycleWrite is only to be used on riscv32");
+    assert(Subtarget.hasStdExtZicsr() &&
+           "ReadCycleWrite is only to be used with Zicsr");
     return emitReadCycleWidePseudo(MI, BB);
   case RISCV::Select_GPR_Using_CC_GPR:
   case RISCV::Select_FPR16_Using_CC_GPR:
   case RISCV::Select_FPR32_Using_CC_GPR:
   case RISCV::Select_FPR64_Using_CC_GPR:
     return emitSelectPseudo(MI, BB, Subtarget);
   case RISCV::BuildPairF64Pseudo:
     return emitBuildPairF64Pseudo(MI, BB);

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 }
 
 def FENCE_TSO : RVInstI<0b000, OPC_MISC_MEM, (outs), (ins), "fence.tso", "">, Sched<[]> {
   let rs1 = 0;
   let rd = 0;
   let imm12 = {0b1000,0b0011,0b0011};
 }
 
+let Predicates = [HasStdExtZifencei] in {
 def FENCE_I : RVInstI<0b001, OPC_MISC_MEM, (outs), (ins), "fence.i", "">, Sched<[]> {
   let rs1 = 0;
   let rd = 0;
   let imm12 = 0;
 }
+} // Predicates = [HasStdExtZifencei]
 
 def ECALL : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ecall", "">, Sched<[WriteJmp]> {
   let rs1 = 0;
   let rd = 0;
   let imm12 = 0;
 }
 
 def EBREAK : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ebreak", "">,
def WRS_STO : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "wrs.sto", "">,
   let rs1 = 0;
   let rd = 0;
   let imm12 = 0b000000011101;
 }
 } // Predicates = [HasStdExtZawrs]
 
 } // hasSideEffects = 1, mayLoad = 0, mayStore = 0
 
+let Predicates = [HasStdExtZicsr] in {
 def CSRRW : CSR_ir<0b001, "csrrw">;
 def CSRRS : CSR_ir<0b010, "csrrs">;
 def CSRRC : CSR_ir<0b011, "csrrc">;
 
 def CSRRWI : CSR_ii<0b101, "csrrwi">;
 def CSRRSI : CSR_ii<0b110, "csrrsi">;
 def CSRRCI : CSR_ii<0b111, "csrrci">;
+} // Predicates = [HasStdExtZicsr]
 
 /// RV64I instructions
 
 let Predicates = [IsRV64] in {
 def LWU   : Load_ri<0b110, "lwu">, Sched<[WriteLDW, ReadMemBase]>;
 def LD    : Load_ri<0b011, "ld">, Sched<[WriteLDD, ReadMemBase]>;
 def SD    : Store_rri<0b011, "sd">, Sched<[WriteSTD, ReadStoreData, ReadMemBase]>;
 

 def : InstAlias<"rdtime $rd",    (CSRRS GPR:$rd, TIME.Encoding, X0)>;
 
 let Predicates = [IsRV32] in {
 def : InstAlias<"rdinstreth $rd", (CSRRS GPR:$rd, INSTRETH.Encoding, X0)>;
 def : InstAlias<"rdcycleh $rd",   (CSRRS GPR:$rd, CYCLEH.Encoding, X0)>;
 def : InstAlias<"rdtimeh $rd",    (CSRRS GPR:$rd, TIMEH.Encoding, X0)>;
 } // Predicates = [IsRV32]
 
+let Predicates = [HasStdExtZicsr] in {
 def : InstAlias<"csrr $rd, $csr", (CSRRS GPR:$rd, csr_sysreg:$csr,      X0)>;
 def : InstAlias<"csrw $csr, $rs", (CSRRW      X0, csr_sysreg:$csr, GPR:$rs)>;
 def : InstAlias<"csrs $csr, $rs", (CSRRS      X0, csr_sysreg:$csr, GPR:$rs)>;
 def : InstAlias<"csrc $csr, $rs", (CSRRC      X0, csr_sysreg:$csr, GPR:$rs)>;
 
 def : InstAlias<"csrwi $csr, $imm", (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm)>;
 def : InstAlias<"csrsi $csr, $imm", (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm)>;
 def : InstAlias<"csrci $csr, $imm", (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm)>;
 
 let EmitPriority = 0 in {
 def : InstAlias<"csrw $csr, $imm", (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm)>;
 def : InstAlias<"csrs $csr, $imm", (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm)>;
 def : InstAlias<"csrc $csr, $imm", (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm)>;
 
 def : InstAlias<"csrrw $rd, $csr, $imm", (CSRRWI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
 def : InstAlias<"csrrs $rd, $csr, $imm", (CSRRSI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
 def : InstAlias<"csrrc $rd, $csr, $imm", (CSRRCI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
 }
+} // Predicates = [HasStdExtZicsr]
 
 def : InstAlias<"sfence.vma",     (SFENCE_VMA      X0, X0)>;
 def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>;
 
 def : InstAlias<"hfence.gvma",     (HFENCE_GVMA      X0, X0)>;
 def : InstAlias<"hfence.gvma $rs", (HFENCE_GVMA GPR:$rs, X0)>;
 
 def : InstAlias<"hfence.vvma",     (HFENCE_VVMA      X0, X0)>;

 // present. This is necessary as it isn't valid to mix __atomic_* libcalls
 // with inline atomic operations for the same object.
 
 /// Access to system registers
 
 // Helpers for defining specific operations. They are defined for each system
 // register separately. Side effect is not used because dependencies are
 // expressed via use-def properties.
-
+let Predicates = [HasStdExtZicsr] in {
 class ReadSysReg<SysReg SR, list<Register> Regs>
   : Pseudo<(outs GPR:$rd), (ins),
            [(set GPR:$rd, (riscv_read_csr (XLenVT SR.Encoding)))]>,
     PseudoInstExpansion<(CSRRS GPR:$rd, SR.Encoding, X0)> {
   let hasSideEffects = 0;
   let Uses = Regs;
 }
 

 
 class SwapSysRegImm<SysReg SR, list<Register> Regs>
   : Pseudo<(outs GPR:$rd), (ins uimm5:$val),
            [(set GPR:$rd, (riscv_swap_csr (XLenVT SR.Encoding), uimm5:$val))]>,
     PseudoInstExpansion<(CSRRWI GPR:$rd, SR.Encoding, uimm5:$val)> {
   let hasSideEffects = 0;
   let Uses = Regs;
   let Defs = Regs;
-}
+} // Predicates = [HasStdExtZicsr]
 
 def ReadFRM : ReadSysReg<SysRegFRM, [FRM]>;
 def WriteFRM : WriteSysReg<SysRegFRM, [FRM]>;
 def WriteFRMImm : WriteSysRegImm<SysRegFRM, [FRM]>;
 def SwapFRMImm : SwapSysRegImm<SysRegFRM, [FRM]>;
 
 let hasSideEffects = true in {
 def ReadFFLAGS : ReadSysReg<SysRegFFLAGS, [FFLAGS]>;
 def WriteFFLAGS : WriteSysReg<SysRegFFLAGS, [FFLAGS]>;
 }
+}
 /// Other pseudo-instructions
 
 // Pessimistically assume the stack pointer will be clobbered
 let Defs = [X2], Uses = [X2] in {
 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
                               [(callseq_start timm:$amt1, timm:$amt2)]>;
 def ADJCALLSTACKUP   : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
                               [(callseq_end timm:$amt1, timm:$amt2)]>;

llvm/test/CodeGen/RISCV/attributes.ll

 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCD %s
 
 ; CHECK: .attribute 4, 16
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
 ; RV32ZMMUL: .attribute 5, "rv32i2p0_zmmul1p0"
 ; RV32MZMMUL: .attribute 5, "rv32i2p0_m2p0_zmmul1p0"
 ; RV32A: .attribute 5, "rv32i2p0_a2p0"
-; RV32F: .attribute 5, "rv32i2p0_f2p0"
-; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
+; RV32F: .attribute 5, "rv32i2p1_f2p2_zicsr2p0"
+; RV32D: .attribute 5, "rv32i2p1_f2p2_d2p2_zicsr2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
 ; RV32ZIHINTPAUSE: .attribute 5, "rv32i2p0_zihintpause2p0"
 ; RV32ZIHINTNTL: .attribute 5, "rv32i2p0_zihintntl0p2"
-; RV32ZFHMIN: .attribute 5, "rv32i2p0_f2p0_zfhmin1p0"
-; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh1p0"
+; RV32ZFHMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfhmin1p0"
+; RV32ZFH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfh1p0"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0"
 ; RV32ZBB: .attribute 5, "rv32i2p0_zbb1p0"
 ; RV32ZBC: .attribute 5, "rv32i2p0_zbc1p0"
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0"
 ; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 ; RV32H: .attribute 5, "rv32i2p0_h1p0"
 ; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 ; RV32ZBKB: .attribute 5, "rv32i2p0_zbkb1p0"
 ; RV32ZBKC: .attribute 5, "rv32i2p0_zbkc1p0"
 ; RV32ZBKX: .attribute 5, "rv32i2p0_zbkx1p0"
-; RV32ZKND: .attribute 5, "rv32i2p0_zknd1p0"
-; RV32ZKNE: .attribute 5, "rv32i2p0_zkne1p0"
+; RV32V: .attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV32COMBINED: .attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 ; RV32ZKNH: .attribute 5, "rv32i2p0_zknh1p0"
 ; RV32ZKSED: .attribute 5, "rv32i2p0_zksed1p0"
 ; RV32ZKSH: .attribute 5, "rv32i2p0_zksh1p0"
 ; RV32ZKR: .attribute 5, "rv32i2p0_zkr1p0"
 ; RV32ZKN: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
 ; RV32ZKS: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
 ; RV32ZKT: .attribute 5, "rv32i2p0_zkt1p0"
 ; RV32ZK: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"

 ; RV32ZCB: .attribute 5, "rv32i2p0_zca1p0_zcb1p0"
 ; RV32ZCD: .attribute 5, "rv32i2p0_zcd1p0"
 ; RV32ZCF: .attribute 5, "rv32i2p0_zcf1p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
 ; RV64MZMMUL: .attribute 5, "rv64i2p0_m2p0_zmmul1p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
-; RV64F: .attribute 5, "rv64i2p0_f2p0"
-; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
+; RV64F: .attribute 5, "rv64i2p1_f2p2_zicsr2p0"
+; RV64D: .attribute 5, "rv64i2p1_f2p2_d2p2_zicsr2p0"
 ; RV64C: .attribute 5, "rv64i2p0_c2p0"
 ; RV64ZIHINTPAUSE: .attribute 5, "rv64i2p0_zihintpause2p0"
 ; RV64ZIHINTNTL: .attribute 5, "rv64i2p0_zihintntl0p2"
-; RV64ZFHMIN: .attribute 5, "rv64i2p0_f2p0_zfhmin1p0"
-; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh1p0"
+; RV64ZFHMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfhmin1p0"
+; RV64ZFH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfh1p0"
 ; RV64ZBA: .attribute 5, "rv64i2p0_zba1p0"
 ; RV64ZBB: .attribute 5, "rv64i2p0_zbb1p0"
 ; RV64ZBC: .attribute 5, "rv64i2p0_zbc1p0"
 ; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0"
 ; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 ; RV64H: .attribute 5, "rv64i2p0_h1p0"
 ; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 ; RV64ZBKB: .attribute 5, "rv64i2p0_zbkb1p0"
 ; RV64ZBKC: .attribute 5, "rv64i2p0_zbkc1p0"
 ; RV64ZBKX: .attribute 5, "rv64i2p0_zbkx1p0"
-; RV64ZKND: .attribute 5, "rv64i2p0_zknd1p0"
-; RV64ZKNE: .attribute 5, "rv64i2p0_zkne1p0"
+; RV64V: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV64COMBINED: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 ; RV64ZKNH: .attribute 5, "rv64i2p0_zknh1p0"
 ; RV64ZKSED: .attribute 5, "rv64i2p0_zksed1p0"
 ; RV64ZKSH: .attribute 5, "rv64i2p0_zksh1p0"
 ; RV64ZKR: .attribute 5, "rv64i2p0_zkr1p0"
 ; RV64ZKN: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
 ; RV64ZKS: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
 ; RV64ZKT: .attribute 5, "rv64i2p0_zkt1p0"
 ; RV64ZK: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"

llvm/test/CodeGen/RISCV/get-register-noreserve.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=riscv32 | FileCheck %s
+; RUN: llc < %s -mtriple=riscv32 -mattr=+zicsr | FileCheck %s
 
 define i32 @get_stack() nounwind {
 ; CHECK-LABEL: get_stack:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mv a0, sp
 ; CHECK-NEXT:    ret
 entry:
   %sp = call i32 @llvm.read_register.i32(metadata !0)

llvm/test/CodeGen/RISCV/readcyclecounter.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+zicsr -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
-; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+zicsr -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 ; Verify that we lower @llvm.readcyclecounter() correctly.
 
 declare i64 @llvm.readcyclecounter()
 
 define i64 @test_builtin_readcyclecounter() nounwind {
 ; RV32I-LABEL: test_builtin_readcyclecounter:

llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir

 # NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-# RUN: llc -mtriple riscv32 -mattr=+zve64x -start-before=prologepilog -o - \
+# RUN: llc -mtriple riscv32 -mattr=+zicsr,+zve64x -start-before=prologepilog -o - \
 # RUN:     -verify-machineinstrs %s | FileCheck %s --check-prefix=RV32
-# RUN: llc -mtriple riscv32 -mattr=+v -start-before=prologepilog -o - \
+# RUN: llc -mtriple riscv32 -mattr=+zicsr,+v -start-before=prologepilog -o - \
 # RUN:     -verify-machineinstrs %s | FileCheck %s --check-prefix=RV32
-# RUN: llc -mtriple riscv64 -mattr=+zve64x -start-before=prologepilog -o - \
+# RUN: llc -mtriple riscv64 -mattr=+zicsr,+zve64x -start-before=prologepilog -o - \
 # RUN:     -verify-machineinstrs %s | FileCheck %s --check-prefix=RV64
-# RUN: llc -mtriple riscv64 -mattr=+v -start-before=prologepilog -o - \
+# RUN: llc -mtriple riscv64 -mattr=+zicsr,+v -start-before=prologepilog -o - \
 # RUN:     -verify-machineinstrs %s | FileCheck %s --check-prefix=RV64
 --- |
   target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
   target triple = "riscv64"
 
   declare void @extern(<vscale x 4 x i32>*)
 
   define void @rvv_stack_align8() #0 {

llvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+zve64x -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+zve64x -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s --check-prefix=RV32
-; RUN: llc -mtriple=riscv64 -mattr=+zve64x -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+zve64x -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s --check-prefix=RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+v -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s --check-prefix=RV32
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+v -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s --check-prefix=RV64
 
 ; FIXME: We are over-aligning the stack on V, wasting stack space.
 
 define ptr @scalar_stack_align16() nounwind {
 ; RV32-LABEL: scalar_stack_align16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -48

llvm/test/CodeGen/RISCV/rvv/vscale-power-of-two.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+Zve64x,+m -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+v,+m -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+Zve64x,+m -verify-machineinstrs < %s | FileCheck %s
 declare i64 @llvm.vscale.i64()
 
 define i64 @vscale_lshr(i64 %TC) {
 ; CHECK-LABEL: vscale_lshr:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    csrr a1, vlenb
 ; CHECK-NEXT:    srli a1, a1, 6
 ; CHECK-NEXT:    addi a1, a1, -1

llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x \
+; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+zve32x \
 ; RUN:     -verify-machineinstrs < %s | FileCheck %s
 
 ; Make sure we don't select a 0 vl to X0 in the custom isel handlers we use
 ; for these intrinsics.
 
 declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, ptr, i64)
 declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, ptr, <vscale x 16 x i1>, i64, i64)
 

llvm/test/CodeGen/RISCV/vlenb.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O3 < %s -mtriple=riscv32 | FileCheck %s
+; RUN: llc -O3 < %s -mtriple=riscv32 -mattr=+zicsr | FileCheck %s
 
 ; These tests demonstrate optimizations involving copies from VLENB.
 
 define void @unused_copy_is_dead() {
 ; CHECK-LABEL: unused_copy_is_dead:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ret
 entry:

llvm/test/MC/RISCV/Ztso.s

-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-ztso -riscv-no-aliases 2>&1 | FileCheck %s
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-ztso -riscv-no-aliases 2>&1 | FileCheck %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-ztso,+zifencei -riscv-no-aliases 2>&1 | FileCheck %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-ztso,+zifencei -riscv-no-aliases 2>&1 | FileCheck %s
 
 # Note: Ztso doesn't add or remove any instructions, so this is basically
 # just checking that a) we accepted the attribute name, and b) codegen did
 # not change.  The ELF header flag is tested in elf-flags.s
 
 # CHECK-NOT: not a recognized feature
 
 # CHECK: fence iorw, iorw
 fence iorw, iorw
 # CHECK: fence.tso
 fence.tso
 # CHECK: fence.i
 fence.i

llvm/test/MC/RISCV/csr-aliases.s

-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d --mattr=+f -M no-aliases - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f,+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+f,+zicsr -M no-aliases - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d --mattr=+f - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f,+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+f,+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d --mattr=+f - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f,+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+f,+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-EXT-F %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-f < %s \
-# RUN:     | llvm-objdump -d --mattr=+f - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-f,+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+f,+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-EXT-F %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-f < %s \
-# RUN:     | llvm-objdump -d --mattr=-f - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-f,+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=-f,+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-EXT-F-OFF %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d --mattr=-f - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f,+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=-f,+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-EXT-F-OFF %s
 
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d --mattr=+f -M no-aliases - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f,+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+f,+zicsr -M no-aliases - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d --mattr=+f - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f,+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+f,+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d --mattr=+f - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f,+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+f,+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-EXT-F %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=-f < %s \
-# RUN:     | llvm-objdump -d --mattr=+f - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=-f,+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+f,+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-EXT-F %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=-f < %s \
-# RUN:     | llvm-objdump -d --mattr=-f - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=-f,+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=-f,+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-EXT-F-OFF %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d --mattr=-f - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f,+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=-f,+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-EXT-F-OFF %s
 
 
 # CHECK-INST: csrrs t0, fcsr, zero
 # CHECK-ALIAS: frcsr t0
 # CHECK-EXT-F:  frcsr t0
 # CHECK-EXT-F-OFF: csrr t0, fcsr
 csrrs t0, 3, zero

llvm/test/MC/RISCV/deprecated-csr-names.s

-# RUN: llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding %s \
+# RUN: llvm-mc -triple riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding %s \
 # RUN:     | FileCheck -check-prefixes CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype obj -triple riscv32 %s \
-# RUN:     | llvm-objdump -d - \
+# RUN: llvm-mc -filetype obj -triple riscv32 -mattr=+zicsr %s \
+# RUN:     | llvm-objdump -d --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 
-# RUN: llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding %s \
+# RUN: llvm-mc -triple riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding %s \
 # RUN:     | FileCheck -check-prefixes CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype obj -triple riscv64 %s \
-# RUN:     | llvm-objdump -d - \
+# RUN: llvm-mc -filetype obj -triple riscv64 -mattr=+zicsr %s \
+# RUN:     | llvm-objdump -d --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 
-# RUN: llvm-mc -triple riscv32 %s 2>&1 | FileCheck -check-prefix CHECK-WARN %s
+# RUN: llvm-mc -triple riscv32 -mattr=+zicsr %s 2>&1 | FileCheck -check-prefix CHECK-WARN %s
 
 # sbadaddr
 # name
 # CHECK-INST: csrrw zero, stval, zero
 # CHECK-ENC: encoding: [0x73,0x10,0x30,0x14]
 # CHECK-INST-ALIAS: csrw stval, zero
 # uimm12
 # CHECK-INST: csrrw zero, stval, zero

llvm/test/MC/RISCV/hypervisor-csr-names.s

-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN:     | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 #
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN:     | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 
 ##################################
 # Hypervisor Trap Setup
 ##################################
 
 # hstatus
 # name

llvm/test/MC/RISCV/machine-csr-names.s

-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN:     | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 #
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN:     | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 
 ##################################
 # Machine Information Registers
 ##################################
 
 # mvendorid
 # name

llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s

-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+zicsr -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN:     | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 
 ##################################
 # Hypervisor Configuration
 ##################################
 
 # henvcfgh
 # name

llvm/test/MC/RISCV/rv32-machine-csr-names.s

-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN:     | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 
 ######################################
 # Machine Trap Setup
 ######################################
 
 # mstatush
 # name

llvm/test/MC/RISCV/rv32-supervisor-csr-names.s

-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN:     | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 
 ##################################
 # Supervisor Trap Setup
 ##################################
 
 # stimecmph
 # name

llvm/test/MC/RISCV/rv32-user-csr-names.s

-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN:     | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 
 ##################################
 # User Counter and Timers
 ##################################
 
 # cycleh
 # name

llvm/test/MC/RISCV/rv32e-valid.s

-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+e -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+e,+zicsr,+zifencei -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+e < %s \
-# RUN:     | llvm-objdump -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+e,+zicsr,+zifencei < %s \
+# RUN:     | llvm-objdump -M no-aliases -d -r --mattr=+zicsr,+zifencei - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
 
 # This file provides a basic test for RV32E, checking that the expected
 # set of registers and instructions are accepted.
 
 # CHECK-ASM-AND-OBJ: lui zero, 1
 lui x0, 1
 # CHECK-ASM-AND-OBJ: auipc ra, 2

llvm/test/MC/RISCV/rv32i-aliases-valid.s

-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases \
 # RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
-# RUN: llvm-mc %s -triple=riscv32 \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr \
 # RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN:     | llvm-objdump -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN:     | llvm-objdump -M no-aliases -d -r --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ-NOALIAS,CHECK-EXPAND,CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN:     | llvm-objdump -d -r - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN:     | llvm-objdump -d -r --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
 
 # The following check prefixes are used in this test:
 # CHECK-INST.....Match the canonical instr (tests alias to instr. mapping)
 # CHECK-ALIAS....Match the alias (tests instr. to alias mapping)
 # CHECK-EXPAND...Match canonical instr. unconditionally (tests alias expansion)
 
 # Needed for testing valid %pcrel_lo expressions

llvm/test/MC/RISCV/rv32i-invalid.s

-# RUN: not llvm-mc -triple riscv32 %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zicsr %s 2>&1 | FileCheck %s
 
 # Out of range immediates
 ## fencearg
 fence iorw, iore # CHECK: :[[@LINE]]:13: error: operand must be formed of letters selected in-order from 'iorw' or be 0
 fence wr, wr # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw' or be 0
 fence rw, rr # CHECK: :[[@LINE]]:11: error: operand must be formed of letters selected in-order from 'iorw' or be 0
 fence 1, rw # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw' or be 0
 fence unknown, unknown # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw' or be 0

llvm/test/MC/RISCV/rv32i-valid.s

-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr,+zifencei -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple riscv64 -mattr=+zicsr,+zifencei -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 < %s \
-# RUN:     | llvm-objdump -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zicsr,+zifencei < %s \
+# RUN:     | llvm-objdump -M no-aliases -d -r --mattr=+zicsr,+zifencei - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-OBJ32,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 < %s \
-# RUN:     | llvm-objdump -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zicsr,+zifencei < %s \
+# RUN:     | llvm-objdump -M no-aliases -d -r --mattr=+zicsr,+zifencei - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-OBJ64,CHECK-ASM-AND-OBJ %s
 
 .equ CONST, 30
 
 # Needed for testing valid %pcrel_lo expressions
 .Lpcrel_hi0: auipc a0, %pcrel_hi(foo)
 
 # CHECK-ASM-AND-OBJ: lui a0, 2

llvm/test/MC/RISCV/rv64-machine-csr-names.s

-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN:     | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 
 # These machine mode CSR register names are RV32 only, but RV64
 # can encode and disassemble these registers if given their value.
 
 ######################################
 # Machine Protection and Translation
 ######################################

llvm/test/MC/RISCV/rv64-user-csr-names.s

-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN:     | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 
 # These user mode CSR register names are RV32 only, but RV64
 # can encode and disassemble these registers if given their value.
 
 ##################################
 # User Counter and Timers
 ##################################

llvm/test/MC/RISCV/rvf-user-csr-names.s

-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+f -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+f,+zicsr -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d --mattr=+f - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f,+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+f,+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f,+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS-NO-F %s
 #
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -mattr=+f -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -mattr=+f,+zicsr -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d --mattr=+f - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f,+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+f,+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f,+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS-NO-F %s
 
 ##################################
 # User Floating Pont CSRs
 ##################################
 
 # fflags
 # name

llvm/test/MC/RISCV/rvi-aliases-valid.s

-# RUN: llvm-mc %s -triple=riscv32 -M no-aliases \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -M no-aliases \
 # RUN:     | FileCheck -check-prefixes=CHECK-S-NOALIAS,CHECK-S-OBJ-NOALIAS %s
-# RUN: llvm-mc %s -triple=riscv32 \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr \
 # RUN:     | FileCheck -check-prefixes=CHECK-S,CHECK-S-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -M no-aliases \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr -M no-aliases \
 # RUN:     | FileCheck -check-prefixes=CHECK-S-NOALIAS,CHECK-S-OBJ-NOALIAS %s
-# RUN: llvm-mc %s -triple=riscv64 \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr \
 # RUN:     | FileCheck -check-prefixes=CHECK-S,CHECK-S-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN:     | llvm-objdump -d -r -M no-aliases - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN:     | llvm-objdump -d -r --mattr=+zicsr -M no-aliases - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ-NOALIAS,CHECK-S-OBJ-NOALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN:     | llvm-objdump -d -r - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN:     | llvm-objdump -d -r --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-S-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN:     | llvm-objdump -d -r -M no-aliases - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr < %s \
+# RUN:     | llvm-objdump -d -r --mattr=+zicsr -M no-aliases - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ-NOALIAS,CHECK-S-OBJ-NOALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN:     | llvm-objdump -d -r - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr < %s \
+# RUN:     | llvm-objdump -d -r --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-S-OBJ %s
 
 # The following check prefixes are used in this test:
 # CHECK-S                 Match the .s output with aliases enabled
 # CHECK-S-NOALIAS         Match the .s output with aliases disabled
 # CHECK-OBJ               Match the objdumped object output with aliases enabled
 # CHECK-OBJ-NOALIAS       Match the objdumped object output with aliases enabled
 # CHECK-S-OBJ             Match both the .s and objdumped object output with

llvm/test/MC/RISCV/rvk-user-csr-name.s

-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+f -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+zicsr,+f -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zkr < %s \
-# RUN:     | llvm-objdump -d --mattr=+zkr - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zkr,+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+zkr,+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 #
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -mattr=+f -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -mattr=+zicsr,+f -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zkr < %s \
-# RUN:     | llvm-objdump -d --mattr=+zkr - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zkr,+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+zkr,+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 
 ##################################
 # Entropy Source CSR
 ##################################
 
 # seed
 # name

llvm/test/MC/RISCV/supervisor-csr-names.s

-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN:     | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 #
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN:     | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 
 ##################################
 # Supervisor Trap Setup
 ##################################
 
 # sstatus
 # name

llvm/test/MC/RISCV/user-csr-names.s

-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN:     | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 #
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN:     | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr < %s \
+# RUN:     | llvm-objdump -d --mattr=+zicsr - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 
 ##################################
 # User Trap Setup
 ##################################
 
 # ustatus
 # name